JPH01141435A - Data communication equipment - Google Patents

Abstract

PURPOSE:To obtain optimum receiving data by processing the optimum error frame data of a storing data in making them into the receiving data when an error re-sending ends to be unsuccessful several times. CONSTITUTION:Data are received with a prescribed frame unit, the error of the received frame data is checked, the re-sending of the frame data is instructed based on the check, and a re-sending frequency is counted. The error frame data of a means to store the optimum error frame data are processed in making them into the receiving data when the re-sending of the error frame by the re-sending instruction ends to be unsuccessful prescribed times. Thus, the normal data contained in the error frame can be effectively used, and the optimum receiving data can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data communication device, and particularly to a data communication device having an error retransmission function.

[Conventional technology]

Conventionally, in this type of apparatus, for example, a facsimile apparatus having an error retransmission function for transmitting image information in HDLC format, when an error frame remains, the following processing is performed.

In the first process, nothing is recorded in the error frame portion, but the preceding and succeeding frames are condensed and recorded.

The second process is to record unique information indicating that an error line has occurred for a certain number of lines in the error frame portion.

In the third process, when an error frame remains, the number of lines in the error frame is estimated from the number of lines in the frames before and after it, and unique information indicating that error lines have occurred is recorded for that number of lines. .

The fourth process is when an error frame remains, the transmitter side notifies the receiver side of the number of lines included in the error frame, and the receiver side informs the receiver that errors have occurred in the received image for the number of error lines. The unique information represented is recorded.

[Problems to be Solved by the Invention] The first to fourth processes of the conventional example do not consider decoding and recording received frame information for error frames. That is, error frames are not recorded, or unique information is recorded instead of error frame data. However, when the number of error bits included in an error frame is small, it is possible to record most of the line information in the error frame by decoding the frame and recording correctly received line information in the received image. Therefore, in conventional error retransmission, there is a problem in that a normally received image included in an error frame is lost.

[Means and effects for solving the problem] According to the present invention, when several error retransmissions are unsuccessful, the optimal error frame data in the storage means is processed as received data, so the error frame The normal data contained in the data can be used effectively, and the optimal received data can be obtained.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

First, a method of error retransmission in the facsimile apparatus of this embodiment will be explained. In this embodiment, on the transmitter side,
The encoded image information is divided into predetermined lengths, formatted into HDLC format as one frame, and a plurality of frames are transmitted at one time (for example, 256 frames are transmitted). On the receiver side, after receiving a plurality of frames (for example, 256 frames), the number of the error frame is transmitted to the transmitter side. On the transmitter side, the error frame is retransmitted. On the receiver side, when there are no more error frames, information to that effect is sent to the transmitter, and the transmitter proceeds to transmit the next block. In addition, if there is still an error frame, for example, even after retransmission three times, the transmitter may continue to retransmit that frame, or it may interrupt the retransmission of that frame and proceed to transmit the next block. You can decide whether to proceed.

The receiver first receives data in a temporary buffer, and when the data for one frame is correctly received, checks the frame number and transfers the data to the corresponding image memory space. Then, if data is continuously and correctly received, recording operations are performed sequentially. In addition, when frame data with an error is received in the temporary buffer during the CRC check, the number of correctly received lines included in that frame is memorized, and the frame data is transferred to the corresponding image memory space. do.

After receiving one block, the receiver transmits the number of the frame in error to the transmitter. On the transmitter side,
The error frame is retransmitted. At this time, if the error frame data is correctly received in the temporary buffer, the receiver transfers it to the corresponding image memory space.

In addition, if the receiver receives frame data with an error in the CRC check of the retransmitted data in the temporary buffer, it counts the number of correctly received lines included in that frame, and Compare the number of correctly received lines included in the frame data, and if the number of currently correctly received lines is greater, the currently received frame data is transferred to the corresponding image memory space and the number of lines included in that frame is transferred. Information on the number of correctly received lines is also updated. Also, if the number of correctly received lines is currently small, nothing is done. That is, the error frame always stores the information with the least errors among the received information (specifically, the information with the largest number of correctly received lines included in the frame). This is a feature of the present invention. If an error frame remains after the transmission of one block is completed, the information with the least number of error lines is stored in that error frame, and that frame data can also be decoded and recorded. became.

Hereinafter, this embodiment will be described in detail based on the drawings. 1st
The figure is a block diagram showing the configuration of the facsimile machine of this embodiment.

In Figure 1, 2 uses the telephone network for data communication, etc., so it connects to the terminal of the line and controls the connection of the telephone exchange network, switches to the data communication path, and maintains the loop. Network control unit NCU (Network
Control Unit).

The signal line 2a is a telephone line. NCU2 is signal line 3
6a is input, and if the signal level is "0", the telephone line is connected to the telephone side, that is, the signal line 2a is connected to the signal line 2b. Also, input the signal of the signal line 36a,
If this signal level is rlJ, the telephone line is connected to the facsimile machine side, that is, the signal line 2a is connected to the signal line 2C. Under normal conditions, the telephone line is connected to the telephone side.

4 is a telephone.

6 is a hybrid circuit that separates the transmission system signal and the reception system signal. That is, the transmission signal on the signal line 20a passes through the signal line 2c, and is sent out to the telephone line via the NCU 2. Also, the signal sent from the other party is sent to NCU2.
After passing through the signal line 2c, the signal is output to the signal line 6a.

8 is a reading circuit, which reads 154 pixels in the main scanning direction from the original to be sent.
Two-part image signals are sequentially read to generate a signal string representing binary values of white and black. It consists of an image sensor such as a COD (charge coupled device) and an optical system. The white and black binary signal strings are output to the signal line 8a.

10 inputs the data output to the signal line 8a,
This circuit outputs encoded data (MW (Modified Huffman) encoding or MR (Modified Read) encoding) to the signal line 10a.

12 is a memory circuit that stores data output to the signal line 10a.

This facsimile apparatus needs to have a memory of at least 11,072 minutes because it retransmits an error frame after transmitting a plurality of frames as one block at a time. When the frame number to be transmitted is output to the signal line 36c, the memory circuit 12 outputs the information of the frame to the signal line 12a.

14, an address field, a control field,
Add the FCF field and PIF field (stores the frame number currently being transmitted) and send that information to H
This circuit outputs DLC formatted information to the signal line 14a. The HDLC framing circuit 14 also outputs a flag for flow control on the transmitter side to the signal line 14a when a signal of signal level rlJ is output to the signal line 36d.

16 is a modulator that performs modulation based on the well-known CCITT recommendation V27ter (differential phase modulation) or v29 (quadrature modulation). The modulator 16 inputs the signal on the signal line 14a, performs modulation, and outputs the modulated data to the signal line 16a.

18 is a modulator that performs modulation based on the known CCITT recommendation V21. The modulator 18 inputs the procedure signal on the signal line 36b, performs modulation, and transmits the modulated data to the signal line 18a.
Output to.

20 inputs the signals of the signal line 16a and the signal line 18a,
The added result is output to the signal line 20a.

22 is a demodulator that performs demodulation based on the known CCITT recommendation V21. The demodulator 22 inputs the signal on the signal line 6a, performs V21 demodulation, and sends the demodulated data to the signal line 22a.
Output to.

24 is a demodulator that performs demodulation based on the well-known CCITT recommendation V27ter (differential phase modulation) or v29 (orthogonal modulation). The demodulator 24 inputs the signal on the signal line 6a, performs demodulation, and outputs demodulated data to the signal line 24a.

26 inputs the demodulated data output to the signal line 24a, performs O-delete of the HDLC data, and
This is an HDLC deframing circuit that outputs data before being converted into C format to the signal line 26a. and,
When the HDLC deframing circuit 26 finishes receiving one frame, it generates a pulse on the signal line 26b. Then, when a pulse is generated on the signal line 26b and one frame is correctly received, the signal line 26 outputs a signal of signal level rlJ to the signal line 26c. Further, when a pulse is generated on the signal line 26b and one frame is not correctly received, a signal with a signal level of "0" is outputted on the signal line 26c. 26 outputs 1 byte of data after HDLC deframing to the signal line 26a.
Every time byte data is output, a pulse is generated on the signal line 26d.

28 is a temporary memory circuit that temporarily stores encoded image information output to the signal line 26a on a frame-by-frame basis.

The flow of data input and output to the temporary memory circuit 28 will be explained below.

28 is temporary buffer 0, temporary buffer 1
, each having a memory space of, for example, 512 bytes. These temporary buffers 0.
1 stores l frames of data sent from the other party's transmitter. Here, the maximum data length of one frame is 256+4 (A, C.

FCF (with 4 bytes of frame number added), so 512 bytes of memory space is allocated. When data is stored in one temporary buffer (data is input from the signal line 26a), the other temporary buffer is
Data is output from the two temporary buffers (data is output from the signal line 28a and the signal line 28c). Set the start address of temporary buffer 0 to TEMPBFO3F
Name it STA, and name the start address of the temporary buffer l TEMPBFISFSTA.

In the temporary memory circuit 28, normally, received data is stored alternately in temporary buffers 01 and 1. In this method, the control circuit 36 first sends TEMPBFO3FST to the signal line 36e as a storage address.
A or TEMPBFISFSTA is output, and when 1-byte data is received, that is, a pulse is generated on the signal line 26d, the data output to the signal line 26a is input and stored in the storage address. And control circuit 3
Step 6 increments the storage address by one. The control circuit 36 controls the number of data for one frame (image information data is 25
6 bytes, other additional information: A, C, FCF
, 4 bytes of frame number), it is always checked to see if it exceeds 260 bytes.

When the reception of data for one frame is completed, that is, when a pulse is generated on the signal line 26b, it is checked whether or not the data has been received correctly. If it has been received correctly, the value of the frame number is checked. The frame number is stored in the 4th byte from the beginning of the received data of the l frame,
This information is output to signal line 28b. Then, the control circuit 36 instructs the transfer start address (output to the signal line 36f) to the temporary memory circuit 28 and the storage start address (output to the signal line 36g) to the image memory circuit 30, and then sets the number of bytes to be transferred. After outputting to the signal line 36e,
A transfer instruction pulse is output to the signal line 36h, and the data received by the temporary memory circuit 28 is transferred to the corresponding image memory space.

When the reception of l-frame data has finished, but it is not received correctly (when an error occurs in the CRC check)
checks the number of received data included in the frame, and if it is less than a predetermined number of bytes, for example 10 bytes, the data is discarded. This means that when transporting the flag,
This is because it is considered that there are many cases where an error occurs.

If the data included in the frame is a predetermined number of bytes, for example, 132 bytes or more, the data is sequentially stored in the image memory. Then, the frame data is decoded, and the number of correctly received lines included in the frame is counted and stored. If the data contained in that frame is the intermediate number of bytes above, i.e. 1
When the size is from 1 byte to 131 bytes, it may be stored in the image memory or discarded. In this example,
think about throwing it away.

Furthermore, when one frame is being received and the number of frames exceeds the number of data in one frame, the data received after that is discarded. The fact that the number of data in one frame is more than 261 bytes occurs when all the flags inserted between frames are broken.

At the time of retransmission, the control is different only when reception of the data of 1 frame is completed, but a CRC error occurs, and the data included in the frame is 132 bytes or more and 260 bytes or less. In this case, this frame data is decoded, the number of correctly received lines included in the frame is counted (by inputting the signal output to the signal line 29a), and the frame data currently stored in the image memory is The number of correctly received lines included in the frame is compared, and if the number is larger, the frame data is sequentially stored in the image memory, and the number of correctly received lines included in the frame is updated.

29 inputs the l-frame data output to the signal line 28C, decodes it (MH (Modified Huffman) decoding or MR (Modified Read) decoding), and decodes the correctly received data included in that frame. This is a decoding line number detection circuit that outputs the number of lines to the signal line 29a.

Reference numeral 30 denotes an image memory circuit, which requires memory space to store at least one block of data. The method for storing the data temporarily stored in the temporary memory circuit 28 in the image memory circuit 30 has been described above. The image memory circuit 30 sequentially outputs one block of information stored in the memory to the signal line 30a when a signal of signal level "1" is output to the signal line 36j.

32 inputs the demodulated data output to the signal line 30a when a signal of signal level "1" is output to the signal line 36j, and performs decoding (MH (Modified Huffman) decoding or MR (Modified Huffman) decoding). This circuit outputs the read/decoded data to the signal line 32a.

34 is a recording circuit which inputs the signal output to the signal line 32a when a signal of signal level "1" is output to the signal line 36j, and sequentially records every l line.

Reference numeral 36 denotes a control circuit that mainly performs the control described in the first section of the embodiment and the sections of the HDLC deframing circuit 26 and the temporary memory circuit 28. The control circuit is composed of a microcomputer and peripheral devices for the microcomputer, such as a read only memory (ROM) for storing a control program for the microcomputer, and a random access memory (RAM) for temporarily storing data.

FIG. 2 is a flowchart showing the control operation of the control circuit 36 of FIG. 1. FIG. 2(a) is a main routine, and FIG. 2(b) is an included routine for receiving an image signal.

In FIG. 2(a), step S40 represents the beginning, and the routine starts in response to power-on.

When the main routine starts, in step S42, a signal of signal level rOJ is output to the signal line 36a,
CML is turned off and the process proceeds to step S44.

In step S44, it is determined whether facsimile reception has been selected. When it is determined that facsimile reception is selected,
Proceed to step 348. If it is determined that facsimile reception is not selected, the process advances to step S46 to execute other processing (for example, transmission, etc.).

When the process proceeds from step S44 to step 548, a signal of signal level rlJ is output to the signal line 36a in step 348, CML is turned on, and a pre-procedure of the facsimile communication procedure is executed in step S50.

When the pre-procedure is completed, the process advances from step S50 to step S52, and it is determined whether reception in error retransmission mode is selected. When reception in error retransmission mode is selected, the process advances from step S52 to step S58. If reception in the error retransmission mode is not selected, the process advances from step S52 to step S54, where normal image signal reception is performed without the error retransmission mode.

When the image signal reception is completed, a post-facsimile communication procedure is performed in step S56.

On the other hand, in the error reproduction mode, from step S52 to step 3
58, a flag indicating whether the transmission of the current block is a retransmission is set to O in step 358. Note that when the retransmission flag is O, it indicates that the block transmission is not a retransmission, and when the retransmission flag is 1, it indicates that the block transmission is a retransmission.

Next, in step S60, the start address of the image memory space is stored in the image memory pointer, and step S62
In step S62, O is set in FRAMNO where the frame number of the data to be received next is stored. Then, in step S64, when the reception of one frame is completed and there is a cRc error, the TRANSF is used to store the number of received bytes.
After setting ERBYTEl:0, step S66
In step 368+, a counter BYTECOUNTl:O for counting the number of received bytes included in one frame is set, and the process proceeds to step 368+.

In step 368, the received data is stored in a temporary buffer. Temporary buffers include temporary buffer 0 and temporary buffer l, and a flag TE indicates which temporary buffer to store data in.
Set MPBFI (temporary buffer in) to O. When TEMPBFI is 0, the received data is stored in temporary buffer 0, and when TEMPBFI is 1, the received data is stored in temporary buffer 1, and the process advances to step S70.

In step S70, when the temporary buffer becomes full, the data stored in the temporary buffer is transferred to an image memory capable of storing 1 block. At this time, a flag TEMPBFO (
Temporary buffer out) is set to 0. TEM
When PBFO is 0, the data is transferred to the image memory when temporary buffer 0 becomes full, and when TEMPBFO is 1, the data is transferred to the image memory when temporary buffer 1 becomes full.

In step S72, a flag TEMPBFOFULL (temporary buffer 0 full) indicating whether the temporary buffer O is full, that is, data has been stored in the temporary buffer O, is set to 0.

When TEMPBFOFULL is 0, it indicates that no data is stored in temporary buffer O, and TE
When MPBFOFULL is 1, it indicates that data has been stored in temporary buffer 0. Step S72
When the flag TEMPBFOFULL is set to O, the process advances to step S74.

In step S74, a flag TEMPBFIFULL (temporary buffer 1 full) indicating whether the temporary buffer 1 is full, that is, data has been stored in the temporary buffer 1, is set to 0.

When TEMPBFIFULL is O, it indicates that no data is stored in the temporary buffer l, and TEMPBFIFULL is O.
When PBFIFULL is 1, temporary buffer l
Indicates that data has been stored in . When the flag TEMPBFIFULL is set to 0 in step S74, the process advances to step S76, and in step S76 MODEM
After storing the start address of temporary buffer O in the contents of PTH, the process advances to step 578.

In step 378, when receiving one block of data, that is, when receiving a maximum of 256 frames of data, it is necessary to know which frame is being received correctly. A bitmap (32 bytes) of the received frame number is provided, and since the l frame has not been correctly received, all are set to 0. Each time frame data is correctly received, the bit of the corresponding frame number is set to 1.

Next, in step S80, the destination address shown in FIG. 2(b) is set as the destination address for interrelated reception of the image signal. This interconnect detects the end of the frame, that is, when a pulse is generated on the signal line 26b,
1 byte of data is input, that is, signal line 26d
It takes when a pulse occurs.

Then, in step S82, a flag LAST is set to 1 when the end signal of l block is detected.
After setting FRMDT (last frame detect) to 0, the process advances to step S84.

In step S84, the flag LASTFRMDT
It is determined whether the signal is O, that is, whether the signal indicating the end of one block has been detected. In step S84, the flag LAS
If TFRMDT is 0, that is, it is determined that the signal at the end of 1 block has not been detected, the process proceeds to step S86, and if the flag LASTFRMDT is 1, that is, it is determined that the signal at the end of 1 block has been detected, the process proceeds to step S86. .

When it is determined in step S84 that the signal at the end of one block has not been detected and the process proceeds to step S86, TEMPBF
It is determined whether O is O, that is, whether to transfer from temporary buffer 0 to the image memory next. T in step S86
If it is determined that EMPBFO is 0, that is, the next time the temporary buffer 0 is transferred to the image memory, the process advances to step 388. Also, in step S86, TEMPBF
If O is determined to be 1, that is, the next time the temporary buffer l is transferred to the image memory, step S94 is performed.
Proceed to.

In step 888, whether TEMPBFOFULL is 0 or
That is, it is determined whether the temporary buffer O is not full, and if it is determined that TEMPBFOFULL is O, that is, when the temporary buffer 0 is not full, the process advances to step S84. Also, in step S88, TEMPBFOF
If it is determined that ULL is 1, that is, if temporary buffer 0 is full, the process advances to step S90 and TE is
Set MPBFOFULL to O.

Then, in step S92, l is set in TEMPBFO, and in step S94, TEMPBFIF
It is determined whether ULL is 0, that is, whether the temporary buffer l is not full. TEMPBFI in step S94
If it is determined that FULL is O, that is, if the temporary buffer l is not full, the process advances to step S84, and TEMP
If BFIFULL is determined to be 1, that is, if the temporary buffer l is full, the process advances to step S96.

Then, in step S96, TEMPBFIFULL
is set to 0, and in step S98 TEMPBF is set to 0.
After setting O to 0, the process advances to step 5100.

In step 5100, although the reception of the l frame has ended, it is determined whether there is a CRC error. If there is a CRC error, the process advances to step 5118, and
If there is no CRC error, the process advances to step 5102.

When the process proceeds from step 5too to step 5102, the frame number is checked and 1 is set in the bitmap of the corresponding correctly received frame number.

Then, in step 5104, the bitmap of the correctly received frame number is checked to determine whether the frame received one or two frames before the currently received frame has been received correctly (i.e. , it is determined whether there were errors in two or more consecutive frames in the frames received before the currently correctly received frame). Check the bitmap of the correctly received frame number, and if the frame received one or two times before the currently received frame has been received correctly, step 51
Proceed to 08. Also, check the bitmap of correctly received frame numbers, and if both the frame received at least one frame before the currently received frame and the frame received two frames ago are not correctly received, step 5
Proceed to step 106. For example, if the currently received frame number is frame 115 when it is not retransmission, if frame 113 or frame 114 is correctly received, the process proceeds to step 3108 and at least frames 113 and 114 are correctly received. If not, proceed to step 5106. In addition, when retransmitting,
Frame numbers to be retransmitted are 11.15, 30, 55
, 100, 150.

Here, for example, if the received frame number is 100 frames and 30 frames or 55 frames are correctly received, the process proceeds to step 8108, and at least 30 frames or 55 frames are not correctly received. If so, proceed to step 5106.

Proceeding to step 5106, O is set to the number of correctly received lines stored in the currently received previous frames that have consecutive errors. That is, in the specific example of step 5104, when it is not the time of retransmission,
At least 113 frames, 114 frames, when retransmitting, store in at least 30 frames, 55 frames, and set O to the number of correctly received lines (
See other examples 4.5).

In step 3108, the frame number is checked, and the number of data for one frame (256 bytes) is transferred from A, C, FCF, and the next data of the frame number to the corresponding image memory space.

In step Sl 10, it is determined whether the current transmission is not a retransmission, that is, whether the retransmission flag is O. If the current transmission is not a retransmission, ie, the retransmission flag is O, proceed to step 5112. Further, when the current transmission is a retransmission, that is, the retransmission flag=1, the process proceeds to step Sl14.

In step 5112, the next address where data was last stored is set in the image memory pointer, and in step 511
In Step 14, the start address for storing the data to be retransmitted next is set in the image memory pointer, and in Step Sl
At step 16, the value obtained by adding l to the received frame number is stored in FRAMNO.

Then, in step S118, TRANSFE
Determine whether RBYTE is 132 bytes or more.

TRANSFERBYTE is 13 in step Sl 18
When the number of bytes is 2 or more, that is, when a CRC error has occurred but the data is larger than the specified number of bytes,
Proceed to step 5120. Also, TRANSFERBY
When TE is less than 132 bytes, that is, when a CRC error occurs and data of a predetermined number of bytes or more is not received, the process advances to step S84.

Proceeding from step St18 to step 5120, it is determined whether the current transmission is a retransmission, that is, whether the retransmission flag is O. If the current transmission is not a retransmission in step 5120, that is, the retransmission flag is 0, the process proceeds to step 5122. Also, the current transmission is a retransmission,
That is, when the retransmission flag is 1, step 51
Proceed to 30.

Proceeding to step 5122, the contents stored in FRAMNO and the number of correctly received lines included in that frame are memorized, and in step 5124, the contents stored in FRAMNO are stored in FRAMNO.
Increment NO by one and proceed to step 5126.

In step 5126, data from the %th byte onward stored in the temporary buffer is transferred by (TRANSFERBYTE number - 4 bytes) after the address of the image memory pointer. Then, in step 5128, the next address where the last data was stored is set in the image memory pointer, and in step 8130, the contents stored in FRAMNO are checked to recognize the currently received frame number. It now recognizes the number of correctly received lines contained in the received frame.

Next, in step 5132, the number of correctly received lines currently included in the received frame is determined as follows:
It is determined whether the number of correctly received lines is greater than the number of correctly received lines contained in the same frame stored in the image memory space. If the number of correctly received lines contained in the currently received frame is greater than the number of correctly received lines contained in the same frame currently stored in the image memory space, the process proceeds to step 5134; , proceed to step 8136.

When the process advances from step 5132 to step 5134, the image memory pointer (TRANSFERBYT)
The data from the 5th byte onward stored in the temporary buffer is transferred by E number - 4 bytes), and in step 5135, the number of correctly received lines is updated.

Then, in step 5136, the start address for storing the data to be retransmitted next is set in the image memory BOINK, and in step 8138, the frame number to be retransmitted is set in FRAMNO, and the process advances to step 5140.

In step 5140, it is determined whether there is an error frame, and if there is an error frame, step 514
2, and if there is no error frame, step 5156
Proceed to.

When it is determined that there is an error frame and the process proceeds from step 5140 to step 5142, a signal is sent to the transmitter side instructing retransmission of the error frame.

Next, in step 5144, it is determined whether or not this is the fourth retransmission instruction. If it is not the fourth retransmission instruction, the error frame is retransmitted from the transmitter side, so the process proceeds to step 5150. Also, when it is the fourth retransmission instruction in step 5144, the transmitter side either retransmits the block just sent, or interrupts the retransmission of the block just sent, and if there is a next lock, then the next lock is issued. Since a signal indicating whether to transmit the block is sent, the process advances from step 5144 to step 5146.

In step 5146, it is determined whether there is an instruction from the transmitter to retransmit the block just sent. In step 5146, if there is an instruction from the transmitter to retransmit the block just sent, the process proceeds to step 8148 after sending a response signal. If there is an instruction from the transmitter to suspend retransmission of the block just sent and to transmit the next block if there is one, the process proceeds to step 5156 after transmitting a response signal.

In step 5148, the counter for the retransmission instruction determined in step 5144 is cleared, and in step 51
Since the retransmission block data is received at step 50, the retransmission flag is set to 1.

Then, in step 5152, the start address for storing the next retransmitted data is set in the image memory pointer, and in step 5154, in FRAMNO,
Stores the frame number to be retransmitted next.

On the other hand, when proceeding from step 5146 to step 5156,
In step 5156, the image signal is recorded. Then, in step 3158, it is determined whether or not it is the final block, and if it is the final block, step 516
0, and if it is not the final block, step 5168
Proceed to.

When the process advances from step 8158 to step 5160, a post-facsimile communication procedure is executed. and step 5
At step 162, a signal with a signal level of "0" is output to the signal line 36a to turn off the CML, and at step 5164, the image signal is recorded again, and at step 5166, the image signal recording continues until it is determined that recording of the image signal is completed. I do. When recording of the image signal is completed, the process returns from step 5166 to step S42.

On the other hand, if it is determined in step 5158 that it is not the final block and the process proceeds to step 8168, it is determined whether or not recording of the image signal has been completed, and when recording of the image signal is completed, step 517
If the process proceeds to step 2 and recording of the image signal is not completed, the process proceeds to step 5170 to adjust the speed between the transmitter and receiver.

At step 5168, it is determined that the image signal recording has ended, and at step 5
When the process proceeds to step 172, an intermediate procedure of the facsimile communication procedure is performed in step 5172, and then the process returns to step 358.

Next, an interwoven routine for image signal reception in the error reproduction mode will be explained.

When the interwoven routine starts in step 318, it is determined in step 3182 whether or not the end of the frame has been detected, that is, whether or not a pulse has been generated on the signal line 26b. If it is determined in step 3182 that the end of the frame has been detected, that is, if a pulse is generated on the signal line 26b, the process advances to step 5194. If it is determined in step 8182 that the end of the frame has not been detected, that is, if no pulse is generated on the signal line 26b, the process advances to step 8184.

When you proceed to step 3184, BYTECOUNT is 260.
In other words, 260 as one frame of data
Determine whether a byte has been received. Step 5184
If it is determined that BYTECOUNT is 260, that is, if 260 bytes of data are being received as data of 1 frame, the process advances to step 5192.

If BYTECOUNT is not 260 in step 5184, that is, 260 bytes of data have not been received as l frame data, step 5186 is determined.
In step 5186, 1 byte of data is stored at the address of the contents of MODEMPTR.

Then, in step 8188, the contents of MODEMPTR are incremented by one, and in step 5190, the BYT
Increment the value of ECOUNT by one, step 5192
Return with .

On the other hand, if it is determined in step 8182 that the end of the frame has been detected and the process proceeds to step 5194, in step 5194
Determine whether the block end signal is detected.

If the signal indicating the end of one block is detected in step 5194, the process proceeds to step 5216, and if the signal indicating the end of one block is not detected, the process proceeds to step 5196.

Proceeding to step 8196, it is determined whether TEMPBFI is O, that is, whether data has been stored in temporary buffer 0. TEMPBFI in step 5196
is 0, that is, data is stored in temporary buffer O, the process advances to step 5198, and TEMP
When BFI is 11, that is, data is stored in temporary buffer 1, the process advances to step 5204.

Also, if TEMPBFI is determined to be O in step 5196 and the process proceeds to step 5198, then in step 5198 the data will be stored in the temporary buffer l, so TE
Set MPBFI to 1.

Then, in step 5200, data is stored in temporary buffer O, so TEMPBFOFULL is set to 1, and in step 5202, data is stored in temporary buffer l, so MODEM
After storing the start address of temporary buffer 1 in the contents of PTR, the process advances to step 5210.

On the other hand, when it is determined in step 5196 that TEMPBFI is l and the process proceeds to step 5204, in step 5204,
This time, in order to store data in temporary buffer O,
Set TEMPBFI to O. And step 5
Since the data has been stored in the temporary buffer l in step 206, TEMPBFIFULL is set to 1, and in step 8208, the data is stored in the temporary buffer O.
In order to store data in , the start address of temporary buffer O is stored in the contents of MODEMPTH, and then the process advances to step 5210.

When the process proceeds to step 5210, it is determined whether or not there is a CRC error. If there is a CRC error, the process proceeds to step 5212; if there is no CRC error, the process proceeds to step 3214.

If there is a CRC error and the process proceeds to step 5212, the TRA
After storing the value of BYTECOUNT in NSFERBYTE, the process proceeds to step 5214, where 0 is set in BYTECOUNT.

Also, in step 5194, it is determined that the end signal of one block has been received, and the process proceeds to step 5216. In step 3216, since the end signal of one block is detected, the LASTF is
Set the RMDT flag to 1.

In the embodiment described above, when one frame causes an error, by comparing the number of correctly received lines included in that frame, the line with the largest number of correctly received lines is always displayed in the image. Stored in memory.

However, one frame data is not a line break. Therefore, the frames before and after the error may be referred to. That is, by referring to the previous frame in which the error occurred, data at the beginning of the error frame may be counted as correct line information. Furthermore, by referring to the frame after the error occurred, data at the end of the error frame may be counted as correct line information. This will increase the number of correctly received lines.

Further, in the embodiment described above, one frame is received, and when the number of frames exceeds one frame of data, the subsequent received data is discarded. However, since this is a case where the flag between frames is broken, this data may be stored in the image memory.

In addition, in the embodiment described above, if an error occurs in two or more consecutive frames in a plurality of frames received at one time, the data is When the number of images is the largest, it is transferred to the image memory space. If that data does not have the largest number of correctly received lines in the same frame received so far, nothing is done. Regardless of whether or not the error frame data is transferred in the image memory space, O is stored in the number of correctly received lines in the consecutive error frames (step 5106).

However, only when transferring data to the image memory space,
0 may be stored in the number of correctly received lines stored in the error frame.

In addition, in the embodiment described above, if an error occurs in two or more consecutive frames in a plurality of frames received at one time, O is stored in the number of correctly received lines in that frame. ing. However, if an error occurs in two or more consecutive frames among a plurality of frames received at one time, the configuration may be such that the consecutive error frame data are not transferred to the image memory. This is because if an error occurs in two or more consecutive frames, depending on how the error occurs, it is possible that the image will not be transferred to the correct image memory space.

As explained above, according to this embodiment, the receiver has one
If an error frame remains after transmission of one block is completed, this error frame contains information about the least error among the frames received a predetermined number of times (specifically, the number of correctly received lines included in the frame). (most common) can be stored.

Although the above-described embodiments have been explained using a facsimile machine as an example, the present invention is not limited to facsimile machines, but can be implemented in any data communication device such as teletex.

〔effect〕

As described above, according to the present invention, optimal reception processing can be performed when error retransmission is not successful.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the facsimile apparatus of this embodiment, and FIG. 2 is a flowchart showing the control operation of the control circuit 36 of FIG. 1. 2 is NCU. 4 is a telephone, 6 is a hybrid circuit, 8 is a reading circuit, 10 is an encoding circuit, 12 is a memory circuit, 14 is an HDLC framing circuit, 16 is a V27ter or V29 modulator, 18 is a V2
1 modulator, 20 is an adder circuit, 22 is a V21 demodulator, 24 is a V27ter or V29 demodulator, 26 is an HD
LC deframing circuit, 28 is a temporary memory circuit, 29 is a decoding/line number detection circuit, 30 is an image memory circuit, 32 is a decoding circuit, 34 is a recording circuit, and 36 is a control circuit.

Claims (1)

[Scope of Claims] A data communication device having an error retransmission function, comprising means for receiving data in units of predetermined frames and checking for errors in the received frame data, and retransmitting the frame data based on the output of the checking means. means for instructing, means for counting the number of retransmissions, and means for identifying the error state of the frame data in which an error has been detected;
It is characterized by comprising means for storing optimal error frame data when the retransmission of the error frame by the retransmission instruction means is unsuccessful a predetermined number of times, and means for processing the error frame data in the storage means as received data. data communication equipment.