JPH01140253A - Bank memory switching control system - Google Patents

Abstract

PURPOSE:To monitor an address bus during the travel of a program and to switch a bank at high speed by setting the specific address of an opportunity for switching as a bank switching address immediately after the start of the travel of the program corresponding to plural bank memories by an address decode/address latch circuit. CONSTITUTION:The address of the opportunity for switching the bank set from the program is internally held as the bank switching address table immediately after the start of the travel of the program by the address latch/address decode circuit 9 connected to the system bus 2 of a control system. One of first-third bank memories 3-5 corresponding thereto is selectively selected by the memory enable signals of signal lines 6-8. This circuit 9 constantly monitors the address signal of the bus during travel of the program, automatically detects the switching address of the bank memories 3-5 and switches the bank at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bank memory switching control system, and more particularly to a bank memory switching control system in an information processing apparatus that switches bank memories.

(Prior Art) Conventionally, this glaze bank memory switching control system has been configured as shown in FIG. In FIG. 2, first to third bank memories 3 to 5 and a microprocessor 1 are interconnected by a system bus 2.
A bank register 10 is connected to. Bank memory/1 (l Memory enable signal t for selectively enabling one of the first to third bank memories 3 to 5
- Generate on signal lines 6-8.

By writing predetermined data in the bank register 10 corresponding to the first to third bank memories 3 to 5, respectively, and activating one of the memory enable signals on the signal lines 6 to 8, The first to third bank memories 3 to 5 are switched.

(Problems to be Solved by the Invention) As mentioned above, the conventional bank memory switching control system requires processing to write data for switching to the bank register by a program.

It has the disadvantage that it is not suitable for information processing systems that frequently require high-speed bank switching.

The object of the invention is to correspond to bank memories.

A specific address that triggers switching to the bank memory is set as a bank switching address table immediately after the program starts running.

Monitor the address bus while the program is running.

To provide a bank memory switching control method configured to eliminate all of the above drawbacks by automatically enabling the corresponding bank memory when a bank switching address is detected, and to enable high-speed bank switching without any hindrance. It is in.

(Means for Solving All Problems) The bank memory switching control method according to the present invention is for an information processing device that is fully equipped with a plurality of bank memories and a microprocessor, and further includes an address decode/address latch circuit. It is composed of

Address decode/address latch circuit.

Corresponding to multiple bank memories, a specific address that triggers switching to a bank memory is set as a bank switching address table immediately after the program starts running.
This is the ninth system that monitors the address bus while the program is running and automatically enables the corresponding bank memory when a bank switching address is detected.

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the bank memory switching control system according to the present invention.

In FIG. 1, 1 is a microprocessor, 2 is a system bus, 3 to 5 are first to third bank memories, and 9 is a system bus.
is an address latch/address decode circuit. 1st
In the figure, elements that are the same as in FIG. 2 are numbered the same.

In FIG. 1, the first to third bank memories 3 to 5 and the microprocessor 1 are interconnected by a system bus 2, and an address latch/address decode circuit 9 for bank switching is connected to the system bus 2. has been done.

Address check/address decode circuit 9.

The address that triggers bank switching, which is set by the processor immediately after the program starts running, is held internally as a bank switching address table, and the corresponding first
~ A memory enable signal for selectively enabling one of the third bank memories 3 to 5 is sent to the signal lines 6 to 8.
It is for generating on. After the bank switching address table is set, the address latch/address decode circuit 9 constantly monitors the address signal on the address bus, and when the address signal detects a specific preset address, the address latch/address decode circuit 9 One of the enable signals on signal lines 6 to 8 corresponding to the address is enabled, and from then on, until another specific address arrives,
It shall have a function to maintain this.

This specific address is the first to third bank memo IJ3 to
Address 25EADRO corresponding to the first bank memory 3, address 25EADRO corresponding to the second bank memory 3,
The address corresponding to bank memory 4 is ADRl, $3
It is assumed that the address corresponding to the bank memory 5 is determined to be the person DR2. In this case, actual bank switching is performed as follows. For example, while the program is running,
Fetch DRO instructions or AD
When you perform read/write access to RO, the address;
(The latch/address decode circuit 9 generates an enable signal T corresponding to the first bank memory 3 on the signal line 6,
Thereafter, the enable signal on the signal line 6 is held as long as the program does not pass through ADR1 or ADR2t-. Therefore, during that time, access to the first bank memory 3 becomes possible.

Hereinafter, the same applies to ADRI and ADR,2.
The third bank memory 4 and the third bank memory 5 can be accessed in the same manner.

Therefore, when creating a program, the address on the program that requires bank switching or the address on the bank grid is determined, and immediately after the program starts running, that address is sent to the address latch/address decode circuit 9 as the bank switching address. By setting, banks can be switched at a desired time.

(Effects of the Invention) As explained above, in the present invention, the special electric address that is the trigger for switching to the bank memory is set as a bank switching address table immediately after the program starts running, corresponding to the bank memory. By monitoring the address bus while the program is running and automatically enabling the troubleshooting bank memory when a bank switching address is detected, there is the effect that high-speed bank switching is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a bank switching control method according to the present invention. FIG. 2 is a block diagram showing an example of a bank switching control method according to the prior art. 1...Microprocessor 2...System nodes 3-5...Bank memory 9...Address latch/address decode circuit 10.
...Bank registers 6 to 8...Signal line patent applicant Hisashi Inoro, patent attorney representing NEC Corporation

Claims (1)

[Claims] A bank memory switching control method in an information processing device including a plurality of bank memories and a microprocessor, wherein a program starts running a specific address that is a trigger for switching to the bank memory corresponding to the plurality of bank memories. The address decode/address latch circuit is set as a bank switching address table immediately after the , monitors the address bus while the program is running, and automatically enables the corresponding bank memory when a bank switching address is detected. A bank memory switching control system comprising: