JPH01136332A - Electron beam lithography method - Google Patents
Electron beam lithography methodInfo
- Publication number
- JPH01136332A JPH01136332A JP62294114A JP29411487A JPH01136332A JP H01136332 A JPH01136332 A JP H01136332A JP 62294114 A JP62294114 A JP 62294114A JP 29411487 A JP29411487 A JP 29411487A JP H01136332 A JPH01136332 A JP H01136332A
- Authority
- JP
- Japan
- Prior art keywords
- marks
- electron beam
- field
- stage
- deflected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 13
- 238000000609 electron-beam lithography Methods 0.000 title claims description 8
- 238000010894 electron beam technology Methods 0.000 claims abstract description 18
- 238000012937 correction Methods 0.000 claims description 31
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 238000001459 lithography Methods 0.000 abstract 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 14
- 235000012431 wafers Nutrition 0.000 description 13
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 210000000936 intestine Anatomy 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子線描画方法とそれに用いる位置合せマーク
の構造に係り、特に改善された偏向歪の補正方法とそれ
に用いるマークに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electron beam lithography method and the structure of an alignment mark used therein, and more particularly to an improved deflection distortion correction method and a mark used therein.
電子線描画における位置合せの方式には大きく分けて以
下の2つが知られている。まず第1は第2図に示したよ
うに1チツプが1フイールドより構成されているもので
、チップ1周辺に配置された位置合せマーク2,3,4
,5をステージを停止した状態で電子ビームを偏向する
ことで検出するものである。(ステージ固定型マーク検
出法と称する。)この例としてはアイビーエム・ジャー
ナル・オブ・リサーチ・ア。ンド・ディベロップメント
ノーベンバー(1977年)第498頁から第505
頁(IBM Journal ofJasearch
andDavslopment、 November
1 9 7 7年、pp4.98−505)が挙げ
られる。この場合の利点はマーク2,3,4.5の位a
m定には電磁レンズ系の偏向歪を含んだ状態で測定され
るため、偏向歪補正は自動的に行われる。しかしながら
フィールドの大きさを越えるチップを描画する時にはチ
ップ中心龜にマークを配置せねばならないという問題が
生じる。もう一つの方法は第3図゛に示したように1チ
ツプが複数のフィールドf1 e f z p f a
gf4で構成されているものでマーク7.8,9゜1
0はチップの4偶に配置されている。この場合のマーク
検出はステージを移動することにより各マークを電子線
の偏向中心近傍に置くことで行われる6 (ステージ移
動形マーク検出と称する。)このときステージ位置はレ
ーザ干渉計により精密に測定される。この例としてはジ
ャーナル・オブ・バキューム・サイエンス・アンド・テ
クノロジー・19(4) 1981年 第927頁か
ら第931頁(Journal of Vacuum
and 5cience andTechnology
l 9(4) 1981 pp927−931)が挙げ
られる。この場合の利点はチップサイズがフィールドに
制限されず大きくとれることである。The following two types of alignment methods in electron beam lithography are known. First, as shown in Fig. 2, one chip consists of one field, and alignment marks 2, 3, and 4 are arranged around the chip 1.
, 5 are detected by deflecting the electron beam with the stage stopped. (This is called fixed stage mark detection method.) An example of this is IBM Journal of Research A. Development November (1977) pp. 498-505
Page (IBM Journal ofJasearch
andDavslopment, November
1977, pp. 4.98-505). The advantage in this case is marks 2, 3, and 4.5 positions a
Since the m constant is measured while including the deflection distortion of the electromagnetic lens system, deflection distortion correction is automatically performed. However, when writing a chip that exceeds the field size, a problem arises in that a mark must be placed at the center of the chip. Another method is as shown in FIG.
It is composed of gf4 and has a mark of 7.8, 9゜1.
0 is placed in the fourth even position of the chip. In this case, mark detection is performed by moving the stage to place each mark near the center of deflection of the electron beam6 (referred to as moving stage mark detection).At this time, the stage position is precisely measured using a laser interferometer. be done. An example of this is Journal of Vacuum Science and Technology 19(4) 1981, pages 927-931.
and 5science and Technology
19(4) 1981 pp927-931). The advantage in this case is that the chip size is not limited by the field and can be made large.
しかし偏向歪は予め被描画試料外のマークを用いて精密
に設定され、補正のための係数を求めておく必要がある
。補正係数を求める方法は例えば第4図のようなフィー
ルド11内の座標を正確に測定した9点のマーク12〜
20を電子線を偏向して検出することにより以下の係数
を最小二乗法により求めることができる。However, the deflection distortion must be precisely set in advance using marks outside the sample to be drawn, and coefficients for correction must be determined. The method of determining the correction coefficient is, for example, by using nine marks 12 to 12 whose coordinates within the field 11 are accurately measured as shown in Fig. 4.
By detecting 20 by deflecting the electron beam, the following coefficients can be determined by the method of least squares.
式(1)
ここでao ”as 、be−bsは偏向歪補正係数、
Xm’jは歪のない場合の電子線描画位置。Equation (1) where ao ”as, be-bs are deflection distortion correction coefficients,
Xm'j is the electron beam drawing position when there is no distortion.
x’ 、y’は偏向歪補正後の電子線描画位置である。x' and y' are the electron beam lithography positions after correction of deflection distortion.
チップサイズの制限のない後者の手法が、現在主に使わ
れている。The latter method, which has no chip size limitations, is currently mainly used.
上記従来技術では描画前に偏向歪の補正係数を求め、描
画中は同一の補正係数を用いることになる。従って偏向
歪の経時的変化がある場合にはフィールド周辺部で層間
の位置合せずれが生じたりフィールド接続部での描画パ
ターンのずれを生じるという問題があった。In the conventional technique described above, a correction coefficient for deflection distortion is determined before drawing, and the same correction coefficient is used during drawing. Therefore, when there is a change in deflection strain over time, there is a problem in that misalignment between layers occurs in the field periphery or deviation in the drawing pattern occurs in the field connection area.
本発明の目的は位置合せマークを偏向中心で検出するス
テージ移動形マーク検出法においても、偏向歪の経時変
化による層問合せずれおよびフィールド接続ずれの少な
い電子描画方法と位置合せマークの構造を提供すること
にある。An object of the present invention is to provide an electronic drawing method and an alignment mark structure that reduce layer interrogation deviations and field connection deviations due to changes in deflection strain over time, even in a stage-moving mark detection method in which alignment marks are detected at the center of deflection. There is a particular thing.
上記の目的を達成するために、まず、電子線描画の前に
被描画試料外に作られた偏向歪補正用のマーク(標準マ
ークと称する)を精密に測定し偏向歪補正係数を求める
0次にパターン描画を行う前に、被描画試料内の少なく
とも1つのフィールド内に配置された位置合せマークを
電子ビームを偏向することで検出して、先に求めた偏向
歪の1部を修正して電子線描画を行う。In order to achieve the above objective, first, before electron beam lithography, marks for deflection distortion correction made outside the sample to be drawn (referred to as standard marks) are precisely measured and the zero-order distortion correction coefficient is determined. Before pattern writing is performed, a part of the previously determined deflection distortion is corrected by detecting alignment marks placed in at least one field within the sample to be drawn by deflecting the electron beam. Perform electron beam drawing.
偏向歪の補正係数を前述した標準マークの測定によって
求めることは数lO秒〜数分の時間を要するため、経時
変化のために描画途中で度々行うことはスループットを
大きく低下するため不利である。しかし本発明者らの実
験によれば、偏向歪の経時的変化は偏向歪補正係数の全
てについて大きい訳でないことが判明した。経時変化が
大きいのは前述した式(1)で言えば0次の項と1次の
項、aoe a1* any bow b工eb2であ
るeこのうちシフト量項ao 、boが最も変化が大き
いがこれはステージ移動マーク検出法においてもチップ
周辺の4個のマークを検出することで補正される。Determining the deflection distortion correction coefficient by measuring the standard mark described above requires a time of several 10 seconds to several minutes, so it is disadvantageous to perform this frequently during writing due to changes over time, as this will greatly reduce the throughput. However, according to experiments conducted by the present inventors, it has been found that changes in deflection distortion over time are not large for all deflection distortion correction coefficients. In Equation (1) mentioned above, the factors that have large changes over time are the zero-order term and the first-order term, aoe a1* any bow b, eb2. Of these, the shift amount terms ao and bo have the largest changes. This can also be corrected in the stage moving mark detection method by detecting four marks around the chip.
次に大きい変化を持つのはゲイン環、at 、 b2と
傾れの項ax 、bxである。従って各チップ毎(又は
数チップ毎)にステージ移動マーク検出法によってマー
ク検出を行い位置座標の判ったマークをフィールド周辺
に配置し、電子線を偏向して検出することで1次の項a
1.ax、b1.bxを求めることができる。このマー
ク検出に要する時間は数秒であるため、1ウエハの描画
途中で行ってもスループットを低下させる心配はない、
従って描画前に求めた精密な補正係数のうち低次の項の
みを被描画試料内のマークの測定で修正することによっ
て偏向歪の経時変化によるフィールド接続精度、眉間位
置合せ精度の低下は大きく改善される。The next largest changes are in the gain ring, at and b2, and the slope terms ax and bx. Therefore, by detecting marks for each chip (or every few chips) using the stage movement mark detection method, placing marks with known position coordinates around the field, and detecting them by deflecting the electron beam, the first-order term a
1. ax, b1. bx can be found. Since the time required for this mark detection is several seconds, there is no need to worry about reducing throughput even if it is performed in the middle of writing one wafer.
Therefore, by correcting only the low-order terms of the precise correction coefficients determined before drawing by measuring the marks in the sample to be drawn, the decline in field connection accuracy and glabella alignment accuracy due to changes in deflection distortion over time can be greatly improved. be done.
以下本発明の一実施例を第1図を用いて説明する。第1
図(a)は本発明の電子線描画法を適用した時のウェル
内のチップ配列を示すもので、ウェハ21にはチップ周
辺に位置合せ用マーク(チップマーク)を有するチップ
Aと300μmDの大きさのウェハマークを有するチッ
プBが配置されている。第1図(b)はチップ内のチッ
プマークの配置を示す図である。1チツプの大きさは1
10でありチップの4隅にチップマーク24゜25.2
6,27が置かれている。ここで用いた電子線描画装置
のフィールドサイズ(ステージを移動しなで描画できる
範囲)は510であるので第1図(b)の2つの破線Q
1とQ2で示すフィールド境界を持つ4つのフィールド
f5.f6゜f7.f8に分割されて描画される。その
うちの1つのフィールドf5に偏向歪補正用のマーク2
8.29が配置されている。An embodiment of the present invention will be described below with reference to FIG. 1st
Figure (a) shows the chip arrangement in the well when the electron beam lithography method of the present invention is applied.The wafer 21 has a chip A with an alignment mark (chip mark) around the chip and a chip A with a size of 300 μmD. A chip B having a wafer mark of 1 is placed. FIG. 1(b) is a diagram showing the arrangement of chip marks within the chip. The size of 1 chip is 1
10, with chip marks 24°25.2 on the four corners of the chip.
6, 27 are placed. The field size (the range that can be drawn by moving the stage) of the electron beam lithography system used here is 510, so the two broken lines Q in Fig. 1(b)
Four fields f5. with field boundaries denoted 1 and Q2. f6゜f7. It is divided into f8 and drawn. Mark 2 for deflection distortion correction is placed in one field f5.
8.29 is placed.
本実施例ではまず第1図(Q)のように5腸口のフィー
ルド30内の位置が予め測定されている25個の十字彫
金マーク31を電子線を偏向することにより検出して、
偏向歪量を測定し、偏向歪補正係数を最小二乗法により
求めた。この金マーク列はステージの一部でウェハが装
置されない領域に設置されたものである0次にウェハ2
1がステージに装着された。まずウェハ左右に配置され
た2個のウェハマーク22.23を検出することによっ
てウェハのステージ移動方向に対する回転角とチップ間
の距離が測定された0次にチップマークと偏向歪補正用
マークの位置検出が行われた。In this embodiment, first, as shown in FIG. 1(Q), 25 cross-engraved marks 31 whose positions in the field 30 of the 5th intestine orifice have been measured in advance are detected by deflecting an electron beam.
The amount of deflection distortion was measured, and the deflection distortion correction coefficient was determined by the least squares method. This gold mark row is a part of the stage where the wafer is not placed.
1 was attached to the stage. First, by detecting the two wafer marks 22 and 23 placed on the left and right sides of the wafer, the rotation angle of the wafer with respect to the stage movement direction and the distance between the chips are measured.The positions of the zero-order chip marks and the deflection distortion correction mark. A detection has been made.
これにはステージを移動することによって各マーク24
,28,25,26,27,29を電子線の偏向中心に
移動し電子線で検出することにより行う、この時のステ
ージの座標と電子線による検出位置から各マーク24〜
29の正確な座標を知ることができる0次にステージを
第1図(b)に示した第1のフィールドf5の中心に移
動し電子ビームを偏向してマーク28.24.29を検
出して偏向歪の補正係数の一部を修正した。しかる後チ
ップAのパターンが描画された。この補正係数の修正の
ためのマーク検出は描画開始直後は頻度を多くするため
1ウニ八につき2回行われ、2枚描画され、3枚目から
は1ウエハにつき1回だ第1表
補正係数初期値
け行われ連続して5枚のウェハが描画された。This is done by moving the stage to each mark 24
, 28, 25, 26, 27, 29 are moved to the center of deflection of the electron beam and detected by the electron beam. From the coordinates of the stage at this time and the detection position by the electron beam, each mark 24-
The exact coordinates of 29 can be found by moving the stage to the center of the first field f5 shown in FIG. 1(b) and deflecting the electron beam to detect marks 28, 24, and 29. Some correction coefficients for deflection distortion have been corrected. After that, the pattern of chip A was drawn. Mark detection for correcting this correction coefficient is performed twice per 1 wafer immediately after the start of writing to increase the frequency, and 2 sheets are written, and from the third sheet onwards, it is performed once per wafer.Table 1 Correction Coefficients Initial pricing was carried out and five wafers were drawn in succession.
5枚の描画に先立って求められた偏向歪の補正係数を表
1に描画途中で修正した係数を第2表に示す、第1表で
式(2)は偏向歪補正のための計算式ao””asとb
o=beが補正係数である。このうち描画途中で修正し
た係数はaOs a is a 21bo、bx、bl
の6個である。この6個の係数の修正により層間の合せ
精度が従来3σ二O,15μmであったものが3σ二〇
、09μmに向上した。Table 1 shows the correction coefficients for deflection distortion obtained before drawing five images, and Table 2 shows the coefficients corrected during the drawing process. ""as and b
o=be is a correction coefficient. Among these, the coefficients modified during drawing are aOs a is a 21bo, bx, bl
There are 6 pieces. By modifying these six coefficients, the alignment accuracy between layers was improved from the conventional 3σ20.15 μm to 3σ20.09 μm.
尚、本実施例では各チップに偏向歪補正係数の修正のた
めのマークを設置したが以上のような変更も可能である
。In this embodiment, a mark for correcting the deflection distortion correction coefficient is provided on each chip, but the above-mentioned changes are also possible.
(i)ウェハマークの設置されたチップのみにイ自正用
マークをffflL、1ウエハに1回だけ補正係数の修
正を行う。(i) A self-correction mark is attached only to the chip on which the wafer mark is installed, and the correction coefficient is corrected only once per wafer.
(五)第1図(b)のチップマーク241個だけの検出
だけで補正係数の修正を行う、すなわちチップマーク検
出の時はマーク24を偏向中心となるようにステージを
移動させるが、偏向歪補正の時はフィールド周辺となる
ようにステージを移動してから電子線による検出を行う
、この場合には新たなマークを用意することなく補正係
数の修正が行える。(5) The correction coefficient is corrected by detecting only the 241 chip marks shown in FIG. During correction, the stage is moved to the periphery of the field and then detection is performed using an electron beam. In this case, correction coefficients can be corrected without preparing new marks.
以上説明したごとく、本発明によれば、電子描画途中の
簡単なマーク検出によって、偏向歪の経時変化を補正す
ることが可能となるため、偏向歪の補正頻度を減らすこ
とができるためスループットが向上し、かつ層間合せの
精度、フィールド接続精度を向上することができる。As explained above, according to the present invention, it is possible to correct the change in deflection distortion over time by simple mark detection during electronic drawing, so the frequency of correction of deflection distortion can be reduced, thereby improving throughput. In addition, the accuracy of layer alignment and field connection accuracy can be improved.
第1図は本発明の一実施例を示す図であり、(a)はウ
ェハ内のチップ記動を示す図、(b)はチップ内のマー
ク配列を示す図、(c)は偏向歪補正のための全十字マ
ーク列を示す図、第2図は従来のステージ停止マーク検
出法を示す図、第3図は従来のステージ移動マーク検出
法を示す図。
第4図は偏向歪補正係数を求めるための9点の全十字マ
ーク列を示す図である。
1・・・1チツプが1フイールドで構成されたチップ。FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) is a diagram showing chip writing in a wafer, (b) is a diagram showing a mark arrangement in a chip, and (c) is a diagram showing deflection distortion correction. FIG. 2 is a diagram showing a conventional stage stop mark detection method, and FIG. 3 is a diagram showing a conventional stage movement mark detection method. FIG. 4 is a diagram showing a complete string of nine cross marks for determining the deflection distortion correction coefficient. 1...A chip in which one chip consists of one field.
Claims (1)
画装置において、ステージを移動しないで描画できる範
囲をフィールドとするとき、被描画試料外に設置された
マークを用いてフィールド内の偏向歪量を測定し、偏向
歪補正のための複数の係数を求めた後、被描画試料内の
フィールド周辺に配置されたマークを電子線を偏向して
位置検出した結果を用いて上記係数のうち一部を修正し
て描画を行うことを特徴とする電子線描画方法。1. In an electron beam lithography system that performs drawing with the stage stopped, when the field is the range that can be drawn without moving the stage, the amount of deflection distortion in the field is determined using marks placed outside the sample to be drawn. After measuring several coefficients for correction of deflection distortion, some of the above coefficients are determined using the results of detecting the positions of marks placed around the field in the sample to be drawn by deflecting the electron beam. An electron beam drawing method characterized by performing drawing by correcting the .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62294114A JPH01136332A (en) | 1987-11-24 | 1987-11-24 | Electron beam lithography method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62294114A JPH01136332A (en) | 1987-11-24 | 1987-11-24 | Electron beam lithography method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01136332A true JPH01136332A (en) | 1989-05-29 |
Family
ID=17803471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62294114A Pending JPH01136332A (en) | 1987-11-24 | 1987-11-24 | Electron beam lithography method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01136332A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07142351A (en) * | 1993-11-17 | 1995-06-02 | Nec Corp | Electron beam exposure apparatus and electron beam deflection method |
JPH07142352A (en) * | 1993-11-17 | 1995-06-02 | Nec Corp | Electron beam lithography equipment and electron beam lithographic method |
US5757015A (en) * | 1995-06-08 | 1998-05-26 | Fujitsu Limited | Charged-particle-beam exposure device and charged-particle-beam exposure method |
JP2006114599A (en) * | 2004-10-13 | 2006-04-27 | Toshiba Corp | Correction apparatus, correction method, correction program, and semiconductor device manufacturing method |
-
1987
- 1987-11-24 JP JP62294114A patent/JPH01136332A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07142351A (en) * | 1993-11-17 | 1995-06-02 | Nec Corp | Electron beam exposure apparatus and electron beam deflection method |
JPH07142352A (en) * | 1993-11-17 | 1995-06-02 | Nec Corp | Electron beam lithography equipment and electron beam lithographic method |
US5757015A (en) * | 1995-06-08 | 1998-05-26 | Fujitsu Limited | Charged-particle-beam exposure device and charged-particle-beam exposure method |
US5969365A (en) * | 1995-06-08 | 1999-10-19 | Fujitsu Limited | Charged-particle-beam exposure device and charged-particle-beam exposure method |
US6242751B1 (en) | 1995-06-08 | 2001-06-05 | Fujitsu Limited | Charged-particle-beam exposure device and charged-particle-beam exposure method |
US6420700B2 (en) | 1995-06-08 | 2002-07-16 | Fujitsu Limited | Charged-particle-beam exposure device and charged-particle-beam exposure method |
JP2006114599A (en) * | 2004-10-13 | 2006-04-27 | Toshiba Corp | Correction apparatus, correction method, correction program, and semiconductor device manufacturing method |
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