JPH01128447A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize flattening without steps which cause constriction or cutting off when forming a metal wiring layer, by carrying out etchback by making plasma-etching on the entire surface of an interlayer insulation layer provided with a via hole. CONSTITUTION:After wiring layers 241, 242 of a primary layer are formed, an interlayer insulation layer 25 is formed on the entire surface of a semiconductor substrate 21 including the wiring layers 241, 242. Then a via hole 27 reaching the wiring layer 241 is formed by etching corresponding to the wiring layer 241 on the interlayer insulation layer 25 which has surface irregularities. The surface of the interlayer insulation layer 25 is entirely etched by reactive ion etching. By this etching process, tapered surface 281, 282,... which continue in the inclines, and a tapered surface 29 of inner circumference whose diameter is larger at the opening are shaped. A wiring layer 30 of a secondary layer is formed on the surface of the interlayer insulation layer 25 thus connecting a wiring layers 241 and 30 through the via hole 27 which has a tapered surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention is directed to a semiconductor device manufacturing method that improves the planarization of interlayer n-layers required in multilayer wiring structures such as LSIs, and improves the means for forming via holes. Regarding.

[Prior Art] Semiconductor devices such as LSIs have a multilayer wiring structure. This multilayer wiring structure is configured such that a plurality of wiring layers are formed on the surface of a semiconductor substrate on which circuit elements are formed, with interlayer insulating layers interposed between each layer. Appropriate electrical connections are made between the wiring layers and between the terminal portions of the circuit elements of the semiconductor substrate and the wiring layers. Electrical connection means between each wiring layer and other layer parts is achieved by forming a via hole penetrating the interlayer insulating layer and burying a conductor in the via hole to connect wiring layers of different layers. Alternatively, the wiring layer and the terminal portion on the upper part of the semiconductor substrate are electrically connected.

The interlayer insulating layer is formed of, for example, an oxide film such as SiO2 or PSG formed by atmospheric pressure CVD, or an oxide film formed by plasma CVD on a semiconductor substrate on which a surface wiring layer is formed. However, a protrusion corresponding to the FA layer formed on the semiconductor substrate appears in the surface shape of the interlayer insulating layer, and the surface shape of the interlayer insulating layer inevitably becomes uneven with steps. It becomes a severe state. Therefore, if another wiring layer is formed on the surface of the interlayer insulating layer having such unevenness, constrictions or breaks will occur in the wiring layer at the stepped portions of the unevenness, and this wiring layer Ia will reliability will no longer be obtained.

Therefore, in order to obtain a multilayer wiring structure, it is necessary to planarize the surface shape of the interlayer insulating layer and then form a metal wiring layer on the interlayer insulating layer.

Possible means for flattening the interlayer insulating layer by eliminating its unevenness include, for example, applying SOG (aspect glass), applying an organic resin, etc. The insulating layer has this F! A penetrating via hole is formed corresponding to a portion of the wiring layer under the inter-XJ insulating layer, and a metal wiring layer is formed roughly corresponding to the via hole portion. However, such means not only require a lot of effort for planarization, but also make it difficult to miniaturize the via hole. In addition, in the case of miniaturized via holes,
In order to prevent breakage, etc., the inner peripheral surface is formed into a tapered shape, but a process for forming the tapered shape must be added.

As an advantageous means for miniaturization, it is known that the surface of the interlayer insulating layer is flattened by etchback using dry etching.

FIG. 6 shows an example of such a flattening means, which is connected to the surface of the semiconductor substrate 11 as appropriate to lead-out terminals of circuit elements formed on this substrate 11.
A surface wiring layer 12 made of metal such as aluminum is formed, and an interlayer insulating layer 13 is further formed on the surface of the semiconductor substrate 11 so as to include the wiring layer 12 portion. In this case, on the surface of the interlayer insulating layer 13,
The shape of the wiring layer 12 protruding from the surface of the semiconductor substrate 11 appears as it is, resulting in an uneven shape having steps. Therefore, if a metal wiring layer is formed on this living room insulating layer 13 as it is, there is a high risk that the wiring layer will be constricted or broken at the step portion.

Therefore, the surface of the interlayer insulating layer 13 having the uneven surface is smoothed, and for this purpose, as shown in FIG. A certain resist 14 is applied to form a flat surface.Then, the entire surface is etched by reactive ion etching to the position shown by the chain line in the figure, and the interlayer insulating layer 13 is formed as shown in FIG. 6(B). A via hole 1 is formed in this interlayer insulating layer 13 so that the surface of the interlayer insulating layer 13 is flattened.
51.152.

However, such a method requires a step of resist coating, which inevitably increases the number of steps, and further requires a step of removing the resist remaining after etching back. Furthermore, since the wiring layer 12 is present on the semiconductor substrate 11, the film thickness t1 of the wiring layer 12 portion and the film thickness t2 of the other portions are
A difference occurs, and mIv distribution occurs in the interlayer insulating layer 13. Therefore, via holes 151 and 152
There is a difference in depth between the lines, which lowers the yield of the wiring process and poses a problem in improving reliability.

[Problems to be Solved by the Invention] This invention was made in view of the above points, and it is possible to form a surface of an interlayer insulating layer having irregularities and a metal wiring layer on the interlayer insulating layer in one simple step. When it is formed, it is flattened so that no constrictions or breaks occur in the first layer of interconnection Ii, and the interlayer insulating layer is made to have no film thickness distribution, so that the inner circumferential surface is roughly tapered with via holes. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a multilayer interconnection structure, which can be formed simultaneously in a simple process and with high reliability.

[Means for Solving the Problems] That is, in the method for manufacturing a semiconductor according to the present invention, a via hole whose inner circumferential surface is vertical is formed in an interlayer insulating layer whose surface is uneven. It forms
The surface of the interlayer insulating layer in which the via hole is formed is completely etched back by plasma etching.

[Function] According to the method for manufacturing a semiconductor device as described above, a via hole with a vertical inner circumferential surface is formed, and the glabellar insulating layer, which has an uneven surface, is etched back from the surface. Become. In this case, the step part on the surface of the interlayer insulating layer becomes continuous with an inclined surface, and the inner peripheral surface of the via hole also becomes a tapered surface, and the surface of the interlayer insulating layer becomes a continuous sloped surface. When formed, it is in a flattened state without any stepped portions that may cause constrictions or breaks.

Further, the film thickness distribution also becomes -like, and a great effect is exerted on improving the reliability of a semiconductor device having a multilayer wiring structure.

[Embodiments of the invention] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIGS. 1 to 4 show the steps of forming insulation layers and via holes in the multilayer wiring process in sequence. First, as shown in FIG. A surface wiring layer 22 is provided on the surface of the semiconductor substrate 21 to be connected to the circuit elements as appropriate.
is made of polysilicon, for example. The surface wiring layer 2 is formed on the surface of this semiconductor substrate 21.
For example, the insulating layer 2 by 5102
3 is formed, and first layer wiring layers 241 and 242 are formed on this insulation 1ii23. The wiring Fm241, 242 is connected to the surface wiring [I23] or the lead-out terminal portion of the circuit element formed on the substrate 21 as appropriate.

Once the first wiring layers 241 and 242 are formed in this manner, the interlayer insulating layer 25 is formed over the entire surface of the semiconductor substrate 21, including the wiring layers 241 and 242. In this case, the surface of this interlayer insulating layer 25 is connected to the surface wiring layer 23 formed on the surface of the semiconductor substrate 21, and further to the surface wiring layer 23 formed on the surface of the semiconductor substrate 21.
The layer arrangement is made into an uneven surface having stepped portions 261, 262, . . . corresponding to the shape of the fit layers 241, 242.

Then, as shown in FIG. 2, for example, a wiring layer 2
A via hole 27 is formed by etching to correspond to the portion 41 and reach the interconnect layer 241. In this case, the inner peripheral surface of this via hole 27 is formed in a vertical state.

Once the via hole 27 is formed in this way, the entire surface of the living room insulating layer 25 is etched by reactive ion etching, and as shown in FIG. Tapered surfaces 281, 282, . . . so that the steps 261, 262, .
...and at the same time, Via Hall 27
The inner peripheral surface is also formed into a tapered surface 29 whose diameter increases in the frontage direction.

Then, on the surface of this interlayer insulating layer 25, a second wiring layer 30 is formed as shown in FIG. 241 and 30 are electrically connected.

In this case, the wiring wA30 is formed along the tapered surfaces 281, 282, . . . on the interlayer insulating layer 25, and the wiring layer 30 is bound or broken. This effectively suppresses this, making it possible to provide a highly reliable FiI layer.

Here, the above-mentioned reactive ion etching is performed by, for example, a magnetron device 41 as shown in FIG.

This magnetron device 41 constitutes a reactive ion etching device, and as shown in FIG. 2, the inside of this device 41 has an uneven surface with steps and a via hole 27. interlayer insulating layer 25
A semiconductor substrate 21 on which is formed is set. A reaction gas made of, for example, C2Fs can be introduced into the inside of this device 41.

The magnetron device 41 includes electrodes 421 and 42.
2 is set, and these electrodes 421 and 42
For example, 500 to 1
000W of high frequency power is applied. Further, this magnetron device 41 includes an electromagnetic magnet 44.
is set, and a magnetic field of about 800 Gauss is set inside the device 41 by this magnet 44.

The interlayer insulating layer 2 formed on the surface of the semiconductor substrate 21 by the reactive ion etching apparatus configured as described above.
When the surface of No. 5 is etched for about 30 seconds to 1 minute at an etching pressure of several Pa to 30 Pa, for example, the stepped portion is relaxed and becomes continuous with the Taber surface as shown in Figure 3. . The angle of this Taber surface may be appropriately set within the range of 45 to 70 degrees.

Reactive ion etching using such a magnetron device has the characteristic that the interlayer insulating layer 25 is etched in an extremely short time, compared to, for example, ordinary reactive ion etching. , 1/1
0. It can be made into a state of ~1/60 or less. Moreover, ordinary reactive ion etching cannot achieve flattening that alleviates the stepped portions as described above.

In a reactive ion etching device using a magnetron device, unsaturated fluorocarbons such as CH2 are easily generated in the plasma by magnetron discharge. Therefore, a polymer having a composition of CX FY is efficiently generated, and the generated polymer adheres to the surface of the inter-bag insulation WJ25. The amount of polymer deposited is determined by the competitive reaction balance of "eratingle deposition."

This competitive reaction balance can be varied depending on the etching conditions, and therefore the etching shape can be controlled by the etching conditions.

The etching reaction of reactive ion etching performed under magnetron discharge is determined by the ratio rV1/V2-rJ of the deposition rate V-1 of the polymer deposited on the surface of the interlayer insulating layer 25 and the etching rate V2 of the polymer. , and the ratio rV2 /V3-RJ of the etching rate V2 of the polymer and the etching rate 3 of the interlayer insulating layer 25. As a result of various experiments, rR>1J and "
When the condition r<IJ is satisfied, the steps 261, 262, . . . of the interlayer insulating layer 25 become the Taber surface 281,
282, . . . , and it was confirmed that the inner circumferential surface of the vertical via hole 27 became a tapered surface 29.

That is, in order to etch the stepped portion to form an inclined surface, the following conditions should be satisfied.

a) The polymer production rate is high.

b) The etching rate of the polymer is high.

C) The etching rate of the insulating layer is high.

d) r<1 and R>1.

In order to effectively form a polymer layer on the surface of the interlayer insulating layer, it is effective to set an insulating plate made of polyimide or Teflon, for example, on the electrode on which the semiconductor substrate 21 is set.

Specific examples are shown below.

Example 1 In the state shown in FIG. 1, the interlayer insulating layer 25 is made of a 1.3 μm thick plasma nitride film formed by a plasma CVD apparatus. And this Kurakai insulation WJ2
A resist is applied to the surface of the substrate 5, a resist pattern corresponding to the via hole is formed by a photo process, and a via hole 27 is formed in CF4 gas using a reactive ion etching device as shown in FIG. In this case, the inner diameter of the via hole 27 is 2 μm. Then, the resist is peeled off and removed.

Once the via hole 27 is opened in the interlayer insulation 1125 in this way, using a magnetron reactive ion etching device, CHF3 gas is used as the reaction gas, the flow rate is 50 QC/min, the RF power is 600 W, and the reaction gas pressure is set. Etching was performed for 3 minutes at an etching rate of about 1700 people/min under conditions of 13 Pa. As a result, as shown in FIG. 3, the stepped portion became an inclined surface, and the inner circumferential surface of the via hole became a tapered surface. At this time, the inclination angle of the portion corresponding to the stepped portion was 40°, and the angle of the tapered surface 29 of the via hole 27 was 606°.

: UUW The same structure as in Example 1 is used, and the interlayer 1i layer 25 is made of PS.
A via hole 2 with an inner diameter of 1 μm is formed in this interlayer insulating layer 25.
7 was formed. Then, 50Cc of reaction gas CHF3
Etching was performed for 70 seconds under the conditions of RF power of 600 W and reaction gas pressure of 6 Pa. As a result, the inclination angle of the step part is 40 degrees, and the taper surface of the via hole 27 is 6
It became 5°.

As shown in each of the above embodiments, the stepped portion has a rounded shape that resembles an inclined surface, and as a means for performing a high-speed etching operation, the magnetic field described in the above embodiments etc. is used. This is only possible with reactive etching. The etching conditions in this case are as shown below, for example.

[Insulating film material: Plasma oxidation WA] Reactive gas (additive gas) CF+50t-1z5 or CHF350 or C2F650 Reaction pressure 6~13 R "Power 400~aoow [Insulating mU material: CVD-8i 02] Reactive gas (additive gas) 02 Fs 50H25 or CHFa 50 Reaction pressure 6-20 RFt<r)-400-600W [Insulating film material: CVD-PSG] Reaction gas (additional gas) 02 F550H23 or HF150 Reaction pressure 6-20 RF power 400-600W [Insulating film Material: CVD-BPSG] Reaction gas C2F6501-123 or Cl-IF550 Reaction pressure 6 to 20 RF power 400 to 600 W [Effects of the Invention] As described above, according to the method for manufacturing a semiconductor device according to the present invention, unevenness is formed on the surface. By performing reactive ion etching only once while forming a via hole with a wall perpendicular to the interlayer insulating layer in which the surface is uneven, the stepped portion forming the surface unevenness is made into a continuous sloped surface, In addition, the inner circumferential surface of the via hole becomes a tapered surface.In other words, by a very simple process, the uneven surface of the interlayer insulating layer can be made into a uniform layer thickness distribution.
This results in a flat surface suitable for construction, and at the same time, a tapered surface on the inner circumferential surface of the via hole. Therefore, not only the manufacturing process is greatly simplified, but also a multilayer wiring structure with sufficiently high reliability can be obtained.

[Brief explanation of the drawing]

1 to 4 are diagrams sequentially showing the cross-sectional structure of a semiconductor device in each step in a semiconductor manufacturing method according to an embodiment of the present invention, and FIG. 5 is a diagram showing the magnetron reactivity used in the above manufacturing process. FIGS. 6A and 6B are diagrams showing a cross-sectional structure of a semiconductor device to sequentially explain the conventional manufacturing process. 21... Semiconductor substrate, 22... Surface electrode, 23...
- Absolute II layer, 241.242... 1st layer wiring layer, 2
5... Interlayer insulating layer, 261.262,... Step,
27...Via hall, 281.282,...29
...Taber surface, 30...2nd layer wiring layer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 44

Claims (2)

[Claims] (1) A step of forming an insulating layer on the surface of the semiconductor substrate on which circuit elements are formed, a step of forming a vertical via hole in the insulating layer by etching, and a step of forming a vertical via hole in this step. plasma etching the surface of the insulating layer including the inner periphery of the via hole, and by this plasma etching step, the stepped portion of the surface of the insulating layer is continuous with an inclined surface. In addition to ensuring that
A method of manufacturing a semiconductor device, characterized in that the inner circumferential surface of the vertical via hole is a tapered surface. (2) The method of manufacturing a semiconductor device according to claim 1, wherein in the plasma etching step, the insulating layer is directly etched by magnetron reactive ion etching.