JPH01115127A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01115127A
JPH01115127A JP62274564A JP27456487A JPH01115127A JP H01115127 A JPH01115127 A JP H01115127A JP 62274564 A JP62274564 A JP 62274564A JP 27456487 A JP27456487 A JP 27456487A JP H01115127 A JPH01115127 A JP H01115127A
Authority
JP
Japan
Prior art keywords
semiconductor chip
section
frame
solder
peripheral side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62274564A
Other languages
Japanese (ja)
Inventor
Toshihiro Nakajima
中嶋　利廣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62274564A priority Critical patent/JPH01115127A/en
Publication of JPH01115127A publication Critical patent/JPH01115127A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent adhesion onto the peripheral side section of a semiconductor chip of solder by forming a section, which is positioned on the side nearer to the center than the peripheral section of the rear of a semiconductor chip in a frame and faced oppositely to passivation and metallizing sections, in height higher than a section oppositely faced to the peripheral side section of the semiconductor chip. CONSTITUTION:A section positioned on the side nearer to the center than the peripheral section of the rear of a semiconductor chip 1 in a frame 11 and oppositely faced to a passivation 2 and a metallizing section 16 is shaped in height higher than a section oppositely faced to the peripheral side section of the semiconductor chip 1. Consequently, excess solder flows out to the section oppositely faced to the peripheral side section of the semiconductor chip 1 in the frame 11, and solder is held between the metallizing section 16 in the semiconductor chip 1 and the section oppositely faced to the metallizing section 16 in the frame 11. Accordingly, solder 4 does not creep up along a mesa groove 1c in the semiconductor chip 1, thus improving the reliability of the semiconductor chip 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は両面メサ形半導体チップがフレームに半田付け
されてなる半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a double-sided mesa-shaped semiconductor chip is soldered to a frame.

〔従来の技術〕[Conventional technology]

従来、中１カデバイスのトチイアツク、サイリスタ等の
半導体装置に使用される両面メサ形半導体チップは、裏
面にメタライズ部が形成され、このメタライズ部とフレ
ームとを半田付けすることによってフレーム上に固着さ
れていた。これを図によって説明すると、第２図は従来
の半導体装置を示す側断面図で、同図において、１は半
導体チップで、この半導体チップ１は表面に表面端子１
ａを有し、裏面にメタライズ部１ｂが形成されており、
かつ周側部にはメサ溝１Ｃが形成され、このメサ溝を覆
うようにガラスパッシベーション２が“汲けられている
。３はフレームで、このフレーム３は前記半導体チップ
１が固着されるダイパッド部３ａと、他の装置へ接続さ
れる外部端子部３ｂとから構成されている。４は前記フ
レーム３のダイパッド部３ａ上に半導体チップ１を固着
させるための半田、５は半導体チップ１の表面電極１ａ
とフレーム３の外部端子部３ｂとを接続するためのアル
ミワイヤで、超音波ボンディングによって接合されてい
る。６は封止用樹脂としてのエポキシ樹脂である。Conventionally, double-sided mesa-shaped semiconductor chips used in semiconductor devices such as power supplies and thyristors for middle-class devices have a metallized part formed on the back side, and are fixed on the frame by soldering the metallized part and the frame. was. To explain this with the help of drawings, FIG. 2 is a side sectional view showing a conventional semiconductor device. In the same figure, 1 is a semiconductor chip, and this semiconductor chip 1 has surface terminals on its surface.
a, and a metallized portion 1b is formed on the back surface,
A mesa groove 1C is formed on the circumferential side, and a glass passivation 2 is scooped out to cover the mesa groove. 3 is a frame, and this frame 3 is a die pad portion to which the semiconductor chip 1 is fixed. 3a and an external terminal portion 3b connected to other devices. 4 is solder for fixing the semiconductor chip 1 on the die pad portion 3a of the frame 3, and 5 is a surface electrode of the semiconductor chip 1. 1a
This is an aluminum wire for connecting the external terminal portion 3b of the frame 3 and is joined by ultrasonic bonding. 6 is an epoxy resin as a sealing resin.

このように構成された半導体装置を組立てるにハ、先ず
、フレーム３のダイパッド部３ａ上に半田片（図示せず
）を載置し、この半田片の上にメタライズ部１ｂが対応
するように半導体チップ１を載置させ、次いで、３００
℃〜４００℃に加熱された熱板上にフレーム３を移載さ
せ、半田片を溶融させることによってダイボンディング
する。しかる後、アルミワイヤ５をワイヤボンディング
し、エポキシ樹脂６により封止することによって組立て
が完了する。To assemble the semiconductor device configured in this way, first, place a solder piece (not shown) on the die pad part 3a of the frame 3, and place the semiconductor so that the metallized part 1b corresponds to the solder piece. Place chip 1, then 300
The frame 3 is transferred onto a hot plate heated to 400°C to 400°C, and die bonding is performed by melting the solder pieces. Thereafter, the aluminum wires 5 are wire-bonded and the assembly is completed by sealing with the epoxy resin 6.

なお、この半導体装置においては、半導体チップ１がフ
レーム３上に固着された際に、メタライズ部１ｂとダイ
パッド部３ａとの間の半田４の厚みが断続通電寿命サイ
クルの関係から３０μｍ以上になるよう定められている
。In this semiconductor device, when the semiconductor chip 1 is fixed on the frame 3, the thickness of the solder 4 between the metallized portion 1b and the die pad portion 3a is set to be 30 μm or more due to the intermittent current life cycle. It is determined.

また、この半導体装置に使用される半導体チップ１は、
ガラスパッシベーション２が施されたものの他ニ、ガラ
スパッシベーション２の代わりに８　ｉ（ｈ膜が形成さ
れたものもある。Moreover, the semiconductor chip 1 used in this semiconductor device is
In addition to those with glass passivation 2, there are also those in which an 8i (h film is formed instead of glass passivation 2).

〔発明が解決しようとする問題点〕 しかるに、このように構成された従来の半導体装置にお
いては、半田４の厚み寸法が小さくならないように半田
４の量を若干多くすると、第２図に示すように、半田４
が半導体チップ１のメサ溝１Ｃに泊ってはい上がるごと
く、盛シ上が１４ａが生じ、この盛シ上がＦ）４ａのた
めに半導体チップ１の信頼性が低下するという問題があ
った。また、この盛シ上がシのために半田を必要以上に
要し、このため製造コストが高くなっていた。[Problems to be Solved by the Invention] However, in the conventional semiconductor device configured as described above, if the amount of solder 4 is slightly increased so as not to reduce the thickness of solder 4, as shown in FIG. To, solder 4
There was a problem in that the reliability of the semiconductor chip 1 was lowered because the embossment 14a occurred as if it were crawling up into the mesa groove 1C of the semiconductor chip 1, and this embossment was F)4a. Further, this embossed surface requires more solder than necessary, which increases the manufacturing cost.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係る半導体装置は、フレームにおける半導体チ
ップの裏面の周縁部より中心側であってパッシベーショ
ンおよびメタライズ部と対向する部位を、半導体チップ
の周側部と対向する部位より高く形成したものである。In the semiconductor device according to the present invention, the part of the frame that is closer to the center than the peripheral edge of the back surface of the semiconductor chip and that faces the passivation and metallized parts is formed higher than the part that faces the peripheral side of the semiconductor chip. .

〔作用〕[Effect]

フレームにおける半導体チップの周側部と対向する部位
に余分な半田が流れ出し、半導体チップのメタライズ部
とフレームにおけるメタライズ部と対向する部位との間
に半田が保持される。Excess solder flows out to a portion of the frame that faces the peripheral side of the semiconductor chip, and the solder is held between the metallized portion of the semiconductor chip and the portion of the frame that faces the metallized portion.

〔実施例〕〔Example〕

以下、その構成等を図に示す実施例により詳細に説明す
る。第１図は本発明に係る半導体装置を示す側断面図で
、同図において第２図で示した部材と同一もしくは同等
部材については同一符号を付し、ここにおいて詳細な説
明は省略する。同図において、１１は本発明の半導体装
置に使用されるフレームで、このフレーム１１は半導体
チップ１が固着されるダイパッド部１１ａと、他の装置
へ接続される外部端子部１１ｂとからなシ、このダイパ
ッド１１ａには、半導体チップ１の周側部に形成された
メサ溝１Ｃと対向する部位に凹部１１Ｃを形成すること
により、半導体チップの裏面の周縁部より中心側であっ
てパッシベーション２およびメタライズ部１ｂと対向す
る部位に凸部１１ｄが形成されている。すなわち、この
凸部１１ｄの上面は、半導体チップ１のメタライズ部１
ｂより大きく、かつ半導体チップ１の裏面全体より小さ
く形成されることになシ、凸部１１ｄの周縁部分は、半
導体チップ１の裏面に形成されたパッシベーション２と
対向することになる。また、この凸部１１ｄの高さ、換
言すれば凹部１１Ｃの深さはエツチング等により約５０
μｍ程度に形成されている。Hereinafter, its configuration and the like will be explained in detail with reference to embodiments shown in the drawings. FIG. 1 is a side cross-sectional view showing a semiconductor device according to the present invention. In the figure, members that are the same as or equivalent to those shown in FIG. In the figure, 11 is a frame used for the semiconductor device of the present invention, and this frame 11 consists of a die pad part 11a to which the semiconductor chip 1 is fixed, and an external terminal part 11b connected to other devices. This die pad 11a is provided with a recess 11C in a portion facing the mesa groove 1C formed on the peripheral side of the semiconductor chip 1, so that the passivation 2 and metallization A convex portion 11d is formed at a portion facing the portion 1b. That is, the upper surface of the convex portion 11d is the metallized portion 1 of the semiconductor chip 1.
b, and smaller than the entire back surface of the semiconductor chip 1, the peripheral portion of the convex portion 11d faces the passivation 2 formed on the back surface of the semiconductor chip 1. Further, the height of the convex portion 11d, in other words, the depth of the concave portion 11C is approximately 50 mm by etching or the like.
It is formed in the order of μm.

とのフレーム１１を使用して半導体装置を組立てるには
、フレーム１１の凸部１１ｄ上に半田片（図示せず）を
載置し、この半田片上に半導体チップ１を載置させる。To assemble a semiconductor device using the frame 11, a solder piece (not shown) is placed on the convex portion 11d of the frame 11, and the semiconductor chip 1 is placed on this solder piece.

次いで、半田片を溶融させてダイボンディングする。し
かる後、アルミワイヤ５をワイヤボンディングし、エポ
キシ樹脂６により封止することによって組立てが完了す
る。Next, the solder pieces are melted and die bonded. Thereafter, the aluminum wires 5 are wire-bonded and the assembly is completed by sealing with the epoxy resin 6.

したがって、半田片が溶融した際に、余分な半田は半導
体チップ１のメサ溝１Ｃに付着することす＜フレーム１
１の凹部１１Ｃに流れ、かつフレーム１１の凸部１１ｄ
上面は半導体チップ１のメタライズ部１ｄより大きく形
成されているから、凸部１１ｄが半導体チップ１の裏面
周側部に形成されたパッシベーション２の内側に嵌入す
ることもないので、メタライズ部１ｂと凸部１１ｄとの
間に半田が所定厚みをもって保持されることになる。Therefore, when the solder piece melts, excess solder adheres to the mesa groove 1C of the semiconductor chip 1.
1, and the convex portion 11d of the frame 11.
Since the upper surface is formed to be larger than the metallized portion 1d of the semiconductor chip 1, the convex portion 11d does not fit inside the passivation 2 formed on the circumferential side of the back surface of the semiconductor chip 1. The solder is held with a predetermined thickness between the portion 11d and the solder portion 11d.

なお、本実施例ではサイリスタ、トライアック等の電力
用半導体装置について説明したが、ＭＯ５ＦＥＴ　、Ｉ
ＧＢＴ等の半導体装置であってもよく、上記実施例と同
等の効果が得られる。In this example, power semiconductor devices such as thyristors and triacs have been explained, but MO5FET, I
A semiconductor device such as a GBT may also be used, and the same effect as the above embodiment can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、フレームにおける
半導体チップ裏面の周縁部より中心側であってパッシベ
ーションおよびメタライズ部と対向する部位を、半導体
チップの周側部と対向する部位より高く形成したため、
余分な半田が半導体チップの周側部に付着することなく
フレームにおける半導体チップの周側部と対向する部位
に流れかつ半導体チップのメタライズ部とフレームにお
けるメタライズ部と対向する部位との間に半田が保持さ
れることになる。したがって、半田が半導体チップの周
側部に沿ってはい上がるごとく盛り上がることがないの
で、この種半導体装置を多数個形成するにあたりフレー
ム毎に半田の塵υ上がシ量が異なるようなことがなく、
全ての半導体装置において半田の厚みを均等にすること
ができ、また、半田の量も半導体チップの裏面周縁部ま
で半田を付着させずに保持でき減らすことができるから
、精度および信頼性の高い半導体装置を安価に得ること
ができる。As explained above, according to the present invention, the part of the frame which is closer to the center than the peripheral edge of the back surface of the semiconductor chip and which faces the passivation and metallized parts is formed higher than the part which faces the peripheral part of the semiconductor chip.
The excess solder does not adhere to the peripheral side of the semiconductor chip, but flows to the part of the frame that faces the peripheral side of the semiconductor chip, and the solder is formed between the metallized part of the semiconductor chip and the part of the frame that faces the metallized part. will be retained. Therefore, the solder does not bulge up along the peripheral side of the semiconductor chip, so when forming a large number of semiconductor devices of this type, the amount of solder dust υ does not vary from frame to frame. ,
The thickness of the solder can be made uniform for all semiconductor devices, and the amount of solder can be reduced by holding the solder all the way to the periphery of the back surface of the semiconductor chip without adhering it to the periphery of the back surface of the semiconductor chip, resulting in highly accurate and reliable semiconductors. The device can be obtained at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に係る半導体装置を示す側断面図、第２
図は従来の半導体装置を示す側断面図である。 １・・・拳半導体チップ、１ｂ・・・・メタライズ部、
２・・・・ガラスパッシベーション、４・・争・半田、
１１・・・ｅフレーム、１１ｄ・・・・凸部。FIG. 1 is a side sectional view showing a semiconductor device according to the present invention, and FIG.
The figure is a side sectional view showing a conventional semiconductor device. 1... fist semiconductor chip, 1b... metallized part,
2...Glass passivation, 4...War/Solder,
11...e frame, 11d...convex portion.

Claims (1)

【特許請求の範囲】[Claims] 　裏面にメタライズ部が形成され、周側部および裏面の
周縁部とがパッシベーションされた両面メサ形半導体チ
ップがフレーム上に半田付けされてなる半導体装置にお
いて、前記フレームにおける半導体チップ裏面の周縁部
より中心側であつてパッシベーションおよびメタライズ
部と対向する部位を、半導体チップの周側部と対向する
部位より高く形成したことを特徴とする半導体装置。In a semiconductor device in which a double-sided mesa-shaped semiconductor chip, in which a metallized portion is formed on the back surface and a peripheral side portion and a peripheral edge portion of the back surface are passivated, is soldered onto a frame, the center of the semiconductor chip is lower than the peripheral edge of the back surface of the frame. A semiconductor device characterized in that a portion of the side facing the passivation and metallized portion is formed higher than a portion facing the peripheral side of the semiconductor chip.
JP62274564A 1987-10-28 1987-10-28 Semiconductor device Pending JPH01115127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62274564A JPH01115127A (en) 1987-10-28 1987-10-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62274564A JPH01115127A (en) 1987-10-28 1987-10-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01115127A true JPH01115127A (en) 1989-05-08

Family

ID=17543488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62274564A Pending JPH01115127A (en) 1987-10-28 1987-10-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01115127A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08508614A (en) * 1993-03-31 1996-09-10 シーメンス コンポーネンツ インコーポレイテッド Lead frame with pedestal supporting semiconductor chip
JP2004511926A (en) * 2000-05-31 2004-04-15 ＠ポス　ドットコム　インコーポレイテッド Secure, encrypted PIN pad
JP2004119944A (en) * 2002-09-30 2004-04-15 Toyota Industries Corp Semiconductor module and mounting substrate
JP2006269751A (en) * 2005-03-24 2006-10-05 Toshiba Corp Semiconductor device and manufacturing method therefor
JP2007134395A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
US7235876B2 (en) * 2005-09-12 2007-06-26 Denso Corporation Semiconductor device having metallic plate with groove
JP2011223035A (en) * 2011-07-25 2011-11-04 Toshiba Corp Semiconductor device
EP2605278A1 (en) * 2011-12-15 2013-06-19 Nxp B.V. Lead Frame with Die Attach Bleeding Control Features
JP2016105508A (en) * 2016-02-29 2016-06-09 株式会社三社電機製作所 Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08508614A (en) * 1993-03-31 1996-09-10 シーメンス コンポーネンツ インコーポレイテッド Lead frame with pedestal supporting semiconductor chip
JP2004511926A (en) * 2000-05-31 2004-04-15 ＠ポス　ドットコム　インコーポレイテッド Secure, encrypted PIN pad
JP2004119944A (en) * 2002-09-30 2004-04-15 Toyota Industries Corp Semiconductor module and mounting substrate
JP2006269751A (en) * 2005-03-24 2006-10-05 Toshiba Corp Semiconductor device and manufacturing method therefor
US7235876B2 (en) * 2005-09-12 2007-06-26 Denso Corporation Semiconductor device having metallic plate with groove
JP2007134395A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
JP2011223035A (en) * 2011-07-25 2011-11-04 Toshiba Corp Semiconductor device
EP2605278A1 (en) * 2011-12-15 2013-06-19 Nxp B.V. Lead Frame with Die Attach Bleeding Control Features
JP2016105508A (en) * 2016-02-29 2016-06-09 株式会社三社電機製作所 Semiconductor device

Similar Documents

Publication Publication Date Title
JP3007023B2 (en) Semiconductor integrated circuit and method of manufacturing the same
JPH06244360A (en) Semiconductor device
JP2895920B2 (en) Semiconductor device and manufacturing method thereof
JPH01115127A (en) Semiconductor device
JPS62202548A (en) Semiconductor device
JP2569400B2 (en) Method for manufacturing resin-encapsulated semiconductor device
US3280383A (en) Electronic semiconductor device
JPH10247701A (en) Semiconductor device and lead frame for manufacturing the same
US3471752A (en) Semiconductor device with an insulating body interposed between a semiconductor element and a part of a casing
JP2000243880A (en) Semiconductor device and its manufacture
JP2000077458A (en) Flip-chip mounting method
JP3670371B2 (en) Semiconductor device and manufacturing method thereof
JP2788011B2 (en) Semiconductor integrated circuit device
JPS63293963A (en) Resin-sealed semiconductor device
JPS6313337A (en) Process of mounting semiconductor element
JPH06241889A (en) Semiconductor device
JPH0287655A (en) Semiconductor device
JPH0451056B2 (en)
JPS5853838A (en) Semiconductor device
JPH01206660A (en) Lead frame and semiconductor device utilizing same
JPH08181168A (en) Semiconductor device
JPS6155778B2 (en)
JPS6218737A (en) Ceramic package for semiconductor device
JPH05235260A (en) Semiconductor device
JPH1155065A (en) Production of solid-state element device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees