JPH01100656A - Microcomputer output circuit - Google Patents

Abstract

PURPOSE:To realize a low consuming power by controlling a mode register by an instruction from a microcomputer and setting to 0 or H impedance according to the contents of the register. CONSTITUTION:The mode register 18 is cleared by a reset signal 17 to bring the output to a non-selective state level and the output of a NAND circuit 14 is set to '1' and supplied to NAND circuits 22, 23. Contents based on the internal input signal 15 of the circuits 22, 23 are supplied to P-type and N-type MOS transistors (Tr), an output signal corresponding thereto is outputted to an output terminal 11 to execute an ordinary operation. Then, the register 18 is reset by a set signal 16 from the microcomputer to set an output signal below a selective level. Then, at the time of a stand-by state, a stand-by signal 19 is made active and the NAND circuit 14 sets the output signal to '0'. Consequently, the circuits 22, 23 supply the output signal '1' to the gate electrode of Trs 12, 21 to make inoperative and set an output to '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit for a microcomputer, and more particularly to an output circuit that can estimate the power consumption of a display element, etc. used in a CMOS microcomputer during standby.

[Conventional technology]

Conventionally, the output circuit of this type of CMOS microcomputer consists of a P-type MO8 transistor and an N-type M08 transistor, as shown in Figure 3.
OS transistors are connected in series and an output buffer drives a light emitting diode (LED) display element, but if the output buffer is set to standby mode with the output fixed at 1, a drive current always flows. For this reason, the power consumption of the output buffer is large, so normally, in order to achieve low power consumption, a program is used to set all output ports to O and then set the standby mode.

[Problem that the invention seeks to solve]

The above-mentioned conventional microcomputer output circuit has a drawback in that in order to reduce the output to zero in a program in order to achieve low power consumption, complicated program processing must be performed.

[Means for solving problems]

The output circuit of the microcomputer of the present invention includes a mode register that can be controlled by instructions from the microcomputer, and means for setting any output of the output circuit to Ol or high impedance during standby according to the contents of the mode register. have.

〔Example〕

Next, implementation of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the invention. In FIG. 1, the first embodiment of the present invention has an output buffer in which a P-type MOS transistor 12 and an N-type MO transistor 21 are connected in series, and the source electrode of the P-type MOS transistor 12 is supplied with a power supply voltage 13, the source electrode of an N-type MOS transistor 21 is an output circuit of a microcomputer connected to the ground potential 20, and the gate electrodes of both transistors 12 and 21 are connected to NAND circuits 22 and 23, respectively. It is connected.

The NAND circuits 22 and 23 are connected so that the internal input signal 15 is supplied to one input terminal, and the NAND circuit 14 is connected to the other input terminal. N
One input terminal of the AND circuit 14 is connected to the mode register 18.
is connected to standby signal 1, and the other input terminal is connected to standby signal 1.
It is connected to input 9. Furthermore, the mode register 18 is connected so that the set signal 16 and the reset signal 17 are inputted thereto.

Next, the operation of the first embodiment will be explained. In this embodiment, mode register 18 is cleared by generation of reset signal 170. The output of this mode register 18 becomes a non-selection level (hereinafter abbreviated as non-active), the output of the NAND circuit 14 becomes II I II, and the NA
It is supplied to ND circuits 22 and 23. Therefore, this NAN
The D circuits 22 and 23 supply the contents based on the internal input signal 15 to the P-type and N-type MOS transistors 12 and 21, output signals corresponding thereto to the output terminal 11, and perform normal operation.

Next, the standby mode will be explained.

The mode register 18 is set by a set signal 16 generated by a command from the microcomputer.

This mode register 18 sets the output signal to a selection level (hereinafter abbreviated as active).

After this, when the standby state is entered, the standby signal 19 becomes active, and the NAND circuit 14 sets its output signal to 0. As a result, the NAND circuits 22 and 23 send their output signal 1° to both MOS transistors .2
1 gate electrode. Both MOS transistors become inactive, and the output of the output terminal 11 is fixed at 0'''.Therefore, since there is no drive current due to the output buffer, low power consumption can be achieved.

Next, a second embodiment of the present invention will be described.

FIG. 2 shows a second embodiment of the invention. In FIG. 2, the second embodiment includes a P-type transistor 32 and an N-type MO9
It has an output buffer in which a transistor 43 is connected in series in a complementary manner, a power supply voltage 33 is supplied to the source electrode of the P-type transistor 32, and a NAND circuit 44 is connected to the source electrode of the N-type transistor 43. N
A NOR circuit 4 is connected to the gate electrode of the type MOS transistor 43.
5 is connected. The NAND circuit and the NOR circuit 45 are connected so that the internal input terminal 15 is supplied to one input terminal, the NAND circuit 36 is connected to the other input terminal of the NAND circuit 44, and the inverter circuit is connected to the input terminal of the NOR circuit 45. A NAND circuit 36 is connected via 34. The NAND circuit 36 has one input terminal connected to the mode register 37, the other input terminal connected to the mode register 37, and the other input terminal connected to input the standby signal 40. Furthermore, the mode register 37 receives a set signal 38 and a reset signal 39.
is connected so that it is input.

To explain the operation of this second embodiment, the reset signal 3
9 occurs, the mode register 37 is cleared and the output of the mode register 37 becomes non-accelerated and becomes NAND.
The output signal of the circuit 36 is set to "1", and the NAND circuit 44
On the other hand, the output via the INV circuit 34 is set to ``0°'' and is supplied to the input terminal of the NOR circuit 45. Therefore, the NAND circuit 44 and the NOR circuit 45 input the internal input signal 41. Sends a signal based on both M
Supplied to oR transistors 32 and 43. Both MOS transistors 32 and 43 output to the output terminal 31 according to their contents and perform normal operation.

Next, in the standby mode, the set signal 38 generated by the command from the microcomputer causes the
Set mode register 37. The output of this mode transistor 37 becomes active, and the NAND circuit 36
is supplied to Thereafter, when the standby state is established, the standby signal 40 becomes active, the NAND circuit 36 sets the output to "0", and the output of the INV circuit 34 becomes 1'. As a result, the NAND circuit 44 and the NOR circuit 45
Both outputs become “1”, and both MOS transistors 32
．． 43. This result side MOS transistor 3
2 and 34 are both in the set-off state, and the output of the output terminal 31 becomes a "high impedance spur," and low power consumption can be achieved because no drive current flows through the output buffer made up of both MO8 transistors.

〔Effect of the invention〕

As explained above, the present invention sets the mode register to set the output to 0 or high during standby.
Since the impedance can be fixed, the drive current flowing to the output buffer can be controlled, resulting in low power consumption.
Another advantage is that no complicated program is required.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the invention, and Fig. 3 is a diagram showing an output circuit of a conventional microcomputer. It is. 11.31...Output terminal, 12.32...P type MO
S transistor, 13.33...Power supply potential, 14°2
2.23, 36.44...NAND circuit, 15°41
...Internal input signal, 16.38...Set signal, 1
7.39... Reset signal, 18.37... Mode register, 19.41... Standby signal, 20°42
...Ground potential, 21.43...N-type MOS transistor, 45...MOR circuit.

Claims (1)

[Claims] In an output circuit of a microcomputer in which a P-type MOS transistor and an N-type MOS transistor are connected in a complementary manner, there is a mode register for setting a set/reset state according to an instruction from the microcomputer, a signal output in a standby state, and the mode. 1. An output circuit for a microcomputer, comprising means for setting the outputs of both MOS transistors to an arbitrary fixed level or high impedance according to an output signal of a register.