JP7461725B2 - Detection device - Google Patents

Description

The present invention relates to a detection device.

In recent years, optical biosensors have become known as biosensors used for personal authentication and the like. Known examples of biosensors include fingerprint sensors (see, for example, Patent Document 1) and vein sensors. Known optical sensors used in biosensors include optical sensors that use organic materials and optical sensors that use inorganic materials.

US Patent Application Publication No. 2018/0012069

Optical sensors using organic materials can detect light in a wider wavelength range than optical sensors using inorganic materials such as amorphous silicon. On the other hand, optical sensors using organic materials may experience changes in sensor output due to aging, etc.

The present invention aims to provide a detection device that can suppress deterioration of detection performance.

A detection device according to one embodiment of the present invention includes a substrate, a plurality of first optical sensors provided in a detection region of the substrate and including an organic material layer having a photovoltaic effect, and at least one second optical sensor provided on the substrate and including an inorganic material layer having a photovoltaic effect.

FIG. 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device having a detection device according to a first embodiment. FIG. 2 is a plan view showing the detection device according to the first embodiment. FIG. 3 is a block diagram illustrating an example of the configuration of the detection device according to the first embodiment. FIG. 4 is a circuit diagram showing the detection device. FIG. 5 is a circuit diagram showing a plurality of partial detection regions. FIG. 6 is a plan view showing the first optical sensor. FIG. 7 is a cross-sectional view taken along line QQ of FIG. FIG. 8 is a graph showing a schematic relationship between the wavelength of light incident on the first optical sensor and the conversion efficiency. FIG. 9 is a timing waveform diagram showing an example of the operation of the detection device. FIG. 10 is a timing waveform diagram showing an example of operation during the readout period in FIG. FIG. 11 is a cross-sectional view taken along line XI-XI' of FIG. 2. FIG. 12 is a circuit diagram showing a drive circuit for the second optical sensor. FIG. 13 is an explanatory diagram for explaining the relationship between the first detection signal output from the first optical sensor and the second detection signal output from the second optical sensor. FIG. 14 is a plan view showing a detection device according to the second embodiment. FIG. 15 is a plan view showing a detection device according to the third embodiment. FIG. 16 is a plan view showing a detection device according to the fourth embodiment. Figure 17 is a cross-sectional view taken along line XVII-XVII' of Figure 16. FIG. 18 is a plan view showing a detection device according to a modified example of the fourth embodiment.

The form (embodiment) for carrying out the invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiment. The components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may show the width, thickness, shape, etc. of each part in a schematic manner compared to the actual embodiment, but they are merely an example and do not limit the interpretation of the present invention. In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

First Embodiment
Fig. 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with an illumination device having a detection device according to the first embodiment. As shown in Fig. 1, a detection device with an illumination device 120 has a detection device 1, an illumination device 121, and a cover glass 122. The illumination device 121, the detection device 1, and the cover glass 122 are layered in this order in a direction perpendicular to the surface of the detection device 1.

The lighting device 121 has a light irradiation surface 121a that emits light, and emits light L1 from the light irradiation surface 121a toward the detection device 1. The lighting device 121 is a backlight. The lighting device 121 may be a so-called side light type backlight having, for example, a light guide plate provided at a position corresponding to the detection area AA and a plurality of light sources arranged at one end or both ends of the light guide plate. For example, a light emitting diode (LED: Light Emitting Diode) that emits light of a predetermined color is used as the light source. The lighting device 121 may also be a so-called direct type backlight having a light source (for example, an LED) provided directly below the detection area AA. The lighting device 121 is not limited to a backlight, and may be provided on the side or above the detection device 1, and may emit light L1 from the side or above the finger Fg.

The detection device 1 is provided opposite the light irradiation surface 121a of the illumination device 121. In other words, the detection device 1 is provided between the illumination device 121 and the cover glass 122. The light L1 irradiated from the illumination device 121 passes through the detection device 1 and the cover glass 122. The detection device 1 is, for example, a light reflection type biosensor, and can detect unevenness (e.g., a fingerprint) on the surface of the finger Fg by detecting the light L2 reflected at the interface between the cover glass 122 and the air. Alternatively, in addition to detecting fingerprints, the detection device 1 may detect information about the living body by detecting the light L2 reflected inside the finger Fg. The information about the living body is, for example, a blood vessel image such as a vein, a pulse, a pulse wave, etc. The color of the light L1 from the illumination device 121 may be different depending on the detection target. For example, in the case of fingerprint detection, the illumination device 121 can irradiate blue or green light L1, and in the case of vein detection, the illumination device 121 can irradiate infrared light L1.

The cover glass 122 is a member for protecting the detection device 1 and the illumination device 121, and covers the detection device 1 and the illumination device 121. The cover glass 122 is, for example, a glass substrate. Note that the cover glass 122 is not limited to a glass substrate, and may be a resin substrate or the like. Also, the cover glass 122 may not be provided. In this case, a protective layer is provided on the surface of the detection device 1, and the finger Fg comes into contact with the protective layer of the detection device 1.

The detection device with illumination device 120 may be provided with a display panel instead of the illumination device 121. The display panel may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode) or an inorganic EL display (μ-LED, Mini-LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using liquid crystal elements as display elements, or an electrophoretic display panel (EPD: Electrophoretic Display) using electrophoretic elements as display elements. Even in this case, the display light emitted from the display panel passes through the detection device 1, and based on the light L2 reflected by the finger Fg, information about the fingerprint and biometric information of the finger Fg can be detected.

Figure 2 is a plan view showing the detection device according to the first embodiment. As shown in Figure 2, the detection device 1 has an insulating substrate 21, a sensor unit 10, a gate line driving circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 102, and a power supply circuit 103.

The control board 101 is electrically connected to the insulating board 21 via the flexible printed circuit board 110. The flexible printed circuit board 110 is provided with a detection circuit 48. The control board 101 is provided with a control circuit 102 and a power supply circuit 103. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 103 supplies voltage signals such as a sensor power supply signal VDDSNS (see FIG. 5) to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16.

The insulating substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area that overlaps with the multiple first optical sensors 30 of the sensor unit 10. The peripheral area GA is an area outside the detection area AA and does not overlap with the first optical sensors 30. In other words, the peripheral area GA is an area between the outer periphery of the detection area AA and the end of the insulating substrate 21. The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA.

The sensor unit 10 is an optical sensor having a first optical sensor 30 and a second optical sensor 50, which are photoelectric conversion elements. The first optical sensors 30 and the second optical sensors 50 are photodiodes, and each outputs an electrical signal corresponding to the light irradiated thereto. The first optical sensors 30 of the sensor unit 10 are arranged in a matrix in the detection area AA. The first optical sensors 30 output an electrical signal corresponding to the light irradiated thereto as a first detection signal Vdet to the signal line selection circuit 16. The detection device 1 detects information about a living body based on the first detection signal Vdet from the first optical sensors 30. In other words, the first optical sensors 30 function as a living body sensor. The first optical sensors 30 perform detection according to the gate drive signal Vgcl supplied from the gate line drive circuit 15.

The second optical sensor 50 of the sensor unit 10 is provided in the peripheral area GA. The second optical sensor 50 is electrically connected to the detection circuit 48, the control circuit 102, and the power supply circuit 103 via the gate line GCL-R, the signal line SGL-R, and the flexible printed circuit board 110. The second optical sensor 50 outputs an electrical signal corresponding to the irradiated light to the detection circuit 48 as a second detection signal Vdet-R. Based on the second detection signal Vdet-R output from the second optical sensor 50, the control circuit 102 detects a change in the first detection signal Vdet from the multiple first optical sensors 30 when the same object to be detected is detected.

Furthermore, the control circuit 102 controls the detection of the multiple first optical sensors 30 based on the second detection signal Vdet-R output from the second optical sensor 50 to suppress changes in the first detection signal Vdet due to aging or the like. In other words, the second optical sensor 50 functions as a reference sensor for the multiple first optical sensors 30. Note that, although one second optical sensor 50 is provided in FIG. 2, there may be two or more second optical sensors 50.

The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the gate line driving circuit 15 is provided in a region of the peripheral area GA that extends along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA that extends along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48.

The first direction Dx is a direction in a plane parallel to the insulating substrate 21. The second direction Dy is a direction in a plane parallel to the insulating substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular to it. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the insulating substrate 21.

Fig. 3 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. As shown in Fig. 3, the detection device 1 further includes a detection control unit 11 and a detection unit 40. Some or all of the functions of the detection control unit 11 are included in the control circuit 102. In addition, some or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 102.

The detection control unit 11 is a circuit that supplies control signals to the gate line driving circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operation. The detection control unit 11 supplies various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST1, to the gate line driving circuit 15. The detection control unit 11 also supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16. The detection control unit 11 also supplies a control signal to the second optical sensor 50, and controls the detection of the second optical sensor 50.

The gate line driving circuit 15 is a circuit that drives multiple gate lines GCL (see FIG. 4) based on various control signals. The gate line driving circuit 15 selects multiple gate lines GCL sequentially or simultaneously, and supplies a gate driving signal Vgcl to the selected gate lines GCL. In this way, the gate line driving circuit 15 selects multiple first optical sensors 30 connected to the gate lines GCL.

The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects multiple signal lines SGL (see FIG. 4). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected signal line SGL to the detection circuit 48 based on the selection signal ASW supplied from the detection control unit 11. As a result, the signal line selection circuit 16 outputs the first detection signal Vdet of the first optical sensor 30 to the detection unit 40.

The second optical sensor 50 is driven based on a control signal supplied from the detection control unit 11. The second optical sensor 50 outputs a second detection signal Vdet-R to the detection unit 40 via the signal line SGL-R. The second optical sensor 50 is not connected to the gate line driving circuit 15 and the signal line selection circuit 16, and is driven independently of the first optical sensor 30. However, this is not limited to the above, and the second optical sensor 50 may be connected to the gate line driving circuit 15 and the signal line selection circuit 16. In other words, the second optical sensor 50 may be driven based on a drive signal supplied from the gate line driving circuit 15, or may be electrically connected to the detection circuit 48 via the signal line selection circuit 16.

The detection unit 40 includes a detection circuit 48, a signal processing unit 44, a coordinate extraction unit 45, a storage unit 46, and a detection timing control unit 47. The detection timing control unit 47 controls the detection circuit 48, the signal processing unit 44, and the coordinate extraction unit 45 to operate in synchronization based on a control signal supplied from the detection control unit 11.

The detection circuit 48 is, for example, an analog front-end circuit (AFE). The detection circuit 48 is a signal processing circuit having at least the functions of a detection signal amplifier 42 and an A/D converter 43. The detection signal amplifier 42 amplifies the first detection signal Vdet and the second detection signal Vdet-R. The A/D converter 43 converts the analog signal output from the detection signal amplifier 42 into a digital signal.

The signal processing unit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When the finger Fg is in contact with or close to the detection surface, the signal processing unit 44 can detect unevenness on the surface of the finger Fg or the palm based on the signal from the detection circuit 48. The signal processing unit 44 can also detect information about the living body based on the signal from the detection circuit 48. The information about the living body is, for example, an image of blood vessels in the finger Fg or the palm, a pulse wave, a pulse rate, blood oxygen saturation, etc. The signal processing unit 44 also calculates a signal ΔV that is the difference between the first detection signal Vdet and the second detection signal Vdet-R.

The memory unit 46 temporarily stores the signal calculated by the signal processing unit 44. The memory unit 46 also stores information about the past first detection signal Vdet, the second detection signal Vdet-R, and the difference signal ΔV. The memory unit 46 may be, for example, a RAM (Random Access Memory), a register circuit, etc.

The coordinate extraction unit 45 is a logic circuit that determines the detection coordinates of the unevenness of the surface of the finger Fg, etc., when the contact or proximity of the finger Fg is detected in the signal processing unit 44. The coordinate extraction unit 45 is also a logic circuit that determines the detection coordinates of the blood vessels of the finger Fg or the palm. The coordinate extraction unit 45 combines the first detection signals Vdet output from each first optical sensor 30 of the sensor unit 10 to generate two-dimensional information that indicates the shape of the unevenness of the surface of the finger Fg, etc. Note that the coordinate extraction unit 45 may output the first detection signal Vdet and the second detection signal Vdet-R as the sensor output Vo without calculating the detection coordinates.

Next, an example of the circuit configuration and operation of the detection device 1 will be described. FIG. 4 is a circuit diagram showing the detection device. FIG. 5 is a circuit diagram showing a partial detection area. Note that FIG. 5 also shows the circuit configuration of the detection circuit 48.

As shown in FIG. 4, the sensor unit 10 has a plurality of partial detection areas PAA arranged in a matrix. A first optical sensor 30 is provided in each of the partial detection areas PAA.

The gate line GCL extends in the first direction Dx and is connected to a plurality of partial detection areas PAA arranged in the first direction Dx. The plurality of gate lines GCL(1), GCL(2), ..., GCL(8) are arranged in the second direction Dy and are each connected to the gate line driving circuit 15. In the following description, when it is not necessary to distinguish between the plurality of gate lines GCL(1), GCL(2), ..., GCL(8), they are simply referred to as gate lines GCL. In addition, in FIG. 4, eight gate lines GCL are shown for ease of explanation, but this is merely an example, and M gate lines GCL (M is 8 or more, for example, M=256) may be arranged.

The signal line SGL extends in the second direction Dy and is connected to the first optical sensors 30 of the multiple partial detection areas PAA arranged in the second direction Dy. The multiple signal lines SGL(1), SGL(2), ..., SGL(12) are arranged in the first direction Dx and are each connected to the signal line selection circuit 16 and the reset circuit 17. In the following description, when it is not necessary to distinguish between the multiple signal lines SGL(1), SGL(2), ..., SGL(12), they will simply be referred to as signal lines SGL.

For ease of understanding, 12 signal lines SGL are shown, but this is merely an example, and N signal lines SGL (N is 12 or more, for example, N=252) may be arranged. The resolution of the sensor is, for example, 508 dpi (dots per inch), and the number of cells is 252×256. In FIG. 4, the sensor unit 10 is provided between the signal line selection circuit 16 and the reset circuit 17. However, this is not limiting, and the signal line selection circuit 16 and the reset circuit 17 may each be connected to the ends of the signal lines SGL in the same direction.

The gate line driving circuit 15 receives various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST1, from the control circuit 102 (see FIG. 2). Based on the various control signals, the gate line driving circuit 15 sequentially selects multiple gate lines GCL(1), GCL(2), ..., GCL(8) in a time-division manner. The gate line driving circuit 15 supplies a gate driving signal Vgcl to the selected gate line GCL. As a result, the gate driving signal Vgcl is supplied to multiple first switching elements Tr connected to the gate line GCL, and multiple partial detection areas PAA arranged in the first direction Dx are selected as detection targets.

The gate line driving circuit 15 may perform different driving for each detection mode of fingerprint detection and information related to a plurality of different biological bodies (pulse wave, pulse, blood vessel image, blood oxygen saturation, etc.). For example, the gate line driving circuit 15 may drive a bundle of multiple gate lines GCL.

Specifically, the gate line driving circuit 15 may simultaneously select a predetermined number of gate lines GCL from the gate lines GCL(1), GCL(2), ..., GCL(8) based on the control signal. For example, the gate line driving circuit 15 simultaneously selects the six gate lines GCL(1) to GCL(6) and supplies the gate driving signal Vgcl. The gate line driving circuit 15 supplies the gate driving signal Vgcl to the first switching elements Tr through the six selected gate lines GCL. As a result, group areas PAG1 and PAG2 including a plurality of partial detection areas PAA arranged in the first direction Dx and the second direction Dy are selected as detection targets. The gate line driving circuit 15 drives a predetermined number of gate lines GCL in a bundle and sequentially supplies the gate driving signal Vgcl to each of the predetermined number of gate lines GCL. Hereinafter, when the positions of the different group areas such as the group areas PAG1 and PAG2 are not particularly distinguished, they are referred to as group areas PAG.

The signal line selection circuit 16 has a plurality of selection signal lines Lsel, a plurality of output signal lines Lout, and a third switching element TrS. The plurality of third switching elements TrS are provided corresponding to the plurality of signal lines SGL, respectively. The six signal lines SGL(1), SGL(2), ..., SGL(6) are connected to a common output signal line Lout1. The six signal lines SGL(7), SGL(8), ..., SGL(12) are connected to a common output signal line Lout2. The output signal lines Lout1, Lout2 are each connected to a detection circuit 48.

Here, the signal lines SGL(1), SGL(2), ..., SGL(6) are defined as a first signal line block, and the signal lines SGL(7), SGL(8), ..., SGL(12) are defined as a second signal line block. The multiple selection signal lines Lsel are each connected to the gate of the third switching element TrS included in one signal line block. Furthermore, one selection signal line Lsel is connected to the gate of the third switching element TrS of multiple signal line blocks.

Specifically, the selection signal lines Lsel1, Lsel2, ..., Lsel6 are connected to the third switching elements TrS corresponding to the signal lines SGL(1), SGL(2), ..., SGL(6), respectively. The selection signal line Lsel1 is connected to the third switching element TrS corresponding to the signal line SGL(1) and the third switching element TrS corresponding to the signal line SGL(7). The selection signal line Lsel2 is connected to the third switching element TrS corresponding to the signal line SGL(2) and the third switching element TrS corresponding to the signal line SGL(8).

The control circuit 102 sequentially supplies the selection signal ASW to the selection signal line Lsel. As a result, the signal line selection circuit 16 sequentially selects the signal lines SGL in one signal line block in a time-division manner by the operation of the third switching element TrS. The signal line selection circuit 16 also selects one signal line SGL each in each of the multiple signal line blocks. With this configuration, the detection device 1 can reduce the number of ICs (Integrated Circuits) including the detection circuit 48, or the number of IC terminals.

The signal line selection circuit 16 may bundle multiple signal lines SGL and connect them to the detection circuit 48. Specifically, the control circuit 102 simultaneously supplies the selection signal ASW to the selection signal lines Lsel. As a result, the signal line selection circuit 16 selects multiple signal lines SGL (e.g., six signal lines SGL) in one signal line block by the operation of the third switching element TrS, and connects the multiple signal lines SGL to the detection circuit 48. As a result, the signal detected in each group area PAG is output to the detection circuit 48. In this case, signals from multiple partial detection areas PAA (first optical sensors 30) are integrated in group area PAG units and output to the detection circuit 48.

By performing detection for each group area PAG through the operation of the gate line driving circuit 15 and the signal line selection circuit 16, the strength of the first detection signal Vdet obtained in one detection is improved, thereby improving the sensor sensitivity. In addition, the time required for detection can be shortened. Therefore, the detection device 1 can repeatedly perform detection in a short period of time, thereby improving the S/N ratio and enabling accurate detection of temporal changes in information about the living body, such as pulse waves.

The reset circuit 17 has a reference signal line Lvr, a reset signal line Lrst, and a fourth switching element TrR. The fourth switching element TrR is provided corresponding to the multiple signal lines SGL. The reference signal line Lvr is connected to one of the sources or drains of the multiple fourth switching elements TrR. The reset signal line Lrst is connected to the gates of the multiple fourth switching elements TrR.

The control circuit 102 supplies a reset signal RST2 to the reset signal line Lrst. This turns on the multiple fourth switching elements TrR, and the multiple signal lines SGL are electrically connected to the reference signal line Lvr. The power supply circuit 103 supplies a reference signal COM to the reference signal line Lvr. This causes the reference signal COM to be supplied to the capacitive elements Ca (see FIG. 5) included in the multiple partial detection areas PAA.

As shown in FIG. 5, the partial detection area PAA includes a first optical sensor 30, a capacitive element Ca, and a first switching element Tr. In FIG. 5, two gate lines GCL(m) and GCL(m+1) arranged in the second direction Dy among the multiple gate lines GCL are shown. Also, two signal lines SGL(n) and SGL(n+1) arranged in the first direction Dx among the multiple signal lines SGL are shown. The partial detection area PAA is an area surrounded by the gate lines GCL and the signal lines SGL. The first switching element Tr is provided corresponding to the first optical sensor 30. The first switching element Tr is composed of a thin film transistor, and in this example, is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT (Thin Film Transistor).

The gates of the first switching elements Tr belonging to the multiple partial detection areas PAA aligned in the first direction Dx are connected to the gate line GCL. The sources of the first switching elements Tr belonging to the multiple partial detection areas PAA aligned in the second direction Dy are connected to the signal line SGL. The drains of the first switching elements Tr are connected to the cathode of the first optical sensor 30 and the capacitive element Ca.

The anode of the first optical sensor 30 is supplied with a sensor power supply signal VDDSNS from the power supply circuit 103. In addition, the signal line SGL and the capacitive element Ca are supplied with a reference signal COM, which is the initial potential of the signal line SGL and the capacitive element Ca, from the power supply circuit 103.

When light is irradiated onto the partial detection area PAA, a current corresponding to the amount of light flows through the first optical sensor 30, causing charge to accumulate in the capacitance element Ca. When the first switching element Tr is turned on, a current flows through the signal line SGL according to the charge accumulated in the capacitance element Ca. The signal line SGL is connected to the detection circuit 48 via the third switching element TrS of the signal line selection circuit 16. This allows the detection device 1 to detect a signal corresponding to the amount of light irradiated onto the first optical sensor 30 for each partial detection area PAA or for each group area PAG.

In the detection circuit 48, the switch SSW is turned on during the read period Pdet (see FIG. 9), and the detection circuit 48 is connected to the signal line SGL. The detection signal amplifier 42 of the detection circuit 48 converts the fluctuation in the current supplied from the signal line SGL into a fluctuation in voltage and amplifies it. A reference potential (Vref) having a fixed potential is input to the non-inverting input terminal (+) of the detection signal amplifier 42, and the signal line SGL is connected to the inverting input terminal (-). A signal that is the same as the reference signal COM is input as the reference potential (Vref). The detection signal amplifier 42 also has a capacitance element Cb and a reset switch RSW. During the reset period Prst (see FIG. 9), the reset switch RSW is turned on, and the charge of the capacitance element Cb is reset.

Next, an outline of a method for manufacturing the first optical sensor 30 of the sensor unit 10 and a process for forming the first optical sensor 30 (OPD formation process) will be described. FIG. 6 is a plan view showing the first optical sensor. FIG. 7 is a cross-sectional view taken along line Q-Q of FIG. 6.

(Outline of manufacturing method)
The manufacturing method of the first optical sensor 30 of the sensor unit 10 will be described below. A backplane BP including LTPS (Low Temperature Poly Silicon) 22 was formed on an undercoat 26, a light-shielding layer 27, and an insulator, which were laminated on a polyimide 25 formed on an insulating substrate 21. The thickness of the polyimide 25 is, for example, 10 μm. The device for forming the backplane BP is peeled off from the glass substrate by LLO (Laser Lift Off) after all the processes for forming the backplane BP are completed. The backplane BP functions as a first switching element Tr. In the embodiment, the LTPS 22 is used as the semiconductor layer, but this is not limited thereto, and other semiconductors such as amorphous silicon may be used.

Each first switching element Tr is composed of a double gate TFT in which two NMOS transistors are directly connected. The NMOS transistor of the first switching element Tr has, for example, a channel length of 4.5 μm, a channel width of 2.5 μm, and a mobility of about 40 to 70 cm ² /Vs. In forming the TFT of the LTPS22, first, a film is formed using four materials, silicon monoxide (SiO), silicon nitride (SiN), SiO, and amorphous silicon (a-Si), and then the a-Si is crystallized by annealing with an excimer laser to form polysilicon. In addition, the circuit of the surrounding driver part is formed of a CMOS (Complementary MOS) circuit consisting of a PMOS transistor and an NMOS transistor. The PMOS transistor of the peripheral circuit has, for example, a channel length of 4.5 μm, a channel width of 3.5 μm, and a mobility of about 40 to 70 cm ² /Vs. The NMOS transistor of the peripheral circuit has, for example, a channel length of 4.5 μm, a channel width of 2.5 μm, and a mobility of about 40 to 70 cm ² /Vs, as described above. After forming the polysilicon, boron (B) and phosphorus (P) are doped to form the PMOS and NMOS electrodes.

After that, SiO is deposited as the insulating film 23a, and a molybdenum tungsten alloy (MoW) is deposited as the two gate electrodes GE-A and GE-B of the double-gate TFT. The thickness of the insulating film 23a is, for example, 70 nm. The thickness of the MoW used to form the gate electrodes GE-A and GE-B is, for example, 250 nm.

After the MoW film is formed, an intermediate film 23b is formed, followed by the electrode layer 28 for forming the source electrode 28a and the drain electrode 28b. The electrode layer 28 is, for example, an aluminum alloy. Vias V1 and V2 for connecting the source electrode 28a and the drain electrode 28b to the PMOS and NMOS electrodes of the LTPS 22 formed by doping are formed by dry etching. The insulating film 23a and intermediate film 23b function as the insulating layer 23 that separates the gate electrodes GE-A and GE-B, which function as the gate lines GCL, from the LTPS 22 and the electrode layer 28.

The backplane BP thus formed includes the LTPS 22 laminated on the first optical sensor 30 side of the light-shielding layer 27, and an electrode layer 28 laminated between the LTPS 22 and the first optical sensor 30, in which the source electrode 28a and drain electrode 28b of the first switching element Tr are formed. The source electrode 28a extends to a position facing the light-shielding layer 27, sandwiching the LTPS 22 therebetween.

After the backplane BP is manufactured, a smoothing layer 29 having a thickness of 2 μm is formed on top to form an organic photodetector layer. Although not shown, a sealing film is further formed on the smoothing layer 29. In addition, a via V3 for connecting the backplane BP to the first optical sensor 30 is formed by etching.

Next, an organic photodiode (OPD) with an inverted structure that is stable in the atmosphere is formed on top of the backplane BP as the first optical sensor 30. The active layer 31 (photoelectric conversion layer) of the first optical sensor 30, which is an organic sensor, is made of a material that is sensitive to near-infrared light (e.g., light with a wavelength of 850 nm). ITO (Indium Tin Oxide) is used for the cathode electrode 35, which is a transparent electrode, and is connected to the backplane BP through a via V3. Furthermore, a zinc oxide (ZnO) layer 35a is formed on the surface of the ITO to adjust the work function of the electrode.

The organic photodiodes are fabricated as two different devices using different types of organic semiconductor materials as the active layers. Specifically, two types of materials, PMDPP3T (Poly[[2,5-bis(2-hexyldecyl)-2,3,5,6-tetrahydro-3,6-dioxopyrrolo[3,4-c]pyrrole-1,4-diyl]-alt-[3',3''-dimethyl-2,2':5',2''-terthiophene]-5,5''-diyl) and STD-001 (Sumitomo Chemical), are used as the different types of organic semiconductor materials. A bulk heterostructure is realized by mixing each material with phenyl C61 butyric acid methyl ester ([6,6]-Phenyl-C ₆₁ -Butyric Acid Methyl Ester: PCBM) and forming a film. Furthermore, a polythiophene-based conductive polymer (PEDOT:PSS) and silver (Ag) are formed as the anode electrode 34. Although not shown, the organic photodiode is sealed with 1 μm-thick parylene, and a chromium and gold (Cr/Au) film is formed on the upper part as a contact pad for connection to a flexible printed circuit board 110 on which an analog front end (AFE) is mounted.

Parylene was used as the sealing film, but silicon dioxide (SiO2) or silicon oxynitride (SiON) may also be used. 10 nm of PEDOT:PSS and 80 nm of Ag were laminated as the anode electrode 34, but the film thickness may be in the range of 10 to 30 nm for PEDOT:PSS and 10 to 100 nm for Ag. Alternative materials for PEDOT:PSS include molybdenum oxide (MoOx), and alternative materials for Ag include aluminum (Al) and gold (Au). ZnO is formed on ITO for the cathode electrode 35, but polymers such as polyethyleneimine (PEI) and PEI ethoxylation (PEIE) may also be formed on ITO.

(OPD Formation Process)
The surface of the chip was subjected to O2 plasma treatment under conditions of 300 W and 10 seconds (sec). Next, a ZnO layer was formed under spin-coating conditions of 5000 rpm and 30 seconds (sec), and annealed at 180 ° C for 30 minutes (min). As an organic layer, a PMDPP3T: PCBM solution or a STD-001: PCBM solution was spin-coated on the ZnO surface at 250 rpm and 4 minutes, respectively. After that, a solution in which PEDOT: PSS (e.g., Al4083) was diluted with isopropyl alcohol (IPA) to (3:17) in a nitrogen atmosphere was filtered with a 0.45 μm PVDF filter, and then a film was formed by spin-coating under conditions of 2000 rpm and 30 seconds (sec). After film formation, annealing was performed in a nitrogen atmosphere at 80 ° C for 5 minutes (min). Finally, silver was vacuum-deposited to a thickness of 80 nm to form an anode electrode 34. After the device was completed, a 1 μm-thick parylene film was formed as a sealing film by a chemical vapor deposition (CVD) method, and Cr/Au was vacuum-deposited to form a contact pad.

The first optical sensor 30 formed by this process includes an active layer 31, which is an organic material layer having a photovoltaic effect, a cathode electrode 35 provided on the backplane BP side with the active layer 31 in between, and an anode electrode 34 provided on the opposite side of the cathode electrode 35 with the active layer 31 in between. The active layer 31 and the anode electrode 34 are continuous along the detection surface with respect to the cathode electrodes 35 of each of the multiple first optical sensors 30 arranged along the detection surface of the sensor unit 10 that is capable of detecting light (see FIG. 7). That is, the cathode electrodes 35 are independently provided in each first optical sensor 30, and the active layer 31 and the anode electrode 34 are continuous across the entire detection area AA.

Figure 8 is a graph that shows a schematic relationship between the wavelength of light incident on the first optical sensor and the conversion efficiency. The horizontal axis of the graph shown in Figure 8 is the wavelength of light incident on the first optical sensor 30, and the vertical axis is the external quantum efficiency of the first optical sensor 30. The external quantum efficiency is expressed, for example, as the ratio between the photon number of light incident on the first optical sensor 30 and the current flowing from the first optical sensor 30 to the external detection circuit 48.

As shown in FIG. 8, the first optical sensor 30 has good efficiency in a wavelength band of about 300 nm to 1000 nm. That is, the first optical sensor 30 has sensitivity from the visible light wavelength region to the infrared light wavelength region, for example. Therefore, even if the lighting device 121 irradiates light L1 of different wavelength regions depending on the detection target, a single first optical sensor 30 can detect multiple lights having different wavelengths.

Next, an example of the operation of the detection device 1 will be described. FIG. 9 is a timing waveform diagram showing an example of the operation of the detection device. As shown in FIG. 9, the detection device 1 has a reset period Prst, an effective exposure period Pex, and a readout period Pdet. The power supply circuit 103 supplies a sensor power supply signal VDDSNS to the anode of the first optical sensor 30 throughout the reset period Prst, the effective exposure period Pex, and the readout period Pdet. The sensor power supply signal VDDSNS is a signal that applies a reverse bias between the anode and cathode of the first optical sensor 30. For example, a reference signal COM of substantially 0.75V is applied to the cathode of the first optical sensor 30, but by applying a sensor power supply signal VDDSNS of substantially -1.25V to the anode, the anode and cathode are reverse biased at substantially 2.0V.

After setting the reset signal RST2 to "H", the control circuit 102 supplies a start signal STV and a clock signal CK to the gate line driving circuit 15, starting the reset period Prst. During the reset period Prst, the control circuit 102 supplies a reference signal COM to the reset circuit 17 and turns on the fourth switching element TrR for supplying a reset voltage by the reset signal RST2. As a result, the reference signal COM is supplied to each signal line SGL as a reset voltage. The reference signal COM is set to, for example, 0.75 V.

In the reset period Prst, the gate line driving circuit 15 sequentially selects the gate lines GCL based on the start signal STV, the clock signal CK, and the reset signal RST1. The gate line driving circuit 15 sequentially supplies the gate driving signals Vgcl {Vgcl(1), ..., Vgcl(M)} to the gate lines GCL. The gate driving signal Vgcl has a pulse-like waveform having a power supply voltage VDD, which is a high-level voltage, and a power supply voltage VSS, which is a low-level voltage. In FIG. 9, M (e.g., M=256) gate lines GCL are provided, and the gate driving signals Vgcl(1), ..., Vgcl(M) are sequentially supplied to each gate line GCL, and the first switching elements Tr are sequentially turned on for each row, and a reset voltage is supplied. For example, the voltage of 0.75 V of the reference signal COM is supplied as the reset voltage.

As a result, during the reset period Prst, the capacitive elements Ca in all partial detection areas PAA are sequentially electrically connected to the signal line SGL and the reference signal COM is supplied. As a result, the capacitance of the capacitive elements Ca is reset. Note that it is also possible to reset the capacitance of some of the capacitive elements Ca in the partial detection area PAA by partially selecting the gate lines GCL and signal lines SGL.

Examples of exposure timing include a gate line scanning exposure control method and a constant exposure control method. In the gate line scanning exposure control method, gate drive signals Vgcl(1), ..., Vgcl(M) are sequentially supplied to all gate lines GCL connected to the first optical sensor 30 to be detected, and a reset voltage is supplied to all first optical sensors 30 to be detected. After that, when all gate lines GCL connected to the first optical sensor 30 to be detected are at a low voltage (the first switching element Tr is off), exposure begins, and exposure is performed during the effective exposure period Pex. When exposure is completed, as described above, gate drive signals Vgcl(1), ..., Vgcl(M) are sequentially supplied to the gate lines GCL connected to the first optical sensor 30 to be detected, and reading is performed during the readout period Pdet.

In the constant exposure control method, it is also possible to control exposure during the reset period Prst and the readout period Pdet (constant exposure control). In this case, the effective exposure period Pex(1) starts after the gate drive signal Vgcl(M) is supplied to the gate line GCL. Here, the effective exposure periods Pex(1), ..., Pex(M) are periods during which the capacitance element Ca is charged from the first optical sensor 30.

Note that the actual effective exposure periods Pex(1), ..., Pex(M) in the partial detection area PAA corresponding to each gate line GCL have different start and end timings. Each of the effective exposure periods Pex(1), ..., Pex(M) starts when the gate drive signal Vgcl changes from the high-level voltage of the power supply voltage VDD to the low-level voltage of the power supply voltage VSS during the reset period Prst. Each of the effective exposure periods Pex(1), ..., Pex(M) ends when the gate drive signal Vgcl changes from the power supply voltage VSS to the power supply voltage VDD during the readout period Pdet. The length of the exposure time for each of the effective exposure periods Pex(1), ..., Pex(M) is equal.

In the gate line scanning exposure control method, during the effective exposure period Pex, a current flows in each partial detection area PAA according to the light irradiated to the first optical sensor 30. As a result, charge is accumulated in each capacitance element Ca.

Before the read period Pdet starts, the control circuit 102 sets the reset signal RST2 to a low-level voltage. This stops the operation of the reset circuit 17. Note that the reset signal may be at a high-level voltage only during the reset period Prst. During the read period Pdet, as in the reset period Prst, the gate line drive circuit 15 sequentially supplies gate drive signals Vgcl(1), ..., Vgcl(M) to the gate line GCL.

Specifically, the gate line driving circuit 15 supplies a gate driving signal Vgcl(1) of a high-level voltage (power supply voltage VDD) to the gate line GCL(1) during period V(1). The control circuit 102 sequentially supplies selection signals ASW1, ..., ASW6 to the signal line selection circuit 16 during the period in which the gate driving signal Vgcl(1) is at a high-level voltage (power supply voltage VDD). As a result, the signal lines SGL of the partial detection area PAA selected by the gate driving signal Vgcl(1) are sequentially or simultaneously connected to the detection circuit 48. As a result, the first detection signal Vdet is supplied to the detection circuit 48 for each partial detection area PAA.

Similarly, the gate line driving circuit 15 supplies high-level voltage gate driving signals Vgcl(2), ..., Vgcl(M-1), Vgcl(M) to the gate lines GCL(2), ..., GCL(M-1), GCL(M) during periods V(2), ..., V(M-1), V(M). That is, the gate line driving circuit 15 supplies the gate driving signal Vgcl to the gate line GCL during each period V(1), V(2), ..., V(M-1), V(M). During each period in which each gate driving signal Vgcl is at a high level voltage, the signal line selection circuit 16 sequentially selects the signal lines SGL based on the selection signal ASW. The signal line selection circuit 16 sequentially connects each signal line SGL to one detection circuit 48. As a result, during the readout period Pdet, the detection device 1 can output the first detection signal Vdet of all partial detection areas PAA to the detection circuit 48.

Figure 10 is a timing waveform diagram showing an example of operation during the readout period in Figure 9. Below, with reference to Figure 10, an example of operation during the supply period Readout of one gate drive signal Vgcl(j) in Figure 9 will be described. In Figure 9, the first gate drive signal Vgcl(1) is given the symbol for the supply period Readout, but the same is true for the other gate drive signals Vgcl(2), ..., Vgcl(M). j is a natural number from 1 to M.

10 and 5, the output (V _out ) of the third switching element TrS is reset in advance to a reference potential (Vref). The reference potential (Vref) is a reset voltage, for example, 0.75 V. Next, the gate drive signal Vgcl(j) goes high to turn on the first switching element Tr of the corresponding row, and the signal line SGL of each row goes to a voltage corresponding to the charge stored in the capacitance element Ca of the corresponding partial detection area PAA.

After a period t1 has elapsed since the rising edge of the gate drive signal Vgcl(j), a period t2 occurs during which the selection signal ASW(k) becomes high. When the selection signal ASW(k) becomes high and the third switching element TrS turns on, the output (V _out ) (see FIG. 5 ) of the third switching element TrS changes to a voltage corresponding to the charge stored in the capacitance element Ca due to the charge stored in the capacitance element Ca of the partial detection area PAA connected to the detection circuit 48 via the third switching element TrS (period t3).

In the example of Figure 10, this voltage drops from the reset voltage as shown in period t3. After that, when the switch SSW is turned on (period t4 when the SSW signal is at high level), the charge stored in the capacitance element Ca is transferred to the capacitance element Cb of the detection signal amplifier 42 of the detection circuit 48, and the output voltage of the detection signal amplifier 42 becomes a voltage according to the charge stored in the capacitance element Cb. At this time, the inverting input part of the detection signal amplifier 42 becomes the imaginary short potential of the operational amplifier, so it returns to the reference potential (Vref).

The output voltage of the detection signal amplifier 42 is read out by the A/D converter 43. In the example of FIG. 10, the waveforms of the selection signals ASW(k), ASW(k+1), ... corresponding to the signal lines SGL of each column go high to sequentially turn on the third switching elements TrS, and similar operations are sequentially performed to sequentially read out the charge accumulated in the capacitance elements Ca of the partial detection areas PAA connected to the gate line GCL. Note that ASW(k), ASW(k+1), ... in FIG. 10 are, for example, any of ASW1-6 in FIG. 9.

Specifically, when a period t4 occurs during which the switch SSW is on, charge moves from the capacitance element Ca in the partial detection area PAA to the capacitance element Cb of the detection signal amplifier 42 of the detection circuit 48. At this time, the non-inverting input (+) of the detection signal amplifier 42 is biased to a reference potential (Vref) (e.g., 0.75 V). Therefore, an imaginary short between the inputs of the detection signal amplifier 42 causes the output (V _out ) of the third switching element TrS to also become the reference potential (Vref).

Furthermore, the voltage of the capacitance element Cb is a voltage corresponding to the charge accumulated in the capacitance element Ca in the partial detection area PAA where the third switching element TrS is turned on in response to the selection signal ASW(k). After the output (V _out ) of the third switching element TrS becomes the reference potential (Vref) due to an imaginary short, the output of the detection signal amplifier 42 becomes a capacitance corresponding to the voltage of the capacitance element Cb, and this output voltage is read by the A/D converter 43. The voltage of the capacitance element Cb is, for example, the voltage between two electrodes provided in the capacitor that constitutes the capacitance element Cb.

Note that period t1 is, for example, 20 μs. Period t2 is, for example, 60 μs. Period t3 is, for example, 44.7 μs. Period t4 is, for example, 0.98 μs.

9 and 10 show an example in which the gate line driving circuit 15 selects the gate lines GCL individually, but this is not limiting. The gate line driving circuit 15 may simultaneously select a predetermined number of gate lines GCL (two or more) and sequentially supply the gate driving signal Vgcl to each of the predetermined number of gate lines GCL. The signal line selection circuit 16 may also simultaneously connect a predetermined number of signal lines SGL (two or more) to one detection circuit 48. Furthermore, the gate line driving circuit 15 may scan a plurality of gate lines GCL by thinning them out.

The detection device 1 can also detect fingerprints using electrostatic capacitance. Specifically, it uses a capacitance element Ca. First, all capacitance elements Ca are charged with a predetermined charge. Then, when a finger Fg touches the area, a capacitance corresponding to the unevenness of the fingerprint is added to the capacitance element Ca of each cell. Therefore, when the finger Fg is in contact, the capacitance indicated by the output from the capacitance element Ca of each cell can be read by the detection signal amplifier 42 and the A/D converter 43, similar to the acquisition of the output from each partial detection area PAA described with reference to Figures 9 and 10, to generate a fingerprint pattern. This method allows fingerprints to be detected using the electrostatic capacitance method. It is preferable to set the distance between the capacitance of the partial detection area PAA and the object to be detected, such as a fingerprint, to 100 um or more and 300 um or less.

Next, the configuration of the second optical sensor 50 will be described. FIG. 11 is a cross-sectional view taken along line XI-XI' in FIG. 2. As shown in FIG. 11, the second optical sensor 50 is provided on the same insulating substrate 21 as the first optical sensor 30. More specifically, the second optical sensor 50 is provided on the smoothing layer 29.

The second optical sensor 50 includes an inorganic material layer (semiconductor layer 51) having a photovoltaic effect. Specifically, the second optical sensor 50 includes a semiconductor layer 51, an anode electrode 54, and a cathode electrode 55. The cathode electrode 55, the semiconductor layer 51, and the anode electrode 54 are stacked in this order on the smooth layer 29. The semiconductor layer 51 is an inorganic semiconductor layer made of, for example, amorphous silicon (a-Si). Note that the semiconductor layer 51 is not limited to amorphous silicon, and may be, for example, polysilicon, or more preferably, LTPS.

The second optical sensor 50 is, for example, a PIN (Positive Intrinsic Negative Diode) type photodiode. Specifically, the semiconductor layer 51 includes an i-type semiconductor layer 51a, an n-type semiconductor layer 51b, and a p-type semiconductor layer 51c. The i-type semiconductor layer 51a, the n-type semiconductor layer 51b, and the p-type semiconductor layer 51c are a specific example of a photoelectric conversion element. In FIG. 11, in the direction perpendicular to the surface of the insulating substrate 21 (third direction Dz), the i-type semiconductor layer 51a is provided between the n-type semiconductor layer 51b and the p-type semiconductor layer 51c. In this embodiment, the n-type semiconductor layer 51b, the i-type semiconductor layer 51a, and the p-type semiconductor layer 51c are stacked in this order on the cathode electrode 55.

The p-type semiconductor layer 51c is formed by doping impurities into a-Si to form an n+ region. The n-type semiconductor layer 51b is formed by doping impurities into a-Si to form a p+ region. The i-type semiconductor layer 51a is, for example, a non-doped intrinsic semiconductor, and has lower conductivity than the p-type semiconductor layer 51c and the n-type semiconductor layer 51b.

The anode electrode 54 and the cathode electrode 55 are made of a translucent conductive material such as ITO (Indium Tin Oxide). The anode electrode 54 is an electrode for supplying a sensor power supply signal to the photoelectric conversion layer. The cathode electrode 55 is an electrode for reading out the second detection signal Vdet-R.

The anode electrode 54 is provided on the smooth layer 29a. An opening is provided in the smooth layer 29a in a region overlapping with the semiconductor layer 51, and the anode electrode 54 is connected to the semiconductor layer 51 through the opening in the smooth layer 29a. The cathode electrode 55 is provided on the smooth layer 29. The cathode electrode 55 is connected to the backplane BP through a contact hole H1 that penetrates the smooth layer 29.

The fifth switching element TrA connected to the second optical sensor 50 has a semiconductor layer 61, a gate electrode 62, a source electrode 63, and a drain electrode 64. A light-shielding film 67 is provided between the semiconductor layer 61 and the insulating substrate 21. The cathode electrode 55 of the second optical sensor 50 is connected to the source electrode 63 via the connection wiring 63s. The cross-sectional structure of the fifth switching element TrA is similar to that of the first switching element Tr described above in FIG. 7, so a detailed description is omitted. Note that the fifth switching element TrA is not limited to being provided in the same layer as the first switching element Tr, and may be formed in a layer different from the first switching element Tr.

Figure 12 is a circuit diagram showing the drive circuit of the second optical sensor. As shown in Figure 12, the gate of the fifth switching element TrA is connected to the gate line GCL-R. The source of the fifth switching element TrA is connected to the signal line SGL-R. The drain of the fifth switching element TrA is connected to the cathode electrode 55 of the second optical sensor 50 and one end of the capacitance element Cr. The anode electrode 54 of the second optical sensor 50 and the other end of the capacitance element Cr are connected to a reference potential, for example, ground potential.

The sixth switching element TrA1 and the seventh switching element TrA2 are connected to the signal line SGL-R. The sixth switching element TrA1 and the seventh switching element TrA2 are elements that constitute a drive circuit that drives the fifth switching element TrA. The sixth switching element TrA1 and the seventh switching element TrA2 are composed of, for example, CMOS (complementary MOS) transistors that combine a p-channel transistor p-TrA2 and an n-channel transistor n-TrA2.

In this embodiment, the drive circuit of the second optical sensor 50 is provided in the peripheral area GA. The drive circuit of the second optical sensor 50 is provided separately from the gate line drive circuit 15 and the signal line selection circuit 16, and the control circuit 102 can drive the second optical sensor 50 independently of the first optical sensor 30. However, the drive circuit of the second optical sensor 50 may be shared with the gate line drive circuit 15 and the signal line selection circuit 16. In addition, the control circuit 102 may drive the second optical sensor 50 in synchronization with the first optical sensor 30.

When light is irradiated onto the second optical sensor 50, a current flows through the second optical sensor 50 according to the amount of light irradiated thereto, and thus a charge is accumulated in the capacitance element Cr. When the fifth switching element TrA is turned on, a current flows through the signal line SGL-R according to the charge accumulated in the capacitance element Cr. The signal line SGL-R is connected to the detection circuit 48 via the seventh switching element TrA2. This allows the detection device 1 to detect a signal according to the amount of light irradiated onto the second optical sensor 50 as the second detection signal Vdet-R. The driving method of the second optical sensor 50 (the reset period Prst, the effective exposure period Pex, and the readout period Pdet) is also the same as that of the partial detection area PAA of the first optical sensor 30 described above, and a detailed description thereof will be omitted.

FIG. 13 is an explanatory diagram for explaining the relationship between the first detection signal output from the first optical sensor and the second detection signal output from the second optical sensor. As shown in FIG. 13, the detection device 1 simultaneously drives the multiple first optical sensors 30 and the second optical sensors 50 at the first time point T-st. The first detection signal Vdet and the second detection signal Vdet-R at the first time point T-st are detection signals when the same object to be detected (e.g., a finger Fg) is detected by the multiple first optical sensors 30 and the second optical sensor 50, respectively. In addition, the first detection signal Vdet may be an individual first detection signal Vdet output from each of the multiple first optical sensors 30, or may be an average value of the multiple first detection signals Vdet.

The signal processing unit 44 calculates a signal ΔV1 that is the difference between the first detection signal Vdet and the second detection signal Vdet-R at the first point in time T-st. The difference signal ΔV1 is stored in the memory unit 46. Note that the first point in time T-st is, for example, when the detection device 1 is started up, and includes a case where the power is turned on from an off state, a case where the detection device 1 returns from a sleep mode, etc.

The detection device 1 simultaneously drives the first optical sensors 30 and the second optical sensors 50 at a second time point T-stx, which is a predetermined period after the first time point T-st. The signal processing unit 44 calculates a signal ΔV2 that is the difference between the first detection signal Vdet and the second detection signal Vdet-R at the second time point T-stx.

The control circuit 102 compares the difference signal ΔV2 with the difference signal ΔV1 and calculates the difference ΔV3 (=|ΔV2-ΔV1|) between the difference signal ΔV2 and the difference signal ΔV1. If the difference ΔV3 is equal to or greater than a predetermined value, the control circuit 102 determines that the first detection signal Vdet has changed due to aging of the first optical sensor 30, etc., even when the same object is detected under the same conditions.

When a change occurs in the first detection signal Vdet, the control circuit 102 changes the drive conditions of the first optical sensor 30 so that the difference ΔV3 becomes smaller than a predetermined value, that is, so that the difference signal ΔV2 approaches the difference signal ΔV1. For example, the control circuit 102 can adjust the first detection signal Vdet by changing the sensor power supply signal VDDSNS of the first optical sensor 30 or by changing the length of the effective exposure period Pex. Alternatively, the control circuit 102 may correct the digital data supplied from the A/D conversion unit 43 in the signal processing unit 44.

Note that in FIG. 13, for ease of understanding, the detection signals at the first time point T-st and the second time point T-stx are illustrated as examples, but the detection device 1 may drive the second optical sensor 50 in any manner. For example, the detection device 1 may constantly drive the second optical sensor 50 in synchronization with the first optical sensor 30. Alternatively, the detection device 1 may drive the second optical sensor 50 every time it is started, or may drive the second optical sensor 50 every one or more frame periods, where the period during which the first optical sensor 30 detects the entire detection area AA is defined as one frame period.

As described above, the detection device 1 of this embodiment has a substrate (insulating substrate 21), a plurality of first optical sensors 30, and at least one or more second optical sensors 50. The plurality of first optical sensors 30 are provided in the detection area AA of the substrate, and include an organic material layer (active layer 31) having a photovoltaic effect. The second optical sensor 50 is provided on the substrate, and includes an inorganic material layer (semiconductor layer 51) having a photovoltaic effect.

Even if the first detection signal Vdet changes due to deterioration over time of the first optical sensor 30 using an organic material, the second optical sensor 50 using an inorganic material has less change over time than the first optical sensor 30. In other words, the change over time of the second detection signal Vdet-R is much smaller than the change over time of the first detection signal Vdet. This allows the detection device 1 to detect the change in the first detection signal Vdet based on the second detection signal Vdet-R from the second optical sensor 50 using an inorganic material. The detection device 1 can suppress the change in the first detection signal Vdet by adjusting the drive of the first optical sensor 30 or adjusting the signal processing in the detection unit 40. This allows the detection device 1 to suppress the deterioration of detection performance.

In addition, in the detection device 1, the multiple first optical sensors 30 are arranged in a matrix in the detection area AA, and one second optical sensor 50 is arranged in the peripheral area GA of the substrate. This allows for more precise detection than when the second optical sensor 50 is provided in the detection area AA. In addition, since one second optical sensor 50 is provided, the circuit size of the peripheral circuit provided in the peripheral area GA can be reduced.

In FIG. 2 and other figures, the multiple first optical sensors 30 and the second optical sensor 50 are substantially rectangular in plan view, but are not limited thereto. The multiple first optical sensors 30 and the second optical sensor 50 may be other shapes, such as polygonal or circular. In addition, the circuits for driving the multiple first optical sensors 30 shown in FIGS. 4 and 5 and the second optical sensor 50 shown in FIG. 12 are merely examples, and can be modified as appropriate.

Second Embodiment
Fig. 14 is a plan view showing a detection device according to the second embodiment. Note that the same components as those described in the first embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted. As shown in Fig. 14, the detection device 1A according to the second embodiment has a plurality of second optical sensors 50.

The second optical sensors 50 are provided in the peripheral area GA and are arranged along at least one side of the detection area AA. More specifically, the second optical sensors 50 are arranged in a frame shape surrounding the four sides of the detection area AA. The second optical sensors 50 are provided between the gate line driving circuit 15 and the detection area AA. The second optical sensors 50 are also provided between the signal line selection circuit 16 and the detection area AA.

The gate line GCL-R (see FIG. 12) connected to the second optical sensor 50 may be connected to the gate line driving circuit 15. In addition, the signal line SGL-R (see FIG. 12) connected to the second optical sensor 50 may be connected to the signal line selection circuit 16.

In this embodiment, the control circuit 102 can compare the first detection signal Vdet and the second detection signal Vdet-R output from the nearby first optical sensor 30 and the second optical sensor 50. For example, the control circuit 102 can divide the detection area AA and the surrounding area GA into multiple areas and compare the first detection signal Vdet and the second detection signal Vdet-R for each area.

The detection device 1A can compare the first optical sensor 30 and the second optical sensor 50 arranged nearby, and therefore can accurately detect changes in the first detection signal Vdet due to aging or other factors of the first optical sensor 30. The control circuit 102 may also calculate the average of the multiple second detection signals Vdet-R output from the multiple second optical sensors 50, and use the average value of the multiple second detection signals Vdet-R as a reference for the first detection signal Vdet.

The arrangement of the second optical sensors 50 is not limited to the example shown in FIG. 14. For example, the second optical sensors 50 are not limited to a configuration surrounding the four sides of the detection area AA, and may not be arranged along one side of the detection area AA. The arrangement pitch of the second optical sensors 50 and the arrangement pitch of the first optical sensors 30 are the same, but may be different. That is, the number of the second optical sensors 50 arranged along the second direction Dy may be different from the number of the first optical sensors 30 arranged along the second direction Dy. The number of the second optical sensors 50 arranged along the first direction Dx may be different from the number of the first optical sensors 30 arranged along the first direction Dx.

Third Embodiment
Fig. 15 is a plan view showing a detection device according to the third embodiment. As shown in Fig. 15, the detection device 1B according to the third embodiment has a plurality of second optical sensors 50. The plurality of first optical sensors 30 and the plurality of second optical sensors 50 are provided in a detection area AA. The plurality of first optical sensors 30 and the plurality of second optical sensors 50 are alternately arranged along the first direction Dx and alternately arranged along the second direction Dy in the detection area AA.

In other words, in a plan view perpendicular to the insulating substrate 21, the second optical sensor 50 is provided between the first optical sensors 30 adjacent to each other in the first direction Dx. Also, the second optical sensor 50 is provided between the first optical sensors 30 adjacent to each other in the second direction Dy.

The gate line GCL-R and the signal line SGL-R are provided in the detection area AA along the gate line GCL and the signal line SGL, respectively. The gate line GCL-R is connected to the gate line driving circuit 15. The signal line SGL-R is connected to the signal line selection circuit 16. The signal line selection circuit 16 may connect a selected signal line SGL-R of the multiple signal lines SGL-R to the detection circuit 48, similar to the signal line SGL.

In this embodiment, a reference second optical sensor 50 is associated with each of the multiple first optical sensors 30. This allows for accurate monitoring of changes over time in the multiple first optical sensors 30. In addition, the gate line driving circuit 15 and the signal line selection circuit 16 can be used in common as the driving circuit for the second optical sensor 50, making it possible to reduce the circuit scale of the peripheral circuits. In addition, since the second optical sensors 50 are arranged in a matrix in the detection area AA, the second detection signal Vdet-R may be used to detect biological information.

In FIG. 15, the multiple first optical sensors 30 and the multiple second optical sensors 50 are arranged alternately one by one in the first direction Dx, but this is not limited to this. One second optical sensor 50 may be provided for multiple first optical sensors 30 (e.g., two or more and several tens or less).

Fourth Embodiment
16 is a plan view showing a detection device according to the fourth embodiment. As shown in FIG. 16, the detection device 1C according to the fourth embodiment has one second optical sensor 50 provided in the detection area AA. More specifically, the second optical sensor 50 is provided to cover the entire area of the detection area AA. The first optical sensors 30 are arranged in a matrix shape, overlapping with the one second optical sensor 50. In addition, the gate lines GCL and the signal lines SGL provided corresponding to the first optical sensors 30 are also arranged to overlap with the one second optical sensor 50.

The second optical sensor 50 may be connected to at least one of the gate line driving circuit 15 and the signal line selection circuit 16. Alternatively, the second optical sensor 50 may be electrically connected to the detection circuit 48 and the control circuit 102 via a connection wiring provided in the peripheral area GA, without going through the gate line driving circuit 15 and the signal line selection circuit 16.

Figure 17 is a cross-sectional view taken along line XVII-XVII' in Figure 16. Figure 17 is a cross-sectional view showing an enlarged portion of the detection device 1C. Figure 17 shows a simplified configuration of the backplane BP, but the backplane BP is provided with first switching elements Tr corresponding to each first optical sensor 30, as in Figure 7. The backplane BP is also provided with a fifth switching element TrA corresponding to the second optical sensor 50.

As shown in FIG. 17, the multiple first optical sensors 30 and the second optical sensor 50 are provided on the same insulating substrate 21. The multiple first optical sensors 30 are provided on the second optical sensor 50. More specifically, the second optical sensor 50 is provided on the first smooth layer 29-1. A cathode electrode 55, a semiconductor layer 51, and an anode electrode 54 are stacked in this order on the first smooth layer 29-1. The cathode electrode 55 is connected to the backplane BP via a contact hole that penetrates the first smooth layer 29-1.

The second smooth layer 29-2 is provided to cover the second optical sensor 50. The multiple first optical sensors 30 are provided on the second smooth layer 29-2. The cathode electrode 35, active layer 31, and anode electrode 34 are stacked in this order on the second smooth layer 29-2. The cathode electrodes 35 are arranged to be spaced apart from each of the multiple first optical sensors 30. In other words, in a plan view, the cathode electrodes 35 are arranged in a matrix. The active layer 31 and anode electrode 34 are provided continuously to cover the multiple cathode electrodes 35.

The second optical sensor 50 has an opening H50 at a position overlapping each of the first optical sensors 30. The cathode electrodes 35 of the first optical sensors 30 are connected to the backplane BP via contact holes that penetrate the second smoothing layer 29-2, the opening H50, and the first smoothing layer 29-1.

With this configuration, the second optical sensor 50 can detect light that has passed through the multiple first optical sensors 30. Since the second optical sensors 50 are provided throughout the entire detection area AA, even if the amount of light passing through each of the first optical sensors 30 is small, the sensitivity of the second optical sensor 50 as a whole can be improved. Furthermore, since the multiple first optical sensors 30 and the second optical sensor 50 are provided overlapping each other, there are fewer restrictions on the arrangement of the multiple first optical sensors 30 in a planar view. In other words, even if the second optical sensor 50 is provided in the detection area AA, the detection device 1C can ensure the light receiving area of the first optical sensor 30 or ensure the resolution of the first optical sensor 30.

(Modification)
18 is a plan view showing a detection device according to a modification of the fourth embodiment. The detection device 1D according to the modification of the fourth embodiment has a plurality of second optical sensors 50 provided in the detection area AA. The second optical sensors 50 are arranged in a matrix in the detection area AA. The plurality of first optical sensors 30 are arranged in a matrix, overlapping one second optical sensor 50. In the example shown in FIG. 18, nine first optical sensors 30 are provided overlapping one second optical sensor 50. However, this is not limited thereto, and ten or more first optical sensors 30 may be provided overlapping one second optical sensor 50, for example, several tens of first optical sensors 30 may be provided.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention.

1, 1A, 1B, 1C, 1D Detector 10 Sensor section 15 Gate line driving circuit 16 Signal line selection circuit 17 Reset circuit 21 Insulating substrate 30 First optical sensor 31 Active layer 34, 54 Anode electrode 35, 55 Cathode electrode 48 Detection circuit 50 Second optical sensor 51 Semiconductor layer 51a i-type semiconductor layer 51b n-type semiconductor layer 51c p-type semiconductor layer 101 Control substrate 102 Control circuit 103 Power supply circuit AA Detection area GA Peripheral area GCL, GCL-R Gate line SGL, SGL-R Signal line Tr First switching element

Claims (6)

A substrate;
a plurality of first optical sensors provided in a detection region of the substrate, the first optical sensors including an organic material layer having a photovoltaic effect;
At least one second optical sensor provided on the substrate, the second optical sensor including an inorganic material layer having a photovoltaic effect ;
The first optical sensors are arranged in a matrix in the detection area,
The second optical sensor is disposed in the peripheral region of the substrate.
Detection device. A substrate;
a plurality of first optical sensors provided in a detection region of the substrate, the first optical sensors including an organic material layer having a photovoltaic effect;
a plurality of second optical sensors provided on the substrate and including an inorganic material layer having a photovoltaic effect;
The first optical sensors are arranged in a matrix in the detection area,
The second optical sensors are provided in a peripheral region of the substrate and are arranged along at least one side of the detection region.
Detection device. A substrate;
a plurality of first optical sensors provided in a detection region of the substrate, the first optical sensors including an organic material layer having a photovoltaic effect;
a plurality of second optical sensors provided on the substrate and including an inorganic material layer having a photovoltaic effect;
The first optical sensors and the second optical sensors are alternately arranged along a first direction in the detection area.
Detection device. The detection device according to claim 1 , wherein the inorganic material layer is an inorganic semiconductor layer made of amorphous silicon. a control circuit for controlling detection of the first optical sensors and the second optical sensors;
5. The detection device according to claim 1, wherein the control circuit controls detection by the first optical sensors based on a change in a differential signal between a first detection signal output from the first optical sensor and a second detection signal output from the second optical sensor. A substrate;
a plurality of first optical sensors provided in a detection region of the substrate, the first optical sensors including an organic material layer having a photovoltaic effect;
At least one second optical sensor is provided on the substrate and includes an inorganic material layer having a photovoltaic effect;
a control circuit for controlling detection of the first optical sensors and the second optical sensors;
The control circuit controls detection by the first optical sensors based on a change in a signal that is a difference between a first detection signal output from the first optical sensor and a second detection signal output from the second optical sensor.
Detection device.

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