JP7423577B2 - gaming machine - Google Patents

Description

The present invention relates to a gaming machine on which games can be played.

As a gaming machine such as a pachinko gaming machine, there is a gaming machine that manages various random numbers using hard random numbers and soft random numbers (for example, Patent Document 1).

Patent No. 6124313

The gaming machine described in Patent Document 1 has room for improvement in updating the random value.

This invention has been made in view of the above-mentioned circumstances, and aims to provide a gaming machine that can appropriately update random numbers.

In order to achieve the above object, the gaming machine according to the present invention:
A gaming machine capable of playing games,
a game control means for controlling the game;
a first updating means capable of updating the first random number value and the second random number value using a random number clock signal;
a second updating means capable of updating the third random number value by random number updating processing;
The game control means performs a first maximum value setting process for setting a random number maximum value of the first random number values when setting a stored value in the storage area by a start-up process executed based on the start of power supply. is executable, and is capable of executing a second maximum value setting process of setting a random number maximum value of the second random number value,
The first updating means starts updating the first random number value when the random number maximum value of the first random number values is set in the first maximum value setting process , and starts updating the first random number value in the second maximum value setting process. Starting to update the second random number by setting the maximum random number of the second random number,
The game control means executes the first maximum value setting process to start updating the first random value, and executes the first maximum value setting process to start updating the first random value. After that, execute the second maximum value setting process to start updating the second random value,
The second updating means can start updating the third random number value after updating the first random number value and updating the second random number value are started.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, the random number circuit 104 or the CPU 103 that executes the random number updating process P_RANDOM. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC or the normal symbol process P_FPROC. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The startup process may be, for example, the main process P_MAIN for game control. The maximum value setting process may be, for example, steps AKS11 to AKS13 in the power supply start support process P_POWER_ON. The first random number may be, for example, random numbers MR1-1, MR3-2, etc. The second random number may be, for example, random numbers MR3-3, MR3-4, etc. The first updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The third random number may be, for example, random numbers MR1-2, MR2-1, etc. The random number update process may be, for example, random number update process P_RANDOM. The second updating means may be, for example, the CPU 103 that executes the random number updating process P_RANDOM in step S56. To start updating the first random number value, for example, use the function setting register storage value table AKT01 to set the maximum value to the 16-bit random number circuit channel RL0 with channel number "0" and the 16-bit random number circuit channel RL2 with channel number "2". It is sufficient if it is a part to be set. To start updating the second random value, for example, use the function setting register storage value table AKT01 to set the maximum value to the 8-bit random number circuit channels RS1 to RS3 of channel numbers "1" to "3". good. The update of the third random number value may be started by executing the random number update process P_RANDOM in step S56 in the game control timer interrupt process P_PCT after the power supply start corresponding process P_POWER_ON in step S1 is executed, for example. .
In such a configuration, uncertainty is increased by starting to update the random number MR1-1, etc., which is highly related to the gaming value, and it becomes possible to update the random number appropriately.

It is a front view of a pachinko game machine. FIG. 3 is a configuration diagram showing various control boards and the like. It is a figure showing an example of the random number for games. It is a flowchart showing main processing for game control. It is a flowchart showing an example of timer interrupt processing for game control. It is a flowchart showing an example of special symbol process processing. It is a diagram showing a configuration example of a special symbol process processing jump table. It is a flowchart which shows the main processing for production control. It is a flowchart etc. which shows an example of production control process processing. It is a diagram showing an example of the configuration of a game control microcomputer. FIG. 3 is a diagram showing an example of an address map. FIG. 7 is a diagram showing main setting examples of addresses included in a function setting register area. FIG. 3 is a diagram showing an example of main settings of addresses included in a function control register area. FIG. 3 is a diagram for explaining a setting example for gaming random numbers. FIG. 3 is a diagram for explaining a random number update cycle. 7 is a flowchart illustrating an example of a power supply start handling process. FIG. 3 is a diagram illustrating a configuration example of a function setting register storage value table. FIG. 3 is a diagram illustrating a configuration example of an RWM access protect register. It is a flowchart which shows an example of power-off processing. FIG. 3 is a diagram for explaining a usage example of a data structure. 3 is a flowchart illustrating an example of random number update processing. FIG. 3 is a diagram for explaining a usage example of a data structure. It is a flowchart which shows an example of initial value change random number update processing. It is a flowchart which shows an example of random number update processing for initial value determination. It is a flow chart which shows an example of starting port switch passage processing. FIG. 3 is a diagram for explaining a usage example of a data structure. It is a flowchart showing an example of special symbol normal processing. FIG. 3 is a diagram for explaining a usage example of a data structure. It is a flowchart showing an example of special symbol determination processing. FIG. 3 is a diagram for explaining a usage example of a data structure. It is a flowchart showing an example of special symbol information setting processing. It is a flowchart which shows an example of jackpot information data selection processing. FIG. 3 is a diagram for explaining a usage example of a data structure. FIG. 3 is a diagram for explaining a usage example of a data structure. 3 is a flowchart illustrating an example of a variation pattern setting process. It is a flowchart etc. which shows an example of a winning time fluctuation pattern type table selection process. It is a flowchart etc. which shows an example of a variation pattern classification table selection process at the time of a loss. FIG. 3 is a diagram for explaining a configuration example of a variation pattern type distribution table. FIG. 3 is a diagram for explaining a configuration example of a variation pattern distribution table. FIG. 3 is a diagram for explaining a configuration example of a variation pattern distribution table. FIG. 3 is a diagram for explaining a configuration example of a variation pattern distribution table. It is a flowchart etc. which shows an example of normal symbol process processing. FIG. 3 is a diagram for explaining a usage example of a data structure. 3 is a flowchart illustrating an example of gate switch passage processing. It is a flowchart showing an example of normal symbol normal processing. FIG. 3 is a diagram for explaining a usage example of a data structure.

(Basic explanation)
First, the basic configuration and control of the pachinko gaming machine 1 will be explained.

(Configuration of pachinko machine 1, etc.)
FIG. 1 is a front view of a pachinko gaming machine 1, showing the layout of the main components. A pachinko game machine (game machine) 1 is roughly divided into a game board (gauge board) 2 that constitutes a game board surface, and a game machine frame (base frame) 3 that supports and fixes the game board 2. A game area is formed on the game board 2, and a game ball as a game medium is fired from a predetermined ball launcher into this game area.

A first special symbol display device 4A and a second special symbol display device 4B are provided at predetermined positions on the game board 2. In the example shown in FIG. 1, it is provided on the right side of the gaming area. The first special symbol display device 4A and the second special symbol display device 4B are each capable of variably displaying special symbols as a plurality of types of special identification information. Special designs are also called "tokuzu." The variable display of special symbols is also called a "special symbol game." The first special symbol display device 4A and the second special symbol display device 4B are both configured using a 7-segment LED or the like. The special symbols are represented by numbers representing "0" to "9", symbols representing "-", and other arbitrary lighting patterns. The special design may include a pattern in which all LEDs are turned off.

"Variable display" of special symbols means, for example, displaying a plurality of types of special symbols in a variable manner. Regarding other symbols such as performance symbols, small symbols, and normal symbols, "variable display" similarly refers to displaying a plurality of types of symbols in a variable manner. The production design is also called a decorative design or a decorative design. The variable display is also referred to as a variable display or simply a fluctuation. Variations include updated display of a plurality of symbols, scrolling display of a plurality of symbols, deformation, enlargement, and reduction of one or more symbols. The variation may include a mode in which a certain symbol is displayed blinking. In the variable display of special symbols and ordinary symbols, a plurality of types of special symbols or ordinary symbols are displayed in an updateable manner. In the variable display of performance symbols, a plurality of types of performance symbols are scrolled or updated, and one or more performance symbols are deformed, enlarged, or reduced. In the variable display of arbitrary symbols, a predetermined symbol is finally displayed in a stopped state as a display result. The stop display is also called a lead-out display or simply a lead-out display. The symbol that is finally stopped and displayed in the variable display is also referred to as the final stop symbol or final symbol. The final stop symbol in a special pattern game is also called a confirmed special symbol. The display results of the variable display include the display results of special symbols, and are also referred to as variable display results. The display result of the special symbol is also referred to as the special symbol display result. The execution time of the variable display includes the special symbol variation time which is the variation time of the special symbol, and is also referred to as the variable display time. The special symbol variation time can be set to different times depending on the variation patterns of special symbols for which a plurality of patterns are prepared in advance.

The special symbol variably displayed on the first special symbol display device 4A is also referred to as a "first special symbol". The special symbol variably displayed on the second special symbol display device 4B is also referred to as a "second special symbol". A special map game using the first special map is also referred to as a "first special map game." A special map game using the second special map is also referred to as a "second special map game." The number of special symbol display devices that perform variable display of special symbols may be one type.

A normal symbol display 20 is provided at a predetermined position on the game board 2. In the example shown in FIG. 1, it is provided on the left side of the gaming area. The normal symbol display device 20 can variably display normal symbols as multiple types of normal identification information different from special symbols. Ordinary designs are also called ``fuzu''. The variable display of ordinary symbols is also called a "general symbol game." The normal symbol display 20 is constructed using a 7-segment LED or the like. The normal symbols are represented by numbers representing "0" to "9", symbols representing "-", and other arbitrary lighting patterns. The normal pattern may include a pattern in which some or all of a plurality of LEDs are turned on, and a pattern in which all of a plurality of LEDs are turned off. The final stop symbol in a regular pattern game is also called a fixed normal symbol. The display result of the normal pattern is also referred to as the normal pattern display result. The execution time during which the normal symbols are variably displayed in the general pattern game is also referred to as the normal pattern fluctuation time. The ordinary symbol fluctuation time can be set to different times in correspondence with the fluctuation patterns of the ordinary symbols for which a plurality of patterns are prepared in advance.

An image display device 5 is provided near the center of the game area on the game board 2. The image display device 5 may be configured using, for example, an LCD (liquid crystal display), an organic EL (electro luminescence), a dot matrix LED, a projector and a screen, a stereoscopic image projection device, or any other mechanism capable of forming an arbitrary image. Bye. The image display device 5 is capable of displaying various effect images. Furthermore, the image display device 5 is not limited to performance images, and can display any control-related images such as inspection images and setting images.

For example, on the screen of the image display device 5, variable display of production symbols can be executed in synchronization with the first special symbol game and the second special symbol game. The production pattern is a display pattern that shows numbers, etc., and is a plurality of types of decorative identification information different from the special pattern and the normal pattern. On the screen of the image display device 5 shown in FIG. In synchronization with the game, the performance symbols are displayed in a variable manner by, for example, being scrolled up and down or updated. The synchronization of the variable display may be such that the timing at which the variation of the symbol starts and the timing at which the variation ends and the symbol is finally stopped and displayed are common timings for different types of symbols. . The final stop symbol in the variable display of performance symbols is also referred to as a determined performance symbol, a determined decorative symbol, or a determined decorative symbol. Since the variable display of the production symbols is synchronized with the first special symbol game and the second special symbol game, the variable display time of the production symbols is the same as the special symbol fluctuation time.

A display area may be provided on the screen of the image display device 5 in which effect images corresponding to the pending display and the active display can be displayed. The pending display is a display corresponding to a variable display that has not been executed yet and is on hold. The active display is a display corresponding to the variable display being executed. The pending display and the active display are also collectively referred to as a variable display compatible display corresponding to the variable display. The display area where the hold display is performed is also referred to as the hold display area. A display area where active display is performed is also referred to as an active display area. The number of pending variable displays is also referred to as the number of pending memories. The number of pending memories corresponding to the first special figure game is also referred to as the first number of pending memories. The number of pending memories corresponding to the second special figure game is also referred to as the second number of pending memories. The total value of the first number of pending memories and the second number of pending memories is also referred to as the total number of pending memories.

Above the first special symbol display device 4A and the second special symbol display device 4B shown in FIG. . The first hold display 25A displays the number of first hold memories based on the number of lit LEDs. The second hold display 25B displays the second hold storage number based on the number of lit LEDs. Above the normal symbol display 20 shown in FIG. 1, a normal symbol holding display 25C including a plurality of LEDs is provided. The ordinary figure holding display 25C displays the number of ordinary figures held stored by the number of LEDs lit. The number of reserved memories of common figures is the number of reserved memories corresponding to the common figure game.

Below the image display device 5, a winning ball device 6A and a variable winning ball device 6B are provided. The winning ball device 6A forms a first starting winning opening which is always kept in a constant open state into which game balls can enter, for example, by a predetermined ball receiving member. The variable prize winning ball device 6B serves as a normal electric accessory and forms a second starting winning opening that can be changed between a closed state and an open state by a normal electric accessory solenoid 81 shown in FIG. The variable prize winning ball device 6B includes, for example, an electric tulip-shaped accessory having a pair of movable wing pieces, and when the normal electric accessory solenoid 81 is in the OFF state, the movable wing pieces are in the vertical position, thereby causing the second start. The winning opening is in a closed state in which game balls do not enter, or the second start winning opening is in a normal open state in which it is difficult for game balls to enter. In the variable winning ball device 6B, when the normal electric accessory solenoid 81 is in the ON state, the movable wing pieces are in the tilted position, so that the second starting prize opening is in an open state in which a game ball can enter or the second starting winning opening is in an open state where a game ball can enter. The mouth is in an enlarged open state where game balls can easily enter. The open state in which the game ball can enter the second starting prize opening and the enlarged open state in which it is easy to enter are also referred to as the first variable state. The closed state in which game balls do not enter the second starting prize opening and the normal open state in which it is difficult to enter are also referred to as the second variable state. The variable winning ball device 6B may be any device that can change between the first variable state and the second variable state, and is not limited to one that includes an electric tulip type accessory.

Entering the game ball into the first starting winning hole formed by the winning ball device 6A is also referred to as a first starting winning. Entering the game ball into the second starting winning hole formed by the variable winning ball device 6B is also referred to as a second starting winning. The game ball that has entered the first starting winning opening is detected by the first starting opening switch 22A shown in FIG. The game ball that has entered the second starting winning opening is detected by the second starting opening switch 22B shown in FIG. Based on the occurrence of the first starting prize, a predetermined number of prize balls, for example three, are paid out, and the first reserved memory number can be updated by one. However, when the number of first reserved memories has reached the upper limit number, even if the first starting winning occurs, the first number of reserved memories is not updated. Corresponding to the case where the first pending storage number is incremented by 1, the first starting condition is satisfied, and the first special symbol game in which the special symbols are variably displayed by the first special symbol display device 4A becomes executable. Based on the occurrence of the second starting prize, a predetermined number of prize balls, for example three, are paid out, and the second pending memory number can be updated by one. However, when the second pending memory number has reached the upper limit number, the second pending memory number is not updated even if a second starting winning occurs. Corresponding to the case where the second pending storage number is incremented by 1, the second starting condition is satisfied, and the second special symbol game in which special symbols are variably displayed by the second special symbol display device 4B becomes executable.

A general prize opening 10 is provided at a predetermined position on the game board 2, and is always kept in a constant open state by a predetermined ball receiving member. In the example shown in FIG. 1, general winning holes 10 are provided at two locations on the lower left side of the gaming area. When a game ball enters any of the general winning holes 10, a predetermined number of prize balls, for example 10, are paid out.

In the game area formed by the game board 2, a first route and a second route are provided as downstream routes for the game balls to flow down. The first path is mainly provided in an area to the left of the image display device 5 when viewed from the front. The second path is mainly provided in an area on the right side of the image display device 5 when viewed from the front. The left side area of the image display device 5 is also referred to as a left side gaming area or a left gaming area. The right area of the image display device 5 is also referred to as a right side gaming area or a right gaming area. The left side game area and the right side game area may be separated by, for example, the end face of the image display device 5 in the game area, the arrangement of game nails, or the like. Shooting the game ball toward the left side game area in order to cause the game ball to flow down the first path is also called left-handed hitting. Shooting the game ball toward the right side game area in order to cause the game ball to flow down the second path is also called right-handed hitting. The first route is also referred to as a left-handed batting route. The second route is also referred to as a right-handed batting route. The first route and the second route may be configured as different routes, or may be partially shared routes.

A game ball is ejected from the ball launcher and driven into a game area in response to an operation of a ball operation handle provided on the ball launcher. When the game ball hit in the game area is guided to the left side game area and flows down the first path, it is guided along the array of game nails, for example, and is guided to the second path in the right side game area. Impossible or difficult to guide. When the game ball hit in the game area is guided to the right side game area and flows down the second path, it is guided along the arrangement of the game nails, for example, so that it does not flow to the first path in the left side game area. Impossible or difficult to guide.

The winning ball device 6A is provided on the first route in the left side gaming area, and game balls flowing down the first route can enter. The variable prize winning ball device 6B is provided on the second route in the right side game area, and allows the game balls flowing down the second route to enter. In addition, the variable prize winning ball device 6B may allow the game balls flowing down the first route in the left side game area to enter. The variable prize winning ball device 6B may be arranged so that the game balls flowing down the second route in the right side gaming area can more easily enter than the game balls flowing down the first route in the left side gaming area.

A passage gate 41 and a special variable winning ball device 50 are provided on the second route in the right side gaming area. The passage gate 41 forms a passage area through which game balls can pass. The game ball that has passed through the passage gate 41 is detected by the gate switch 21 shown in FIG. Based on the game ball passing through the passage gate 41, it becomes possible to add and update the number of normal reserved memories, and it becomes possible to perform variable display of normal symbols by the normal symbol display 20 as a normal symbol game. The passage gate 41 can be configured as a normal symbol operation opening into which game balls can enter. In this case, the gate switch 21 can be configured as a normal symbol operating port switch that can detect a game ball that has entered the normal symbol operating port.

The special variable winning ball device 50 forms a big winning hole that can be changed between a closed state and an open state by a big winning hole solenoid 82 as a special electric accessory. The upper part of the special variable winning ball device 50 is formed with a guide passage having a passage width in the front and back direction to the extent that the game balls can pass through. This guide path slopes downward from the right side to the left side, and walls are provided on the front side and the back side on both sides of the extended passage. In the center of the guide path, there is formed an access entrance that serves as a big prize opening. In the special variable winning ball device 50, a movable member 52 movable in the front and back direction is provided as a big winning hole opening/closing member at a position where the big winning hole can be opened and closed. In the special variable winning ball device 50, a fixed member 53 that forms a fixed passage is provided in a portion of the guiding passage where the big winning opening is not formed.

The movable member 52 is driven by the big prize opening solenoid 82, and can move forward and backward to open and close the accessory entrance which becomes the big prize opening. In the special variable winning ball device 50, the game ball that enters the inside from the big winning hole is detected by the count switch 23. Inside the special variable winning ball device 50, a V winning area 51, which is a specific area, is provided as a winning area through which game balls can pass. Further, inside the special variable winning ball device 50, a normal area different from the V winning area 51 is provided. A plate-shaped distribution member that can switch the V winning area 51 between an open state and a closed state is provided above the V winning area 51 as a V winning opening opening/closing member. The distribution member is driven by the specific area solenoid 83 and can move forward and backward to open and close the V winning area 51. A game ball can pass through the V winning area 51 when it is in an open state, and a game ball cannot pass through it when it is in a closed state. The game ball that has passed through the V winning area 51 is detected by the specific area switch 24. The game ball that does not pass through the V winning area 51 passes through the normal area. The game balls that have passed through the V winning area 51 and the gaming balls that have passed through the normal area without passing through the V winning area 51 are both detected by the ejection port switch 26 and then released outside the special variable winning ball device 50. is discharged to.

In addition to the above structure, the surface of the game board 2 is provided with a windmill that changes the downward direction and speed of the game ball and a large number of obstacle nails. At the bottom of the gaming area, there is provided an out opening into which game balls that have not entered any of the winning openings are taken in. Speakers 8L and 8R for reproducing and outputting sound effects, etc. are provided at the left and right upper positions of the gaming machine frame 3, and game effect lamps 9 for lighting effects are provided around the gaming area. There is. The game effect lamp 9 includes an LED. A movable body 32 is provided at a predetermined position on the game board 2 to operate according to the performance.

At the lower right position of the gaming machine frame 3, there is provided a ball-striking operation handle that is operated by a player or the like in order to fire a game ball toward the gaming area using a ball-striking device. The batting operation handle is also referred to as an operation knob. At a predetermined position of the gaming machine frame 3 below the gaming area, there is a batting ball that holds game balls paid out as prize balls and game balls lent out by a predetermined ball lending machine so as to be able to be supplied to the batting ball firing device. A feeding tray is provided. The batted ball supply tray is also called an upper tray. A prize ball storage tray is provided below the upper tray, in which prize balls dispensed when the upper tray is full flow down and are stored. The prize ball storage tray is also called the lower tray.

At a predetermined position of the gaming machine frame 3 below the gaming area, a stick controller 31A and a push button 31B are provided. The stick controller 31A can be held and tilted by the player, and is provided with a trigger button that can be pushed or pulled by the player. An operation on the stick controller 31A is detected by a controller sensor unit 35A shown in FIG. The push button 31B can be pressed by the player. An operation on push button 31B is detected by push sensor 35B shown in FIG. In the pachinko game machine 1, the stick controller 31A and the push buttons 31B are used as detection means for detecting actions such as operations by the player, but detection means other than these may be used.

(Summary of game progress)
When a player rotates a ball-hitting operation handle provided in the pachinko game machine 1, a game ball is launched toward a game area. When the game ball passes through the passage gate 41, the normal pattern display 20 starts the normal pattern game. In addition, if the game ball passes through the passing gate 41 during the period when the previous Fuzu game is being executed, the Fuzu game based on the passage cannot be executed immediately, so the Fuzu game based on the passage cannot be executed immediately. , for example, up to a predetermined upper limit number such as "4". In the common pattern game, when a specific normal symbol, such as a common pattern winning symbol, is stopped and displayed as a confirmed normal symbol, the display result of the normal symbol becomes "common pattern winning". On the other hand, when a normal symbol other than the normal pattern winning pattern, such as a normal pattern loss pattern, is stopped and displayed as a confirmed normal pattern, the display result of the normal pattern becomes "normal pattern loss". When it is a "normal map hit", opening control is performed to bring the variable winning ball device 6B into an open state or an enlarged open state for a predetermined period of time. At this time, the second starting prize opening is in an open state or an enlarged open state.

When the game ball passes through and enters the first starting prize opening formed in the winning ball device 6A, the first special symbol game by the first special symbol display device 4A can be started. When the game ball passes through and enters the second start winning hole formed in the variable winning ball device 6B, the second special symbol game by the second special symbol display device 4B can be started. In addition, even if the game ball enters the starting prize opening and a starting prize occurs during the period when the special drawing game is being executed or during the period when the jackpot game state or the small winning game state is controlled, the corresponding prize will not be awarded. Since the special figure game based on the starting winning cannot be executed immediately, the special drawing game based on the starting winning is suspended until a predetermined upper limit number such as "4" is reached, for example. In the special symbol game, when a specific special symbol such as a jackpot symbol is stopped and displayed as a confirmed special symbol, the display result of the special symbol becomes a "jackpot". On the other hand, when a predetermined special symbol different from the jackpot symbol, such as a small prize symbol, is stopped and displayed as a confirmed special symbol, the display result of the special symbol becomes a "small prize". Further, when a special symbol different from a jackpot symbol or a small prize symbol, such as a losing symbol, is stopped and displayed as a confirmed special symbol, the display result of the special symbol becomes "losing". Furthermore, when a special symbol different from a jackpot symbol, small prize symbol, or loss symbol, such as a time-saving symbol, is stopped and displayed as a confirmed special symbol, the display result of the special symbol may become "time-saving". . The special symbol may not include a time-saving symbol. That is, the display result of the special symbol may not include "time saving".

In the special pattern game, after the display result of the special pattern becomes a "jackpot", the game is controlled to a jackpot game state as an advantageous state for the player. In the jackpot game state, the jackpot formed in the special variable winning ball device 50 can be opened in a predetermined manner. The open state at this time is until the timing when a predetermined period elapses, such as 29 seconds or 1.8 seconds, or the timing when the number of game balls that have entered the grand prize opening reaches a predetermined number, whichever is earlier. Continued. The predetermined period in which the big winning hole can be controlled to be open is the upper limit period during which the big winning hole can be opened in one round, and is also referred to as the upper limit opening period. One cycle in which the jackpot opening is open in the jackpot game state is called a round or a round game. In the jackpot game state, such rounds can be repeated until a predetermined upper limit number of times is reached, such as 15 times or 2 times. In the jackpot game state, the player can obtain a prize ball by entering the game ball into the jackpot opening. Therefore, the jackpot gaming state is an advantageous state advantageous to the player. The greater the number of rounds in the jackpot game state and the longer the open upper limit period, the more advantageous it becomes to the player.

When the display result of the special symbol is a "jackpot", it includes a plurality of jackpot types. For example, the opening mode of the big winning opening such as the number of rounds and the upper limit opening period, and the gaming state after the end of the jackpot gaming state such as the normal state, time saving state, and variable probability state can be set in multiple types, and the jackpot can be set according to each setting. Type is specified. The plurality of jackpot types may include some or all of the jackpot types that can get many prize balls, the jackpot types that can get few prize balls, or the jackpot types that can hardly get any prize balls. Alternatively, the prize balls that can be obtained may include jackpot types of the same degree. Being controlled to a jackpot gaming state based on the display result of a special symbol being a "jackpot" is also referred to as a symbol jackpot, a special symbol jackpot, a variable display jackpot, or a direct jackpot.

In the special pattern game, after the display result of the special pattern becomes a "small win", the game is controlled to a small win game state. In the small winning game state, the large winning opening formed in the special variable winning ball device 50 can be opened in a predetermined opening manner. For example, in the small winning game state, the big winning opening may be opened in the same manner as the jackpot gaming state in some jackpot types. It is sufficient that the big prize openings can be opened in the same manner by sharing the number of openings and the opening period. Alternatively, in the small winning gaming state, the big winning opening may be opened in a different opening manner from that in the jackpot gaming state. Similar to the jackpot type, a plurality of small hit types may be included even when the display result of the special symbol is a "small hit." The jackpot type and the small hit type are also collectively referred to as the hit type. The operation of opening and closing the big prize opening in the small winning game state is also referred to as the starting operation. When in the small winning game state, when the accessory entrance which becomes the big winning opening of the special variable winning ball device 50 is opened and the game ball passes through the V winning area 51 and is detected by the specific area switch 24, The conditions for generating a jackpot are established, and it becomes possible to control the jackpot game state. The fact that the game ball is controlled to the jackpot game state based on the occurrence of a V winning by passing through the V winning area 51 in the small winning gaming state is also referred to as a jackpot via small winning.

After the jackpot gaming state ends, the gaming state can be controlled to a time saving state or a variable probability state in accordance with the jackpot type. Further, in the special figure game, after the display result of the special symbol becomes "time saving", the gaming state is not controlled to the jackpot gaming state but is controlled to the time saving state. The time saving state is a gaming state in which the second special symbol game by the second special symbol display device 4B is more easily executed than in the normal state. A game state in which the second special figure game is more likely to be executed than in the normal state is a game state in which the game ball is more likely to pass through and enter the second starting prize opening than in the normal state. The control of whether or not the game ball can easily pass through the second starting prize opening is also referred to as base control. Base control in the normal state is also referred to as normal base control or low base control. The base control in the time saving state includes high base control. In addition to high base control, the time saving state may include medium base control. The medium base control is a base control in which the game ball is easier to pass through the second starting prize opening than the low base control, but it is more difficult for the game ball to pass through the second starting winning opening than the high base control. The gaming state in which the medium base control is performed is also referred to as the medium base state. The gaming state in which high base control is performed is also referred to as a high base state. High base control is also referred to as high open control.

In the normal state, the medium base state, and the high base state, the time-saving symbol can be stopped and displayed as a result of displaying the special symbol. However, in the case of the medium base state and the case of the high base state, even if the time saving symbol is stopped and displayed as a result of displaying the special symbol, the base control based on the time saving symbol is not performed, and the medium base state or the high base state No new control to transition to the high base state is initiated. In the time saving state, time saving control is possible in which the average variable display time is made shorter than in the normal state. Accordingly, the time saving state is also referred to as a time saving state.

The time saving state is a state in which the variation efficiency of special symbols, especially the second special symbol, is improved, so it is included in special states that are advantageous for the player and are different from the jackpot gaming state. When the gaming state is in a variable probability state, in addition to time saving control, variable probability control is possible in which the probability that the display result of the special symbol will be a "jackpot" is higher than in the normal state. As a result, the probability variable state is also referred to as the probability variable state. In addition to improving the variation efficiency of special symbols, the variable probability state is a state in which a "big hit" is likely to occur, so it is included in special states that are advantageous for the player and are different from the jackpot gaming state. The time saving state and the variable probability state continue until any one of predetermined end conditions is satisfied first, such as the execution of the special figure game a predetermined number of times or the control to the next jackpot game state. A condition where the termination condition is that the special figure game has been executed a predetermined number of times is also called a number-of-time cut. The time-saving state where the number of times is cut is also referred to as the time-saving state where the number of times is cut. The number-cut definite variable state is also called the number-cut definite variable.

The gaming state that becomes the normal state is a gaming state that is not included in an advantageous state such as a jackpot gaming state that is advantageous to the player, a predetermined state such as a small winning gaming state, or a special state such as a time saving state or a variable probability state. In the normal state, the probability that the displayed result in the general drawing game is a "normal drawing hit", the probability that the displayed result in the special drawing game is a "jackpot", etc. is controlled to be the same as the initial setting state of the pachinko gaming machine 1. It is in a gaming state. The initial setting state of the pachinko game machine 1 is a control state after the initial setting process is executed without executing a predetermined recovery process after the power is turned on, such as when a system reset is performed, for example.

A state in which variable probability control is being executed is also referred to as a high probability state, and a state in which variable probability control is not executed is also referred to as a low probability state. A state in which time saving control is being executed is also referred to as a high base state, and a state in which time saving control is not being executed is also referred to as a low base state. Combining these, the time-saving state is also called a low-probability high-base state, the variable-probability state is a high-probability high-base state, and the normal state is called a low-probability low-base state. The high certainty state and low base state is also referred to as the high certainty low base state. Note that the pachinko gaming machine 1 may not include a variable probability state as a gaming state.

After the small winning gaming state ends, there are cases where the gaming state is controlled to the jackpot gaming state based on the occurrence of a V winning, and cases where the gaming state before the small winning gaming state is not changed without a V winning occurring. be. However, if the display result of the special figure game becomes a "small win" and the special figure game is executed a predetermined number of times in the number cut, the control of the time saving state and variable probability state may end and the state returns to the normal state. . Note that the pachinko gaming machine 1 may not include a small winning gaming state as a gaming state. That is, the display result of the special symbol may not include a "small hit".

It may be possible to control the gaming state to a time saving state when a time saving condition based on the number of executions of the variable display is satisfied. This time-saving state is also called relief time-saving. The time saving condition is that even if variable display is performed a specific number of times, a new jackpot game state or Any condition may be satisfied as long as it can be satisfied when control to the time saving state is not performed.

(Progress of production, etc.)
The pachinko game machine 1 can perform various effects as the game progresses. This performance includes a performance that notifies the progress of the game and a performance that makes the game more exciting. These effects include displaying various effect images on the image display device 5, outputting sound effects from the speakers 8L and 8R, lighting the game effect lamp 9, operating the movable body 32, and controlling the stick controller. It may include vibrating the push button 31A or the push button 31B, or a combination of some or all of these, as long as it can be executed using any production device.

Performances that can be executed as the game progresses include variable display of performance symbols. In response to the start of the first special figure game or the second special figure game, "left", "middle", and "right" production symbol display areas 5L provided on the screen of the image display device 5, At 5C and 5R, variable display of performance symbols is started. When the confirmed special symbol that becomes the display result in the first special symbol game or the second special symbol game is stopped and displayed, the confirmed performance symbol that becomes the display result in the variable display of the performance symbol is stopped and displayed. The confirmed performance symbols are composed of a combination of three performance symbols corresponding to the "left", "middle", and "right" performance symbol display areas 5L, 5C, and 5R. During the period from the start to the end of the variable display of performance symbols, the display mode in the variable display of performance symbols may become a ready-to-reach mode. The reach mode is a mode in which when the effect symbols that have stopped on the screen of the image display device 5 constitute a part of the jackpot combination, the effect symbols that have not yet stopped continue to fluctuate. . The fact that the display mode in the variable display of the performance symbols becomes the ready-to-reach mode is also said to be established.

A ready-to-win presentation can be executed in response to the variable display of the presentation symbol being in a ready-to-win mode. The pachinko game machine 1 is capable of executing a plurality of types of ready-to-win performances such that when the performance modes are different, the percentage of the display result of the variable display being a "jackpot" is different. The proportion of "jackpots" corresponding to the performance mode is also referred to as jackpot reliability or jackpot expectation. The reach performance includes, for example, normal reach and super reach, which has higher jackpot reliability than normal reach. In addition, it may include a short reach and a long reach whose execution time is longer than the short reach, depending on the execution time of the reach effect.

When the display result of the special symbol becomes a "jackpot", confirmed performance symbols forming a predetermined jackpot combination are stopped and displayed on the screen of the image display device 5 as the display result of the performance symbol. As an example, in the "left", "middle", and "right" production symbol display areas 5L, 5C, and 5R, the same production symbols, such as a production symbol showing the number "7", are aligned and are on a predetermined effective line. will stop appearing. In the case of a "probable variable jackpot" which is controlled to a variable probability state after the end of the jackpot game state, odd-numbered performance symbols such as performance symbols showing the number "7" may be stopped and displayed all together. In the case of a "non-probable variable jackpot" which is not controlled to a variable probability state after the end of the jackpot game state, even-numbered performance symbols such as performance symbols showing the number "6" may be stopped and displayed all together. The "non-probable jackpot" is also referred to as the "normal jackpot." In this case, the odd-numbered production pattern is also referred to as a variable probability pattern. Even-numbered production symbols are also called non-probable variations or regular symbols. After reaching the reach mode with non-probability variable symbols, a promotion performance that ultimately becomes a "probability variable jackpot" may be executed.

When the display result of the special symbol becomes a "small win", confirmed performance symbols that form a predetermined small win combination are stopped and displayed as the display result of the performance symbol on the screen of the image display device 5. As an example, in the "left", "middle", and "right" production symbol display areas 5L, 5C, and 5R, the same production symbols, such as production symbols indicating numbers other than "7", are aligned and a predetermined effective line is displayed. It may be displayed stopped above. A common confirmed performance pattern may be stopped and displayed when the display result of the special pattern becomes a "big hit" and a "small win."

When the display result of a special symbol is a "lose", the display result may be stopped and displayed without becoming a ready-to-win mode in the variable display of the production symbol. In this case, as a display result of the performance symbols, the confirmed performance symbols of the non-reach combination are stopped and displayed. A display result in which the fixed effect pattern of a non-reach combination is stopped and displayed without becoming a reach mode is also referred to as a non-reach loss. When the display result of the special symbol is a "lose", the variable display of the effect symbol becomes a ready-to-win mode, and the display result may be stopped and displayed after the ready-to-reach effect is executed. In this case, as a display result of the performance symbols, the confirmed performance symbols of the ready-to-win combinations that are not the jackpot combination or the small win combination are stopped and displayed. The display result in which the fixed effect design of the reach combination is stopped and displayed after reaching the reach mode is also referred to as reach loss.

The performances that can be executed by the pachinko gaming machine 1 include displays corresponding to variable displays such as a pending display and an active display. In addition, for example, a preview performance that foretells the jackpot reliability can be executed while the performance symbols are being displayed variably. The preview performance includes a variable preview performance that foretells the jackpot reliability that corresponds to the variable display that is being executed, and a look-ahead preview performance that foretells the jackpot reliability that corresponds to the variable display that is pending before execution. May include. The pre-read preview effect may be a change effect that changes the display mode of a variable display compatible display such as a hold display or an active display to a different mode than usual.

On the screen of the image display device 5, by temporarily stopping the performance design during the variable display of the performance design and then restarting the variable display, one variable display can be pseudo-like multiple variable display. It may also be possible to perform a pseudo-coupling effect that makes it look like this. The pseudo-continuous performance may be set so that the jackpot reliability is higher when the number of re-variations in which the variable display is restarted after temporarily stopping the performance symbol is greater than when the number of re-variations is small. . The variable display of performance symbols may include a case where a pseudo-continuous performance is executed before the ready-to-win mode is reached, and a case where a pseudo-continuous presentation is executed after the ready-to-win mode is achieved. In addition, in the variable display of the performance symbols, it may be possible to execute the pseudo continuous performance at a plurality of timings.

While controlling the jackpot game state, it is possible to execute a jackpot performance for notifying the jackpot game state. The jackpot performance may include a performance that notifies the number of rounds, and a promotion performance that suggests or notifies that the advantage of the jackpot game state will improve. While controlling the small winning game state, it is possible to execute a small winning performance for notifying the small winning gaming state. By executing a common effect while controlling the jackpot gaming state and the small winning gaming state, the player can determine whether the current gaming state is a jackpot gaming state or a small winning gaming state. It may be made unrecognizable or difficult to recognize.

In a non-gaming state in which a special figure game or the like is not being executed and the game is not in progress, a demonstration image can be displayed on the screen of the image display device 5. The performance image for demonstration is also referred to as a demo image. Displaying a demo image is also referred to as demo display. Performances based on demonstration displays are also referred to as customer-waiting demonstration performances.

(Substrate configuration)
The pachinko game machine 1 is equipped with a main board 11, an effect control board 12, an audio control board 13, a lamp control board 14, a relay board 15, a power supply board 17, etc. as shown in FIG. 2, for example. In addition, various other boards are arranged on the back of the pachinko game machine 1, such as a payout control board, an information terminal board, and a firing control board.

The main board 11 is a main side control board, and has a function of controlling the progress of the game in the pachinko game machine 1. The progress of the game is the execution of various games and game states, such as the execution of a special figure game with pending management, the execution of a general figure game with pending management, jackpot game state, small win game state, time saving state, variable probability state, etc. including migration. The main board 11 includes a game control microcomputer 100, a switch circuit 110, and a solenoid circuit 111.

The game control microcomputer 100 provided on the main board 11 is, for example, a one-chip microcomputer, and includes a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, a CPU (Central Processing Unit) 103, and a random number. It can be configured to include a circuit 104 and an I/O (Input/Output port) 105. Part or all of the ROM 101, RAM 102, and random number circuit 104 may have a configuration that can be externally attached to the game control microcomputer 100, or may have a configuration that is built in the game control microcomputer 100. good. The switch circuit 110 takes in detection signals from various switches for detecting game balls and transmits them to the game control microcomputer 100. Various switches for game ball detection include, for example, a gate switch 21, starting ports switches such as a first starting port switch 22A and a second starting port switch 22B, a count switch 23, a specific area switch 24, and a discharge port switch 26. The detection signal indicates that a game ball has passed or entered and a switch has been turned on. The transmission of the detection signal means that the passage or entry of the game ball has been detected. The solenoid circuit 111 can supply a solenoid drive signal from the game control microcomputer 100 to the normal electric accessory solenoid 81, the big prize opening solenoid 82, and the specific area solenoid 83. The solenoid drive signal may be any signal that turns on each solenoid.

The ROM 101 included in the game control microcomputer 100 is a nonvolatile storage device that stores computer programs and data used for game control. The data stored in the ROM 101 includes variable patterns, performance control commands, and other various settings, judgments, and table data constituting a table used for determination. The RAM 102 included in the game control microcomputer 100 is a temporary storage device that provides a work area used for game control and a stack for saving data. The RAM 102 may be a backup RAM that saves the storage contents in part or all of the storage area so that they can be restored within a predetermined period even if the power supply to the pachinko gaming machine 1 is stopped. The RAM 102 is also called RWM (Read/Write Memory). The work area of the RAM 102 includes a storage area that can store various data used for game control, such as counters, timers, buffers, and other storage areas for various codes and numerical values. The CPU 103 included in the game control microcomputer 100 can control the progress of the game in the pachinko game machine 1 by executing processes corresponding to programs stored in the ROM 101.

A random number circuit 104 included in the game control microcomputer 100 updatesably counts numerical data indicating various random numbers used when controlling the progress of the game. The random numbers used to control the progress of the game are also referred to as gaming random numbers. A part or all of the gaming random numbers may be updated by hardware using a dedicated circuit, or may be updated by software such as a computer program executed by the CPU 103.

FIG. 3 shows an example of random numbers for gaming. The random numbers for gaming are random number MR1-1 for special symbol determination, random number MR1-2 for winning symbols, random number MR1-3 which becomes the initial value for winning symbols, and random number MR2-1 for symbols per normal symbol. , a random number MR2-2 that becomes the initial value for the symbol per normal symbol, a random number MR3-1 for the normal symbol variation pattern, a random number MR3-2 for selecting a losing effect, and a random number MR3-3 for selecting the variation pattern type. , random numbers MR3-4 for the fluctuation pattern.

The random number MR1-1 for special symbol judgment determines the display result of the special symbol, such as whether or not to make the display result of the special symbol a "big hit" or not, and whether or not to make the display result of the special symbol a "small hit." Used for judgment. Random numbers MR1-2 for winning symbols are used to select confirmed special symbols, such as jackpot symbols when the display result of a special symbol is changed to a "jackpot" or small win symbols when the display result of a special symbol is changed to a "small win." Used to select from multiple special symbols. The random number MR1-3, which is the initial value for the winning symbol, is used to set the initial value of the random number MR1-2. The random number MR2-1 for symbols per normal symbol is used to select a confirmed normal symbol to be displayed from a plurality of normal symbols when the display result is "per ordinary symbol" in the variable display of the normal symbol. The random number MR2-2, which is the initial value for each symbol, is used to set the initial value of the random number MR2-1. The random number MR3-1 for the normal symbol variation pattern is used to determine the variation pattern of the normal symbol to one of a plurality of patterns prepared in advance. The random number MR3-2 for selecting a loss performance is used to select whether or not to take the ready-to-win mode in the variable display of performance symbols when the display result of the special symbol is a "loss". The random number MR3-3 for selecting the variation pattern type is used to select the variation pattern type of the special symbol. The special symbol variation pattern type is a group in which the special symbol variation patterns are classified in advance based on, for example, the performance mode during variable display of the production symbol, and is configured to include one or more variation patterns. Bye. The random number MR3-4 for the variation pattern is used to select the variation pattern of the special symbol.

The CPU 103 reads out and refers to various tables from the ROM 101 when making various judgments and decisions based on random numerical values, such as numerical data indicating the value of random numbers for gaming. Even when random numbers are not used, necessary tables may be read out from the ROM 101 and referred to to perform various judgments, decisions, settings, etc.

The I/O 105 included in the game control microcomputer 100 includes an input port to which various signals are input, and an output port to which various signals are output. The various signals input to the input port of the I/O 105 may include detection signals from various switches transmitted via the switch circuit 110. Various signals output from the output port of the I/O 105 include a first special symbol display device 4A, a second special symbol display device 4B, a normal symbol display 20, a first reservation display 25A, a second reservation display 25B, It suffices if it includes a signal for controlling the ordinary figure holding display 25C, etc., and a solenoid drive signal for driving the ordinary electric accessory solenoid 81, the big prize opening solenoid 82, the specific area solenoid 83, etc.

The main board 11 outputs, by the game control microcomputer 100, a performance control command according to the progress of the game to the performance control board 12 as part of the operation for controlling the progress of the game. The performance control command is a command that specifies or notifies the progress of the game. The production control command output from the main board 11 is relayed by the relay board 15 and supplied to the production control board 12. The production control commands include commands that specify various decision results on the main board 11, such as display results of special drawing games, winning types, and fluctuation patterns; Any command may be used as long as it includes a command that specifies the gaming situation, such as the occurrence of an error, the number of pending memories, and the gaming status, and a command that specifies the occurrence of an error.

The production control board 12 is a sub-side control board independent of the main board 11, and has a function of receiving production control commands and controlling production based on the received production control commands. The performances that can be controlled by the performance control board 12 are various performances according to the progress of the game, such as driving the movable body 32, and also include various notifications such as error notification and power failure recovery notification. The production control board 12 includes a production control CPU 120, a ROM 121, a RAM 122, a display control section 123, a random number circuit 124, and an I/O 125.

The effect control CPU 120 executes a program stored in the ROM 121 to perform processing for controlling the execution of the effect together with the display control unit 123. This process is a process for realizing various functions of the effect control board 12, and includes determining the effect to be executed. The performance control CPU 120 uses various data stored in the ROM 121, such as data on various tables, and also uses the RAM 122 as a main memory. The performance control CPU 120 may instruct the display control unit 123 to execute the performance based on detection signals from the controller sensor unit 35A and the push sensor 35B. The detection signal here is a signal that is output when an operation by the player is detected, and may be any signal that appropriately indicates the content of the operation.

The display control unit 123 includes a VDP (Video Display Processor), a CGROM (Character Generator ROM), a VRAM (Video RAM), etc., and mainly executes effects related to display based on instructions to execute effects from the effect control CPU 120. control possible. The display control unit 123 displays the effect image on the screen of the image display device 5 by supplying the image display device 5 with a video signal corresponding to the effect to be executed. The display control unit 123 further supplies a sound designation signal to the audio control board 13 and a lamp signal to the lamp control board 14. The sound designation signal designates the sound to be output from the speakers 8L and 8R. The lamp signal specifies the lighting mode and extinguishing mode of the game effect lamp 9. By supplying the sound designation signal and the lamp signal, it becomes possible to output audio from the speakers 8L and 8R and to turn on or off the game effect lamp 9 in synchronization with the display of the effect image. The display control unit 123 may be able to supply a signal for operating the movable body 32 to a motor or a solenoid of the movable body 32 or to a driver circuit that drives the movable body 32. Separately from the production control board 12, a driver board for driving the movable body 32 may be provided.

The random number circuit 124 updatesably counts numerical data indicating various random numbers used when controlling the execution of various effects. The random numbers used to control the execution of the performance are also referred to as performance random numbers. The random number for presentation may be updated by software such as a computer program executed by the presentation control CPU 120. The performance control CPU 120 reads out and refers to various tables from the ROM 121 when making various judgments and decisions based on random numerical values, such as numerical data indicating the value of the random number for performance. Even when random numbers are not used, the performance control CPU 120 may read out and refer to necessary tables from the ROM 121 to perform various judgments, decisions, settings, and the like.

The I/O 125 includes, for example, an input port for receiving production control commands transmitted from the main board 11, and an output port for transmitting various signals. The input port of the I/O 125 may include an input terminal for a detection signal supplied from the controller sensor unit 35A and an input terminal for a detection signal supplied from the push sensor 35B. The output port of the I/O 125 is an output terminal for a video signal supplied to the image display device 5, an output terminal for a sound designation signal supplied to the audio control board 13, and an output terminal for a lamp signal supplied to the lamp control board 14. It is sufficient if it includes an output terminal.

The audio control board 13 is equipped with various circuits that drive the speakers 8L and 8R, and drives the speakers 8L and 8R based on the sound designation signal from the display control unit 123, and outputs the sound specified by the sound designation signal to the speaker. Output from 8L and 8R. The lamp control board 14 is equipped with various circuits for driving the game effect lamp 9, and drives the game effect lamp 9 based on a lamp signal from the display control unit 123, and operates the game effect lamp in a manner specified by the lamp signal. Turn 9 on or off. In this way, the audio output from the speakers 8L and 8R and the lighting and extinguishing of the game effect lamp 9 can be controlled based on the signal from the display control section 123. Note that the control of the movable body 32, such as the supply of sound designation signals and lamp signals, the control of audio output and lighting and extinguishing of lamps, and the supply of signals for operating the movable body 32, are partially performed by the performance control CPU 120. Or all of them may be executed. Boards other than the main board 11, such as the production control board 12, the audio control board 13, and the lamp control board 14, are also referred to as subboards. As in the configuration example shown in FIG. 2, a plurality of sub-boards may be provided for each function, or unlike the configuration example shown in FIG. 2, one sub-board may be configured to have multiple functions. good.

The power supply board 17 can supply power from an alternating current power source such as AC 100V in an external power source such as a commercial power source to electrical components including various control boards such as the main board 11 and the production control board 12. The power supply board 17 includes, for example, a rectifier circuit for converting alternating current (AC) into direct current (DC), a power supply circuit for converting a predetermined direct current voltage into a specific direct current voltage (for example, 12 V direct current, 5 V direct current, etc.), etc. We are prepared. The pachinko game machine 1 can switch between starting and ending power-on by operating the power switch 91. A reset signal, a power-off signal, and a clear signal from the power supply board 17 are taken into the switch circuit 110 of the main board 11 and transmitted to the game control microcomputer 100. The reset signal is an operation stop signal for stopping the operation of a control circuit such as the game control microcomputer 100, and can be output using either a power supply monitoring circuit, a watchdog timer built-in IC, or a system reset IC. Good to have. The power-off signal becomes an OFF state when a predetermined power supply voltage used in the pachinko game machine 1 exceeds a predetermined value, and becomes an ON state when a period in which the predetermined power supply voltage is below a predetermined value continues for a power-off reference time or longer. Become. The clear signal is turned on, for example, when a clear switch 92 provided on the power supply board 17 is pressed.

(motion)
Next, the operation (function) of the pachinko gaming machine 1 will be explained.

(Main operations of main board 11)
First, the main operations of the main board 11 will be explained. When power supply to the pachinko game machine 1 is started, the game control microcomputer 100 is activated, and the CPU 103 executes main processing for game control.

FIG. 4 is a flowchart showing the main processing P_MAIN for game control executed by the CPU 103 on the main board 11. When the main process P_MAIN for game control shown in FIG. 4 is started, the CPU 103 executes the power supply start corresponding process P_POWER_ON (step S1), and then executes the RWM check process P_RWM_CHK (step S2). The power supply start corresponding process P_POWER_ON in step S1 can perform initial settings of the game control microcomputer 100 and the like in response to the start of power supply to the pachinko game machine 1. Initial settings of the game control microcomputer 100 may include initialization of output ports, settings of interrupt vectors, settings of built-in device registers, and settings of specific registers. The RWM check process P_RWM_CHK in step S2 includes a checksum calculation process, and the checksum data obtained as a result of the process is compared with the data stored in the checksum buffer, and if both data match, the data stored in the RAM 102 is The content is determined to be normal.

Subsequently, it is determined whether a predetermined recovery condition is satisfied (step S3). The recovery conditions can be established when the clear signal corresponding to the operation of the clear switch 92 is in an off state, the checksum buffer has normal stored data, and the stored contents in the RAM 102 as a backup RAM are normal. . For example, if the clear switch 92 provided on the power supply board 17 is pressed down when the pachinko game machine 1 is powered on, a clear signal in an on state is input to the game control microcomputer 100. If such an on-state clear signal is input, it may be determined in step S3 that the recovery condition is not satisfied. The checksum buffer stores checksum data calculated in a checksum calculation process when a backup determination time is measured by a backup monitoring timer at the previous power-off. If the measured value of the backup monitoring timer does not match the specific value corresponding to the backup determination time, it may be determined in step S3 that the recovery condition is not satisfied. The backup data may be data stored in a game work area in the RAM 102, which serves as a backup RAM for game control. In step S3, it may be determined whether the recovery conditions can be satisfied based on the results of checking or inspecting the presence or absence of backup data, the presence or absence of data errors, etc. by the RWM check process P_RWM_CHK of step S2.

If the recovery condition is satisfied (step S3; Yes), backup setting processing P_BACKUP_SET is executed (step S4). The backup time setting process P_BACKUP_SET uses the backup time command transmission table to enable the production control command corresponding to the backup time to be transmitted from the main board 11 to the production control board 12. Further, the backup setting process P_BACKUP_SET enables initialization by clearing the process code, timer, counter, and flag specified by the backup setting table.

If the recovery condition is not satisfied (step S3; No), initialization setting processing P_INIT_SET is executed (step S5). The initialization setting process P_INIT_SET enables clear data to be transferred to the game work area which becomes the work area in the RAM 102. As a result, the game work area in the RAM 102 is initialized. The initialization setting process P_INIT_SET uses the initialization command transmission table to enable the production control command corresponding to the initialization to be transmitted from the main board 11 to the production control board 12. Further, the initialization setting process P_INIT_SET enables initialization by clearing the buffer, timer, pointer, and counter specified by the initialization setting table.

Thereafter, control start setting processing P_STACON is executed (step S6). The control start setting process P_STACON may include wait processing. The wait process ensures that sub-boards such as the effect control board 12 can be activated by executing a loop process and waiting until a set standby time elapses. Further, the control start setting process P_STACON may include a specific number of times command transmission process or a chip individual number information command transmission process. The specific number of times command transmission process enables the main board 11 to transmit the effect control command that specifies the count value of the specific number of times counter when the power is turned on to the effect control board 12. The specific number of times counter may be provided at a predetermined address in the RAM 102 and can count the remaining number of times until the number of executions of the variable display reaches a specific number corresponding to the time saving condition. The chip individual number information command transmission process enables the main board 11 to transmit the performance control command specifying the stored value of the chip individual number register to the performance control board 12. The chip individual number register may be included in the built-in register of the game control microcomputer 100, as long as it can store different values assigned to each chip as the chip individual number.

The control start setting process P_STACON may include processing outside the startup area. The startup-time out-of-area process is a process that is executed by reading a program stored in the non-gaming program area of the ROM 101 in response to the start of power supply to the pachinko gaming machine 1. The out-of-area processing at startup may be, for example, performance display RWM initial value setting processing. The performance display RWM initial value setting process enables setting of initial values for initial display by the 7-segment LEDs forming the performance display monitor. The performance display monitor may be mounted on the main board 11, for example, and can display content related to set values and content related to the base. The setting value can be changed to any one of multiple stages, for example 6 stages, when the pachinko gaming machine 1 is in a setting change state where the settings can be changed, and the probability that the display result of the special symbol will be a "jackpot" be configurable. The base is calculated by dividing the number of prize balls paid out when the game balls pass through each winning hole, such as the starting prize hole, general prize hole, and big prize hole, by the number of game balls fired into the gaming area. Calculated.

After the control start setting process P_STACON in step S6, timer interrupt counter setting is performed (step S7). In step S7, the PTC counter output value is set so that a regular timer interrupt occurs at predetermined intervals of, for example, 4 [ms (milliseconds)]. After that, the main process P_MAIN for game control enters a loop process. In this loop processing, interrupts are disabled (step S8), initial value determination random number update processing P_TFINIT is executed (step S9), and after executing loop outside area processing P_REGOUT (step S10), interrupts are enabled. is set (step S11), and the process returns to step S8. Then, each time an interrupt request signal is input from the PTC to the CPU 103 when the interrupt is enabled, the CPU 103 becomes able to execute timer interrupt processing. This allows the CPU 103 to execute timer interrupt processing every time a predetermined period of time, such as 4 [ms], elapses.

FIG. 5 is a flowchart showing an example of timer interrupt processing P_PCT for game control. In the timer interrupt process P_PCT shown in FIG. 5, a power-off process P_POWER_OFF is executed (step S51). Subsequently, it is determined whether the fraud monitoring flag is "0" (step S52). The fraud monitoring flag is set to "1" corresponding to the on state when magnetism is detected by the magnet sensor or when radio waves are detected by the frame radio wave sensor. Otherwise, the fraud monitoring flag is set to "0", which corresponds to an off state.

If the fraud monitoring flag is "1" (step S52; No), a game stop process P_GAME_STOP is executed (step S53). The game stop process P_GAME_STOP may be a process that initializes the output port and turns off the output of the connection confirmation signal. The connection confirmation signal is transmitted from the main board 11 to the payout control board, and when it is in the off state, execution of the payout process in the payout control board is stopped.

If the fraud monitoring flag is "0" (step S52; Yes), the switch process P_SW is executed (step S54), the switch error notification process P_CON_CHK is executed (step S55), and the random number update process P_RANDOM is executed. (Step S56), and executes initial value determination random number update processing P_TFINIT (Step S57). In addition, the special symbol process process P_TPROC is executed (step S58), the normal symbol process process P_FPROC is executed (step S59), the information output process P_JYOUHOU is executed (step S60), and the prize ball process P_PAY is executed (step S61). ), the display process P_HYOUZI is executed (step S62). Further, other timer interrupt handling processing is executed (step S63). Thereafter, after interrupt permission is set (step S64), the timer interrupt process P_PCT ends.

The power-off process P_POWER_OFF in step S51 determines the power confirmation signal transmitted from the power supply board 17, and enables execution of checksum calculation processing and the like at the time of power-off. The switch process P_SW in step S54 determines the state of the input port and enables updating of the switch-on buffer and the like. The switch error notification process P_CON_CHK in step S55 can update the count value of the sensor on counter specified by the switch error notification determination table, for example, and when the count value reaches the sensor abnormality error determination value, an error notification is displayed. make it executable. The random number update process P_RANDOM in step S56 allows software to update the gaming random numbers that become software random numbers. The initial value determining random number update process P_TFINIT in step S57 allows software to update the random number used as the random number initial value among the gaming random numbers.

The special symbol process process P_TPROC in step S58 includes processing related to the variable display of special symbols and the gaming state, such as managing the execution and suspension of the special symbol game, controlling the jackpot gaming state and small winning gaming state, and controlling the gaming state. It will be done. The normal symbol process process P_FPROC in step S59 manages the execution and suspension of the common symbol game based on the detection signal from the gate switch 21, and controls the opening/closing of the variable winning ball device 6B based on "hitting a common symbol", etc. Processing related to variable display and state control of the second starting prize opening is included. Information output processing P_JYOUHOU in step S60 sets an information output signal. The information output signal is a signal corresponding to information supplied to a hall management computer installed outside the pachinko game machine 1, such as jackpot information, starting information, and probability fluctuation information. The jackpot information indicates the number of jackpot occurrences. The starting information indicates the number of starting prizes and the like. The probability variation information indicates the number of times the probability variation state has occurred. The prize ball process P_PAY in step S61 includes a prize ball command output counter addition process and a prize ball control process. The prize ball command output counter addition process uses the prize ball number table to determine whether the switch is on, and when the switch is turned on, updates the prize ball command output counter and the winning information output counter. The prize ball control process selects a process corresponding to the prize ball process code and controls the game ball to be paid out based on the detection of game balls. The display process P_HYOUZI in step S62 performs settings regarding the display by the first hold indicator 25A, the second hold indicator 25B, the standard hold indicator 25C, and other various status indicator lights.

FIG. 6 is a flowchart showing an example of a process that can be executed in step S58 shown in FIG. 5 as the special symbol process process P_TPROC. The CPU 103 performs the first starting winning correspondence flag setting in the special symbol process process P_TPROC (step S101). The first starting prize corresponding flag setting reflects the state of the first starting port switch 22A included in the switch-on buffer in the flag register of the CPU 103 by executing a logical operation instruction or the like. At this time, the fact that the zero flag in the flag register is in the on state indicates that the first starting prize corresponding flag is in the off state. On the other hand, the fact that the zero flag is in the OFF state indicates that the first starting prize winning flag is in the ON state. Subsequently, a first starting slot winning table is set by a transfer command for setting a table pointer (step S102). After that, it is determined whether or not the first starting prize corresponding flag is on (step S103). When the first starting prize corresponding flag is on (step S103; Yes), starting port switch passage processing P_TZU_ON is executed (step S104).

If the first starting prize corresponding flag is off in response to step S103 (step S103; No), or after the starting port switch passing process P_TZU_ON in step S104, the second starting winning corresponding flag is set (step S105). . The second starting prize corresponding flag setting reflects the state of the second starting port switch 22B included in the switch-on buffer in the flag register of the CPU 103 by executing a logical operation instruction or the like. At this time, the fact that the zero flag in the flag register is in the on state indicates that the second starting prize corresponding flag is in the off state. On the other hand, the fact that the zero flag is in the OFF state indicates that the second starting prize-winning flag is in the ON state. Subsequently, a second starting slot winning table is set by a transfer command for setting a table pointer (step S106). After that, it is determined whether or not the second starting prize corresponding flag is on (step S107). When the second starting prize corresponding flag is on (step S107; Yes), starting port switch passage processing P_TZU_ON is executed (step S108).

The starting port switch passing process P_TZU_ON in step 104 uses the first starting port winning table set in step S102 to determine whether the first pending memory number or the total pending memory number is less than the upper limit number. The memory number is updated by adding 1, and random number MR1-1 for special symbol judgment, random number MR3-2 for selecting loss effect, random number MR3-3 for selecting variation pattern type, and random number MR3 for variation pattern. -4 is extracted and stored in each random number buffer, and then transferred to the first special symbol holding buffer. Further, by using the first pending storage information designation command transmission table, the first pending storage information designation command in which the first pending storage number is specified can be transmitted from the main board 11 to the production control board 12. Then, a value indicating "1" as the starting opening winning designation value is stored in the starting opening winning buffer.

The starting port switch passing process P_TZU_ON in step S108 uses the second starting port winning table set in step S106 to determine whether the second pending memory number or the total pending memory number is less than the upper limit number. The memory number is updated by adding 1, and random number MR1-1 for special symbol judgment, random number MR3-2 for selecting loss effect, random number MR3-3 for selecting variation pattern type, and random number MR3 for variation pattern. -4 is extracted and stored in each random number buffer, and then transferred to the second special symbol holding buffer. Further, by using the second pending storage information designation command transmission table, it is possible to transmit a second pending storage information designation command in which the second pending storage number is specified from the main board 11 to the production control board 12. Then, a value indicating "2" as the starting opening winning designation value is stored in the starting opening winning buffer.

A common starting port switch passage process P_TZU_ON can be executed in step S104 and step S108. On the other hand, the starting port switch passing process P_TZU_ON in step S104 uses the first starting port winning table set in step S102, whereas the starting port switch passing process P_TZU_ON in step S108 uses the first starting port winning table set in step S106. Use the 2-start winning table. In this way, the common starting port switch passing process P_TZU_ON is executed using different starting port winning tables. Therefore, when the game ball enters the first starting winning hole and when the game ball enters the second starting winning hole, different data settings and control can be performed by common processing. Note that the starting port switch passing process P_TZU_ON may include a winning performance process using the extracted gaming random number.

If the second starting prize corresponding flag is off in response to step S107 (step S107; No), or after the starting port switch passing process P_TZU_ON in step S108, a special symbol process processing jump is performed by a transfer command that sets a pointer. A table is set (step S109). The special symbol process processing jump table is an address management table that makes it possible to select and execute the process corresponding to the read value of the special symbol process code. The special symbol process code can be updated to any one of 00[H] to 0B[H] in accordance with the progress of game control in the pachinko game machine 1, and is also referred to as a special symbol process code. Here, [H] indicates a hexadecimal number. Note that [B] may also indicate a binary number.

Following step S109, a special symbol process code is loaded by a transfer command for reading stored data (step S110). Next, by executing the 2-byte data selection process P_ABXEXEC (step S111), the address of the process selected in accordance with the special symbol process code is acquired. The address obtained at this time is set to a pointer. Thereafter, by executing the process pointed to by the pointer using the subroutine call command (step S112), the process selected in response to the special symbol process code becomes executable. When the selected process is finished and the return command returns to the special symbol process process P_TPROC, this special symbol process process P_TPROC also ends, and the return command returns to the game control timer interrupt process P_PCT.

FIG. 7 shows a configuration example TT01 of a special symbol process jump table used in the special symbol process P_TPROC. The special symbol process processing jump table is configured to include table data that can set the address of the process selected corresponding to the special symbol process code in the internal register of the CPU 103 used as a pointer. The special symbol process processing jump table of configuration example TT01 includes special symbol normal processing P_TNORMAL when the special symbol process code is 00 [H] and special symbol variation processing P_TSTART when the special symbol process code is 01 [H]. , Special symbol stop processing P_TSTOP when the special symbol process code is 02[H], Small hit opening preprocessing P_TLFAN when the special symbol process code is 03[H], Special symbol process code is 04[H] Processing during small hit opening P_TLOPEN when the special symbol process code is 05[H], P_TLCLSF after small winning opening when the special symbol process code is 06[H], and small winning when the special symbol process code is 06[H] Ejection ball standby process P_TLOUT, small hit end process P_TLEND when the special symbol process code is 07 [H], big prize opening pre-opening process P_TINT when the special symbol process code is 08 [H], and special The process P_TOPEN during opening of the big winning hole when the symbol process code is 09[H], the post-opening process P_TCLSF when the special symbol process code is 0A[H], and the special symbol process code 0B[ A jackpot end process P_TEND in the case of [H], and table data that can set the corresponding address value as a pointer are included.

The special symbol normal processing P_TNORMAL determines whether or not to start the special symbol game based on the presence or absence of stored reservation information, and determines the special symbol display result using the random number MR1-1 for special symbol determination. To make it possible to determine a fixed special symbol to be stopped and displayed in variable display of special symbols and to determine a variation pattern of the special symbol. The special figure display results include "big hit", "small hit", "loss", etc., and when it is determined to be a "big hit", the game is controlled to a jackpot gaming state as an advantageous state for the player. It is decided that. In addition, when the display result of the special symbol is a "jackpot", which jackpot game among multiple types of jackpot game states with different advantages for the player corresponds to the jackpot symbol that becomes the confirmed special symbol. It is determined whether the state is controlled or not. Therefore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine whether or not to control to an advantageous state that is advantageous for the player, and among multiple types of advantageous states that have different degrees of advantage for the player. It is possible to determine which of the following is to be controlled. Furthermore, the CPU 103 can determine one of a plurality of types of variation patterns by executing the special symbol normal process P_TNORMAL.

Special symbol fluctuation processing P_TSTART measures the elapsed time after the special symbol starts to fluctuate in the first special symbol display device 4A or second special symbol display device 4B, and measures the elapsed special symbol fluctuation time corresponding to the fluctuation pattern. It is possible to determine whether or not the The special symbol stop process P_TSTOP measures the time elapsed since the special symbol stopped changing in the first special symbol display device 4A or the second special symbol display device 4B, and determines whether or not the symbol stop time has elapsed. enable. The symbol stop time may be set as the time for stopping and displaying the special symbol when it is determined that the special symbol variation time has elapsed in the special symbol variation process P_TSTART. When the symbol stop time has elapsed, the special symbol process code is updated and various settings are performed in accordance with the special symbol display result. For example, if the special pattern display result is a "big hit", the special pattern process code can be updated to 08[H], and if the special pattern display result is a "small win", the special pattern process code can be updated to 03[H]. It is sufficient as long as it is updateable and the special symbol process code can be updated to 00[H] when the special symbol display result is "lost".

The small hit release preprocessing P_TLFAN, the small winning opening process P_TLOPEN, the small winning release process P_TLCLSF, the small winning ball waiting process P_TLOUT, and the small winning ending process P_TLEND are the processes for controlling the progress of the game in the small winning game state. It is. The big winning opening pre-opening process P_TINT, the big winning opening opening process P_TOPEN, the big winning opening post opening process P_TCLSF, and the jackpot ending process P_TEND are processes for controlling the progress of the game in the jackpot gaming state.

(Main operations of the production control board 12)
Next, the main operations in the production control board 12 will be explained. When the effect control board 12 receives power supply voltage from the power supply board 17 or the like, the effect control CPU 120 is activated and executes effect control main processing.

FIG. 8 is a flowchart showing the main process S_MAIN for effect control executed by the effect control CPU 120 in the effect control board 12. When the main process S_MAIN for effect control shown in FIG. 8 is started, the effect control CPU 120 executes the effect control initialization process S_INIT (step S71). The production control initialization process S_INIT includes clearing the RAM 122, setting various initial values, register settings for the timer circuit mounted on the production control board 12, etc. Subsequently, initial operation control processing S_SYOKI is executed (step S72). The initial motion control process S_SYOKI enables control of the initial motion of the movable body 32, such as driving the movable body 32 to return it to its initial position and performing predetermined operation checks. Thereafter, it is determined whether the timer interrupt flag is on (step S73). The timer interrupt flag is set to an on state every time a predetermined period of time, such as 2 [ms (milliseconds)] elapses, based on register settings for the timer circuit. Corresponding to the timer interrupt flag being off (step S73; No), step S73 is repeated and the process waits.

In response to the timer interrupt flag being turned on (step S73; Yes), the timer interrupt flag is cleared and turned off (step S74), command analysis processing S_COMMAND is executed (step S75), and production control process processing S_CPROC is executed. is executed (step S76), a random number update process S_RANDOM for effect is executed (step S77), and an output process S_OUT for effect is executed (step S78). After executing other timer interrupt handling processes (step S79), the process returns to step S73.

The command analysis process S_COMMAND in step S75 enables reading of the production control command stored in the production control command reception buffer, and setting and control corresponding to the read production control command. By executing the command analysis process S_COMMAND, the production control CPU 120 stores data indicating the state of the flag, data stored in the register, and the work area of the RAM 122 in response to the production control command sent from the main board 11. It is possible to update any stored data etc. in . The performance control process S_CPROC in step S76 includes, for example, the display of a performance image on the screen of the image display device 5, the audio output from the speakers 8L and 8R, and the lighting or lighting of decorative light emitters such as the game effect lamp 9 and the decorative LED. It is possible to control execution of performances using various performance devices including turning off lights and controlling the drive of a movable body 32. If it becomes possible to determine, decide, and set the control contents of performances using various production devices based on the production control commands transmitted from the main board 11 and the execution results of processing by the production control CPU 120, etc. good. The effect random number update process S_RANDOM in step S77 allows at least a part of the effect random numbers used on the effect control board 12 to be updated by executing a program as software.

FIG. 9(A) is a flowchart showing an example of a process that can be executed in step S76 shown in FIG. 8 as the production control process process S_CPROC. The performance control CPU 120 executes the pre-read performance setting process S_SAKI_SET in the performance control process process (step S151). The look-ahead effect setting process S_SAKI_SET enables judgment, determination, setting, etc. regarding the execution of the look-ahead preview effect, based on the effect control command at the time of start winning, which is transmitted from the main board 11, for example. In addition, the pre-read effect setting process S_SAKI_SET enables the pending display to be updated based on the number of pending memories specified from the effect control command.

After the prefetch performance setting process S_SAKI_SET in step S151, a performance control process jump table is set by a transfer command to set a pointer (step S152). The production control process processing jump table is an address management table that enables selection and execution of the process corresponding to the read value of the production control process code. The performance control process code can be updated to any one of 00[H] to 0A[H] in accordance with the progress of performance control in the pachinko game machine 1, and is also referred to as a performance process code. The production control process code is loaded by a transfer command for reading stored data (step S153). Corresponding to the effect control process code thus obtained, the address of the selected process is set in the effect control pointer (step S154). Therefore, by executing the process pointed to by the production control pointer (step S115), the process selected in accordance with the production control process code becomes executable.

FIG. 9(B) shows a configuration example TT02 of the production control process jump table used in the production control process S_CPROC. The performance control process jump table is configured to include table data that allows the address of the process selected in response to the performance control process code to be set in a register used as a performance control pointer. The production control process processing jump table of configuration example TT02 includes a variation pattern command wait process when the production control process code is 00 [H], and a production pattern fluctuation start process when the production control process code is 01 [H]. , the production symbol fluctuation processing when the production control process code is 02[H], the production symbol fluctuation stop processing when the production control process code is 03[H], and the production pattern fluctuation processing when the production control process code is 04[H]. ], the small hit display process, the small hit opening process when the production control process code is 05[H], and the small hit end production process when the production control process code is 06[H]. , jackpot display processing when the production control process code is 07 [H], in-round processing when the production control process code is 08 [H], and processing when the production control process code is 09 [H] Table data is included in which address values corresponding to round post-processing and jackpot end performance processing when the performance control process code is 0A[H] can be set in the performance control pointer.

The variation pattern command reception waiting process makes it possible to determine whether or not the variation pattern designation command transmitted from the game control microcomputer 100 of the main board 11 has been received. When it is determined that the fluctuation pattern designation command has been received, the production control process code is updated to 01[H] corresponding to the production symbol fluctuation start processing, and when it is determined that the fluctuation pattern designation command has not been received, the demonstration Make display controllable. The performance symbol variation start process enables the start of a variation performance corresponding to the special symbol game. For example, in response to a variation pattern command transmitted from the main board 11, it is possible to select a production pattern used for controlling the variation performance and to start updating a production process timer that measures production execution time. The processing during performance symbol variation makes it possible to control the switching timing of each performance element constituting the performance pattern, and also makes it possible to determine whether the performance execution time has elapsed based on the timed value of the performance process timer. When it is determined that the performance execution time has elapsed, the performance control process code is updated to 03[H] corresponding to the performance symbol fluctuation stop processing. The production symbol fluctuation stop processing is based on the completion condition of the variation production, such as the elapse of the production execution time or the reception of the production symbol confirmation command, and the end control of the variation production and the confirmation special. To enable display control of performance results corresponding to symbols. At this time, the production control process code is updated and various settings are performed in accordance with the display results of the variable display. For example, if the display result of the variable display is "Jackpot", the production control process code can be updated to 07[H], and if the display result of the variable display is "Small win", the production control process code can be updated to 04[H]. ], and when the display result of the variable display is "losing", the production control process code can be updated to 00[H].

The small win display process, the small win opening process, and the small win end performance process are processes for controlling the progress of the performance corresponding to the small win game state. The jackpot display process, in-round process, post-round process, and jackpot end performance process are processes for controlling the progress of the performance corresponding to the jackpot game state.

(Variations of basic explanation, etc.)
The pachinko gaming machine 1 is not limited to the configuration, function, processing, and operation described in the basic explanation and other explanations, and various modifications and applications are possible. For example, the pachinko gaming machine 1 does not need to have all the technical features described in the embodiment, but may include some of the technical features described in the embodiment so as to solve at least one problem in the prior art. It may also have the following configuration. In the case where a matter that is a subordinate concept is described in the embodiment, an invention of a generic concept using cognate matters or similar matters, or an invention of a generic concept using common properties is considered as the claimed invention. The present invention may include some of the structures and characteristics described in the embodiments so that at least one problem in the prior art can be solved.

The pachinko game machine 1 may be a payout type game machine that pays out a predetermined number of game media as prizes based on the occurrence of a prize, or an enclosed type game machine in which game media are enclosed and points are awarded depending on the occurrence of a prize. It may be a machine.

What is displayed during the variable display of special symbols may be, for example, only one type of symbol, such as a symbol indicating "-", and a variable display may be performed in which this symbol is repeatedly displayed and turned off. One type of symbol may be displayed during the variable display, and this symbol may not be displayed when the variable display is stopped. For example, the display result may be a non-display state in which no symbol indicating "-" is displayed and no special symbol is displayed.

The pachinko gaming machine 1 may have a configuration in which the jackpot winning probability and ball payout rate change in response to a plurality of setting values. For example, in the special symbol normal processing of the special symbol process processing, it may be possible to change the probability of winning the jackpot and the ball payout rate by using different jackpot determination values for each set value. As a specific example, the setting value has six levels from 1 to 6, where 6 has the highest probability of winning the jackpot, and as the value decreases in the order of 6, 5, 4, 3, 2, and 1, the probability of winning the jackpot increases. It gets lower. In this case, if 6 is set as the setting value, it is the most advantageous for the player, and as the value decreases in the order of 6, 5, 4, 3, 2, and 1, the advantage gradually decreases. If the probability of winning the jackpot changes according to the set value, the ball payout rate may also change according to the set value. While the probability of winning a jackpot is constant regardless of the set value, the number of rounds in the jackpot game state may vary depending on the set value. The pachinko gaming machine 1 may be configured to be able to set any one of a plurality of setting values that have different degrees of advantage for the player. The setting values set in the pachinko gaming machine 1 may be notified by transmitting a setting value designation command from the main board 11 side to the performance control board 12 side. During execution of the variable display, it may be possible to execute a setting suggestion performance that suggests setting values in the pachinko gaming machine 1 at a predetermined rate. The suggestion regarding the setting value of the pachinko gaming machine 1 is not limited to suggesting the setting value of the pachinko gaming machine 1, and may be, for example, suggesting whether the setting value of the pachinko gaming machine 1 has been changed. . The setting suggestion performance may be such that it is possible to suggest the expected level of jackpot by an arbitrary performance and also to make a suggestion regarding the setting values of the pachinko gaming machine 1.

Instead of part or all of the suggestions regarding the control of the jackpot gaming state, or together with some or all of the suggestions regarding the control of the jackpot gaming state, make suggestions regarding the control of a state that is advantageous for the player and is different from the jackpot gaming state. It may be something. For example, it may provide a suggestion regarding a variable probability state that is controlled after the end of the jackpot gaming state. In addition, as an advantageous state, a suggestion may be made depending on whether or not to be controlled regarding a state in which an arbitrary game value advantageous to the player is awarded.

The invention related to gaming machines is not limited to the pachinko gaming machine 1, but can be applied to slot machines as appropriate. In the slot machine, medals are inserted and a predetermined number of bets are set, multiple types of symbols are rotated in response to the operation of a control lever by the player, and the symbols are stopped in response to the operation of a stop button by the player. Sometimes, when the combination of stopped symbols becomes a specific combination of symbols, a game can be executed in which a predetermined number of medals are paid out to the player. In a slot machine, an advantageous state advantageous to a player may include one or more of so-called bonuses such as a big bonus, regular bonus, RT, AT, ART, and CZ.

Programs and data for realizing various controls including the progress of the game and the execution of performances can be distributed and provided to the computer device included in a gaming machine such as the pachinko gaming machine 1 using a removable recording medium. It may be possible to distribute and provide the information by installing it in a storage device of a computer device or the like in advance. Furthermore, it may include a communication processing unit that can be connected to an external device on a network via a communication line or the like, and can be distributed or provided by downloading programs and data from the external device. The execution form of games and performances may also be one that can be executed by attaching a removable recording medium, or the program and data downloaded via a communication line etc. may be temporarily stored in an internal memory etc. It may be directly executable using the hardware resources of an external device on a network connected via a communication line, or it may be directly executable using the hardware resources of an external device connected via a communication line or the like. It may also be possible to execute games and performances by exchanging data with other players via a network.

When comparing various percentages, such as processing and data determination ratios, performance execution ratios, etc., expressions such as "high", "low", and "different" mean that one is "0%" or "100%". It may also include being. For example, regarding one decision result or execution content, it may include a case where there is no decision or execution at a rate of 0%, or a case where there is always a decision or execution at a rate of 100%.

(Explanation regarding characteristic part 01AK)
FIG. 10-1 shows an example of the configuration of the game control microcomputer 100 regarding the feature section 01AK. In addition to the ROM 101, RAM 102, and CPU 103, the game control microcomputer 100 of the feature section 01AK has an external bus interface 131, a clock circuit 132, a unique information storage circuit 133, a reset controller 134, an interrupt controller 135, a timer circuit 136, and an address decode. It is configured to include a circuit 137, a free run counter 138, and a serial communication circuit 139. Further, the random number circuit 104 shown in FIG. 2 is configured to include a 16-bit random number circuit 104A and an 8-bit random number circuit 104B. The I/O 105 shown in FIG. 2 includes a PIP (Parallel Input Port) 105A and a POP (Parallel Output Port) 105B.

The external bus interface 131 is a bus interface that has an interface function between an external bus and an internal bus of the chip constituting the game control microcomputer 100, and a function to control the direction of an address bus, a data bus, and each control signal. For example, the external bus interface 131 is connected to an external memory, an external input/output device, etc. externally attached to the game control microcomputer 100, and exchanges address signals, data signals, various control signals, etc. with these external devices. It is good if it is possible to send and receive. The external bus interface 131 may include an internal resource access control circuit that controls access to internal data of the gaming control microcomputer 100 from an external device.

The clock circuit 132 can generate the internal system clock SCLK using an oscillation signal input to the control external clock terminal EXC. A control clock generated by a control clock generation circuit provided in the game control microcomputer 100 may be input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 132 can be supplied to various circuits in the game control microcomputer 100, such as the CPU 103, the 16-bit random number circuit 104A, and the 8-bit random number circuit 104B. Further, the internal system clock SCLK can be output from the system clock output terminal CLKO to the outside of the game control microcomputer 100. Alternatively, the internal system clock SCLK may be restricted so that it is not output to the outside of the game control microcomputer 100, thereby making it difficult to specify the operating state of the game control microcomputer 100 from the outside. good.

The unique information storage circuit 133 can store a plurality of types of unique information, which is internal information of the game control microcomputer 100, for example. For example, the unique information storage circuit 133 only needs to be able to store the ROM code, chip individual number, and ID number as unique information that differs for each chip of the game control microcomputer 100. The ROM code is numerical data that can be generated from data stored in a predetermined area of the ROM 101. The chip individual number and ID number are numbers given at the time of manufacturing the game control microcomputer 100, and indicate different numerical values for each chip. It is only necessary that the chip individual number can be set so that it can be read by a user program such as a gaming program, while the ID number cannot be read by a user program. The unique information storage circuit 133 may be included in a predetermined area of the ROM 101, or may be included in a built-in register of the game control microcomputer 100.

The reset controller 134 can control various resets that occur inside or outside the game control microcomputer 100. Resets that can be controlled by reset controller 134 include system resets and user resets. A system reset occurs when the input signal of the external system reset terminal XSRST is at a low level for a certain period of time. A user reset occurs due to a predetermined factor, such as the occurrence of a timeout signal of the watchdog timer 134A or the occurrence of an out-of-designated-area travel prohibition (IAT). Reset controller 134 includes a watchdog timer 134A. The watchdog timer 134A can set a timer value corresponding to the monitoring time, and can perform a countdown that periodically updates the timer value by subtracting 1, and when the timer value becomes "0" and a timeout occurs, , it is possible to output a timeout signal to reset the game control microcomputer 100 and restart it. Thereby, the watchdog timer 134A can measure the monitoring time and reset the game control microcomputer 100 when it is determined that the monitoring time has elapsed. The watchdog timer 134A can be set to enable or disable its operation, for example, according to a gaming program.

The interrupt controller 135 can control various interrupt requests generated inside or outside the game control microcomputer 100. Interrupts that can be controlled by the interrupt controller 135 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is accepted unconditionally even when the CPU 103 is in an interrupt-disabled state, and occurs when the input signal of the external non-maskable interrupt terminal XNMI (also used as the input port PI6) is at a low level for a certain period of time. The maskable interrupt INT is an interrupt whose acceptance of an interrupt request can be permitted or prohibited according to a setting instruction from the CPU 103, and multiple interrupts can be executed by setting priorities. The causes of the maskable interrupt INT are that the input signal of the external maskable interrupt terminal It is sufficient that some or all of the interrupt factors can be set, including the fact that the 8-bit random number circuit 104B has stored numerical data indicating a random value in the random value register.

The timer circuit 136 includes a PTC (Programmable Timer Counter) as a timer counter corresponding to three channels PTC0 to PTC2, and enables generation of real-time interrupts and time measurement. Each channel PTC0 to PTC2 of the timer circuit 136 uses a count clock generated based on the internal system clock SCLK to detect signal changes in the count clock, such as the falling timing when the clock signal changes from high level to low level. It is sufficient if the timer value can be updated accordingly.

The address decoding circuit 137 can decode various signals obtained from each functional block inside the game control microcomputer 100, and can output a chip select signal that is a decoded signal for an external device. The chip select signal selectively activates the internal circuit of the game control microcomputer 100 or an external device serving as a peripheral device, and enables access from the CPU 103. The output terminals that can be used by the address decode circuit 137 are the parallel output signal from the POP 105B, the serial transmission signal from the serial communication circuit 139, the clock output signal from the clock circuit 132, and the chip select signal generated by the address decode circuit 137. , as long as it can selectively output .

Free run counter 138 is configured to include counter circuits corresponding to four channels FRC0 to FRC3, and can update count values independently of the operation of CPU 103. Each of the channels FRC0 to FRC3 of the free run counter 138 can be started with an independent update clock, and can be set to stop or change its operation, for example, according to a game program. The count value by the free run counter 138 can be stored in the hard latch register in correspondence with the latch signal transmitted from the input terminal serving as the latch signal input terminal in the PIP 105A. The count value stored in the hard latch register can be read by the CPU 103 and used when executing a game program.

The serial communication circuit 139 is configured to include serial communication units corresponding to three channels SCU0, SCU1, and STU2, and enables communication with external devices using a serial communication method. Each channel SCU0, SCU1, and STU2 of the serial communication circuit 139 is capable of processing communication data in, for example, full duplex, asynchronous, and standard NRZ (Non Return to Zero) format. Channels SCU0 and SCU1 of the serial communication circuit 139 are included in a first channel transmitting/receiving circuit capable of bidirectionally transmitting and receiving serial data to and from an external circuit. Channel STU2 of the serial communication circuit 139 is included in a second channel transmission circuit that can only transmit serial data in one direction to an external circuit. For example, channel SCU0 of the serial communication circuit 139 is used for data communication with the payout control board. Further, the channel SCU1 of the serial communication circuit 139 is used for data communication with the production control board 12. Instead of channel SCU1 of serial communication circuit 139, channel STU2 of serial communication circuit 139 may be used for data communication with production control board 12.

The 16-bit random number circuit 104A is configured to include random number generation units corresponding to four channels RL0 to RL3, each of which operates independently to generate numbers from "0" to "65535" using numerical data indicating the value of a 16-bit pseudo-random number. It is possible to generate random values up to ”. The maximum value of the random numbers generated by each channel RL0 to RL3 in the 16-bit random number circuit 104A can be set to any value in the range from "256" to "65535". By setting such a maximum value, initial settings can be made to select a random number activation method so that updating of numerical data indicating a random number value is started. Alternatively, each channel RL0 to RL3 in the 16-bit random number circuit 104A selects a random number startup method so that the channels RL0 to RL3 in the 16-bit random number circuit 104A are automatically started when the operation mode of the gaming control microcomputer 100 shifts from the security mode to the user mode. Initial settings are possible. The 16-bit random number circuit 104A can update the random number MR1-1 for special symbol determination using the channel RL0, and can update the random number MR3-2 for selecting a losing effect using the channel RL2.

The 8-bit random number circuit 104B is configured to include random number generation units corresponding to four channels RS0 to RS3, each of which operates independently to generate numbers from "0" to "255" using numerical data indicating the value of an 8-bit pseudo-random number. It is possible to generate random values up to ”. The maximum value of the random numbers generated by each channel RS0 to RS3 in the 8-bit random number circuit 104B can be set to any value in the range of "16" to "255". By setting such a maximum value, initial settings can be made to select a random number activation method so that updating of numerical data indicating a random number value is started. Alternatively, each channel RS0 to RS3 in the 8-bit random number circuit 104B selects a random number activation method so that the channels RS0 to RS3 are automatically activated when the operation mode of the gaming control microcomputer 100 shifts from the security mode to the user mode. Initial settings may be possible. The 8-bit random number circuit 104B can update the random number MR3-3 for fluctuating pattern type selection through the channel RS1, can update the random number MR3-4 for fluctuating pattern through the channel RS2, and can update the random number MR3-4 for fluctuating pattern selection through the channel RS3. The random number MR3-1 for the pattern can be updated.

The PIP 105A has, for example, a built-in 8-bit width dedicated input port, and allows various signals to be input from outside the game control microcomputer 100. The PIP 105A can use input terminals corresponding to input ports PI0 to PI7. Input port PI5 uses a functional terminal that can also be used as external maskable interrupt terminal XINT. Input port PI6 uses a functional terminal that can also be used as external non-maskable interrupt terminal XNMI. Input port PI7 uses a functional terminal that can also be used as the receiving terminal of channel SCU0 in serial communication circuit 139. The POP 105B has, for example, a built-in 11-bit width output-only port, and is capable of outputting various signals to the outside of the game control microcomputer 100. POP 105B can supply parallel output signals corresponding to output ports PO0 to PO7 and PO10 to PO12 to address decode circuit 137.

FIG. 10-2 shows an example of an address map in the game control microcomputer 100. In the example shown in FIG. 10-2, the areas from addresses 0000[H] to 3FFF[H] are allocated to the ROM 101, including a gaming program area, gaming data area, non-gaming program area, non-gaming data area, ROM comment area, Contains program management area and other unused areas. The area from addresses F000[H] to F3FF[H] is allocated to the RAM 102 and includes a gaming work area, a gaming stack area, a non-gaming work area, a non-gaming stack area, and other unused areas. The area from addresses FE00[H] to FEBF[H] is a function setting register area assigned to the built-in register of the game control microcomputer 100. The area from addresses FF00[H] to FFFF[H] is a function control register area assigned to the built-in register of the game control microcomputer 100.

In the ROM 101, the game program area can store a game program that is a computer program related to the progress of the game. The game data area can store game data used by the game program. The non-gaming program area can store a non-gaming program which is a computer program related to control and processing different from the progress of the game. The non-gaming data area can store non-gaming data used by the non-gaming program. The programs and data stored in these ROMs 101 are designed and created in advance by the manufacturer of the pachinko game machine 1, which is the user of the game control microcomputer 100. Therefore, gaming programs and non-gaming programs are included in the user program. Game data and non-game data are included in user data.

The storage area of the ROM 101 is separately provided with a game program area that can store game programs related to game progress, and a non-game program area that is related to control and processing different from game progress. The area in front of the non-gaming program area to which the rear address is assigned in the gaming program area is an unused area with a storage area larger than the boundary byte number, such as 16 bytes, for example. As a result, it is possible to easily specify a gaming program area in which a gaming program related to the progress of a game can be stored, and a non-gaming program area in which a non-gaming program related to control and processing different from the progressing of a game can be stored. It becomes easier to design and manage programs and data stored in the ROM 101.

The storage area of the ROM 101 is separately provided with a game program area that can store a game program related to the progress of the game, and a game data area that can store game data used by the game program. The area in front of the game data area to which the rear address is assigned is an unused area with a storage area larger than the boundary byte number, such as 16 bytes, for example. As a result, it is possible to easily specify the game program area in which a game program related to the progress of the game can be stored and the game data area in which game data used by the game program can be stored. Easier data design and management.

The storage area of the ROM 101 has a non-gaming program area that can store non-gaming programs related to control and processing different from the progress of the game, and a non-gaming data area that can listen to non-gaming data used by the non-gaming programs. Among the non-gaming program area and non-gaming data area that are provided adjacent to each other, the area behind the non-gaming program area to which the forward address is assigned becomes the non-gaming data area, and the non-gaming data area to which the backward address is assigned. The area in front of the area becomes a non-gaming program area. As a result, the non-gaming program area that can store non-gaming programs related to control and processing different from the progress of the game, and the non-gaming data area that can store non-gaming data used by the non-gaming programs, are arranged at consecutive addresses. It can be provided in an allocated storage area to improve integrity, and it becomes easier to design and manage programs and data stored in the ROM 101. Furthermore, by providing an unused area between the non-gaming program area and the non-gaming data area with a storage area larger than the boundary number of bytes, it is possible to easily identify the non-gaming program area and the non-gaming data area. You can do it like this.

In the storage area of the ROM 101, data indicating a value of "0" may be stored in all unused storage areas. Thereby, the gaming program area and gaming data area, the non-gaming program area and non-gaming data area, and the unused area can be easily distinguished. Furthermore, if invalid data is stored in an unused area, the data can be easily discovered. Note that data indicating a value of "1" may be stored in all of the storage areas that are unused areas. In other words, data indicating the same value may be stored in all storage areas that are unused areas. Thereby, multiple types of storage areas can be easily distinguished, and invalid stored data can be easily discovered.

In the RAM 102, a game work area can be used as a work area when the CPU 103 executes a game program. The game stack area can be used as a stack area when the CPU 103 executes a game program. The non-gaming work area can be used as a work area when the CPU 103 executes a non-gaming program. The non-gaming stack area can be used as a stack area when the CPU 103 executes a non-gaming program.

A game program area and a game data area provided in the storage area of the ROM 101, and a game work area and a game stack area provided in the storage area of the RAM 102 are included in the storage area for game control. The non-gaming program and non-gaming data area provided in the storage area of ROM 101, and the non-gaming work area and non-gaming stack area provided in the storage area of RAM 102 are included in the storage area for non-gaming control.

A ROM comment area provided in the storage area of the ROM 101 stores data indicating arbitrary program specific information such as the program title and version. A program management area provided in the storage area of the ROM 101 can store setting information necessary for internal settings of the gaming control microcomputer 100 in order for the CPU 103 to execute gaming programs and non-gaming programs.

FIG. 10-3 shows a main setting example AKA01 of addresses included in the function setting register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function setting register area is a register area for setting functions using various circuits included in the game control microcomputer 100, such as the watchdog timer 134A of the reset controller 134, the interrupt controller 135, the timer circuit 136, and the serial communication circuit 139. 1 area.

In setting example AKA01, the setting values of the WDT start register at address FE1A[H] and the WDT clear register at addresses FE1B[H] to FE1C[H] are invalid values corresponding to unused states. As a result, the monitoring time measurement function using the watchdog timer 134A of the reset controller 134 is set to an unused state. Since the setting value of the interrupt mask register at address FE00[H] is 7E[H], the interrupt control function using the interrupt controller 135 is set to enable the maskable interrupt IR0. Since the setting value of the register related to channel PTC0 of timer circuit 136 at addresses FE01[H] to FE03[H] is a valid value, the time measurement function using channel PTC0 of timer circuit 136 is set to a usable state. Ru. At addresses FE04[H] to FE09[H], the setting values of the registers regarding channels PTC1 and PTC2 of the timer circuit 136 are invalid values corresponding to unused states, so that time measurement using channels PTC1 and PTC2 of the timer circuit 136 is performed. The function is set to an unused state.

Since the register settings for channels SCU0 and SCU1 of serial communication circuit 139 are valid values at addresses FE0A[H] to FE11[H], the serial communication function using channels SCU0 and SCU1 of serial communication circuit 139 is , set to enabled state. At addresses FE12[H] to FE14[H], the setting value of the register related to channel STU2 of serial communication circuit 139 is an invalid value corresponding to unused, so the serial communication function using channel STU2 of serial communication circuit 139 is detected. is set to an unused state.

Since the setting value of the register regarding the input port of the PIP 105A at addresses FE2C[H] to FE2E[H] is a valid value, the signal input function using each input port is set to a usable state. Since the setting value of the register related to the random number circuit 104 at addresses FE36[H] to FE4A[H] includes a valid value and an invalid value, the random number generation function using the random number circuit 104 is configured such that the channel corresponding to the valid value is The channels corresponding to the disabled values are set to the unused state. For example, among the four channels RL0 to RL3 in the 16-bit random number circuit 104A, channels RL0 and RL2 whose corresponding maximum value setting register setting value is a valid value are set to have their random number generation function enabled. , channels RL1 and RL3 for which the setting value of the corresponding maximum value setting register is an invalid value, the random number generation function is set to an unused state. Furthermore, among the four channels RS0 to RS3 in the 8-bit random number circuit 104B, the channels RS1 to RS3 for which the setting value of the corresponding maximum value setting register is a valid value are set to have their random number generation function enabled and are not supported. The random number generation function of the channel RS0 whose maximum value setting register setting value is an invalid value is set to an unused state.

In this way, the various circuits included in the game control microcomputer 100 are set so that various functions using the respective circuits are set to either a usable state or an unused state, depending on the setting values in the function setting register area. Good if possible. The function setting register area is not limited to various circuits included in the game control microcomputer 100, and may be a first area for setting any function.

FIG. 10-4 shows a main setting example AKA02 of addresses included in the function control register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function control register area becomes a second area for function control using various circuits included in the game control microcomputer 100, such as the RAM 102, the random number circuit 104, the PIP 105A, and the serial communication circuit 139.

In the setting example AKA02, the RWM access protect register at address FF00[H] can control the function to prohibit or permit access to RAM 102, which is RWM, in response to the setting value 00[H] or 01[H]. Make it. The set value of the internal information register at address FF01[H] is an invalid value corresponding to unused status, and the function control using the corresponding circuit becomes unused. The internal information register can store data indicating internal information such as an abnormality in the random number update state, an abnormality in the frequency of the random number update clock, occurrence of system reset, occurrence of WDT timeout, occurrence of IAT, etc., but in this embodiment, it is in an unused state. Not used as.

Each register at addresses FF25[H] to FF28[H] is used to control the serial communication function using channel SCU0 of the serial communication circuit 139 in response to the fact that the serial communication function using channel SCU0 is available. Setting values can be stored. Each register at addresses FF29[H] to FF2C[H] is used to control the serial communication function using channel SCU1 of the serial communication circuit 139 in response to the fact that the serial communication function using channel SCU1 is available. It is possible to store the setting delay.

Each register at addresses FF60[H] to FF67[H] can store random numbers that can be obtained using the soft latch random number obtaining function of the 16-bit random number circuit 104A. Of these, the RL0 soft latch random value registers at addresses FF60[H] to FF61[H] soft latch numerical data indicating the random numbers that can be generated by channel RL0 provided in the 16-bit random number circuit 104A. can be stored if it is acquired by The RL1 soft latch random value registers at addresses FF62[H] to FF63[H] acquire numerical data indicating the value of random numbers that can be generated by channel RL1 provided in the 16-bit random number circuit 104A by soft latch. can be memorized if The RL2 soft latch random value registers at addresses FF64[H] to FF65[H] acquire numerical data indicating the value of random numbers that can be generated by channel RL2 provided in the 16-bit random number circuit 104A by soft latch. can be memorized if The RL3 soft latch random value registers at addresses FF66[H] to FF67[H] acquire numerical data indicating the value of random numbers that can be generated by channel RL3 provided in the 16-bit random number circuit 104A by soft latch. can be memorized if

Each register at addresses FF68[H] to FF6B[H] can store random numbers that can be obtained using the soft latch random number obtaining function of the 8-bit random number circuit 104B. Among these, the RS0 soft latch random value register at address FF68[H] is used when numerical data indicating the value of a random number that can be generated by channel RS0 provided in the 8-bit random number circuit 104B is obtained by soft latch. can be memorized. The RS1 soft latch random value register at address FF69[H] can store a random number that can be generated by channel RS1 provided in the 8-bit random number circuit 104B, when numerical data indicating the value is acquired by soft latch. It is. The RS2 soft latch random value register at address FF6A[H] can store a random number that can be generated by channel RS2 provided in the 8-bit random number circuit 104B, when numerical data indicating the value is obtained by soft latch. It is. The RS3 soft latch random value register at address FF6B[H] can store a random number that can be generated by channel RS3 provided in the 8-bit random number circuit 104B, when numerical data indicating the value is obtained by soft latch. It is.

The RL0 hard latch random value register number “0” at addresses FF88[H] to FF89[H] and the RL0 hard latch random value register number “1” at addresses FF98[H] to FF99[H] are 16-bit random number circuits. Regarding the random numbers that can be generated by the channel RL0 provided in the channel 104A, when numerical data indicating the value is acquired by a hard latch, it can be stored. Here, the RL0 hard latch random value register includes a plurality of storage areas corresponding to a plurality of register numbers, and different hard latch conditions can be set corresponding to storage areas of different register numbers. For example, the RL0 hard latch random value register number "0", which is the RL0 hard latch random value register corresponding to the register number "0", is set when the game ball detection signal from the first starting port switch 22A is in the on state. A hard latch condition can be established. On the other hand, the RL0 hard latch random value register number "1", which is the RL0 hard latch random value register corresponding to the register number "1", is set when the game ball detection signal by the second starting port switch 22B is in the on state. In this case, the hard latch condition can be satisfied. As a result, the RL0 hard latch random value register number "0" acquires numerical data indicating the value of the random number MR1-1 for special symbol determination acquired in response to the occurrence of the first starting winning by the hard latch. can be memorized if the RL0 hard latch random value register number "1" is when numerical data indicating the value of random number MR1-1 for special symbol determination obtained in response to the occurrence of the second starting winning is obtained by hard latch. can be memorized.

Each register at addresses FFF0[H] to FFF2[H] and FF35[H] corresponds to the fact that the signal input function using the input port of PIP105A is available, and the registers are input at each input port. Can store signal values. Among these, the input port number "0" register of address FFF0[H] can store the input signal value for the input port of port number "0" provided in the PIP 105A. The input port number "1" register at the address FFF1[H] can store the input signal value for the input port with the port number "1" provided in the PIP 105A. The input port number "2" register at address FFF2[H] can store the input signal value for the input port with port number "2" provided in the PIP 105A. The input port number "3" register at address FF35[H] can store the input signal value for the input port with port number "3" provided in PIP 105A.

In this way, the various circuits included in the game control microcomputer 100 only need to be able to control their respective operating states in accordance with the values stored in the function control register area. Further, the various circuits included in the game control microcomputer 100 may be able to update the values stored in the function control register area in accordance with their respective operating states. The function control register area is not limited to various circuits included in the game control microcomputer 100, and may be a second area for controlling any function.

FIG. 10-5 is a diagram for explaining a setting example in this embodiment regarding the gaming random numbers shown in FIG. 3. The gaming random numbers shown in FIG. 3 are divided into random numbers used to determine the display result in the variable display of special symbols and random numbers used to determine the display result in the variable display of normal symbols, depending on their respective uses. , random numbers used to determine the display mode in the variable display of special symbols and normal symbols.

FIG. 10-5(A) shows a setting example AKA11 of gaming random numbers used for determining display results in variable display of special symbols. The gaming random numbers in setting example AKA11 include random numbers MR1-1 for special symbol determination, random numbers MR1-2 for winning symbols, and random numbers MR1-3 serving as initial values for winning symbols. For example, the random number MR1-1 for special symbol determination can be used to determine whether the special symbol display result is a "big hit" or "small win." Random numbers MR1-2 for winning symbols can be used to determine the designated jackpot symbol value or the designated small winning symbol value corresponding to the confirmed special symbol when the special symbol display result is "big hit" or "small hit". be. The random numbers MR1-3, which are the initial values for winning symbols, can be used when setting the initial values of the random numbers MR1-2.

The range of the random number MR1-1 is the range of numerical values that can update the random number MR1-1, and is from "0" to "65535". The size of the random number MR1-1 is the total number of random values included in the update range of the random number MR1-1, and is "65536", which corresponds to the range of the random number MR1-1 from "0" to "65535". Since the random number MR1-1 has a size of "65536", the total number of random values included in the update range is not a prime number. The number of bytes of numerical data used to update the random number MR1-1 is "2". The method of setting the maximum value of the random number MR1-1 is by initial setting of a register provided corresponding to the 16-bit random number circuit 104A. The random number MR1-1 is updated by hardware update using a 16-bit random number circuit 104A. The update condition for the random number MR1-1 is the system clock input to the 16-bit random number circuit 104A. The acquisition conditions for the random number MR1-1 include a hard latch corresponding to the starting prize, and reading to the random number buffer by software corresponding to the starting winning. The period of the random number MR1-1 is 4.369 [ms].

The range of the random number MR1-2 is the range of numerical values that can update the random number MR1-2, and is from "0" to "199". The size of the random number MR1-2 is the total number of random numbers included in the update range of the random number MR1-2, and is "200" corresponding to the range of the random number MR1-2 from "0" to "199". Since the random number MR1-2 has a size of "200", the total number of random values included in the update range is not a prime number. The number of bytes of numerical data used to update the random number MR1-2 is "1". The method for setting the maximum value of the random numbers MR1-2 is to set an immediate value in the program code. The method for updating random numbers MR1-2 is software update SA1. The update condition for the random numbers MR1-2 is a timer interrupt upon the elapse of a predetermined time. The condition for obtaining the random numbers MR1-2 is that they be read by software that is compatible with starting winnings. The period of the random numbers MR1-2 is 800 [ms].

The range of the random number MR1-3 is the range of numerical values that can update the random number MR1-3, and is "0" to "199", which is the same as the random number MR1-2. The size of the random number MR1-3 is the total number of random values included in the update range of the random number MR1-3. It is "200" which is the same as "200". Since the random numbers MR1-3 have a size of "200", the total number of random values included in the update range is not a prime number. The number of bytes of numerical data used to update the random numbers MR1-3 is "1". The maximum value setting method for the random numbers MR1-3 is based on immediate value setting in the program code. The method for updating random numbers MR1-3 is software update SA2. The conditions for updating the random numbers MR1-3 include a timer interrupt due to the passage of a predetermined time, and a loop process that becomes a standby process in the main process P_MAIN for game control. The condition for obtaining the random numbers MR1-3 is that the random numbers MR1-2 have completed one cycle. The period of the random numbers MR1-3 is indefinite due to the update conditions.

FIG. 10-5(B) shows a setting example AKA12 of gaming random numbers used to determine the display result in the variable display of normal symbols. The gaming random numbers in the setting example AKA12 include a random number MR2-1 for symbols per normal symbol and a random number MR2-2 serving as an initial value for symbols per normal symbol. For example, the random number MR2-1 for each normal symbol can be used to determine the normal symbol designation value corresponding to the confirmed normal symbol as the display result of the normal symbol. Random number MR2-2, which is the initial value for symbols per normal symbol, can be used when setting the initial value of random number MR1-2.

The range of the random number MR2-1 is the range of numerical values that can update the random number MR2-1, and is from "0" to "198". The size of the random number MR2-1 is the total number of random values included in the update range of the random number MR2-1, and is "199" corresponding to the range of the random number MR2-1 from "0" to "198". Since the random number MR2-1 has a size of "199", the total number of random values included in the update range is a prime number. The number of bytes of numerical data used to update the random number MR2-1 is "1". The method for setting the maximum value of the random number MR2-1 is to set an immediate value in the program code. The method for updating the random number MR2-1 is software update SA1. The update condition for the random number MR2-1 is a timer interrupt upon the elapse of a predetermined time. The acquisition condition for the random number MR2-1 is reading by the software corresponding to the game ball passing through the passage gate 41 which can be configured as a normal symbol operation port. The period of the random number MR2-1 is 796 [ms].

The range of the random number MR2-2 is the range of numerical values that can update the random number MR2-2, and is "0" to "198", which is the same as the random number MR2-1. The size of the random number MR2-2 is the total number of random values included in the update range of the random number MR2-2. It is "199" which is the same as "199". Since the random number MR2-2 has a size of "199", the total number of random values included in the update range is a prime number. For the random number MR2-2, the number of bytes of numerical data used to update its value is "1". The method for setting the maximum value of the random number MR2-2 is to set an immediate value in the program code. The method for updating the random number MR2-2 is software update SA2. The conditions for updating the random number MR2-2 include a timer interrupt due to the passage of a predetermined time, and a loop process that becomes a standby process in the main process P_MAIN for game control. The condition for obtaining the random number MR2-2 is that the random number MR2-1 has completed one cycle. The period of the random number MR2-2 is indefinite due to its update conditions.

FIG. 10-5(C) shows a setting example AKA13 of gaming random numbers used to determine the display mode in the variable display of special symbols and normal symbols. The random numbers for gaming in setting example AKA13 are random number MR3-1 for normal symbol fluctuation patterns, random number MR3-2 for selecting loss effect, random number MR3-3 for selecting fluctuation pattern type, and random number MR3 for fluctuation pattern. -4. For example, the random number MR3-1 for the normal symbol variation pattern can be used to determine the normal symbol variation pattern corresponding to the variable display of the normal symbol. The random number MR3-2 for selecting a loss effect can be used to determine a variable display mode corresponding to the variable display of a special symbol whose special symbol display result is a "loss". The random number MR3-3 for selecting the type of variation pattern can be used to select the type of variation pattern corresponding to the variable display of special symbols. The random number MR3-4 for the variation pattern can be used to determine a variation pattern corresponding to the variable display of special symbols.

The range of the random number MR3-1 is the range of numerical values that can update the random number MR3-1, and is from "0" to "232". The size of the random number MR3-1 is the total number of random values included in the update range of the random number MR3-1, and is "233" corresponding to the range of the random number MR3-1 from "0" to "232". Since the random number MR3-1 has a size of "233", the total number of random values included in the update range is a prime number. For the random number MR3-1, the number of bytes of numerical data used to update its value is "1". The method of setting the maximum value of the random number MR3-1 is by initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The method for updating the random number MR3-1 is hardware updating using an 8-bit random number circuit 104B. The update condition for the random number MR3-1 is the system clock input to the 8-bit random number circuit 104B. The acquisition condition for the random number MR3-1 is the start of variation in the variable display of normal symbols. The period of the random number MR3-1 is 0.249 [ms].

The range of the random number MR3-2 is the range of numerical values that can update the random number MR3-2, and is from "0" to "65518". The size of the random number MR3-2 is the total number of random values included in the update range of the random number MR3-2, and is "65519" corresponding to the range of the random number MR3-2 from "0" to "65518." Since the random number MR3-2 has a size of "65519", the total number of random values included in the update range is a prime number. The number of bytes of numerical data used to update the random number MR3-2 is "2". The method for setting the maximum value of the random number MR3-2 is by initial setting of a register provided corresponding to the 16-bit random number circuit 104A. The method for updating the random number MR3-2 is hardware updating using a 16-bit random number circuit 104A. The update condition for the random number MR3-2 is the system clock input to the 16-bit random number circuit 104A. The conditions for obtaining the random number MR3-2 include reading it into the random number buffer by software corresponding to the starting prize. The period of the random number MR3-2 is 139.774 [ms].

The range of the random number MR3-3 is the range of numerical values that can update the random number MR3-3, and is from "0" to "240". The size of the random number MR3-3 is the total number of random values included in the update range of the random number MR3-3, and is "241" corresponding to the range of the random number MR3-3 from "0" to "240". Since the random number MR3-3 has a size of "241", the total number of random values included in the update range is a prime number. For the random number MR3-3, the number of bytes of numerical data used to update its value is "1". The maximum value setting method for the random number MR3-3 is based on initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The random number MR3-3 is updated by hardware update using an 8-bit random number circuit 104B. The update condition for the random number MR3-3 is the system clock input to the 8-bit random number circuit 104B. The conditions for obtaining the random number MR3-3 include reading it into the random number buffer by software compatible with the starting winnings. The period of the random number MR3-3 is 0.257 [ms].

The range of the random number MR3-4 is the range of numerical values that can update the random number MR3-4, and is "0" to "250". The size of the random number MR3-4 is the total number of random values included in the update range of the random number MR3-4, and is "251" corresponding to the range of the random number MR3-4 from "0" to "250". Since the random number MR3-4 has a size of "251", the total number of random values included in the update range is a prime number. The number of bytes of numerical data used to update the random number MR3-4 is "1". The method of setting the maximum value of the random numbers MR3-4 is by initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The random number MR3-4 is updated by hardware update using an 8-bit random number circuit 104B. The update condition for the random number MR3-4 is the system clock input to the 8-bit random number circuit 104B. The conditions for obtaining the random number MR3-4 include reading it into the random number buffer by software that corresponds to the starting winnings. The period of the random number MR3-4 is 0.268 [ms].

The software update SA1, which is a method of updating the random numbers MR1-2 and MR2-1, can be updated by adding 1 to the previous value each time update processing by software is executed. At this time, if the updated value exceeds the maximum random number value, it is changed to "0" as the minimum random number value. Furthermore, if the updated value matches the initial random number value, the current random number value is set using the random number that becomes the corresponding initial value, and is stored as a new initial random number value. For example, if the updated value of random number MR1-2 matches the initial random number value, the current random number is set using random number MR1-3, which becomes the initial value for the winning symbol, and the random number is used as the new random number. Store as random initial value. Regarding random number MR2-1, if the updated value matches the initial random number value, set the current random number using random number MR2-2, which is the initial value for symbols per normal symbol, and use that random number as the new random number. Store as random initial value.

Software update SA2, which is a method for updating random numbers MR1-3 and MR2-2, can be updated by adding 1 to the previous value each time update processing by software is executed. At this time, if the updated value exceeds the maximum random number value, it is changed to "0" as the minimum random number value. In this case, unlike software update SA1, a random number initial value is not used, so the updated value will be either the previous value plus 1 or "0" which is the minimum random number value. .

FIG. 10-6 is a diagram for explaining a random number update cycle when a random number value is updated using the 16-bit random number circuit 104A or the 8-bit random number circuit 104B included in the random number circuit 104. Here, the random number that can be generated by channels RL0 to RL4 provided in the 16-bit random number circuit 104A is assumed to be a 16-bit random number RLn. Further, a random number that can be generated by channels RS0 to RS4 provided in the 8-bit random number circuit 104B is assumed to be an 8-bit random number RSn. The period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A goes around corresponds to whether the maximum value of the 16-bit random number RLn is a specific maximum value expressed using a power of two. are determined by different relational expressions. The period in which the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B goes around corresponds to whether the maximum value of the 8-bit random number RSn is a specific maximum value expressed using a power of two. are determined by different relational expressions.

FIG. 10-6(A) shows a 16-bit random number cycle setting example AKA21 in the 16-bit random number circuit 104A. The 16-bit random number cycle is a cycle in which the 16-bit random number RLn, which can be updated by the 16-bit random number circuit 104A, goes around once. In the 16-bit random number cycle setting example AKA21, if the maximum value of the 16-bit random number RLn corresponds to 2 ^m -1 when m = 9 to 16, the cycle in which the 16-bit random number sequence completes one cycle is is proportional to the reciprocal of the count clock frequency, ie, the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 16-bit random number RLn, is used as a variable. On the other hand, if the maximum value of the 16-bit random number RLn does not correspond to 2 ^m -1 when m = 9 to 16, the period in which the 16-bit random number sequence goes around is equal to the count clock frequency. is proportional to the reciprocal of , that is, 32 times the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 16-bit random number RLn, is used as a variable. In this way, when the maximum value of the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A is a specific maximum value, the random number update period is shorter than when the maximum value is other than the specific maximum value, that is, , the update speed of random values becomes faster.

FIG. 10-6(B) shows an 8-bit random number cycle setting example AK22 in the 8-bit random number circuit 104B. The 8-bit random number cycle is a cycle in which the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B makes one cycle. In the 8-bit random number cycle setting example AKA22, when the maximum value of the 8-bit random number RSn corresponds to 2 ^m -1 when m = 5 to 8, the cycle in which the 8-bit random number sequence completes one cycle. is proportional to the reciprocal of the count clock frequency, ie, the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 8-bit random number RSn, is used as a variable. On the other hand, if the maximum value of the 8-bit random number RSn does not correspond to 2 ^m -1 when m = 5 to 8, the cycle of the 8-bit random number sequence is equal to the count clock frequency. is proportional to the reciprocal of , that is, 16 times the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 8-bit random number RSn, is used as a variable. In this way, when the maximum value of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B is a specific maximum value, the random number update cycle becomes shorter than when the maximum value is other than the specific maximum value, that is, , the update speed of random values becomes faster.

FIG. 10-6(C) shows a random number comparison example AKA23 in which random numbers updatable by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B are compared. The 16-bit random number circuit 104A can update random numbers corresponding to the random number MR1-1 for special symbol determination and the random number MR3-2 for selecting a loss effect. The 8-bit random number circuit 104B can update random numbers corresponding to the random number MR3-3 for selecting the type of variation pattern and the random number MR3-4 for variation pattern.

The maximum value of the random number MR1-1 is "65535", which corresponds to 2 ^m -1 when m=16. As a result, the period of the random number MR1-1 becomes 4.369 [ms], and the update speed at this time becomes 15000 [times/ms]. The maximum value of the random number MR3-2 is "65518", which does not correspond to 2 ^m -1 when m=9 to 16. As a result, the period of the random number MR3-2 becomes 139.774 [ms], and the update speed at this time becomes 469 [times/ms]. The random number MR3-3 has a maximum value of "240" and does not correspond to 2 ^m -1 when m=5 to 8. As a result, the period of the random number MR3-3 becomes 0.257 [ms], and the update speed at this time becomes 938 [times/ms]. The random number MR3-4 has a maximum value of "250" and does not correspond to 2 ^m -1 when m=5 to 8. As a result, the period of the random number MR3-4 becomes 0.268 [ms], and the update speed at this time becomes 938 [times/ms].

In this way, the gaming random numbers that can be updated by the 16-bit random number circuit 104A include the random number MR1-1 for special symbol determination and the random number MR3-2 for selecting a losing effect. The random number MR1-1 and the random number MR3-2 both have the number of bytes of numerical data "2" and are composed of 2 bytes as the specific number of bytes. Since the size of random number MR1-1 is "65536" and the size of random number MR3-2 is "65519", it is assumed that the total number of random numbers included in the update range of random number MR1-1 is a specific number. In this case, the total number of random numbers included in the update range of random number MR3-2 is a predetermined number smaller than the specific number. The update speed of random number MR1-1 is 15000 [times/ms], and the update speed of random number MR3-2 is 469 [times/ms], so random number MR1-1 has a faster update speed than random number MR3-2. becomes faster. This makes it possible to suppress the synchronous occurrence of random values and update the random values appropriately.

Further, the gaming random numbers that can be updated by the 16-bit random number circuit 104A include a random number MR3-2 for selecting a losing effect. The gaming random numbers that can be updated by the 8-bit random number circuit 104B include a random number MR3-3 for selecting a variation pattern type and a random number MR3-4 for variation patterns. For these random numbers MR3-2 to MR3-4, the total number of random values included in the update range is a prime number. The update speed of the random number MR3-2 is 469 [times/ms], while the update speed of the random numbers MR3-3 and MR3-4 is 938 [times/ms]. That is, the update speed of random numbers MR3-3 and MR3-4 is twice the update speed of random number MR3-2, which is an integral multiple. Therefore, when the random number MR3-2 is the first random value, and the random numbers MR3-3 and MR3-4 are the second random values, the first random value is updated at the first speed, and the second random value is The update speed is a second speed that is an integral multiple of the first speed. The update range of random number MR3-2 is "0" to "65518", the update range of random number MR3-3 is "0" to "240", and the update range of random number MR3-3 is "0" to "65518". Since it is "250", the total number of random numbers included in each update range is different between the first random number value and the second random number value, and the total number of random numbers included in each update range is a prime number. This makes it possible to suppress the synchronous occurrence of random values and update the random values appropriately.

A plurality of registers are provided inside the CPU 103, such as a program counter, an interrupt register, a stack pointer, an index register, a flag register, an address register, and general-purpose registers including an accumulator. The index register, flag register, and general-purpose register may be provided with a main register and a sub-register. The registers included in the main register and sub-registers and the stack pointer may be provided so that a plurality of register banks can be configured. The plurality of register banks may include a first register bank for use within the area that can be used when executing a gaming program, and a second register bank for use outside the area that can be used when executing a non-gaming program. . This eliminates the need to save the values stored in general-purpose registers to and from the stack area when switching between a gaming program and a non-gaming program, for example, and restore them from the stack area, increasing the program size and processing load. can be prevented.

The program counter is for holding the address value of the next instruction to be executed by the CPU 103, and is also called a PC register. The value stored in the program counter is sequentially counted up each time each instruction is executed, or the address value of a branch destination by a branch instruction is set. The interrupt register can hold the upper address value of the interrupt vector table, and is also called an I register. The value stored in the I register is set in response to the start of power supply to the pachinko gaming machine 1.

The stack pointer can hold an address value corresponding to a game stack area or a non-game stack area, and is also called an SP register. The stored value of the stack pointer is specified by a predetermined register or instruction, including the program counter, in response to the occurrence of an interrupt, the execution of a PUSH instruction, or the execution of a subroutine call instruction such as a CALL instruction, CALLF instruction, or RST instruction. It is possible to specify a save destination address for saving and holding the stored value or immediate value in the register, and with this saving, the value is updated to a value indicating the start address of the storage area holding the stored value. Furthermore, the stored value of the stack pointer can specify a read address for restoring the stored value of the saved register in response to the end of interrupt processing, execution of a POP instruction, end of subroutine processing, etc. Upon this return, the stored value is updated to a value indicating the corresponding address after being read. In addition, the stored value of the stack pointer can be set to a stored value or an immediate value of a register specified by a load instruction such as an LD instruction.

The index register includes an IX register and an IY register having a 2-byte storage capacity capable of storing 16-bit data. The accumulator is also called the A register. Other general-purpose registers include a plurality of registers such as B register, C register, D register, E register, H register, and L register, each having a storage capacity of 1 byte that can store 8-bit data. The B register and C register can be used as a BC register, which is a pair of registers that can store 16-bit data. The D register and the E register can be used as a DE register, which is a pair of registers that can store 16-bit data. The H register and the L register can be used as an HL register, which is a pair of registers that can store 16-bit data.

The internal registers of the CPU 103 can update stored values in response to arithmetic instructions, transfer instructions, etc. executed by the CPU 103, and specify program addresses, data addresses, or built-in register addresses provided in the gaming control microcomputer 100, and arithmetic data. It is used for storing transfer data, etc.

In the game control microcomputer 100, the instruction set for causing the CPU 103 to execute a program includes transfer instructions such as a load instruction, a subroutine call instruction, a jump instruction, arithmetic instructions including arithmetic operation instructions and logical operation instructions, and input instructions. It consists of output commands, etc. Computer programs such as gaming programs and non-gaming programs that can be executed by the CPU 103 are prepared in advance as program codes in which these various instructions are written, and are stored in the ROM 101.

The load instruction is used to store and set data read from the memory area of the ROM 101 or RAM 102 or the built-in device area into the internal register of the CPU 103, or to set the stored value in the internal register of the CPU 103 to the memory area of the RAM 102 or the built-in device area. This transfer instruction can be used to write and store a value specified by an operand, and to set or store a numerical value specified by an operand as an immediate value in an internal register of the CPU 103, a storage area of the RAM 102, or a built-in device area. The target to which data is transferred by a load instruction can be specified in accordance with the instruction code and operand, and generally includes a data transfer source and a data transfer destination. However, if an immediate value is specified by the operand, the data transfer source is not included.

Load instructions include a normal LD instruction, a special LDQ instruction, a special LDF instruction, and a special ICPLD instruction. A normal LD instruction is also called a normal transfer instruction. The special LDQ command is also referred to as a first special transfer command. The special LDF instruction is also referred to as a second special transfer instruction. The special ICPLD command is also referred to as a third special transfer command.

The LD instruction, which is a normal transfer instruction, is a normal transfer instruction that can specify both an upper address and a lower address to transfer data when transferring data to the storage area of the ROM 101 or RAM 102 or the built-in device area. . In addition, the LD instruction, which is a normal transfer instruction, uses a paired register such as the HL register as a pointer when transferring data to the storage area of the ROM 101 or RAM 102 or the built-in device area. Data can be transferred by specifying an address using a pointer.

The LDQ instruction, which is the first special transfer instruction, uses the Q register, which is a special register included in the internal registers of the CPU 103, and can transfer data by specifying only the lower address. A storage value indicating an upper address is preset in the Q register, and by combining it with a lower address specified by an LDQ command, it is possible to specify a transfer destination or transfer source address and transfer data.

The LDQ instruction, which is the first special transfer instruction, can transfer data with a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, in a program that frequently changes the value stored in the Q register, the amount of program code may actually increase compared to a normal LD instruction. Therefore, in the gaming work area from address F000[H] to F0D7[H], the function setting register area from address FE00[H] to FEBF[H], and the function control register area from address FF00[H] to FFFF[H]. It is sufficient if data transfer using the LDQ instruction, which is the first special transfer instruction, can be executed in response to processing that requires transferring various data multiple times.

The LDF instruction, which is the second special transfer instruction, can transfer data by specifying only the lower address for storage data in a specific address range. The specific address range is, for example, the range of addresses 1200[H] to 1DFF[H]. Therefore, the game data area of the ROM 101 is set in advance to be included in this specific address range, and by combining it with the lower address specified by the LDF command, the transfer source address can be specified and the data can be transferred. Can be done. Note that the game data area of the ROM 101 is read-only and cannot be written to, so the address of the game data area is never designated as the transfer destination address.

The LDF instruction, which is the second special transfer instruction, can transfer data with a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, since the specific address range is fixed according to the specifications, the storage area of frequently used data, such as the game data area of the ROM 101, is set to be included in the specific address range, and the second special transfer command is It is sufficient if data transfer using an LDF instruction can be executed.

The ICPLD instruction, which is the third special transfer instruction, compares the update target value and the comparison judgment value, and updates the update target value by adding 1 if the update target value is less than the comparison judgment value. When the update target value is equal to or greater than the comparison judgment value, the update target value is changed to "0" which is the minimum value. The value to be updated may be a value indicated by the stored data at the address pointed to by the pointer, or may be a value stored in a register. The comparison judgment value may be a value stored in a register, or may be a value indicated by an operand of an ICPLD instruction.

In this way, the ICPLD instruction, which is the third special transfer instruction, compares the update target value with the comparison judgment value, adds 1 to the update target value if the comparison result is less than the comparison judgment value, and This is a single comparison and addition instruction that includes changing the update target value to the minimum value if the value is greater than or equal to the comparison judgment value.

Note that setting a stored value in an internal register of the CPU 103 using an immediate value or the like based on an operand of a transfer instruction is also referred to as setting. Reading storage data in the game data area of the ROM 101 or the game work area of the RAM 102 and storing it in the internal register of the CPU 103 is also called loading. Storing the stored value in the internal register of the CPU 103 in a buffer, counter, timer, or other arbitrary storage area provided in the game work area of the RAM 102 is also called storing.

FIG. 10-7 is a flowchart illustrating an example of the power supply start corresponding process P_POWER_ON. The power supply start corresponding process P_POWER_ON is included in the processes that can be called from the game control main process P_MAIN shown in FIG. 4, and can be executed in step S1 in response to the start of power supply to the pachinko gaming machine 1. It is. When the CPU 103 executes the power supply start corresponding process P_POWER_ON, it sets interrupts to disabled (step AKS1) and then sets the initial value of the stack pointer in the area to the stack pointer (step AKS2). The initial value of the intra-area stack pointer may be the address F200[H], which is the final address of the game stack area plus 1, corresponding to the initial state where no save data is stored in the game stack area.

Following step AKS2, a connection confirmation signal ON output value is set by a transfer command for setting an internal register of the CPU 103 (step AKS3). The connection confirmation signal ON output value is a value indicating that the connection confirmation signal is in the ON state, and may be, for example, 00 [H]. At this time, the upper address of the function control register is set in the Q register by a transfer command for setting the Q register included in the internal registers of the CPU 103 (step AKS4). The function control register upper address is a value FF[H] indicating the upper address of the function control register area in the setting example AKA02 shown in FIG. 10-4. After setting the upper address of the function control register in this way, the connection confirmation signal ON output value is stored by a transfer command using the upper address indicated by the value stored in the Q register (step AKS5). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The stored value of the Q register is set to the upper address of the function control register area in step AKS4. Therefore, the connection confirmation set in step AKS3 in the function control register of the specified address in the function control register area by a transfer instruction for writing to the storage area of the specified address, such as a special 2-byte LDQ instruction that specifies the lower address. The signal on output value can be stored. In step AKS5, the connection confirmation signal ON output value is stored in the output port number "1" register provided in the function control register area. As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to the on state.

When the connection confirmation signal is turned on in step AKS5, the SCU0 command register clear output value is stored by a transfer command using the upper address indicated by the value stored in the Q register (step AKS6). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The stored value of the Q register is set to the upper address of the function control register area in step AKS4. The SCU0 command register clear output value can be specified by the operand of the transfer instruction. Therefore, a transfer instruction to write to a storage area at a specified address, such as a special 3-byte LDQ instruction that specifies a lower address and an SCU0 command register clear output value, causes the SCU0 Command register clear output value can be stored. In step AKS6, the SCU0 command register clear output value is stored in the SCU0 command register provided at address FF28[H] of the function control register area in the setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using channel SCU0 of the serial communication circuit 139 is controlled to the initial state.

After step AKS6, the SCU1 command register clear output value is stored by a transfer command using the upper address indicated by the value stored in the Q register (step AKS7). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The stored value of the Q register is set to the upper address of the function control register area in step AKS4. The SCU1 command register clear output value can be specified by the operand of the transfer instruction. Therefore, a transfer instruction to write to a storage area at a specified address, such as a special 3-byte LDQ instruction that specifies a lower address and an SCU0 command register clear output value, causes the function control register at the specified address in the function control register area to be Command register clear output value can be stored. In step AKS7, the SCU1 command register clear output value is stored in the SCU1 command register provided at address FF2C[H] of the function control register area in the setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using channel SCU1 of the serial communication circuit 139 is controlled to the initial state.

When these serial communication functions are controlled to the initial state, the upper address of the interrupt vector table is set by a transfer command for setting the internal register of the CPU 103 (step AKS8). The interrupt vector table upper address is the upper address of the interrupt vector table provided in the game program area of the ROM 101. In the interrupt vector table, for example, for timer interrupt processing P_PCT for game control that is executed in response to the occurrence of a timer interrupt, the start address is stored in a table position corresponding to the interrupt order. Such an upper address of the interrupt vector table is set in the I register by a transfer instruction for setting an internal register of the CPU 103 (step AKS9).

After step AKS9, the value stored in the Q register is updated to subtract 1 (step AKS10). The stored value of the Q register was set to the upper address of the function control register area in step AKS4. When this stored value is subtracted by 1, the upper address of the function setting register area in the setting example AKA01 shown in FIG. 10-3 is stored in the Q register. In this way, after the function control registers provided in the function control register area are set, the function setting registers provided in the function setting register area can be set. At this time, a function setting register storage value table address is set by a transfer instruction for setting a pointer (step AKS11). The function setting register storage value table address is the address of the function setting register storage value table stored in the game data area of the ROM 101. Then, the processing number is loaded by a transfer command for reading the stored data at the address pointed to by the pointer (step AKS12). Furthermore, the function setting register store command performs setting using the function setting register storage value table (step AKS13). The function setting register store instruction specifies the function setting register by the stored data at the address when adding 1 to the address pointed to by the pointer, and specifies the function setting register setting indicated by the stored data at the address when adding 2 to the address pointed to by the pointer. Any instruction that repeats the steps of storing a value in a specified function setting register, adding 2 to the value stored in the pointer, and subtracting 1 from the number of processes until the number of processes becomes 0 may be used. In this way, it is possible to initialize the function setting register.

When the initial setting of the function setting register is completed in step AKS13, the access permission output value is stored in the RWM access protect register (step AKS14). The access permission output value of the RWM access protect register is set to, for example, 01[H] by a transfer instruction for setting an internal register of the CPU 103. Such an access permission output value is stored in the RWM access protection register by a transfer command for writing to the storage area at the start address in the function setting register area. The RWM access protect register enables functional control to permit access to the RAM 102, which is RWM, in response to the setting of 01[H], which is the access permission output value. Therefore, by storing the access permission output value in the RWM access protect register in step AKS14, access to the RAM 102 is permitted in response to the start of power supply to the pachinko gaming machine 1.

After step AKS14, the upper address of the game work area which becomes the work area of the RAM 102 is set in the Q register (step AKS15), and then the power supply start corresponding process P_POWER_ON ends. In this way, after access to the RAM 102 is permitted in step AKS14, the value F0[H] indicating the upper address of the gaming work area in the RAM 102 is set in the Q register. When the LDQ instruction, which is the first special transfer instruction, is executed after step AKS15, the value stored in the Q register, F0[H], can be used as the upper address of the transfer destination or transfer source without specifying it with an operand. can. Thereby, the program capacity for processing using the gaming work area in the RAM 102 can be reduced, and the marketability of the gaming machine can be improved.

FIG. 10-8 shows a configuration example AKT01 of a function setting register storage value table used in the power supply start corresponding process P_POWER_ON. In the power supply start corresponding process P_POWER_ON, for example, using the function setting register storage table whose address has been set in step AKS11, the processing number is loaded in step AKS12, and each function setting register is stored by the function setting register store instruction in step AKS13. The value is stored. In the function setting register storage value table of configuration example AKT01, a value 18 [H] indicating the number of processes is stored at the top address 1200 [H]. In step AKS12, this table data is read out and loaded into the internal register of the CPU 103. After that, the function setting register store instruction in step AKS13 sequentially reads table data that combines the lower addresses of the function setting registers and the stored values, and makes it possible to store the stored values in the function setting registers corresponding to each lower address. .

In the function setting register storage value table of configuration example AKT01, the stored value of the function setting register with a small value indicating a lower address can be set first, and the stored value of a function setting register with a larger value indicating a lower address can be set later. The table data is structured as follows. As a result, in the function setting register area, the stored value of the function setting register near the start address is set first, and the stored value of the function setting register near the final address is set after. The value is set. This facilitates the design and management of data indicating the values stored in the function setting registers, and improves the marketability of the gaming machine.

The 16-bit random number circuit 104A can start updating from the channel for which the stored value indicating the maximum random number value is set in the maximum value setting register, corresponding to the four channels RL0 to RL3. The 8-bit random number circuit 104B can start updating from the channel for which the stored value indicating the maximum random number value is set in the maximum value setting register, corresponding to the four channels RS0 to RS3. The function setting register area of the setting example AKA01 shown in Figure 10-3 includes the RL0 maximum value setting register at addresses FE3F[H] to FE40[H] and the RL1 maximum value setting register at addresses FE41[H] to FE42[H]. The setting register, the RL2 maximum value setting register at addresses FE43[H] to FE44[H], and the RL3 maximum value setting register at addresses FE45[H] to FE46[H] are the four in the 16-bit random number circuit 104A. It is provided corresponding to channels RL0 to RL3. This function setting register area also contains the RS0 maximum value setting register at address FE47[H], the RS1 maximum value setting register at address FE48[H], the RS2 maximum value setting register at address FE49[H], and the RS2 maximum value setting register at address FE4A. [H] RS3 maximum value setting register is provided corresponding to four channels RS0 to RS4 in the 8-bit random number circuit 104B. In the function setting register storage value table of the configuration example AKT01, among these maximum value setting registers, the stored value of the RL0 maximum value setting register is set first, the stored value of the RL2 maximum value setting register is set next, The table data is configured such that the value stored in the RS1 maximum value setting register is set next, the value stored in the RS2 maximum value setting register is set next, and the RS3 maximum value setting register is set last. Therefore, the update of channel RL0 in 16-bit random number circuit 104A is started first, the update of channel RL2 in 16-bit random number circuit 104A is started next, and the update of channel RS1 in 8-bit random number circuit 104B is started next. The update of channel RS2 in 8-bit random number circuit 104B is started next, and the update of channel RS3 in 8-bit random number circuit 104B is started last. In this way, since updates are started in order from the random numbers for which the maximum random number value has been set, the uncertainty of the random numbers is increased depending on the timing when updating the random numbers, reducing the processing load and ensuring that appropriate random Numerical values can be updated.

The power supply start corresponding process P_POWER_ON is included in the process that can be called from the main process P_MAIN for game control, which is a startup process executed based on the start of power supply to the pachinko gaming machine 1, and is a function setting of the configuration example AKT01. Using a register storage value table, it is possible to set a storage value in a function setting register area as a storage area related to a function. At this time, since the maximum random number value of the random number values updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can be set, the power supply start corresponding process P_POWER_ON can be executed as a maximum value setting process. The 16-bit random number circuit 104A is capable of updating a first random number value composed of 16 bits corresponding to 2 bytes as the specific number of bytes. The 8-bit random number circuit 104B can update a second random number value composed of 8 bits corresponding to 1 byte as a predetermined number of bytes smaller than the specific number of bytes. When executing the power supply start corresponding process P_POWER_ON, after setting the maximum random number value of the first random number that can be updated by the 16-bit random number circuit 104A using the function setting register storage value table of the configuration example AKT01, The maximum random number value of the second random number value that can be updated by the 8-bit random number circuit 104B is set. In this way, by setting the second random value of a predetermined number of bytes after setting the first random value of a specific number of bytes, the first random value and the second random value can be updated stably, and an appropriate random number can be obtained. Numerical values can be updated.

FIG. 10-9 shows an example of the configuration of the RWM access protect register. The RWM access protect register is provided at address FF00[H] in the functional control register area configuration example AKA02 shown in FIG. 10-4. The value stored in the RWM access protect register becomes a different value depending on whether access to the RAM 102 serving as RWM is prohibited or permitted.

FIG. 10-9(A) shows an example of the bit configuration of the RWM access protect register. The RWM access protect register can store 8-bit data RAP with bit numbers "0" to "7", and bit data RAP0 with bit number "0" is set to 0 [B] or 1 [B]. It is possible. On the other hand, bit data from bit number "1" to bit number "7" indicates a fixed value that is always set to 0 [B] and is never set to "1".

FIG. 10-9(B) is a diagram for explaining an example of use of bit data RAP of the RWM access protect register. In bit data RAP, bit data RAP0 with bit number "0" is an RWM access control bit, and setting 0 [B] prohibits access to RWM, and setting 1 [B] allows access to RWM. In response to the start of power supply to the pachinko game machine 1, bit data RAP0 with bit number "0" is set to 0 [B], which is an initial value. Thereby, in response to the start of power supply to the pachinko gaming machine 1, access to the RAM 102, which serves as RWM, can be prohibited.

FIG. 10-10 is a flowchart illustrating an example of power-off processing P_POWER_OFF. The power-off process P_POWER_OFF is included in the process that can be called from the game control timer interrupt process P_PCT shown in FIG. 5, and can be executed in step S51 every time a timer interrupt occurs. When the CPU 103 executes the power-off process P_POWER_OFF, the CPU 103 sets the backup monitoring timer address using a transfer command for setting a pointer (step AKS31). The backup monitoring timer address is the address of a backup monitoring timer provided in the game work area of the RAM 102.

The input port number "3" is input (step AKS32). The input port number "3" is an input port to which "3" is assigned as the port number, and includes a power supply confirmation signal input bit. Therefore, an AND operation is performed using the input data of the input port number "3" and the check data corresponding to the bit position of the power supply confirmation signal input bit. At this time, it is determined whether the power supply confirmation signal input bit is "0" depending on whether the zero flag is on or not (step AKS33). The power supply confirmation signal input bit indicates that the power supply confirmation signal is in the OFF state when the bit value is 0[B] corresponding to "0", and 1[B] when the bit value corresponds to "1". ] indicates that the power confirmation signal is in the on state.

If the power supply confirmation signal input bit is "1" instead of "0" (step AKS33; No), backup monitoring timer clear data is stored by a transfer command that can update the storage data at the address pointed to by the pointer (step AKS34). In step AKS34, by storing clear data in the backup monitoring timer, the backup monitoring timer can be cleared when the power confirmation signal is in the on state, in response to the fact that the power is not being determined to be turned off.

Corresponding to step AKS33, if the power supply confirmation signal input bit is "0" (step AKS33; Yes), the time value measured by the backup monitoring timer is updated to add 1 (step AKS35). Further, the backup monitoring timer is loaded by a transfer command for reading the stored data at the address pointed to by the pointer (step AKS36). Then, it is confirmed that the backup monitoring timer does not indicate the backup judgment time (step AKS37) by using a calculation return instruction that can compare the time value measured by the backup monitoring timer and the judgment value corresponding to the backup judgment time (step AKS37). AKS38). This calculation return instruction completes the power-off process and proceeds to the special symbol process process in response to the zero flag that is turned off when the measured value by the backup monitoring timer and the judgment value corresponding to the backup judgment time are different. allows for the return of In this way, if the backup monitoring timer does not indicate the backup determination time (step AKS38; Yes), the power-off process ends.

If the backup monitoring timer indicates the backup determination time in response to step AKS38 (step AKS38; No), checksum calculation processing P_SUM_CALC is executed (step AKS39). The checksum calculation process P_SUM_CALC in step AKS39 may be the same process as the checksum calculation process included in the RWM check process P_RWM_CHK in step S2 in the main process P_MAIN for game control shown in FIG. In this way, by executing a common checksum calculation process in response to the start and stop of power supply in the pachinko gaming machine 1, it is possible to determine whether or not the stored contents in the gaming work area of the RAM 102 are maintained without change. This makes it possible to determine whether recovery using backup data is possible. The checksum data created by the checksum calculation process P_SUM_CALC in step AKS39 is stored in the checksum buffer by a transfer command for writing to the storage area at the address pointed to by the pointer (step AKS40).

After step AKS40, clear data is set to output value data by an exclusive OR operation instruction (step AKS41). This exclusive OR operation instruction calculates the exclusive OR of the stored values in a single register, so that all bit values become the exclusive OR of the same values, so the stored value is It can be initialized to clear data of 00[H]. Such clear data is stored in the RWM access protect register by a transfer command for writing to the storage area at the start address in the function setting register area (step AKS42). The RWM access protect register enables functional control to prohibit access to the RAM 102, which is RWM, in response to the setting of 00[H], which is clear data. Therefore, by storing the clear data in the RWM access protection register in step AKS42, access to the RAM 102 is prohibited in response to the stoppage of power supply to the pachinko gaming machine 1.

After step AKS42, output port numbers "0" to "10" are cleared (step AKS43). Output port numbers "0" to "10" are output ports with port numbers "0" to "10", and are all output ports in the game control microcomputer 100. Therefore, in step AKS43, in response to the stoppage of power supply to the pachinko game machine 1, all output ports in the game control microcomputer 100 are set to the clear state. At this time, the connection confirmation signal off output value is set by a transfer command for setting the internal register of the CPU 103 (step AKS44). The connection confirmation signal off output value is a value indicating that the connection confirmation signal is in the off state, and may be, for example, 01[H]. Such a connection confirmation signal OFF output value is stored in the output port number "1" register by a transfer command for writing to the storage area of the designated address in the function control register area (step AKS45). As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to the OFF state.

Following step AKS45, the PTC0 interrupt disable output value is set by a transfer instruction for setting the internal register of the CPU 103 (step AKS46). The PTC0 interrupt disable output value is an output value for setting generation of a timer interrupt using channel PTC0 of the timer circuit 136 to a disabled state. This PTC0 interrupt disable output value is stored in the PTC0 control register by a transfer command to write to the function setting register at the specified address in the function setting register area (step AKS47). The PTC0 control register can set the usage state of the time measurement function using channel PTC0 of the timer circuit 136. In step AKS47, the PTC0 interrupt disable output value set in step AKS46 is stored in the PTC0 control register, so that in response to the stoppage of power supply to the pachinko game machine 1, timer interrupts for game control are disabled. Set.

When settings corresponding to the elapse of the backup determination time are performed, a transition is made to a standby state by executing loop processing. In this standby state, the input port number "3" is input (step AKS48), and it is determined whether the power supply confirmation signal input bit is "0" (step AKS49). If the power confirmation signal input bit is "0" in response to the off state of the power confirmation signal (step AKS49; Yes), the loop process returning to step AKS48 is continued. Thereby, in response to the stoppage of power supply to the pachinko game machine 1, by maintaining the standby state until the operation is stopped due to power cutoff, it is possible to prevent inconvenient changes in stored data and runaway processing by the CPU 103.

Corresponding to step AKS49, if the power supply confirmation signal input bit is "1" and not "0" (step AKS49; No), the vector table address is set in the stack pointer at the time of power-off recovery, and then (step AKS50) , terminate the power-off process P_POWER_OFF using an interrupt return command. The power-off recovery vector table address is the address of the power-off recovery vector table provided in the game program area of the ROM 101. The interrupt return instruction can use the stack pointer as a pointer to set the stored data in the storage area indicated by the address specified by the stored value of the stack pointer in the program counter. For example, the storage data of the storage area indicated by the address specified by the stored value of the stack pointer is set to the lower byte of the program counter, and the storage data of the storage area specified by the address specified by the value obtained by adding 1 to the stored value of the stack pointer is set. Set the stored data to the upper byte of the program counter.

FIGS. 10-11 are diagrams for explaining a usage example of a data structure related to power-off processing P_POWER_OFF. In the power-off process P_POWER_OFF, for example, step AKS38 executes a branch process using the clocked value of the backup monitoring timer, and step AKS40 stores checksum data using a checksum buffer. In addition, by setting the vector table address at the time of power failure recovery in step AKS50, the game control is performed when the pachinko game machine 1 does not stop operating after a power supply stoppage is detected and normal power supply is resumed. Make the program executable from the beginning. In this way, the power-off process P_POWER_OFF enables control when the power supply to the pachinko game machine 1 is stopped using the backup monitoring timer, checksum buffer, and power-off recovery vector table.

FIG. 10-11(A) shows a configuration example AKB01 of a storage area serving as a backup data area. The backup data area of the configuration example AKB01 can store backup setting data used when backing up data stored in the gaming work area of the RAM 102. This backup data area includes a backup monitoring timer at address F000[H] and a checksum buffer at address F0DE[H]. Address F000[H] is the start address of the gaming work area, and address F0DE[H] is the final address of the gaming work area. In this way, by providing the backup data area at the start address and the end address of the game work area, it is possible to appropriately back up the data stored in the game work area of the RAM 102.

FIG. 10-11(B) shows a configuration example AKT11 of the vector table at the time of power-off recovery. The power-off recovery vector table of the configuration example AKT 11 can specify a return destination address from power-off processing in response to an interrupt return command when normal power supply is resumed. The vector table at the time of power-off recovery includes lower address designation data 00 [H] stored at address 0016 [H] in the game program area of ROM 101 and upper address stored at address 0017 [H] in the game program area of ROM 101. It is configured to include specified data 00[H] as table data. In step AKS50 of the power-off process P_POWER_OFF, data indicating address 0016[H] is set in the stack pointer as the vector table address at the time of power-off recovery. Thereafter, the stored value of the program counter is set to 0000 [H] by an interrupt return instruction, and the process is returned, thereby making it possible to execute the main process P_MAIN for game control from the beginning.

FIG. 10-12 is a flowchart showing an example of the random number update process P_RANDOM. The random number update process P_RANDOM is included in the processes that can be called from the game control timer interrupt process P_PCT shown in FIG. It can be executed in step S56. On the other hand, the random number update process P_RANDOM is not included in the processes that can be called from the main process P_MAIN for game control shown in FIG. 4, and is executed in a loop process that is repeated until a timer interrupt occurs after step S7. Never. Therefore, although the random number update process P_RANDOM is included in the first process that can be executed in response to a timer interrupt after a predetermined time has elapsed, it is not included in the second process that can be repeatedly executed until the first process is executed. do not have. Although the random number update process P_RANDOM can be called and executed in the game control timer interrupt process P_PCT that controls the progress of the game, the game control is executed based on the start of power supply to the pachinko game machine 1. In the main process P_MAIN, after the startup process such as the power supply start corresponding process P_POWER_ON in step S1, it is not called and cannot be executed in the standby process as a repeated loop process.

The random number update process P_RANDOM uses the internal registers of the CPU 103, such as the B register, DE register, and HL register, to indicate the values of random numbers MR1-2 for winning symbols and random numbers MR2-1 for normal symbols. Make numerical data updatable. The random number MR1-2 for the winning symbol corresponds to a special symbol game that is a variable display of a special symbol on the first special symbol display device 4A or the second special symbol display device 4B, and is a determined special symbol that results in the display of a special symbol. Used to determine the design. The random number MR2-1 for symbols per normal symbol is used to determine a fixed normal symbol that is the display result of the normal symbol corresponding to the common symbol game that is the variable display of the normal symbol on the normal symbol display 20. The random number update process P_RANDOM uses the B register, DE register, and HL register as common internal registers when updating the random number MR1-2 for winning symbols and when updating the random number MR2-1 for normal symbols. Each random value can be updated using registers.

When the CPU 103 executes the random number update process P_RANDOM, the CPU 103 sets the random number counter address for the winning symbol by a transfer command for setting the HL register used as the random number pointer (step AKS61). The random number counter address for winning symbols is the address of the random number counter for winning symbols provided in the game work area of the RAM 102. The random number pointer can store the address of the random number counter corresponding to the random number value to be updated, and the random number value to be updated can be specified by setting the stored value. In step AKS61, by storing the address of the random number counter for winning symbols in the random number pointer using the LDQ command, the random numbers MR1-2 for winning symbols can be set as random numbers to be updated.

Following step AKS61, the random number maximum value corresponding to the random number maximum judgment value for winning symbols is set by a transfer command for setting the B register used as the random number maximum value register (step AKS62). The random number maximum value register can store the maximum value that the random number to be updated can take, and the maximum random number value can be specified by setting the stored value. In step AKS62, for the random number MR1-2 for the winning symbol, the maximum value included in the update range of the random number MR1-2, such as C7[H] corresponding to "199", is stored in the random number maximum value register by the LD command. . Thereby, it is possible to set the maximum random number value of the random numbers MR1-2, which are the random numbers to be updated in step AKS61.

Next to step AKS62, a random number initial value data buffer address for winning symbols is set by a transfer command for setting a DE register used as an initial value pointer (step AKS63). The random number initial value data buffer address for winning symbols is the address of the random number initial value data buffer for winning symbols provided in the game work area of the RAM 102. The initial value pointer can store the address of the random number initial value data buffer corresponding to the random number value to be updated, and allows the random number initial value to be acquired or changed by setting the stored value. In step AKS63, by storing the address of the random number initial value data buffer for winning symbols in the initial value pointer using the LDQ command, it is possible to obtain the random number initial value corresponding to the random number MR1-2 that is set as the random number to be updated in step AKS61. and set as changeable. Subsequently, initial value change random number update processing P_RANCP is executed by a subroutine call instruction (step AKS64). The initial value change random number update process P_RANCP in step AKS64 can update the random numbers MR1-2 for winning symbols, which are the random values to be updated, and change the random number initial value, based on the settings in steps AKS61 to AKS63. Make it.

After the initial value change random number update process P_RANCP in step AKS64, a random number counter address for symbols per normal symbol is set by a transfer command for setting the HL register used as a random number pointer (step AKS65). The random number counter address for symbols per normal symbol is the address of the random number counter for symbols per normal symbol provided in the game work area of the RAM 102. In step AKS65, by storing the address of the random number counter for symbols per normal symbol in the random number pointer by the LDQ command, the random number MR2-1 for symbols per normal symbol can be set as the random number value to be updated.

Following step AKS65, a transfer command for setting the B register used as the random number maximum value register sets the maximum random number value corresponding to the random number maximum judgment value for symbols per normal symbol (step AKS66). In step AKS66, for the random number MR2-1 for symbols per normal symbol, the maximum value included in the update range of the random number MR2-1, such as C6[H] corresponding to the maximum value "198", is set to the maximum random number by the LD command. Store in register. Thereby, it is possible to set the maximum random number value of the random number MR2-1, which is the random number to be updated in step AKS65.

Next to step AKS66, a random number initial value data buffer address for symbols per normal symbol is set by a transfer command for setting a DE register used as an initial value pointer (step AKS67). The random number initial value data buffer address for symbols per normal symbol is the address of the random number initial value data buffer for symbols per normal symbol provided in the game work area of the RAM 102. In step AKS67, by storing the address of the random number initial value data buffer for symbols per normal symbol in the initial value pointer using the LDQ command, it is possible to obtain the random number initial value for the random number MR2-1, which is the random number to be updated in step AKS65. and set as changeable. Subsequently, initial value change random number update processing P_RANCP is executed by a subroutine call instruction common to step AKS64 (step AKS68). The initial value change random number update process P_RANCP in step AKS68 updates the random number MR2-1 for symbols per normal symbol, which is the random value to be updated, and changes the random number initial value, based on the settings in steps AKS65 to AKS67. Make it executable.

FIGS. 10-13 are diagrams for explaining a usage example of a data structure related to the random number update process P_RANDOM. In the random number update process P_RANDOM, the random number counter for winning symbols whose address is set in the random number pointer in step AKS61 and the random number initial value data buffer for winning symbols whose address is set in the initial value pointer in step AKS63 are used to update the random number in step AKS64. Initial value change random number update process P_RANCP is executed. In addition, in the random number update process P_RANDOM, a random number counter for normal symbols per symbol whose address is set in the random number pointer in step AKS65, a random number initial value data buffer for symbols per normal symbol whose address is set in the initial value pointer in step AKS67, The initial value change random number update process P_RANCP of step AKS68 is executed using . The random number counter for winning symbols is provided in the random number buffer area for special symbols, and is capable of storing numerical data corresponding to random numbers MR1-2 for winning symbols. The random number initial value data buffer for winning symbols is provided in the random number data area for winning symbols, and is capable of storing numerical data corresponding to the initial random numbers of random numbers MR1-2. The random number counter for symbols per normal symbol is provided in the random number data area for winning symbols, and can store numerical data corresponding to the random number MR2-1 for symbols per normal symbol. The random number initial value data buffer for symbols per normal symbol is provided in the random number data area for winning symbols, and is capable of storing numerical data corresponding to the random number initial value of random number MR2-1. In this way, the random number update process P_RANDOM includes the random number initial value data buffer for winning symbols provided in the random number data area for winning symbols, the random number counter for symbols per normal symbol, and the random number initial value data buffer for symbols per normal symbol. , and a random number counter for winning symbols provided in the random number buffer area for special symbols, it is possible to update the random numbers MR1-2 and MR2-1 by software.

FIG. 10-13(A) shows a configuration example AKB11 of the random number data area for winning symbols. The winning symbol random number data area of configuration example AKB11 includes a random number initial value data buffer for winning symbols at address F050[H], an initial value random number counter for winning symbols at address F051[H], and a normal symbol at address F052[H]. It includes a random number counter for winning symbols, a random number initial value data buffer for symbols per normal symbol at address F053[H], and an initial value random number counter for symbols per normal symbol at address F054[H]. Among these, the address F050[H] of the random number initial value data buffer for winning symbols is set to the initial value pointer by step AKS63 of the random number update process P_RANDOM, and the address F052[H] of the random number counter for normal symbols is set in the random number update process. The random number pointer is set by step AKS65 of P_RANDOM, and the address F053[H] of the random number initial value data buffer for symbols per normal symbol is set to the initial value pointer by step AKS67 of the random number update process P_RANDOM. The initial value random number counter for winning symbols can store numerical data corresponding to random numbers MR1-3, which are the initial values for winning symbols. The initial value random number counter for symbols per normal symbol can store numerical data corresponding to the random number MR2-2 which becomes the initial value for symbols per normal symbol.

FIG. 10-13(B) shows a configuration example AKB12 of the special symbol random number buffer area. The random number buffer area for special symbols in configuration example AKB12 includes a random number buffer for special symbol determination at address F07F[H], a random number counter for winning symbols at address F081[H], and a fluctuation pattern type selection at address F082[H]. It includes a random number buffer, a random number buffer for fluctuating patterns at address F083[H], and a random number buffer for selecting a losing effect at address F084[H]. Among these, the address F081 [H] of the random number counter for winning symbols is set to the random number pointer by step AKS61 of the random number update process P_RANDOM. The random number buffer for special symbol determination can store numerical data corresponding to the random number MR1-1 for special symbol determination obtained from the 16-bit random number circuit 104A. The random number buffer for selecting a variation pattern type can store numerical data corresponding to the random number MR3-3 for selecting a variation pattern type obtained from the 8-bit random number circuit 104B. The fluctuation pattern random number buffer can store numerical data corresponding to the fluctuation pattern random numbers MR3-4 obtained from the 8-bit random number circuit 104B. The random number buffer for selecting a losing performance can store numerical data corresponding to the random number MR3-2 for selecting a losing performance obtained from the 16-bit random number circuit 104A.

FIG. 10-14 is a flowchart showing an example of the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP is included in the process that can be called from the random number update process P_RANDOM shown in FIG. It can be executed in step AKS68 after setting the random number MR2-1 for symbols per normal symbol in steps AKS65 to AKS67. Such an initial value change random number update process P_RANCP enables the value of the random number MR1-2 to be updated using the numerical data corresponding to the random number MR1-2 for the winning symbol in step AKS64. In addition, the initial value change random number update process P_RANCP allows the value of the random number MR2-1 to be updated using numerical data corresponding to the random number MR2-1 for symbols per normal symbol in step AKS68.

When the CPU 103 executes the initial value change random number update process P_RANCP, it first executes a comparison addition instruction (step AKS101). This comparison and addition instruction uses the stored data at the address indicated by the value stored in the HL register, which is a random number pointer, as the update target value, and the value stored in the B register, which is the maximum random number value register, as the comparison judgment value. It can be executed by a single ICPLD instruction. The value stored in the HL register, which is a random number pointer, indicates the address of the random number counter where numerical data corresponding to the random number value to be updated is stored. The value stored in the B register, which is the maximum random number value register, indicates the maximum random number value set corresponding to the random number value to be updated. Then, when the count value of the random number counter indicating the random value to be updated is less than the value stored in the random number maximum value register, the count value of the random number counter is updated by adding 1, so that the random value to be updated is increased by 1. be done. On the other hand, if the count value of the random number counter indicating the random value to be updated is greater than or equal to the value stored in the random number maximum value register, by clearing the random number counter and initializing the count value to "0", the update target The random value is changed to the minimum random number value. Therefore, the comparison and addition instruction in step AKS101 is to compare the random number value to be updated with the maximum random number value, to add 1 to the random number value to be updated if the result of the comparison is less than the maximum random number value, and to add 1 to the random number value to be updated if the result of the comparison is the maximum random number value. This is a single instruction that includes changing the random number value to be updated to the minimum random number value if it is greater than or equal to the value. In this way, when updating the random number value to be updated by the initial value change random number update process P_RANCP, a single comparison and addition instruction is executed first. By first executing such a single comparison and addition instruction, it is possible to suppress the occurrence of defects and update the random value appropriately.

When the comparison addition instruction is executed in step AKS101, a transfer instruction for reading stored data loads the random value pointed to by the random number pointer (step AKS102). Furthermore, the random number pointer and the initial value pointer are exchanged (step AKS103). Then, the random number value loaded in step AKS102 is compared with the random number initial value data buffer pointed to by the initial value pointer (step AKS104). It is determined whether the random number value compared at this time is a value different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105). The value stored in the DE register, which is the initial value pointer, indicates the address of the random number initial value data buffer corresponding to the random number value to be updated. Therefore, in step AKS104, after executing the comparison addition instruction in step AKS101, the update target random number value updated by the comparison addition instruction is compared with the random number initial value.

Corresponding to step AKS105, if the random number value is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105; Yes), the initial value change random number update process P_RANCP ends. When the comparison and addition instruction of step AKS101 is executed, the count value of the random number counter indicating the random number value to be updated will indicate the random number value to be updated after the update. Then, when the initial value change random number update process P_RANCP is terminated as a result of the determination in step AKS105, the stored value of the random number counter indicating the updated random number value to be updated is stored as is as the current random number value. Therefore, in step AKS105, if the updated random number value does not match the random number initial value, the initial value change random number update process P_RANCP is completed, and the updated random number value is stored as the current random number value. be able to.

Corresponding to step AKS105, when the random value is the same as the stored value of the random number initial value data buffer pointed to by the initial value pointer (step AKS105; No), the initial value pointed to when the stored value of the initial value pointer is added by 1 A random number counter is loaded (step AKS106). In the configuration example AKB11 of the random number data area for winning symbols shown in FIG. 10-13(A), the next address F051[H] is added by 1 to the address F050[H] where the random number initial value data buffer for winning symbols is provided. H] is provided with an initial value random number counter for winning symbols. In addition, an initial value random number counter for symbols per normal symbol is provided at the next address F054[H] when 1 is added to address F053[H] where the random number initial value data buffer for symbols per normal symbol is provided. . Therefore, in step AKS106, when the stored value of the initial value pointer indicates the address of the random number initial value data buffer for winning symbols, the count value of the initial value random number counter for winning symbols is read out. Further, in step AKS106, when the stored value of the initial value pointer indicates the address of the random number initial value data buffer for symbols per normal symbol, the count value of the initial value random number counter for symbols per normal symbol is read out. In this way, in step AKS106, the count value of the initial value random number counter can be read out as the initial value random value.

When the initial value random number counter is loaded in step AKS106, the count value of the initial value random number counter thus read is stored in the random number counter pointed to by the random number pointer (step AKS107). Since the stored value of the random number pointer indicates the address of the random number counter corresponding to the random number value to be updated, step AKS107 allows the count value of the initial value random number counter to be stored as the current random number value to be updated. Therefore, if the updated random number value matches the random number initial value according to the determination result in step AKS105, step AKS107 stores the initial value random number read out in step AKS106 as the current random number value. Can be done.

Following step AKS107, the count value of the initial value random number counter read out in step AKS106 is stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS108), and then the initial value change random number update process P_RANCP is performed. finish. Since the stored value of the initial value pointer indicates the address of the random number initial value data buffer corresponding to the random number value to be updated, step AKS108 allows the count value of the initial value random number counter to be stored as a new random number initial value. Therefore, if the updated random number value matches the initial random number value according to the determination result in step AKS105, the random number value for the initial value is stored as the current random number value in step AKS107, and the random number value for the initial value is stored as the current random number value in step AKS108. The generated random number for initial value can be stored as a new random number initial value. In this way, by setting a new random number initial value, the uncertainty of the random number value is increased, and by storing it as the current random number value, an increase in data capacity is prevented, and it is possible to update the random number value appropriately.

The random number update process P_RANDOM shown in FIG. 10-12 is performed in steps AKS61 to AKS63, after setting the random number to be updated, the maximum random number value, and the random number initial value for the random number MR1-2 for winning symbols, and then returns to step AKS64. Execute the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP makes it possible to update the random number value to be updated and change the initial random number value based on the settings regarding the random number value to be updated, the maximum random number value, and the initial random number value. The initial value change random number update process P_RANCP in step AKS64 uses the random number maximum value set in step AKS62 and the random number initial value set in step AKS63 for the random numbers MR1-2 for winning symbols that are set as the random values to be updated in step AKS61. enable updates. In addition, the initial value change random number update process P_RANCP in step AKS64 is performed when the random number MR1-2 for the winning symbol, which is set as the random value to be updated in step AKS61, matches the random number initial value set in step AKS63. Enables changing the initial value of random numbers. In this way, by updating the set random number value to be updated, it becomes possible to update the random number value appropriately.

In the random number update process P_RANDOM, after setting the random number to be updated, the maximum random number value, and the random number initial value for the random number MR2-1 for symbols per normal symbol in steps AKS65 to AKS67, the initial value change random number update in step AKS68 is performed. Execute processing P_RANCP. The initial value change random number update process P_RANCP in step AKS68 uses the random number maximum value set in step AKS66 and the random number initial value set in step AKS67 for the random number MR2-1 for the symbol per normal symbol, which is the random number to be updated in step AKS65. Enables updates using . In addition, the initial value change random number update process P_RANCP in step AKS68 is performed when the random number MR2-1 for the symbol per normal symbol, which is set as the random value to be updated in step AKS65, matches the random number initial value set in step AKS67. In addition, it is possible to change the initial value of random numbers. In this way, by updating the set random number value to be updated, it becomes possible to update the random number value appropriately. Further, by updating the set random number value to be updated or changing the initial value of the random number, it becomes possible to update the random number value appropriately.

The random number update process P_RANDOM can update the random numbers MR1-2 for winning symbols, which are used to determine the display results of special symbols, by the first update process consisting of steps AKS61 to AKS64, and update the display results of normal symbols. The random number MR2-1 for symbols per normal symbol used for determination can be updated by a second update process consisting of steps AKS65 to AKS68. Then, in steps AKS61 to AKS64, the random number MR1-2 for the winning symbol is updated as the first random number, and then, the random number MR2-1 for the normal symbol per symbol is updated as the second random number in steps AKS65 to AKS68. . The confirmed special symbol that is the display result of the special symbol corresponds to the maximum number of openings of the jackpot opening in the jackpot game state. In addition, the confirmed special symbol that is the display result of the special symbol will be controlled in a variable probability state after the end of the jackpot game state, and the maximum number of variable displays that can be executed in the time saving state after the end of the jackpot game state. In some cases, it corresponds to On the other hand, the confirmed normal symbol, which is the display result of the normal symbol, corresponds to the opening time and the number of openings of the second grand prize opening. Therefore, the display result of the special symbol attracts a higher degree of attention from the player than the display result of the normal symbol. The random number update process P_RANDOM, which is a specific update process, updates the random number MR1-2 as the first random value, and then updates the random number MR2-1 as the second random value, so that the displayed results that are of high interest to the players can be updated. By updating the first random value used for determination before the second random value, it is possible to suppress the occurrence of problems and to update the random value appropriately.

In the random number update process P_RANDOM, steps AKS61 to AKS64 can update the random number MR1-2, which is the first random value, and steps AKS65 to AKS68 can update the random number MR2-1, which is the second random value. Then, it is possible to call and execute the initial value change random number update process P_RANCP of step AKS64 in response to the random number MR1-2 that is the first random value, and step AKS68 in response to the random number MR2-1 that is the second random value. It can be executed by calling the initial value change random number update process P_RANCP. In this way, the random number update process P_RANDOM, which is a specific update process, updates the first random number by calling the initial value change random number update process P_RANCP, which is a common update process, corresponding to the first random value and the second random value. The random number MR1-2 as a numerical value and the random number MR2-1 as a second random value are updated, and their initial values can be changed. The initial value change random number update process P_RANCP, which is a common update process, prevents an increase in program capacity, stably updates the first random value and second random value, and allows appropriate random value updates. become.

In the random number update process P_RANDOM, steps AKS61 to AKS64 that make it possible to update the random number MR1-2 that becomes the first random value become the first update process, and steps AKS65 to AKS65 that make it possible to update the random number MR2-1 that becomes the second random value. AKS68 becomes the second update process. The first update process can be executed by calling the initial value change random number update process P_RANCP in step AKS64, and the second update process can be executed by calling the initial value change random number update process P_RANCP in step AKS68. In this way, the random number update process P_RANDOM calls the initial value change random number update process P_RANCP as a common update process in the first update process and the second update process, thereby changing the random numbers MR1-2 and MR1-2 as the first random values. The random number MR2-1 as the second random value is updated, and its initial value can be changed. The initial value change random number update process P_RANCP, which is a common update process, prevents an increase in program capacity, stably updates the first random value and second random value, and allows appropriate random value updates. become.

In the random number update process P_RANDOM, steps AKS61 to AKS64 that make it possible to update the random number MR1-2 that becomes the first random value become the first update process, and steps AKS65 to AKS65 that make it possible to update the random number MR2-1 that becomes the second random value. AKS68 becomes the second update process. Then, in the first update process and the second update process, the HL register, B register, and DE register of the CPU 103, which are common internal storage means, are used to generate the random numbers MR1-2 as the first random value and the second random number MR1-2 as the first random value. The random number MR2-1 as a numerical value is made updateable. In this way, it is possible to stably update the first random number value and the second random number value using a common internal storage means, and to update the appropriate random number value.

In the random number update process P_RANDOM, before executing the initial value change random number update process P_RANCP in step AKS64, steps AKS61 to AKS63 change the random number counter address for winning symbols, the random number maximum judgment value for winning symbols, and the random number initial value data for winning symbols. Reference destination information such as a buffer address is stored in the HL register, B register, and DE register of the CPU 103, which is an internal storage means. In addition, in the random number update process P_RANDOM, before executing the initial value change random number update process P_RANDCP in step AKS68, in steps AKS65 to AKS67, the random number counter address for symbols per normal symbol, the random number maximum judgment value for symbols per normal symbol, the normal Reference destination information such as a random number initial value data buffer address for each symbol is stored in the HL register, B register, and DE register of the CPU 103, which is an internal storage means. The instruction used to update the random number MR1-2, which becomes the first random value in step AKS61, and the instruction used to update the random number MR2-1, which becomes the second random value in step AKS65, set the HL register of the CPU 103. These instructions are common in that step AKS61 sets the random number counter address for winning symbols, but step AKS65 sets the random number counter address for normal symbols, so different reference destination information can be set. The instruction used to update the random number MR1-2, which becomes the first random value in step AKS62, and the instruction used to update the random number MR2-1, which becomes the second random value in step AKS66, set the B register of the CPU 103. This is a common command in that step AKS62 sets the maximum random number value corresponding to the maximum random number judgment value for winning symbols, but step AKS66 sets the maximum random number value corresponding to the maximum random number judgment value for normal symbols. Different reference destination information can be set. The instruction used to update the random number MR1-2, which becomes the first random value in step AKS63, and the instruction used to update the random number MR2-1, which becomes the second random value in step AKS67, set the DE register of the CPU 103. This command is common in that step AKS63 sets the random number initial value data buffer address for winning symbols, but step AKS67 sets the random number initial value data buffer address for normal symbols, so different reference destination information can be set. be. These steps AKS61 to AKS63 and steps AKS65 to AKS67 make it possible to set different reference destination information using common instructions, such as the LD instruction and LDQ instruction, which are transfer instructions for setting the internal registers of the CPU 103. do. Then, in step AKS64 and step AKS68, the initial value change random number update process P_RANCP is called and executed by a common subroutine call instruction. In this way, in the random number update process P_RANDOM, which is a specific update process, an instruction used to update the random number MR1-2, which is the first random value, and an instruction used to update the random number MR2-1, which is the second random value. , is common. By making it possible to update the random number MR1-2 as the first random value and the random number MR2-1 as the second random value using a common instruction, the first random value and the second random value can be updated stably. This makes it possible to update appropriate random values.

The random number update process P_RANDOM makes it possible to update the random numbers MR1-2, which are the first random values, through steps AKS61 to AKS64, which are the first update process, and update them with the second random values, which are the steps AKS65 to AKS68, which are the second update process. The random number MR2-1 can be updated. Then, the initial value change random number update process P_RANCP can be called and executed in steps AKS64 and AKS68. The initial value change random number update process P_RANCP shown in Figure 10-14 first executes a single comparison and addition instruction, so when updating the random numbers MR1-2 as the first random value and as the second random number In both cases, the comparison and addition instruction is made executable first. By first executing such a comparison and addition instruction, it is possible to suppress the occurrence of defects in the first random number value and the second random number value, and to update the random number value appropriately.

The initial value change random number update process P_RANCP can update the random numbers MR1-2 for winning symbols when executed in step AKS64 of the random number update process P_RANDOM, and can update the random numbers MR1-3 that will be the initial value for the winning symbols. It is possible to change the random number initial value corresponding to the random number MR1-2 for winning symbols by using the random number MR1-2. In addition, when the initial value change random number update process P_RANCP is executed in step AKS68 of the random number update process P_RANDOM, it is possible to update the random number MR2-1 for the symbol per normal symbol, and the initial value for the symbol per normal symbol. It is possible to change the random number initial value corresponding to the random number MR2-1 for symbols per normal symbol using the random number MR2-2. Therefore, the random numbers MR1-3, which are the initial values for winning symbols, are changed when the random number to be updated becomes the first random number by executing the initial value change random number update process P_RANCP in step AKS64 of the random number update process P_RANDOM. This is a first initial value random number used when changing the random number initial value corresponding to the random number MR1-2 for symbols. The random number MR2-2, which is the initial value for the symbol per normal symbol, is changed to the normal value where the random number to be updated becomes the second random number by executing the initial value change random number update process P_RANCP at step AKS68 of the random number update process P_RANDOM. This is a second initial value random number used when changing the random number initial value corresponding to the random number MR2-1 for each symbol.

FIG. 10-15 is a flowchart showing an example of the initial value determination random number update process P_TFINIT. The initial value determination random number update process P_TFINIT is included in the process that can be called from the main process P_MAIN for game control shown in FIG. 4, and is executed in step S9 of the loop process that is repeated until a timer interrupt occurs after step S7. It is executable. In addition, the initial value determination random number update process P_TFINIT is included in the processes that can be called from the game control timer interrupt process P_PCT shown in FIG. It can be executed in step AKS57 in response to the occurrence. Therefore, the initial value determination random number update process P_TFINIT consists of a first process that can be executed in response to a timer interrupt after a predetermined time has elapsed, and a second process that can be repeatedly executed until the first process is executed. included. In addition, the initial value determination random number update process P_TFINIT can be called and executed in the game control timer interrupt process P_PCT that controls the progress of the game, and can also be executed based on the start of power supply to the pachinko game machine 1. In the main process P_MAIN for game control, after startup processes such as the power supply start corresponding process P_POWER_ON in step S1, it can be called and executed by step S9 included in the standby process as a repeated loop process. . In this way, the initial value determining random number update process P_IFINIT is included in the processes that can be executed in response to regular timer interrupts as a random number update process for initial values, and can also be executed irregularly and repeatedly. By being included, the update period and update speed of the random value for initial value become undefined, so the uncertainty of the random value for initial value is increased, and it becomes possible to update the random value appropriately.

When the CPU 103 executes the initial value determining random number update process P_TINIT, the CPU 103 sets the initial value random number counter address for the winning symbol by a transfer command for setting a pointer (step AKS81). The initial value random number counter address for winning symbols is the address F051[H] assigned to the initial value random number counter for winning symbols in the configuration example AKB11 of the random number data area for winning symbols shown in FIG. 10-13(A). be. When the pointer is set in this way, the count value of the initial value random number counter for winning symbols can be updated within the update range of "0" to "199" by the comparison addition instruction (step AKS82). This comparison and addition instruction uses the stored data at the address pointed to by the pointer as the update target value, uses the immediate value specified by the operand as the comparison judgment value, and can be executed by a single ICPLD instruction, which is the third special transfer instruction. The stored value of the pointer indicates the address of the random number counter where numerical data corresponding to the random value for the initial value to be updated is stored. The immediate value specified by the operand indicates the maximum random number value for initial values set corresponding to the random number value for initial values to be updated. Then, when the count value of the random number counter indicating the random value for the initial value to be updated is less than the maximum random number value for the initial value, by updating the count value of the random number counter by adding 1, A random value is added by 1. On the other hand, if the count value of the random number counter indicating the random value for the initial value to be updated is greater than or equal to the value stored in the random number maximum value register for the initial value, the random number counter is cleared and the count value is initialized to "0". By doing so, the random number value for the initial value to be updated is changed to the minimum random number value. Therefore, the comparison and addition instruction in step AKS82 sets the random numbers MR1-3, which are the initial values for the winning symbols, as the random numbers for the initial values to be updated, and compares the random numbers for the initial values to be updated with the maximum random number value for the initial values. If the result of comparison is less than the maximum random number for initial value, add 1 to the random number for initial value to be updated.If the result of comparison is greater than or equal to the maximum random number for initial value, add random number for initial value to be updated. It is a single instruction that involves changing a number to a random minimum value. Note that the comparison and addition instruction is not limited to the ICPLD instruction in which the address of storage data indicating the value to be updated is specified by a pointer; for example, the upper address is set using the Q register and specified by the first operand of the comparison and addition instruction. Even if it is an ICPLDQ instruction in which the lower address is set using the immediate value set. In this case, the immediate value specified by the second operand of the comparison and addition instruction may be set as the comparison judgment value. By updating the random number value for the initial value to be updated using such a comparison and addition instruction, it is possible to suppress the occurrence of problems and update the random number value appropriately.

After step AKS82, an initial value random number counter address for symbols per normal symbol is set by a transfer command for setting a pointer (step AKS83). The initial value random number counter address for symbols per normal symbol is the address F054 assigned to the initial value random number counter for symbols per normal symbol in the configuration example AKB11 of the random number data area for winning symbols shown in FIG. 10-13(A). [H]. When the pointer is set in this way, the count value of the initial value random number counter for symbols per normal symbol can be updated in the update range of "1" to "198" by the comparison addition instruction (step AKS84), and the initial value The determining random number update process P_TFINIT ends. The comparison and addition instruction in step AKS84 may be any comparison and addition instruction similar to step AKS82. However, in the comparison and addition instruction in step AKS84, the random number MR2-2, which is the initial value for each symbol per symbol, is set as the random value for the initial value to be updated, so it is The immediate value is set to a different value from the compare and add instruction in step AKS82. Therefore, in the comparison and addition instruction of step AKS84, the random number MR2-2, which is the initial value for the symbol per normal symbol, is set as the random number for the initial value to be updated, and the random number for the initial value to be updated is set to the maximum random number for the initial value. If the comparison result is less than the maximum random number value for initial values, add 1 to the random value for the initial value to be updated.If the comparison result is greater than or equal to the maximum random number value for initial values, the initial value to be updated. This is a single instruction that includes changing the random number value to the minimum random number value. By updating the random number value for the initial value to be updated using such a comparison and addition instruction, it is possible to suppress the occurrence of problems and update the random number value appropriately.

The initial value determining random number update process P_TFINIT updates the random numbers MR1-3, which become the initial values for winning symbols, by steps AKS81 and AKS82, as an update of the first initial value random number. At the same time, the initial value determining random number update process P_TFINIT updates the random number MR2-2, which becomes the initial value for the symbol per normal symbol, by steps AKS83 and AKS84, as an update of the second initial value random number. The random number MR1-3 that becomes the initial value for the winning symbol is the first random number used when changing the initial random number value when the random number to be updated is the random number MR1-2 for the winning symbol that becomes the first random number. This is a random value for the initial value. Random number MR2-2, which is the initial value for symbols per normal symbol, is used when changing the initial random number value when the random number to be updated is random number MR2-1 for symbols per normal symbol, which is the second random value. This is a random number value for the second initial value. Steps AKS81 and AKS82 of the initial value determining random number update process P_TFINIT become a first initial value update process that can update the random number value for the first initial value. Steps AKS83 and AKS84 of the initial value determining random number update process P_TFINIT are second initial value update processes that can update the second initial value random number value. By updating the random value for the first initial value and the random value for the second initial value, it is possible to update the random value appropriately so that the uncertainty of the first random value and the second random value is reliably increased. Become.

In addition, in the initial value determination random number update process P_TFINIT, the random numbers MR1-3, which are the initial values for winning symbols, are updated as the first initial value random numbers in steps AKS81 and AKS82, and then the second random numbers MR1-3 are updated in steps AKS83 and AKS84. The random number MR2-2, which becomes the initial value for the symbol per normal symbol, is updated as the random number for the initial value. Therefore, in the initial value determining random number update process P_TFINIT, after updating the random numbers MR1-3, which are the random values for the first initial value and become the initial values for winning symbols, in steps AKS81 and AKS82, which are the first initial value update process, Steps AKS83 and AKS84, which are the second initial value updating process, update the random number MR2-1, which is the random value for the second initial value and is the initial value for the symbol per normal symbol.

FIG. 10-16 is a flowchart showing an example of the starting port switch passage process P_TZU_ON. The starting port switch passing process P_TZU_ON is included in the processes that can be called from the special symbol process process P_TPROC shown in FIG. 6, and can be executed in step S104 when the first starting prize corresponding flag is on in step S103. Yes, and it can be executed in step S108 if the second starting prize corresponding flag is on in step S107. When the CPU 103 executes the starting port switch passing process P_TZU_ON, the CPU 103 sets the starting port winning storage counter address by a transfer command for setting a pointer (step AKS201). The starting opening winnings storage counter address is the address of the first starting opening winnings storage counter or the second starting opening winnings storage counter provided in the game work area of the RAM 102. In step AKS201, it is possible to specify a different address in the game work area corresponding to the first starting opening winning table or the second starting opening winning table set by the special symbol process P_TPROC. For example, the upper address F0 [H] of the game work area, which is the work area, is set in the upper byte of the pointer by a transfer command, and is stored in the first starting slot winning table or the second starting opening winning table pointed to by the table pointer. The lower address of the starting opening prize storage counter is set in the lower byte of the pointer by the transfer command. As a result, the value indicating the address of the first starting opening winning storage counter or the second starting opening winning storage counter is stored in the internal register of the CPU 103, which serves as a pointer. Subsequently, the starting opening prize storage counter is loaded by a transfer command for reading the storage data at the address pointed to by the pointer (step AKS202).

Next to step AKS202, it is determined whether or not the count value of the starting opening prize storage counter is greater than or equal to the maximum value of the counter (step AKS203). For example, by using a comparison return command that can compare the value loaded in step AKS202 and a counter maximum value such as "4", if the counter maximum value is greater than or equal to the maximum value (step AKS203; Yes), the starting port switch passing process P_TZU_ON is completed and returns to special pattern process processing P_TPROC. On the other hand, if it is less than the maximum value of the counter (step AKS203; No), the count value of the starting opening winnings storage counter is updated to be incremented by 1 (step AKS204). In this case, an arithmetic and logic operation instruction that increments the stored data at the address pointed to by the pointer makes it possible to update the count value of the first starting opening winnings storage counter or the second starting opening winnings storage counter by adding one.

After step AKS204, a special symbol determination buffer address is set to the transfer destination (step AKS205). The special symbol determination buffer address is the first special symbol determination buffer included in the first special symbol retention buffer provided in the game work area of the RAM 102 or the second special symbol determination buffer included in the second special symbol retention buffer. This is the address. In step AKS205, the first starting opening winning table or the second starting opening winning table set by the special symbol process P_TPROC and the count value of the first starting opening winning counter or the second starting opening winning counter loaded in step AKS202 are used. , it is possible to specify different addresses in the game work area.

The first special symbol holding buffer includes a first special symbol determination buffer, a first winning symbol buffer, a first variation pattern type selection buffer, a first variation pattern buffer, and a first loss effect selection buffer. For example, the buffer number changes from "0" to "4" in response to the case where the first reserved storage buffer is currently executing the variable display of the first special symbol and the number of first reserved memories that have not been executed yet. '' are secured as multiple storage areas, such as five storage areas corresponding to ``.''. The second special symbol holding buffer includes a second special symbol determination buffer, a second winning symbol buffer, a second variation pattern type selection buffer, a second variation pattern buffer, and a second loss performance selection buffer. For example, the buffer number changes from "0" to "4" in the second pending memory buffer corresponding to the case where the variable display of the second special symbol is being executed and the number of second pending memories that have not been executed yet. '' are secured as multiple storage areas, such as five storage areas corresponding to ``.''.

In step AKS205, the value corresponding to the buffer size of the first pending storage buffer and the second pending storage buffer is multiplied by the count value of the starting opening winning counter, and the first pending storage buffer with buffer number "1" is Alternatively, the multiplied value is added to the lower address of the second pending storage buffer. By setting such an added value to the transfer destination pointer, it is sufficient if the special symbol determination buffer address can be set to the transfer destination.

Following step AKS205, the RL0 hard latch random value register address is set (step AKS206). The RL0 hard latch random value register address is the address of the RL0 hard latch random value register provided in the function control register area. For example, the upper address FF[H] of the function control register area is set to the upper byte of the pointer by a transfer command, and the RL0 hard drive stored in the first start prize table or the second start prize table pointed to by the table pointer is The lower address of the latch random value register is set in the lower byte of the pointer by the transfer instruction. The first starting opening winning table stores the lower address of the RL0 hard latch random value register, which is the buffer number "0". The second starting opening winning table stores the lower address of the RL0 hard latch random value register, which is the buffer number "1". As a result, as the address of the RL0 hard latch random value register, different addresses are stored in the internal register of the CPU 103, which serves as a pointer, in the case of the first starting prize and the second starting winning.

After step AKS206, the RL0 hard latch random value register is loaded by a transfer command for reading the stored data at the address pointed to by the pointer (step AK207). The stored value of the RL0 hard latch random value register thus obtained is stored in the special symbol determination random number buffer by a transfer command for writing to the storage area of the designated address in the game work area of the RAM 102 (step AKS208). In this way, by storing the numerical data obtained from the RL0 hard latch random value register in the random number buffer for special symbol determination, numerical data indicating the value of the random number MR1-1 for special symbol determination is extracted, The value of random number MR1-1 can be stored in the random number buffer for special symbol determination.

After step AKS208, the RL2 soft latch random value register is loaded by a transfer command for reading stored data from the storage area at the specified address in the function control register area (step AKS209). The stored value of the RL2 soft latch random value register acquired at this time is stored in the random number buffer for losing performance selection by a transfer command for writing to the storage area of the specified address in the game work area of the RAM 102 (step AKS210). In this way, by storing the numerical data obtained from the RL2 soft latch random value register in the random number buffer for selecting a losing effect, numerical data indicating the value of the random number MR3-2 for selecting a losing effect is extracted, The value of the random number MR3-2 can be stored in the random number buffer for selecting a losing performance.

After step AKS210, the RS1 soft latch random value register is loaded by a transfer command for reading stored data from the storage area at the specified address in the function control register area (step AKS211). The stored value of the RS1 soft latch random value register acquired at this time is stored in the random number buffer for variation pattern type selection by a transfer command for writing to the storage area of the specified address in the game work area of the RAM 102 (step AKS212). In this way, by storing the numerical data obtained from the RS1 soft latch random value register in the random number buffer for fluctuating pattern type selection, numerical data indicating the value of the random number MR3-3 for fluctuating pattern type selection is extracted. Then, the value of the random number MR3-3 can be stored in the random number buffer for variation pattern type selection.

After step AKS212, the RS2 soft latch random value register is loaded by a transfer command for reading stored data from the storage area at the specified address in the function control register area (step AKS213). The stored value of the RS2 soft latch random value register acquired at this time is stored in the random number buffer for variable patterns by a transfer command for writing to the storage area of the specified address in the game work area of the RAM 102 (step AKS214). In this way, by storing the numerical data obtained from the RS2 soft latch random value register in the random number buffer for fluctuation patterns, the numerical data indicating the value of random numbers MR3-4 for fluctuation patterns is extracted, and A value of -4 can be stored in the random number buffer for variation patterns.

Following step AKS214, a block is transferred from the random number buffer to the special symbol determination buffer (step AKS215). The random number buffer is a random number buffer for special symbol determination in which the value of random number MR1-1 is stored in step AKS208, a random number buffer for loss effect selection in which the value of random number MR3-2 is stored in step AKS210, and a random number buffer for selecting random number MR3- in step AKS212. It is configured to include a random number buffer for fluctuating pattern type selection in which a value of MR3 is stored, and a random number buffer for fluctuating pattern in which a value of random numbers MR3-4 is stored in step AKS214. In step AKS215, the address of the random number buffer for special symbol determination is set as the transfer source, and the value corresponding to the buffer size of the random number buffer is set as the number of transfers. In addition, the buffer address for special symbol determination which becomes a transfer destination is set by step AKS205. Based on these settings, by executing a block transfer instruction, each random number value temporarily stored in the random number buffer is stored as new pending information in the first pending storage buffer or the second pending storage buffer. can be done.

After the new storage information is stored in step AKS215, it is determined whether or not the winning performance condition is satisfied (step AKS216). The winning effect condition may be set in advance as a condition for enabling the pre-read effect. For example, when the starting opening winning designation value is "2", it is determined that the winning presentation condition is satisfied. In addition, when the starting opening winning designation value is "1", the time saving function flag is "0" corresponding to not being in a time saving state, and also corresponding to not being in a small winning gaming state or a jackpot gaming state. When the special symbol process code is less than 03[H], it is determined that the winning performance condition is satisfied. When it is determined that the winning performance condition is satisfied (step AKS216; Yes), the winning performance process P_GAME_CHK is executed (step AKS217). The winning performance process P_GAME_CHK includes the determination of the winning of special symbols, selects the specified performance value corresponding to the determination result, etc., and enables the transmission of the winning performance command.

If it is determined in step AKS216 that the winning presentation condition is not satisfied (step AKS216; No), or after executing the winning presentation processing in step AKS217, the presentation is performed by a transfer command for setting a pointer. A storage information designation command transmission table address is set (step AKS218). The performance storage information designation command transmission table address is the address of the performance storage information designation command transmission table stored in the game data area of the ROM 101. Then, by executing the command set process P_COM_SET (step AKS219), it becomes possible to transmit the first performance storage information designation command or the second performance storage information designation command as the start winning command. The first performance storage information designation command is a performance control command that designates the first pending storage number indicated by the count value of the first starting opening winning storage counter. The second performance storage information designation command is a performance control command that designates the second pending storage number indicated by the count value of the second starting gate winning storage counter. In this way, by the command set process P_COM_SET of step AKS219, it is possible to transmit the production control command which becomes the start winning command from the main board 11 to the production control board 12.

Next to step AKS219, a starting opening winning buffer storage counter address is set by a transfer command for setting a pointer (step AKS220). The starting opening winning buffer storage counter address is the address of the starting opening winning buffer storage counter provided in the game work area of the RAM 102. In this way, the count value of the starting opening winning buffer storage counter to which the address has been set is updated to be incremented by 1 (step AKS221). Furthermore, the pointer is updated in accordance with the starting opening winning buffer storage counter using a composite transfer instruction for setting a register or a pointer (step AKS222). For example, by loading the count value of the starting slot winning buffer storage counter updated in step AKS221 into the internal register of the CPU 103, and updating the stored value of the pointer by adding 1, the start address of the starting slot winning buffer A value indicating the value is stored in the pointer. Furthermore, by adding the loaded count value of the starting opening winning buffer storage counter to the stored value of the pointer, it is possible to specify the storage area of the buffer number to be updated in the starting opening winning buffer.

When the pointer is updated in step AKS222, the starting opening winning designation value is loaded (step AKS223). The starting slot winning designation value corresponds to the first starting slot winning table or the second starting slot winning table set by the special symbol process processing P_TPROC, and is "1" indicating the first starting winning or the second starting winning. "2" can be set. In step AKS223, the starting opening winning designation value can be obtained by a transfer command for reading table data from the first starting opening winning table or the second starting opening winning table. The starting slot winning designation value thus obtained is stored in the starting slot winning buffer by a transfer command for writing to the storage area of the address pointed to by the pointer (step AKS224), and the starting slot switch passing process P_TZU_ON ends.

FIG. 10-17 is a diagram for explaining a usage example of the data structure regarding the starting port switch passage process P_TZU_ON. In the starting port switch passing process P_TZU_ON, various types of winnings are made using the first starting port winning table set in step S102 of the special symbol process P_TPROC shown in FIG. 6 or the second starting port winning table set in step S106. Settings and controls are performed. For example, the first starting opening winning memory counter and the second starting opening winning memory counter whose count values can be updated in step AKS204 are provided in the special symbol control data area, and are set to the first pending memory number and the second pending memory number. Corresponding data can be stored. The starting slot winning buffer storage counter whose count value can be updated by AKS221 and the starting opening winning buffer where the designated starting opening winning value is stored by AKS224 are provided in the starting opening winning buffer area, and are used to store first starting winnings and second starting winnings. It is possible to memorize the total number of winnings and the order in which they occurred. Further, in the command set process P_COM_SET of step AKS219, the first effect storage information designation command transmission table or the second effect storage information designation command transmission table whose address is set in step AKS218 is used.

In this way, the starting port switch passing process P_TZU_ON is executed by the first starting port winning table, the second starting port winning table, the first starting port winning memory counter or the second starting port winning memory counter provided in the special symbol control data area. , Variable display of special symbols using the starting opening winning buffer storage counter, the starting opening winning buffer, the first performance storage information specification command transmission table or the second performance storage information specification command transmission table provided in the starting opening winning buffer area. This enables control regarding the special figure game.

FIG. 10-17 (A1) shows a configuration example AKT21 of the first starting opening winning table. The first starting hole winning table of the configuration example AKT21 includes the lower address of the first starting hole winning memory counter, the lower address of the RL0 hard latch random value register number "0", and the first special symbol determination buffer number "1". , the address of the first performance storage information designation command transmission table, and the starting opening winning designation value "1".

The first starting opening prize storage counter is provided in the game work area of the RAM 102, and is capable of storing data corresponding to the first pending storage number. The RL0 hard latch random value register number "0" is the RL0 hard latch random value register with the register number "0" provided in the function control register area, and the channel RL0 provided in the 16-bit random number circuit 104A can be generated. Regarding the random number MR1-1 for special symbol determination, numerical data indicating its value can be acquired and stored by a hard latch. The first special symbol determination buffer number "1" is a first special symbol determination buffer included in the first reservation storage buffer with the buffer number "1" in the first special symbol reservation buffer. The first performance storage information designation command transmission table is stored in the game data area of the ROM 101, and is used when transmitting the first performance storage information designation command that designates the first pending storage number. The starting opening winning designation value "1" is a specified value that specifiably indicates that the first starting winning has occurred.

FIG. 10-17 (A2) shows a configuration example AKT22 of the second starting opening winning table. The second starting opening winning table of the configuration example AKT22 includes the lower address of the second starting opening winning memory counter, the lower address of the RL0 hard latch random value register number "1", and the second special symbol determination buffer number "1". , the address of the second performance storage information designation command transmission table, and the starting opening winning designation value "2".

The second starting opening winning/winning storage counter is provided in the game work area of the RAM 102, and is capable of storing data corresponding to the second pending storage number. RL0 hard latch random value register number "1" is an RL0 hard latch random value register with register number "1" provided in the function control register area, and can generate channel RL0 provided in the 16-bit random number circuit 104A. Regarding the random number MR1-1 for special symbol determination, numerical data indicating the value can be acquired and stored by a hard latch. The second special symbol determination buffer number "1" is a second special symbol determination buffer included in the second reservation storage buffer with the buffer number "1" in the second special symbol reservation buffer. The second performance storage information designation command transmission table is stored in the game data area of the ROM 101, and is used when transmitting the second performance storage information designation command that designates the second pending storage number. The starting opening winning designation value "2" is a specified value that specifiably indicates that the second starting winning has occurred.

FIG. 10-17 (B1) shows a configuration example AKB21 of the special symbol control data area. The special symbol control data area of the configuration example AKB21 is related to control by special symbol process processing P_TPROC, such as a special symbol game that is a variable display of special symbols, a small win game state and a jackpot game state that can be controlled based on the display results. Various data can be stored. This special symbol control data area contains the special symbol process timer at address F030[H], the hit flag at address F032[H], the special symbol process code at address F033[H], and the first symbol at address F034[H]. The starting opening winning memory counter, the jackpot symbol determination buffer at address F035[H], the small winning symbol determination buffer at address F036[H], the big winning opening winning number counter at address F037[H], and the address F038[H] ], the big winning hole opening number counter, the big winning hole opening pattern timer at address F039[H], the big winning hole opening pattern table pointer at address F03B[H], and the demo display flag at address F03D[H], It includes a second starting gate winning memory counter at address F099[H].

The special symbol process timer can store a time value corresponding to the control time by the special symbol process process P_TPROC. The special symbol process code can specify the process selected in the special symbol process process P_TPROC. The first starting opening prize storage counter is capable of storing a count value corresponding to the first pending storage number. The jackpot symbol determination buffer can store data corresponding to the jackpot symbol designation value. The jackpot design designation value is a designation value corresponding to a confirmed special symbol displayed when the display result is "jackpot" in the variable display of special symbols, and allows the type of jackpot game state to be set. The small hit symbol determination buffer can store data corresponding to the small win symbol designation value. The small win design designation value is a designation value corresponding to a confirmed special symbol displayed when the display result is "small win" in the variable display of special symbols, and allows setting of alcoholic beverages in a small win game state. The big winning hole winning number counter can store a count value corresponding to the number of game balls that have passed through the big winning hole formed by the special variable winning ball device 50. The big winning opening number counter can store a count value corresponding to the number of openings of the big winning opening in the small winning game state or the jackpot gaming state. The big winning opening opening pattern timer can store a time value corresponding to the remaining time for controlling the big winning opening in the open state in the small winning game state or the jackpot gaming state. The big winning hole opening pattern table pointer can specify the storage address of the big winning hole opening pattern table in which the opening time of the big winning hole is set. The demonstration display flag can store a flag value corresponding to an on state or an off state, depending on whether a demonstration display is being executed. The second starting opening prize storage counter can store a count value corresponding to the second pending storage number.

FIG. 10-17 (B2) shows a configuration example AKB22 of the starting opening winning buffer area. The starting opening winning buffer area of the configuration example AKB22 can store various data regarding the first starting winning and the second starting winning that occur when the game ball enters the first starting winning opening and the second starting winning opening. This starting opening winning buffer area includes a starting opening winning buffer storage counter at address F0BA[H] and starting opening winning buffer numbers "0" to "8" at addresses F0BB[H] to F0C3[H]. There is.

The starting opening winning buffer storage counter can store a count value corresponding to the number of valid starting opening winning designation values stored in the starting opening winning buffer area. Therefore, the count value of the starting opening winning buffer storage counter indicates the total number of first starting winnings and second starting winnings. The starting slot winning buffer numbers "0" to "8" are the starting slot winning buffers to which the buffer numbers "0" to "8" are assigned, and the starting slot winning buffers are allocated in the order in which the first starting prize and the second starting prize occur. The winning designation value can be stored. Thereby, the storage information of the starting opening winning buffer indicates the order of occurrence of the first starting winning and the second starting winning.

FIG. 10-17 (C1) shows a configuration example AKT23 of the first effect storage information designation command transmission table. The first performance storage information designation command transmission table of the configuration example AKT23 is configured to include table data indicating the upper byte of the first performance storage information designation command and the first starting opening prize storage counter reference designation value. There is. The command set process P_COM_SET of step AKS219 makes it possible to transmit the first performance storage information designation command when the first performance storage information designation command transmission table is used. The first performance storage information designation command can set the lower byte corresponding to the count value of the first starting gate winning storage counter. By transmitting such a first effect storage information designation command, it is possible to notify the effect control board 12 of the first pending storage number.

FIG. 10-17 (C2) shows a configuration example AKT24 of the second effect storage information designation command transmission table. The second performance storage information designation command transmission table of the configuration example AKT24 is configured to include table data indicating the upper byte of the second performance storage information designation command and the second starting opening prize storage counter reference designation value. There is. The command set process P_COM_SET of step AKS219 enables the second performance storage information designation command to be transmitted when the second performance storage information designation command transmission table is used. The second performance storage information designation command can set the lower byte corresponding to the count value of the second starting gate winning storage counter. By transmitting such a second performance storage information designation command, it is possible to notify the performance control board 12 of the second pending storage number.

The starting port switch passing process P_TZU_ON shown in FIG. 10-16 stores the stored value of the RL2 soft latch random value register loaded in step AKS209 in the random number buffer for selecting a losing effect in step AKS210. Numerical data indicating the value of the random number MR3-2 can be extracted. In addition, the starting port switch passing process P_TZU_ON stores the stored value of the RS1 soft latch random value register loaded in step AKS211 in the random number buffer for fluctuating pattern type selection in step AKS212, thereby generating the random number MR3- for fluctuating pattern type selection. 3, numerical data indicating its value can be extracted. Furthermore, the starting port switch passage process P_TZU_ON stores the stored value of the RS2 soft latch random value register loaded in step AKS213 in the random number buffer for fluctuation patterns in step AKS214, so that the random number MR3-4 for the fluctuation pattern is stored in the random number buffer for fluctuation patterns. Numerical data indicating values can be extracted. Here, the random number MR3-2 for selecting a losing effect was set as the first random number, the random number MR3-3 for selecting the variation pattern type was set as the second random number, and the random number MR3-4 for the variation pattern was set as the third random number. In this case, the starting port switch passage process P_TZU_ON is executed in response to the occurrence of a starting prize, so the first random value, the second random value, and the third random value are used to generate a common extraction that is the occurrence of a starting winning. Extraction becomes possible when the conditions are met. The random number MR3-2 for selecting a losing effect is included in the gaming random numbers that can be updated by the 16-bit random number circuit 104A, and the random number MR3-3 for selecting the variation pattern type and the random number MR3-4 for the variation pattern are 8-bit random numbers. The total number of random numbers included in the gaming random numbers that can be updated by the random number circuit 104B and that are all included in the update range is a prime number. The update speed of the random number MR3-2 is 469 [times/ms], while the update speed of the random numbers MR3-3 and MR3-4 is 938 [times/ms]. That is, the update speed of the random numbers MR3-3 and MR3-4 is twice the update speed of the random number MR3-2, which is an integral multiple. The update range of random number MR3-2 is "0" to "65518", the update range of random number MR3-3 is "0" to "240", and the update range of random number MR3-4 is "0" to "250". ” Therefore, the total number of random numbers included in each update range is different, and the total number of random numbers included in each update range is a prime number. In this way, when the update speed of the second random value and the third random value is an integer multiple of the update speed of the first random value, the total number of random values included in each update range is different, and both are updated. The total number of random numbers included in the range is a prime number. Thereby, it is possible to suppress the occurrence of synchronization between the first random value, the second random value, and the third random value, and to update the random value appropriately.

FIG. 10-18 is a flowchart showing an example of special symbol normal processing P_TNORMAL. The special symbol normal process P_TNORMAL is included in the processes that can be called from the special symbol process process P_TPROC shown in FIG. It is executable. When the CPU 103 executes the special symbol normal process P_TNORMAL, the CPU 103 sets the starting opening winning buffer storage counter address by a transfer command for setting a pointer (step AKS241). The starting opening winning buffer storage counter address is the address of the starting opening winning buffer storage counter provided in the game work area of the RAM 102. In this way, it is determined whether the count value of the starting opening winning buffer storage counter to which the address has been set is "0" (step AKS242). For example, an arithmetic jump instruction that branches processing depending on whether or not the stored data at the address pointed to by the pointer is 00[H] corresponding to "0" causes the count value of the starting opening prize buffer storage counter to be "0". ” and when the value is other than “0”, different processing contents can be executed.

Corresponding to step AKS242, if the count value of the starting opening winning buffer storage counter is not "0" (step AKS242; No), the counting value of the starting opening winning buffer storage counter is updated to subtract 1 (step AKS243). ). In addition, block transfer for shifting of the starting opening winning buffer is performed (step AKS244). In step AKS244, the transfer destination address is set to the lower address BB[H] of the starting opening prize buffer number "0", the transfer source address is set to the lower address BC[H] of the starting opening winning buffer number "1", and the number of transfers is started. Each is set to "8" which is the buffer size of the winning buffer. Thereafter, by executing a block transfer command, the contents stored in the starting opening winning buffer may be transferred and shifted one unit at a time to the previous buffer. Then, the storage area of the starting opening winning buffer number "8" may be initialized by clearing it.

Next to step AKS244, a second special symbol determination control table address is set by a transfer command for setting a table pointer (step AKS245). The second special symbol determination control table address is the address of the second special symbol determination control table stored in the game data area of the ROM 101. At this time, by executing the starting opening winning check process, it is determined whether the starting opening winning designation value is "1" (step AKS246). For example, in the starting slot winning check process, when the starting opening winning designation value is "1", the zero flag is turned on, and when the starting opening winning designation value is "2", the zero flag is turned off. After such a starting slot winning check process is executed, a jump instruction that branches the process depending on whether or not the zero flag is in the OFF state is used to determine whether the starting slot winning designation value is "1" or "2". ”, different processing contents can be executed.

Corresponding to step AKS246, when the starting opening winning designation value is "1" (step AKS246; Yes), the first special symbol determination control table address is set by a transfer command for setting the table pointer (step AKS247). The first special symbol determination control table address is the address of the first special symbol determination control table stored in the game data area of the ROM 101. In step AKS247, the value of the table pointer is overwritten by a transfer command for setting the table pointer. In this way, in the special symbol normal processing P_TNORMAL, after setting the second special symbol determination control table address in step AKS245, the first special symbol determination control table address is set in step AKS247 in response to the starting opening winning designation value being "1" in step AKS246. Reset the symbol judgment control table address using overwrite settings. As a result, when the frequency of use of the second special symbol determination control table is higher than the frequency of use of the first special symbol determination control table, the program capacity required for table setting can be reduced, and the marketability of the pachinko gaming machine 1 is improved. be able to. In addition, when the frequency of use of the second special symbol determination control table is higher than the frequency of use of the first special symbol determination control table, processing using a jump instruction as a branch instruction is simplified, making it easier to check at the design stage. Therefore, the marketability of the pachinko game machine 1 can be improved.

Corresponding to step AKS246, if the starting opening winning designation value is "2" and not "1" (step AKS246; No), or after step AKS247, special symbol determination processing P_TDECISION is executed (step AKS248), After executing the fluctuation pattern setting process P_TPATSET (step AKS249), the special symbol normal process ends.

Corresponding to step AKS242, when the count value of the starting opening prize buffer storage counter is "0" (step AKS242; Yes), it is determined whether the demonstration display flag is on (step AKS250). The demonstration display flag is a flag indicating that a demonstration display is being executed. If the demonstration display flag is on (step AKS250; Yes), the special symbol normal processing ends. On the other hand, if the demo display flag is off (step AKS250; No), a transfer command for setting the demo display flag stores 01[H], which is the specified value during demo display, in the demo display flag. (Step AKS251). As a result, the demo display flag is set to the on state. Further, a standby command transmission table address is set by a transfer command for setting a pointer (step AKS252). The standby command transmission table address is the address of the standby command transmission table stored in the game data area of the ROM 101. Then, after executing the command set process P_COM_SET (step AKS253), the special symbol normal process ends.

FIG. 10-19 is a diagram for explaining a usage example of the data structure regarding special symbol normal processing P_TNORMAL. In the special symbol normal process P_TNORMAL, the special symbol determination process in step AKS248 is executed using the second special symbol determination control table whose address is set in step AKS245 or the first special symbol determination control table whose address is set in step AKS247. Ru. Further, in the command set process P_COM_SET in step AKS253, the standby command transmission table whose address has been set in step AKS252 is used. In this way, the special symbol normal processing P_TNORMAL enables control regarding the special symbol game, which is a variable display of special symbols, using the first special symbol determination control table, the second special symbol determination control table, and the standby command transmission table. Make it.

FIG. 10-19 (A1) shows a configuration example AKT31 of the first special symbol determination control table. The first special symbol determination control table of the configuration example AKT31 includes the address of the first special symbol buffer shift control table, the lower address of the first special symbol determination buffer number "0", and the first winning symbol buffer number "0". '', the lower address of the first special symbol buffer, and the address of the work setting table after the first special symbol hit determination. The first special symbol buffer shift control table is stored in the game data area of the ROM 101, and is used when shifting the storage contents of the first special symbol reservation buffer. The first special symbol determination buffer number "0" is a first special symbol determination buffer included in the first reservation storage buffer with the buffer number "0" in the first special symbol reservation buffer. The first winning symbol buffer number "0" is the first winning symbol buffer included in the first pending storage buffer with the buffer number "0" in the first special symbol pending buffer. The first special symbol buffer is provided in the game work area of the RAM 102 and is capable of storing special symbol pattern designation values corresponding to confirmed special symbols that are stopped and displayed in the first special symbol game by the first special symbol display device 4A. . The first special symbol hit determination work setting table is stored in the game data area of the ROM 101, and is used when initializing the data in response to the end of the special symbol determination process P_TDECISION.

FIG. 10-19 (A2) shows a configuration example AKT32 of the second special symbol determination control table. The second special symbol determination control table of the configuration example AKT32 includes the address of the second special symbol buffer shift control table, the lower address of the second special symbol determination buffer number "0", and the second winning symbol buffer number "0". '', the lower address of the second special symbol buffer, and the address of the work setting table after second special symbol hit determination. The second special symbol buffer shift control table is stored in the game data area of the ROM 101, and is used when shifting the storage contents of the second special symbol reservation buffer. The second special symbol determination buffer number "0" is a second special symbol determination buffer included in the second reservation storage buffer with the buffer number "0" in the second special symbol reservation buffer. The second winning symbol buffer number "0" is a second winning symbol buffer included in the second pending storage buffer with the buffer number "0" in the second special symbol pending buffer. The second special symbol buffer is provided in the game work area of the RAM 102 and is capable of storing special symbol pattern designation values corresponding to confirmed special symbols that are stopped and displayed in the second special symbol game by the second special symbol display device 4B. . The second special symbol hit determination work setting table is stored in the game data area of the ROM 101, and is used when initializing the data in response to the end of the special symbol determination process P_TDECISION.

FIG. 10-19(B) shows a configuration example AKT33 of the standby command transmission table AKT33. The standby command transmission table of the configuration example AKT33 includes the processing number, the upper byte of the second specific number of times designation command, the specific number of times command buffer reference designation value, the upper byte of the background color designation command, and the special symbol status designation code reference designation value. , the upper byte of the customer waiting demo command, and the lower byte of the customer waiting demo command. The command set process P_COM_SET of step AKS253 uses the standby command transmission table of the configuration example AKT33 to enable the transmission of the second specific number of times designation command, background color designation command, and customer waiting demo command, respectively. The second specific number of times designation command can set the lower byte corresponding to the value stored in the specific number of times command buffer. The background color designation command can set the lower byte corresponding to the special symbol state designation code. The customer waiting demo command can set the lower byte using a fixed value of 03[H].

FIG. 10-20 is a flowchart showing an example of the special symbol determination process P_TDECISION. The special symbol determination process P_TDECISION is included in the process that can be called from the special symbol normal process P_TNORMAL shown in FIG. 10-18, and can be executed in step AKS248 when starting variable display of the special symbol. When the CPU 103 executes the special symbol determination process P_TDECISION, the CPU 103 sets the special symbol buffer shift control table address by a transfer command for setting a pointer (step AKS301). The special symbol buffer shift control table address is the address of the first special symbol buffer shift control table or the second special symbol buffer shift control table stored in the game data area of the ROM 101. In step AKS301, a different address in the game data area can be specified in accordance with the first special symbol determination control table or the second special symbol determination control table set by the special symbol normal processing P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating address 13C2[H] of the first special symbol buffer shift control table is set to the pointer. Further, when the second special symbol determination control table is set, a value indicating address 13C8[H] of the second special symbol buffer shift control table is set to the pointer.

Following step AKS301, special symbol buffer shift processing P_TBUFSHIFT is executed (step AKS302). The special symbol buffer shift process P_TBUFSHIFT in step AKS302 uses the first special symbol buffer shift control table or the second special symbol buffer shift control table whose address has been set in step AKS301. It is possible to shift the storage contents of the symbol holding buffer. For example, by executing a block transfer command after setting the transfer destination address, transfer source address, and number of transfers, the first pending storage buffer of the first special symbol buffer and the second pending storage buffer of the second special symbol buffer can be set. The contents stored in the buffer may be transferred and shifted one unit at a time to the previous buffer.

Next to step AKS302, the special symbol determination buffer with buffer number "0" is loaded (step AKS303). The special symbol determination buffer with buffer number "0" is the first special symbol determination buffer included in the first reservation storage buffer with buffer number "0" in the first special symbol retention buffer, or the second special symbol determination buffer. This is a buffer for In step AKS303, special symbols are extracted from the first special symbol retention buffer or the second special symbol retention buffer in accordance with the first special symbol determination control table or the second special symbol determination control table set by the special symbol normal processing P_TNORMAL. The value stored in the determination buffer can be read. For example, the upper address F0 [H] of the game work area, which is the work area, is set in the upper byte of the pointer by a transfer command, and the upper address F0 [H] of the game work area, which is the work area, is set in the upper byte of the pointer, and the upper address F0 [H] of the game work area, which is the work area, is set in the upper byte of the pointer, and at the same time, After setting the lower address of the stored first special symbol determination buffer number "0" or second special symbol determination buffer number "0" to the lower byte of the pointer by a transfer command, It is only necessary that the random number MR1-1 for special symbol determination stored in the special symbol determination buffer with buffer number "0" can be read by reading the memory data of the address.

After step AKS303, special symbol jackpot determination processing P_TFVR_CHK is executed (step AKS304). The special symbol jackpot determination process P_TFVR_CHK in step AKS304 determines the special symbol display result as a "jackpot" by comparing the random number MR1-1 for special symbol determination read in step AKS303 with the jackpot determination value. It is possible to determine whether or not to do so. The determination as to whether or not the special symbol display result is a "jackpot" is also referred to as special symbol jackpot determination, and is a determination as to whether or not to control to a jackpot gaming state as an advantageous state. Then, when it is determined that the special symbol display result is a "jackpot" in the special symbol jackpot determination, 01[H], which is the designated jackpot value, is stored in the hit flag. The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F032[H]. The special symbol jackpot determination process in step AKS304 may be performed by making it possible to store a jackpot designated value in the winning flag by a transfer command for writing to a storage area at a designated address in the gaming work area of the RAM 102. It should be noted that the hit flag may be set to the initial value 00 [H] by a clear command executed in response to the start of the special symbol jackpot determination process P_TFVR_CHK in step AKS304.

Along with the special symbol jackpot determination process P_TFVR_CHK in step AKS304, the special symbol small hit determination process P_TLITTLE_CHK is executed (step AKS305). The special symbol small hit determination process P_TLITTLE_CHK in step AKS305 compares the value of the random number MR1-1 for special symbol determination read by loading the special symbol determination buffer in step AKS303 with the small hit determination value. By doing so, it is possible to determine whether or not the special figure display result is a "small hit". The determination as to whether or not the special symbol display result is a "small win" is also referred to as the special symbol small win determination, and is a determination as to whether or not to control the small win game state as a predetermined state. Then, when it is determined that the special symbol display result is a "small hit" in the special symbol small hit determination, 02[H], which is the small hit designated value, is stored in the hit flag. In the special symbol small hit determination process P_TLITTLE_CHK of step AKS305, the small hit specified value may be stored in the hit flag by a transfer command for writing to the storage area of the specified address in the game work area of the RAM 102.

In the special symbol small hit determination process P_TLITTLE_CHK in step AKS305, since the small hit determination value is included in a different range from the jackpot determination value, the special symbol display result is determined to be a "jackpot" by the special symbol jackpot determination. After that, the special symbol display result is not determined to be a "small hit" by the special symbol small hit determination. However, if, for example, due to the occurrence of an error, the special pattern display result is determined to be a "big hit" by the special symbol jackpot determination, and then the special symbol display result is determined to be a "small hit" by the special symbol small hit determination. , the small win specified value will be stored in the win flag. Therefore, if there is a conflict between the determination that the special symbol display result is a "big hit" by the special symbol jackpot determination and the determination that the special symbol display result is a "small win" by the special symbol small hit determination, the small hit game state In order to avoid being controlled to a jackpot game state with a high advantage, fraudulent acts due to defects in determination processing are prevented, and games can be appropriately controlled.

When the special symbol small hit determination process P_TLITTLE_CHK in step S305 is executed, the winning symbol buffer with buffer number "0" is loaded (step AKS306). The winning symbol buffer with buffer number "0" is the first winning symbol buffer included in the first holding storage buffer with buffer number "0" in the first special symbol buffer, or the buffer number in the second special symbol buffer. This is the second winning symbol buffer included in the second pending storage buffer of "0". In step AKS306, the winning symbols are extracted from the first special symbol buffer or the second special symbol buffer in accordance with the first special symbol determination control table or the second special symbol determination control table whose address is set by the special symbol normal processing P_TNORMAL. It is possible to read the value stored in the buffer. For example, the upper address F0 [H] of the game work area, which is the work area, is set in the upper byte of the buffer pointer by a transfer command, and the first special symbol determination control table or the second special symbol determination control table pointed to by the table pointer After setting the lower address of the special symbol determination buffer stored in the buffer pointer in the lower byte of the buffer pointer by a transfer command, by reading the stored data of the address in the gaming work area pointed to by the buffer pointer, the buffer number "0" is set. It is only necessary that the random numbers MR1-2 for winning symbols stored in the buffer for winning symbols can be read out.

After step AKS306, the special symbol buffer lower address is loaded (step AKS307). The special symbol buffer lower address is the address of the first special symbol buffer or the second special symbol buffer provided in the game work area of the RAM 102. In step AKS307, a different lower address can be specified corresponding to the first special symbol determination control table or the second special symbol determination control table whose address is set by the special symbol normal processing P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating the lower address B8[H] of the first special symbol buffer is set to the lower byte of the buffer pointer. Further, when the second special symbol determination control table is set, a value indicating the lower address B9[H] of the second special symbol buffer is set in the lower byte of the buffer pointer. The upper address F0[H] of the game work area has already been stored in the upper byte of the buffer pointer in step AKS306.

Following step AKS307, special symbol information setting process P_TZU_SET is executed (step AKS308). The special symbol information setting process P_TZU_SET enables determining the confirmed special symbol to be stopped and displayed in the special symbol game, and stores the special symbol pattern designation value corresponding to the determination result in the special symbol buffer. Next to the special symbol information setting process P_TZU_SET, the work setting table address is set after the special symbol hit determination (step AKS309). The special symbol hit determination work setting table address is the address of the first special symbol hit determination work setting table or the second special symbol hit determination work setting table stored in the game data area of the ROM 101. In step AKS309, a different address in the game data area can be specified in response to the first special symbol determination control table or the second special symbol determination control table whose address is set by the special symbol normal processing P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating address 12BB[H] of the first special symbol hit determination post-work setting table is set in the pointer. Further, when the second special symbol determination control table is set, a value indicating the address 12C0[H] of the second special symbol hit determination post-work setting table is set in the pointer.

Next to step AKS309, data set processing P_DATASET is executed (step AKS310), and special symbol determination processing P_TDECISION is completed. The data set process P_DATASET in step AKS310 uses the special symbol hit determination work setting table whose address has been set in step AKS309 to set data in the first pending storage buffer or second pending storage buffer with buffer number "0". Initialization is enabled by clearing the special symbol determination buffer and the winning symbol buffer. For example, when the work setting table is set after the first special symbol hit determination, the first special symbol determination buffer and the first special symbol determination buffer are The first winning symbol buffer is initialized. In addition, when the work setting table after the second special symbol hit determination is set, the second special symbol determination buffer and the second special symbol determination buffer are The second winning symbol buffer is initialized.

FIG. 10-21 is a diagram for explaining a usage example of the data structure regarding the special symbol determination process P_TDECISION. In the special symbol determination process P_TDECISION, the special symbol jackpot determination process P_TFVR_CHK in step AKS304 and the special symbol small hit determination process P_TLITTLE_CHK in step AKS305 use the random number MR1-1 for special symbol determination to determine the display result in the variable display of the special symbol. It is determined whether or not to be a "big hit" or a "small hit" in response to the start of the variable display. Further, in the special symbol information setting process P_TZU_SET of step AKS308, the special symbol buffer loaded with the lower address in step AKS307 is used. In this way, the special symbol determination process P_TDECISION uses the random number MR1-1 for special symbol determination and the special symbol buffer to enable control regarding the special symbol game, which is a variable display of special symbols.

FIG. 10-21(A) shows a special symbol determination example AKC01 by the special symbol jackpot determination process P_TFVR_CHK in step AKS304 and the special symbol small hit determination process P_TLITTLE_CHK in step AKS305. The special symbol jackpot determination process P_TFVR_CHK in step AKS304 can perform a comparison calculation with the jackpot determination value for the random number MR1-1 for special symbol determination in order to determine whether the value is within the jackpot determination range. Make it. The jackpot determination value includes a jackpot lower limit determination value and a jackpot upper limit determination value. Then, when the value of random number MR1-1 is subtracted from the jackpot lower limit judgment value, if the carry flag is off, the value of random number MR1-1 is less than the jackpot lower limit judgment value, and if the carry flag is on If so, the value of the random number MR1-1 exceeds the jackpot lower limit judgment value. If the value of the random number MR1-1 is less than or equal to the jackpot lower limit judgment value, it corresponds to the fact that it is not within the jackpot judgment range, and the special pattern jackpot judgment process P_TFVR_CHK is ended to return to the special pattern judgment process P_TDECISION. On the other hand, when the value of the random number MR1-1 exceeds the jackpot lower limit judgment value, the value of the random number MR1-1 is subtracted from the jackpot upper limit judgment value. At this time, if the carry flag is off, the value of random number MR1-1 is less than or equal to the jackpot upper limit judgment value, and if the carry flag is on, the value of random number MR1-1 is a value that exceeds the jackpot upper limit judgment value. It is. Therefore, if the value of the random number MR1-1 is less than or equal to the jackpot upper limit judgment value, 01 [H], which is the jackpot designated value, is stored in the winning flag, corresponding to the fact that it is within the jackpot judgment range. If the value of the random number MR1-1 exceeds the jackpot upper limit determination value, it corresponds to the fact that it is not within the jackpot determination range, and the special symbol jackpot determination process P_TFVR_CHK is ended to return to the special symbol determination process P_TDECISION.

As an example, the jackpot lower limit determination value may be set in advance to be "60000" and the jackpot upper limit determination value to be "60285". As a result, as in the special symbol determination example AKC01, the jackpot determination range where the random number MR1-1 value is from "60001" to "60285" corresponds to the starting opening winning designation value "1" and "2". If it is within the range, the judgment result regarding the special figure display result is a "jackpot".

The special symbol small hit determination process P_TLITTLE_CHK in step AKS305 performs a comparison operation with the small hit determination value for the random number MR1-1 for special symbol determination in order to determine whether the value is within the small hit determination range. make it executable. The small hit determination value includes a small hit lower limit determination value and a small hit upper limit determination value. Then, when the value of random number MR1-1 is subtracted from the small hit lower limit judgment value, if the carry flag is off, the value of random number MR1-1 is less than the small hit lower limit judgment value, and the carry flag is on. If so, the value of the random number MR1-1 is a value exceeding the small hit lower limit judgment value. If the value of the random number MR1-1 is less than the small hit lower limit judgment value, it corresponds to the fact that it is not within the small hit judgment range, and by ending the special symbol small hit judgment process P_TLITTLE_CHK, the special symbol judgment process P_TDECISION is executed. Return. On the other hand, when the value of the random number MR1-1 exceeds the small hit lower limit determination value, the value of the random number MR1-1 is subtracted from the small hit upper limit determination value. At this time, if the carry flag is off, the value of random number MR1-1 is less than the small hit upper limit judgment value, and if the carry flag is on, the value of random number MR1-1 is less than the small hit upper limit judgment value. It exceeds the value. Therefore, if the value of the random number MR1-1 is less than or equal to the small hit upper limit judgment value, 02[H], which is the specified small hit value, is stored in the hit flag, corresponding to the fact that it is within the small hit judgment range. . If the value of the random number MR1-1 exceeds the small hit upper limit judgment value, it corresponds to the fact that it is not within the small hit judgment range, and by ending the special symbol small hit judgment process P_TLITTLE_CHK, the special symbol judgment process P_TDECISION is executed. Return. The small hit upper limit determination value may be set to different values depending on whether the starting opening winning designation value is "1" or "2".

As an example, the small hit lower limit judgment value may be set in advance to be ``21000'', which is the same value when the starting opening winning designation value is ``1'' and when it is ``2''. In addition, the small hit upper limit judgment value is set in advance so that it becomes ``21285'' when the starting opening winning judgment value is ``1'', and ``29282'' when the starting opening winning designation value is ``2''. It would be fine if it had been done. As a result, as in the special symbol determination example AKC01, when the starting opening winning designation value is "1" and the value of the random number MR1-1 is within the small hit determination range from "21001" to "21285". If the value of the random number MR1-1 is within the small hit determination range from "21001" to "29282" in response to the starting opening winning designation value of "2", the determination result of the special figure display result becomes a “small hit”.

FIG. 10-21(B) shows a configuration example AKB31 of the special symbol buffer area. The special symbol buffer area of the configuration example AKB31 can store a special symbol pattern designation value corresponding to a confirmed special symbol that is stopped and displayed as a display result of the special symbol. This special symbol buffer area includes a first special symbol buffer at address F0B8[H] and a second special symbol buffer at address F0B9[H]. The first special symbol buffer can store a special symbol pattern designation value when the first special symbol game is executed by the first special symbol display device 4A. The second special symbol buffer can store a special symbol pattern designation value when a second special symbol game is executed by the second special symbol display device 4B. The special symbol pattern designation value is the designation value of the display pattern corresponding to the confirmed special symbol that is the display result in the variable display of the special symbol by the first special symbol display device 4A or the second special symbol display device 4B, and is the designated value of the display pattern corresponding to the confirmed special symbol It includes a pattern designation value and a small winning special symbol pattern designation value. The jackpot special symbol pattern designation value is the display corresponding to the confirmed special symbol displayed by the first special symbol display device 4A or the second special symbol display device 4B when the display result is "jackpot" in the variable display of the special symbol. This is the specified value of the pattern. The small hit special symbol pattern designation value corresponds to the confirmed special symbol displayed by the first special symbol display device 4A or the second special symbol display device 4B when the display result is “small win” in the variable display of special symbols. This is the specified value of the displayed display pattern.

FIG. 10-22 is a flowchart showing an example of the special symbol information setting process P_TZU_SET. The special symbol information setting process P_TZU_SET is included in the processes that can be called from the special symbol determination process P_TDECISION shown in FIG. can be executed in step AKS308. When the CPU 103 executes the special symbol information setting process P_TZU_SET, the CPU 103 loads the hit flag (step AKS321). The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F032[H]. In step AKS321, the winning flag may be loaded by a transfer command for reading storage data at a designated address in the game work area of the RAM 102. Then, it is confirmed that the winning flag is not the designated jackpot value using an arithmetic jump instruction that can compare the winning flag and the determination value corresponding to the designated jackpot value (step AKS322).

Corresponding to step AKS322, if the hit flag is the designated jackpot value (step AKS322; No), a winning symbol buffer with buffer number "0" is set (step AKS323). The stored value of the winning symbol buffer with buffer number "0" has been loaded by step AKS306 of the special symbol determination process P_TDECISION shown in FIG. 10-20. This load content may be set as a processing target by transferring it to a processing register included in the internal registers of the CPU 103. Regarding the winning symbol buffer with the buffer number "0" set in this way, the stored value is stored in the special symbol buffer (step AKS324). The special symbol buffer is the first special symbol buffer or the second special symbol buffer into which the lower address is loaded by step AKS307 of the special symbol determination process P_TDECISION shown in FIGS. 10-20. As a result, for the random number MR1-2 for winning symbols stored in the winning symbol buffer with buffer number "0", numerical data indicating the random number is stored in the first special symbol buffer or the second special symbol buffer. . Therefore, the numerical data indicating the value of the random number MR1-2 can be used as the jackpot special symbol pattern designation value corresponding to the special symbol whose confirmed special symbol is the jackpot symbol when the special symbol display result is "jackpot". be.

Following step AKS324, the starting opening winning buffer with buffer number "0" is loaded into the starting opening winning designation value (step AKS325). The starting opening winning buffer with buffer number "0" is provided in the starting opening winning buffer area of the configuration example AKB22 shown in FIG. 10-17 (B2), and is assigned the address F0BB[H]. In step AKS325, the starting opening winning buffer with buffer number "0" may be loaded by a transfer command for reading stored data from the storage area of the designated address in the game work area of the RAM 102.

After step AKS325, jackpot information data selection process P_TFVR_ZU is executed (step AKS326). The jackpot information data selection process P_TFVR_ZU stores the starting opening winning designation value loaded in step AKS325, the value stored in the winning symbol buffer loaded in step AKS306 of the special symbol determination process P_TDECISION shown in FIG. 10-20, etc. It is possible to determine the jackpot symbol designation value by using the jackpot symbol designation value, and to set the jackpot information setting data corresponding to the determination result. The jackpot information setting data is data indicating a jackpot effect specification value, a fanfare display specification value, and a jackpot end display specification value. The jackpot symbol designation value determined by such jackpot information data selection process P_TFVR_ZU is stored in the jackpot symbol determination buffer (step AKS327). The jackpot symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned address F035[H]. In step AKS327, the jackpot designation value may be stored by a transfer command for writing to the storage area of the designated address in the game work area of the RAM 102.

After step AKS327, data for setting jackpot information is transferred (step AKS328). In this case, in the jackpot information setting table stored in the game data area of the ROM 101, the storage address of the jackpot information setting data corresponding to the determination result of the jackpot symbol designation value is set to the pointer specifying the transfer source. . Further, the address of the performance symbol information buffer provided in the game work area of the RAM 102 is set to the buffer pointer that specifies the transfer destination. Further, the data size of the jackpot information setting data is set to the number of transfers. Thereafter, by a block transfer command, the jackpot information setting data read from the jackpot information setting table may be transferred and stored in the performance symbol information buffer, fanfare display buffer, and jackpot end display buffer. At this time, a variable command designation buffer is set (step AKS329). The variable command designation buffer is provided at the next address of the jackpot end display buffer in the game work area of the RAM 102, and a stored value can be set using the transfer destination address updated by the block transfer instruction in step AKS327. For example, 01 [H], which is the variable command designation value corresponding to the fact that the special figure display result has been determined as a "jackpot", may be set as the stored value in the fluctuation command designation buffer. In addition, if the stored value is initialized to 00 [H] by clearing the variable command specification buffer in accordance with the performance state after the end of the jackpot game state or the stored value of the performance symbol information buffer, etc. There may be.

When the variable command designation buffer is set in step AKS329, the maximum value buffer for the number of openings of the big winning opening is set (step AKS330). The maximum number of times the big winning hole is opened is provided in the game work area of the RAM 102 at the address next to the variable command designation buffer, and can store the maximum number of times the big winning hole is opened to control the big winning hole in the open state in the jackpot game state. be. In step AKS330, the jackpot symbol designation value determined by the jackpot information data selection process P_TFVR_ZU in step AKS326 and the maximum number of jackpot openings table stored in the game data area of the ROM 101 are used to determine the number of jackpot openings. The maximum value can be determined. If the storage value corresponding to the maximum number of opening times of the big winning opening decided at this time is stored in the maximum value buffer for the number of opening times of the big winning opening by a transfer command for writing to the storage area of the specified address in the gaming work area of the RAM 102. good.

Corresponding to step AKS322, if the hit flag is not the designated jackpot value (step AKS322; Yes), the hit flag is flagged by an arithmetic jump instruction that can compare the hit flag and the judgment value corresponding to the designated small hit value. It is confirmed that is not the specified small hit value (step AKS331). When the hit flag is the small hit designated value (step AKS331; No), the small hit special symbol pattern designated value is stored in the special symbol buffer (step AKS332). The small winning special symbol pattern designation value may be created by adding a preset small winning symbol addition value to the stored value read from the winning symbol buffer with buffer number "0". Further, the small hit special symbol pattern designation value may be prepared in advance with a value different from the jackpot special symbol pattern designation value. The special symbol buffer is the first special symbol buffer or the second special symbol buffer into which the lower address is loaded by step AKS307 of the special symbol determination process P_TDECISION shown in FIGS. 10-20. In step AKS332, the small winning special symbol pattern designation value created using the small winning symbol addition value etc. is transferred to the first special symbol buffer or All you have to do is store it in the second special symbol buffer.

After storing the small hit special symbol pattern designation value in step AKS332, the small win design designation value is determined (step AKS333). The small winning symbol designation value is the first value set corresponding to the value stored in the winning symbol buffer loaded by step AKS306 of the special symbol determination process P_TDECISION shown in FIG. 10-20 and the starting opening winning designation value. It can be determined using the small win state setting table or the second small win state setting table. The small winning symbol designation value determined at this time is stored in the small winning symbol determination buffer (step AKS334). The small hit symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F036[H]. In step AKS334, the small winning symbol designation value may be stored by a transfer command for writing to the storage area of the designated address in the game work area of the RAM 102.

Next to step AKS334, a small winning effect designation value is determined (step AKS335). The small win performance designation value can be determined using the small win information setting table stored in the game data area of the ROM 101 and the small win symbol designation value determined in step AKS333. The small winning performance designation value determined at this time is stored in the performance symbol information buffer (step AKS336). In step AKS336, the small winning performance designation value determined in step AKS335 may be stored in the performance symbol information buffer by a transfer command for writing to the storage area of the specified address in the gaming work area of the RAM 102.

When the small win effect designation value is stored in step AKS336, the small win information setting data is transferred (step AKS337). The small win information setting data is data indicating a small win fanfare display designated value and a small win ending display designated value. In step AKS337, in the small winning information setting table stored in the game data area of the ROM 101, the storage address of the small winning information setting data corresponding to the determination result of the small winning effect designation value is set to the pointer specifying the transfer source. Set. Further, the address of the small win fanfare display buffer provided in the game work area of the RAM 102 is set as the transfer destination. Further, the data size of the small winning information setting data is set to the number of transfers. Thereafter, by a block transfer command, the small win information setting data read from the small win information setting table may be transferred and stored in the small win fanfare display buffer and the small win ending display buffer.

Corresponding to step AKS331, if the hit flag is not the small hit designated value (step AKS331; Yes), the loss special symbol pattern designated value is stored in the special symbol buffer (step AKS338). The loss special symbol pattern designation value may be a value different from the jackpot special symbol pattern designation value or the small hit special symbol pattern designation value, as long as it is prepared in advance. For example, it may be possible to set F1[H] as the loss special symbol pattern designation value. The special symbol buffer is the first special symbol buffer or the second special symbol buffer into which the lower address is loaded by step AKS307 of the special symbol determination process P_TDECISION shown in FIGS. 10-20. In step AKS338, the loss special symbol pattern designation value prepared in advance is stored in the first special symbol buffer or the second special symbol buffer by a transfer command for writing to the storage area of the designated address in the game work area of the RAM 102. good.

Following step AKS338, the production symbol information buffer is cleared (step AKS339). The performance symbol information buffer can store a performance designation value corresponding to the case where the special symbol display result is a “big hit” or a “small hit”. On the other hand, in response to the case where the special figure display result is a "loss", the production symbol information buffer is cleared and its stored value is initialized to 00 [H]. Additionally, the variable command designation buffer is cleared (step AKS340).

After steps AKS330, AKS337, and AKS340, the pre-fluctuation start command transmission table address is set by a transfer command for setting a pointer (step AKS341). The pre-variation start command transmission table address is the address of the pre-variation start command transmission table stored in the game data area of the ROM 101. Then, after executing the command set process P_COM_SET (step AKS342), the special symbol information setting process P_TZU_SET ends.

FIG. 10-23 is a flowchart showing an example of the jackpot information data selection process P_TFVR_ZU. The jackpot information data selection process P_TFVR_ZU is called in the special symbol information setting process P_TZU_SET shown in FIG. 10-22, and can be executed in step AKS326 when the hit flag is the jackpot specified value in step AKS322. When the CPU 103 executes the jackpot information data selection process P_TFVR_ZU, the CPU 103 sets the second jackpot state setting table address by a transfer command for setting a pointer (step AKS401). The second jackpot state setting table address is the address of the second jackpot state setting table stored in the game data area of the ROM 101.

Following step AKS401, it is confirmed that the starting opening winning designation value is not "1" (step AKS402). The starting opening winning designation value is stored in the internal register of the CPU 103 by step AKS325 of the special symbol information setting process P_TZU_SET shown in FIG. 10-22. When this starting opening winning designation value is "1" (step AKS402; No), the first jackpot state setting table address is set by a transfer command for setting a pointer (step AKS403). The first jackpot state setting table address is the address of the first jackpot state setting table stored in the game data area of the ROM 101. In step AKS403, the value of the pointer is overwritten by a transfer command for setting the pointer. In this way, in the special symbol information setting process P_TZU_SET, after setting the table address for setting the second jackpot state in step AKS401, the first jackpot state setting table address is set in step AKS403 in response to the starting opening winning designation value being "1" in step AKS402. Reset the table address for jackpot status setting by overwriting settings. As a result, when the frequency of use of the table for setting the second jackpot state is higher than the frequency of use of the table for setting the first jackpot state, the program capacity required for setting the table can be reduced, and the marketability of the pachinko gaming machine 1 is improved. be able to. In addition, when the frequency of use of the second jackpot status setting table is higher than the usage frequency of the first jackpot status setting table, processing using a jump instruction as a branch instruction is simplified, making it easier to confirm at the design stage. Therefore, the marketability of the pachinko game machine 1 can be improved.

Corresponding to step AKS402, if the starting opening winning designation value is "2" and not "1" (step AKS401; Yes), or after step AKS403, a buffer for winning symbols is set (step AKS404). The winning symbol buffer is a winning symbol buffer whose stored value is the buffer number "0" loaded by step AKS306 of the special symbol determination process P_TDECISION shown in FIGS. 10-20. This load content may be set as a processing target by transferring it to a processing register included in the internal registers of the CPU 103. The stored value of the winning symbol buffer thus set is used together with the second jackpot state setting table set in step AKS401 or the first jackpot state setting table set in step AKS403 to determine the second distribution. Value comparison processing P_HANTEI2 is executed (step AKS405).

The second distribution determination value comparison process P_HANTEI2 initializes the start number data as the distribution result data, with the storage data of the table top address as the start number data and the storage data of the next address as the processing number data. After that, the process of comparing the numerical data set as the comparison value and the distribution judgment value indicated by the stored data at the next address and subsequent addresses of the processing number data is performed in the order of increasing table addresses from the first side to the last side. Enable execution until the distribution judgment value exceeds the value. At this time, if the distribution judgment value is less than or equal to the comparison value, the distribution result data is updated to add 1 and the process proceeds to the next comparison, and if the distribution judgment value exceeds the comparison value, the second distribution judgment value comparison process P_HANTEI2 is executed. finish. Even if the number of comparisons reaches the number corresponding to the processing number data, if the distribution judgment value does not exceed the comparison value, the process can be repeated from the setting of the start number data and processing number data using the stored data from the next address onward. . In the second distribution judgment value comparison process P_HANTEI2 of step AKS405, the random number MR1-2 for winning symbols, which is the value stored in the buffer for winning symbols, is set as a comparison value, and the table for setting the first jackpot state or the second jackpot state is set. The jackpot symbol designation value indicated by the distribution result data can be determined as the type of jackpot game state corresponding to the display result by the first special symbol display device 4A or the second special symbol display device 4B by the storage data of the table. The second distribution determination value comparison process P_HANTEI2 may be executed as long as it can be executed also when determining the small hit symbol designation value by step AKS333 of the special symbol information setting process P_TZU_SET. In this case, the random number MR1-2 for the winning symbol, which is the value stored in the winning symbol buffer, is set as a comparison value, and according to the data stored in the first small winning state setting table or the second small winning state setting table, The designated small win value indicated by the distribution result data can be determined as the type of small win game state corresponding to the display result by the first special symbol display device 4A or the second special symbol display device 4B.

When the second distribution judgment value comparison process P_HANTEI2 in step AKS405 is completed, data for setting jackpot information is determined (step AKS406). The jackpot information setting data includes the jackpot information data specification table selected corresponding to the stored value of the performance state selection buffer and the jackpot symbol specification value determined by the second distribution judgment value comparison process P_HANTEI2 of step AKS405. It is sufficient if the data set can be selected from among a plurality of types of data sets prepared in advance. The performance state selection buffer may be capable of setting a stored value corresponding to the performance state after the end of the jackpot game state.

FIG. 10-24 is a diagram for explaining an example of the use of the data structure corresponding to the control of the jackpot game state regarding the special symbol information setting process P_TZU_SET and the jackpot information data selection process P_TFVR_ZU. When the hit flag is the jackpot specified value in step AKS322 of the special symbol information setting process P_TZU_SET, the jackpot information data selection process P_TFVR_ZU can be executed in step AKS326. In this jackpot information data selection process P_TFVR_ZU, the second jackpot state setting table whose address is set in step AKS401 or the first jackpot state setting table whose address is set in step AKS403 is used to perform the second distribution in step AKS405. By executing the judgment value comparison process P_HANTEI2, it becomes possible to determine the jackpot symbol designation value. After that, in step AKS328 of the special symbol information setting process P_TZU_SET, the jackpot information setting data read from the jackpot information setting table corresponding to the specified jackpot symbol value is sent to the performance symbol information buffer, fanfare display buffer, and jackpot end display buffer. It can be transferred and stored. The production symbol information buffer, the fanfare display buffer, and the jackpot end display buffer are provided in the production symbol information area and can store setting data when controlled to a jackpot game state. Further, in step AKS330 of the special symbol information setting process P_TZU_SET, the maximum value of the number of openings of the jackpot hole corresponding to the specified jackpot symbol value can be determined using the maximum number of openings of the jackpot hole table.

In this way, the jackpot information data selection process P_TFVR_ZU enables the jackpot symbol designation value to be determined using the first jackpot state setting table or the second jackpot state setting table. The special symbol information setting process P_TZU_SET can set the storage values of the production symbol information buffer, fanfare display buffer, and jackpot display buffer provided in the production symbol information area, as well as the number of openings of the big winning hole corresponding to the specified jackpot symbol value. Make the maximum value determinable.

FIG. 10-24 (A1) shows a configuration example AKT41 of the first jackpot state setting table. In the first jackpot state setting table of configuration example AKT41, the jackpot symbol designation value "1" and the corresponding value 00[H] are stored in the first address 1AFD[H], and the number of processing is shown in the next address 1AFE[H]. A value 0A[H] is stored. Then, the stored data after address 1AFF[H] indicates the distribution determination values corresponding to the jackpot design designation values "1" to "10". The second distribution judgment value comparison process P_HANTEI2 of step AKS405 corresponds to the random number MR1-2 for the winning symbol indicated by the stored value of the winning symbol buffer when the first jackpot state setting table of the configuration example AKT41 is used. Therefore, the jackpot symbol designation value can be determined to be any one of "1" to "10". For example, when the random number MR1-2 for the winning symbol is 00[H] corresponding to the minimum random number value "0", the designated jackpot symbol value "1" is determined.

FIG. 10-24 (A2) shows a configuration example AKT42 of the second jackpot state setting table. In the second jackpot state setting table of the configuration example AKT42, the jackpot symbol designation value "11" and the corresponding value 0A[H] are stored in the first address 1B09[H], and the number of processing is shown in the next address 1B0A[H]. The value 04[H] is stored. Then, the stored data after address 1B0B[H] indicates the distribution determination values corresponding to the jackpot design designation values "11" to "14". The second distribution judgment value comparison process P_HANTEI2 of step AKS405 corresponds to the random number MR1-2 for the winning symbol indicated by the stored value of the winning symbol buffer when the second jackpot state setting table of the configuration example AKT42 is used. Therefore, the jackpot symbol designation value can be determined to be any one of "11" to "14". For example, when the random number MR1-2 for the winning symbol is 00[H] corresponding to the minimum random number value "0", the designated jackpot symbol value "11" is determined.

FIG. 10-24(B) shows a configuration example AKB41 of the production symbol information area. The performance symbol information area of the configuration example AKB41 can store various data regarding game control and performance control including variable display of performance symbols corresponding to the case where the game is controlled to a jackpot game state or a small win game state. This production symbol information area includes a production symbol information buffer at address F056[H], a fanfare display buffer at address F057[H], a jackpot end display buffer at address F058[H], and a fluctuation command at address F059[H]. It includes a specified buffer, a maximum value buffer for the number of openings of big winning openings at address F05A[H], a small win fanfare display buffer at address F05F[H], and a small win ending display buffer at address F060[H]. .

FIG. 10-24(C) shows an example AKD01 of determining the maximum value of the number of openings of the big winning opening. In step AKS330 of the special symbol information setting process P_TZU_SET, the maximum number of times the jackpot opening is determined corresponds to the specified jackpot symbol value determined by the second distribution judgment value comparison process P_HANTEI2 in step AKS405 of the jackpot information data selection process P_TFVR_ZU. It is possible. In the example AKD01 for determining the maximum number of openings for the grand prize opening, the maximum number of openings for the grand prize opening corresponds to 02 [H] corresponding to "2", 04 [H] corresponding to "4", and "7". 07[H], which corresponds to "10", and 0A[H], which corresponds to "10". In addition, the first jackpot state setting table of the configuration example AKT41 is used when the starting opening winning designation value is "1", and makes it possible to determine any of the jackpot symbol designation values "1" to "10". . On the other hand, the second jackpot state setting table of configuration example AKT42 is used when the starting opening winning designation value is "2", and can determine any of the jackpot symbol designation values "11" to "14". Make it. On the other hand, in the maximum value determination example AKD01 for the number of times the big winning hole is opened, the maximum value for the number of times the big winning hole is opened is , 04[H] corresponding to "4", or 0A[H] corresponding to "10". On the other hand, in the maximum value determination example AKD01 for the number of times the big winning hole is opened, the maximum value for the number of times the big winning hole is opened is , 02[H] corresponding to "2", 04[H] corresponding to "4", 07[H] corresponding to "7", and 0A[H] corresponding to "10". It can be determined either way.

In this way, in the example AKD01 for determining the maximum number of openings of the big winning opening, when the maximum number of openings of the opening of the big winning opening is 00[H] corresponding to the specified jackpot symbol value "1", the maximum number of openings of the opening opening of the big winning opening is 04[H], which corresponds to "4". H]. This corresponds to "4", which is the smaller of "4" or "10", which is the maximum value of the number of openings of the big winning slot that can be determined when the starting opening winning designation value is "1". The jackpot design designation value "1" can be determined when the random number MR1-2 for the winning symbol indicated by the stored value in the winning symbol buffer is the minimum random number value "0". In addition, in the example AKD01 for determining the maximum number of times the big winning hole is opened, when the value is 0A[H] corresponding to the specified jackpot symbol value "11", the maximum number of times the big winning hole is opened is 02[H] corresponding to "2". becomes. This is "2", which is the smallest among "2", "4", "7", and "10", which are the maximum number of times the opening of the big winning opening can be determined when the starting opening winning designation value is "2". It corresponds to The jackpot design designation value "11" can be determined when the random number MR1-2 for the winning symbol indicated by the stored value in the winning symbol buffer is "0", which is the minimum random number value. Therefore, among the special symbol games in which the special symbol is variablely displayed on the first special symbol display device 4A or the second special symbol display device 4B, the winning result corresponds to the special symbol game in which the special symbol display result is a “jackpot” When the random number MR1-2 for symbols is the minimum random number value "0", the display result is not determined to be more advantageous than when it is other than the minimum random number value. As a result, when the random numbers MR1-2 for winning symbols are used as the first random numbers, it becomes possible to update the random numbers appropriately so as to prevent fraudulent acts due to defects in the first random numbers.

FIG. 10-25 is a diagram for explaining a usage example of a data structure corresponding to the control of the small winning game state regarding the special symbol information setting process P_TZU_SET and the like. When the hit flag is the small hit designation value in step AKS331 of the special symbol information setting process P_TZU_SET, the small hit design designation value can be determined in step AKS333. In this case, if the starting opening winning designation value is "1", the small winning symbol designation value is determined using the first small winning state setting table. On the other hand, if the starting opening winning designation value is "2", the small winning symbol designation value is determined using the second small winning state setting table. After that, in step AKS339 of the special symbol information setting process P_TZU_SET, the small hit performance designation value determined in step AKS338 is stored in the performance symbol information buffer. Then, in step AKS340 of the special symbol information setting process P_TZU_SET, the small win information setting data read from the small win information setting table corresponding to the specified small win symbol value is transferred to the small win fanfare display buffer and the small win ending display buffer. It can be transferred and stored. The production symbol information buffer, the small win fanfare display buffer, and the small win ending display buffer are provided in the production symbol information area shown in FIG. 10-24(B), and are data for setting when controlled to a small win game state. can be stored. In addition, in step S112 of the special symbol process process P_TPROC shown in FIG. 6, when the special symbol process code corresponds to 03[H] and the small hit opening preprocessing P_TLFAN is executed, the work setting during small hit opening is performed. Using a table or the like, it is possible to determine the opening time and number of openings of the big prize opening.

In this way, the special symbol information setting process P_TZU_SET makes it possible to determine the small winning symbol designation value using the first small winning state setting table or the second small winning state setting table. In addition, the special symbol information setting process P_TZU_SET can set the storage value of the production symbol information buffer, small win fanfare display buffer, and small win ending display buffer provided in the production symbol information area. Furthermore, the small winning opening preprocessing P_TLFAN executed in response to being controlled to the small winning gaming state can determine the opening time and number of openings of the big winning opening.

FIG. 10-25 (A1) shows a configuration example AKT43 of the first small hit state setting table. In the first small hit state setting table of the configuration example AKT43, the small winning symbol designation value "1" and the corresponding value 00[H] are stored in the first address 1B0B[H], and the processing number is stored in the next address 1B0C[H]. A value 01 [H] indicating the value is stored. The stored data at address 1B0D[H] indicates the distribution determination value corresponding to the small winning symbol designation value "1". Step AKS333 of the special symbol information setting process P_TZU_SET corresponds to the random number MR1-2 for the winning symbol indicated by the stored value of the winning symbol buffer when using the first small winning state setting table of the configuration example AKT43. , it is possible to determine only the small winning symbol designation value "1". Therefore, when the random number MR1-2 for the winning symbol is 00[H] corresponding to the minimum random number value "0", the small winning symbol designation value "1" is determined.

FIG. 10-25 (A2) shows a configuration example AKT44 of the second small hit state setting table. In the second small hit state setting table of the configuration example AKT44, the small winning symbol designation value "2" and the corresponding value 01[H] are stored in the first address 1B0E[H], and the processing number is stored in the next address 1B0F[H]. A value 06[H] indicating the value is stored. The stored data after the address 1B10[H] indicates the distribution determination values corresponding to the small winning symbol designation values "2" to "7". Step AKS333 of the special symbol information setting process P_TZU_SET corresponds to the random number MR1-2 for the winning symbol indicated by the stored value of the winning symbol buffer when using the second small winning state setting table of the configuration example AKT44. , the small winning symbol designation value can be determined to be any one of "2" to "7". For example, when the random number MR1-2 for winning symbols is 00[H] corresponding to the minimum random number value "0", the small winning symbol designation value "2" is determined.

FIG. 10-25(B) shows an example AKD02 of determining the opening mode of the grand prize opening. In the small win opening preprocessing P_TLFAN, it is possible to determine the large winning opening opening mode corresponding to the starting opening winning designation value. The opening mode of the grand prize opening may be any one of a plurality of modes in which the opening time and number of openings of the grand prize opening are different. In the grand prize opening mode determination example AKD02, a grand prize opening mode is determined in which the opening time is 36 [ms] and the number of openings is 15 [times] in response to the starting hole winning designation value "1". In addition, in the grand prize opening mode determination example AKD02, the grand prize opening mode is determined in which the opening time is 1600 [ms] and the number of openings is 1 [times] in response to the starting opening winning designation value "2". Ru.

In this way, the opening mode of the big winning opening in the small winning gaming state is determined by the opening time and number of times the opening of the big winning opening corresponds to the starting opening winning designation value, regardless of the value of the small winning symbol designation value. can be determined to be different. The small winning symbol designation value can be determined in accordance with the random number MR1-2 for winning symbols indicated by the stored value of the winning symbol buffer. If the starting opening winning designation value is the same value, the big winning will be common when the random number MR1-2 for the winning symbol is the minimum random number value "0" and when it is other than the minimum random number value. It is decided to open the mouth. Therefore, among the special symbol games in which special symbols are variablely displayed on the first special symbol display device 4A or the second special symbol display device 4B, corresponding to the special symbol game in which the special symbol display result is a “small hit”, When the random number MR1-2 for the winning symbol is the minimum random number value "0", the display result is not determined to be more advantageous than when it is other than the minimum random number value. As a result, when the random numbers MR1-2 for winning symbols are used as the first random numbers, it becomes possible to update the random numbers appropriately so as to prevent fraudulent acts due to defects in the first random numbers.

FIG. 10-26 is a flowchart showing an example of the fluctuation pattern setting process P_TPATSET. The variable pattern setting process P_TPATSET is included in the process that can be called from the special symbol normal process P_TNORMAL shown in FIGS. 10-18, and can be executed in step AKS249 when starting variable display of the special symbol. When the CPU 103 executes the fluctuation pattern setting process P_TPATSET, the CPU 103 loads the hit flag (step AKS361). The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F032[H]. In step AKS361, the winning flag may be loaded by a transfer command for reading storage data at a designated address in the game work area of the RAM 102. Then, it is confirmed that the winning flag is not the designated jackpot value using an arithmetic jump instruction that can compare the winning flag and the judgment value corresponding to the designated jackpot value (step AKS362).

Corresponding to step AKS362, when the hit flag is the jackpot designated value (step AKS362; No), the jackpot symbol determination buffer is loaded (step AKS363). The jackpot symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned address F035[H]. In step AKS363, the jackpot symbol determination buffer may be loaded by a transfer command for reading storage data at a designated address in the gaming work area of the RAM 102. At this time, a state-based jackpot selection table address is set by a transfer command for setting a pointer (step AKS364). The state-based jackpot selection table address is the address of the state-based jackpot selection table stored in the ROM 101. Thereafter, the winning time variation pattern type table selection process P_TPATA is executed (step AKS365). The winning time fluctuation pattern type table selection process P_TPATA in step AKS365 enables selection of the fluctuation pattern type distribution table in response to the special figure display result being "jackpot".

Corresponding to step AKS362, if the hit flag is not the designated jackpot value (step AKS362; Yes), the hit flag is flagged by an arithmetic jump instruction that can compare the hit flag with the judgment value corresponding to the designated small hit value. It is confirmed that is not the specified small hit value (step AKS366). If the hit flag is the small hit designated value (step AKS366; No), a variable command designation buffer is set (step AKS367). The variable command designation buffer is provided in the performance symbol information area of the configuration example AKB41 shown in FIG. 10-24(B), and is assigned the address F059[H]. In step AKS367, 01[H] may be stored in the variable command designation buffer by a transfer command for writing to the storage area of the designated address in the game work area of the RAM 102. Also, the small hit symbol determination buffer is loaded (step AKS368). The small hit symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F036[H]. In step AKS368, the small hit symbol determination buffer may be loaded by a transfer command for reading the storage data at the specified address in the game work area of the RAM 102. At this time, a state-specific small hit selection table address is set by a transfer command for setting a pointer (step AKS369). The state-based small hit selection table address is the address of the state-based small win selection table stored in the ROM 101. Thereafter, the winning time variation pattern type table selection process P_TPATA is executed (step AKS370). The win time fluctuation pattern type table selection process P_TPATA in step AKS370 enables selection of the fluctuation pattern type distribution table in response to the special figure display result being "small win".

Corresponding to step AKS366, if the hit flag is not the small hit specified value (step AKS366; Yes), loss time variation pattern type table selection process P_TPATH is executed (step AKS371). The loss time fluctuation pattern type table selection process P_TPATH in step AKS371 enables selection of the fluctuation pattern type distribution table in response to the special figure display result being "lose".

After steps AKS365, AKS370, and AKS371, the fluctuation pattern type selection buffer with buffer number "0" is loaded (step AKS372). The fluctuation pattern type selection buffer with buffer number "0" is the first fluctuation pattern type selection buffer included in the first reservation storage buffer with buffer number "0" in the first special symbol reservation buffer, or the second special symbol reservation buffer. This is a second fluctuation pattern type selection buffer included in the second suspension storage buffer with buffer number "0" in the symbol suspension buffer. In step AKS372, after setting the address of the second fluctuation pattern type selection buffer with buffer number "0", a starting opening winning check process is executed, and if the starting opening winning designation value is "1", the buffer number After setting the address of the first fluctuation pattern type selection buffer of "0", the data is stored in the fluctuation pattern type selection buffer of buffer number "0" by a transfer command to read the stored data of the set address. It is sufficient if the random number MR3-3 for selecting the variation pattern type can be read out.

When the random number MR3-3 for selecting a variation pattern type is read out in step AKS372, a variation pattern distribution table selection process P_TPATTBL is executed (step AKS373). The fluctuation pattern distribution table selection process P_TPATTBL in step AKS373 includes the fluctuation pattern type distribution table selected in step AKS365, AKS370, or AKS371, and the random number MR3-3 for fluctuation pattern type selection read out in step AKS372. , to make it possible to select a variation pattern distribution table.

After step AKS373, the fluctuation pattern buffer with buffer number "0" is loaded (step AKS374). The fluctuation pattern buffer with buffer number "0" is the first fluctuation pattern buffer included in the first reservation storage buffer with buffer number "0" in the first special symbol reservation buffer, or in the second special symbol reservation buffer. This is the second fluctuation pattern buffer included in the second pending storage buffer with buffer number "0". In step AKS374, after setting the address of the second fluctuation pattern buffer with the buffer number "0", a starting opening winning check process is executed, and if the starting opening winning designation value is "1", the buffer number "0" is set. '' After setting the address of the first fluctuation pattern buffer, the random number for the fluctuation pattern is stored in the fluctuation pattern buffer with buffer number "0" by a transfer command to read the stored data at the set address. It is sufficient if MR3-4 can be read.

When the random numbers MR3-4 for the fluctuation pattern are read out in step AKS374, the second distribution determination value comparison process P_HANTEI2 is executed (step AKS375). The second distribution judgment value comparison process in step AKS375 can determine a variation pattern using the variation pattern distribution table selected in step AKS373 and the random numbers MR3-4 for variation patterns read in step AKS374. Make it. At this time, the variation pattern designation data corresponding to the determined variation pattern is stored in the production symbol variation pattern buffer (step AKS376). The effect symbol variation pattern buffer is provided in the game work area of the RAM 102, and is capable of storing different variation pattern designation data corresponding to the determination result of the variation pattern.

Following step AKS376, a variable command transmission table is selected (step AKS377). In step AKS377, a variable command transmission table is made selectable using the variable command transmission table selection table and the stored value of the variable command designation buffer. Thereby, it is only necessary to be able to select different variable command transmission tables, for example, when the special figure display result is a "big hit" or "small hit" and when it is a "loss". The fluctuation command transmission table includes the processing number, the upper byte of the symbol information designation command, the designation information designation code reference designated value, the upper byte of the production symbol designation command, the designation designation code reference value, the production symbol variation command, It is configured to include table data indicating a fluctuation pattern designation data reference designation value. Thereafter, command set processing P_COM_SET is executed (step AKS378). The command set process P_COM_SET in step AKS378 uses the variation command transmission table selected in step AKS377 to enable transmission of the symbol information designation command, production symbol designation command, and production symbol variation command, respectively. By such command set processing P_COM_SET of step AKS378, it is possible to transmit the effect control command which becomes the fluctuation start command from the main board 11 to the effect control board 12.

When the fluctuation start time command is enabled to be transmitted in step AKS378, a special symbol fluctuation time is set (step AKS379). In step AKS379, by executing time data development processing using the special symbol fluctuation time table and the fluctuation pattern designation data, it is possible to set different special symbol fluctuation times in accordance with the determination result of the fluctuation pattern. Subsequently, a transfer command for setting a pointer is used to set a work table address after setting a variable pattern (step AKS380). The post-variation pattern setting work table address is the address of the post-variation pattern setting work table stored in the game data area of the ROM 101. Next, data set processing P_DATASET is executed (step AKS381), and fluctuation pattern setting processing P_TPATSET is completed. The data set process P_DATASET in step AKS381 uses the work table after setting the variation pattern whose address has been set in step AKS380 to set the special symbol process code to 01[H], which is the special symbol variation processing specified value, and The stored value of the display buffer during fluctuation is set to 01[H], which is the display data during special symbol fluctuation. Also, clear the special symbol display update timer, the buffer number ``0'' for selecting a loss effect, the buffer number ``0'' for selecting a variation pattern type, and the buffer number ``0'' for variation patterns. It can be initialized by At this time, different buffers and timers may be set and cleared by referring to different tables when the starting opening winning designation value is "1" and when it is "2".

FIG. 10-27(A) is a flowchart showing an example of the winning time variation pattern type table selection process P_TPATA. The winning time variation pattern type table selection process P_TPATA is included in the process that can be called from the variation pattern setting process P_TPATSET shown in FIG. It is executable, and if the hit flag is the small hit specified value in step AKS366, it is executable in step AKS370. When the CPU 103 executes the winning time variation pattern type table selection process P_TPATA, the CPU 103 loads the performance state selection buffer (step AKS421). The performance state selection buffer is provided in the game work area of the RAM 102, and can set a stored value corresponding to the performance state after the end of the jackpot game state. In step AKS421, it is only necessary that the value stored in the performance state selection buffer can be read out by a transfer command for reading out data stored at a designated address in the gaming work area of the RAM 102.

Following step AKS421, a variation pattern type selection table is determined (step AKS422). In step AKS422, a variation pattern type selection table can be determined using the state-based jackpot selection table or state-based small win selection table and the stored value of the performance state selection buffer read out in step AKS421. The state-based jackpot selection table has an address set in step AKS364 when the winning time fluctuation pattern type table selection process P_TPATA is executed in step AKS365 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26. The address of the state-based small hit selection table is set in step AKS369 when the winning variation pattern type table selection process P_TPATA is executed in step AKS370 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. . The state-based jackpot selection table and the state-based small win selection table are configured to include table data that allows different variation pattern type selection tables to be determined in accordance with the stored values in the production state selection buffer. Therefore, in step AKS422, different fluctuation pattern type selection tables can be determined depending on the stored value of the performance state selection buffer depending on whether the special figure display result is a "big hit" or a "small hit". .

After determining the variation pattern type selection table in step AKS422, a winning symbol designation value is set (step AKS423). In step AKS423, the content loaded from the jackpot symbol determination buffer or the small hit symbol determination buffer may be set as a processing target by transferring it to a processing register included in the internal registers of the CPU 103. The jackpot symbol determination buffer is loaded in step AKS363 when the winning variation pattern type table selection process P_TPATA is executed in step AKS365 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. The small hit symbol determination buffer is loaded in step AKS368 when the winning variation pattern type table selection process P_TPATA is executed in step AKS370 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. The stored value of the jackpot symbol determination buffer indicates the jackpot symbol designation value. The value stored in the small hit symbol determination buffer indicates the small win symbol designation value. Using the winning symbol designation value set in this way together with the variation pattern type selection table determined in step AKS422, the distribution determination value comparison process P_HANTEI is executed (step AKS424).

The distribution judgment value comparison process P_HANTE compares the numerical data set as the comparison value and the distribution judgment value indicated by the table storage data. Execution is enabled until the distribution judgment value exceeds . At this time, if the distribution determination value is less than or equal to the comparison value, the process proceeds to the next comparison, and in response to the distribution determination value exceeding the comparison value, the table storage data is made readable as specified data. In the distribution judgment value comparison process P_HANTEI of step AKS424, the jackpot symbol designation value or the small hit symbol designation value is set as a comparison value, and the specification corresponding to the distribution determination value that exceeds the comparison value is determined by the data stored in the fluctuation pattern type selection table. Data is read.

When the distribution judgment value comparison process P_HANTEI in step AKS424 is completed, a variation pattern type distribution table is determined (step AKS425), and the winning variation pattern type table selection process P_TPATA is completed. In step AKS425, the specified data read out by the distribution judgment value comparison process P_HANTEI in step AKS424 is added to the start address of the fluctuation pattern type distribution table, so that the address of the fluctuation pattern type distribution table to be used is set as a pointer. By setting this, it becomes possible to determine the fluctuation pattern type distribution table.

FIG. 10-27 (B1) shows a variation pattern type distribution table determination example AKD11 in which the special figure display result corresponds to "jackpot". When the special figure display result is "Jackpot", in step AKS405 of the jackpot information data selection process P_TFVR_ZU shown in FIG. 10-23, the jackpot symbol designation value "1" to It can be determined to be one of the values 00[H] to 0D[H] corresponding to "14". When the winning time fluctuation pattern type table selection process P_TPATA is executed in step AKS365 of the fluctuation pattern setting process P_TPATSET shown in FIG. It is possible to determine the distribution table. In the variation pattern type distribution table determination example AKD11, one of the variation pattern type distribution tables AKU01 to AKU03 can be determined corresponding to the values 00 [H] to 0D [H] indicating the jackpot symbol designation value.

FIG. 10-27 (B2) shows a variation pattern type distribution table determination example AKD12 in which the special figure display result corresponds to "small hit". When the special symbol display result is "small hit", in step AKS333 of the special symbol information setting process P_TZU_SET shown in FIG. 10-22, the value 00 corresponding to the small winning symbol designation value "1" to "7" It can be determined to be any one of [H] to 06[H]. When the winning time fluctuation pattern type table selection process P_TPATA is executed in step AKS370 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26, the fluctuation pattern It is possible to determine the type distribution table. In the variation pattern type distribution table determination example AKD12, it is possible to determine one of the variation pattern type distribution tables AKU11 and AKU12 corresponding to 00 [H] to 06 [H] indicating the small winning symbol designation value.

FIG. 10-28(A) is a flowchart illustrating an example of the loss time variation pattern type table selection process P_TPATH. The loss variation pattern type table selection process P_TPATH is included in the process that can be called from the variation pattern setting process P_TPATSET shown in FIG. It can be executed with When the CPU 103 executes the loss time variation pattern type table selection process P_TPATH, the CPU 103 sets the state-based loss selection table address by a transfer command for setting a pointer (step AKS441). The state-based loss selection table address is the address of the first state-based loss selection table or the second state-based loss selection table stored in the game data area of the ROM 101. In step AKS441, different addresses in the game data area can be specified depending on whether the starting opening winning designation value is "1" or "2". As a result, if the starting opening winning designation value is "1", it is possible to set the address of the first state-based loss selection table, and if the starting opening winning designation value is "2", the second state-specific losing selection table can be set. Table address can be set. Then, the performance state selection buffer is loaded (step AKS442). The performance state selection buffer is provided in the game work area of the RAM 102, and can set a stored value corresponding to the performance state after the end of the jackpot game state.

Following step AKS442, a pending loss performance distribution selection table is determined (step AKS443). In step AKS443, by using the first state-specific loss selection table or the second state-based loss selection table whose address was set in step AKS441, and the stored value of the production state selection buffer loaded in step AKS442, To make it possible to determine a losing performance distribution selection table. The first state-based loss selection table and the second state-based loss selection table are configured to include table data that enables different pending loss performance distribution selection tables to be determined in accordance with the stored values of the performance state selection buffer. has been done. Further, the losing performance distribution selection table by reservation is configured to include table data that allows different losing performance distribution tables to be determined in accordance with the count value of the starting opening winning memory counter. Therefore, in step AKS443, a different losing performance distribution selection table by reservation is determined depending on the stored value of the performance state selection buffer when the starting opening winning designation value is "1" and when it is "2". can do.

Next to step AKS443, a starting opening prize storage counter is loaded (step AKS444). The starting opening winnings memory counter is the first starting opening winnings storing counter when the starting opening winnings designated value is "1" or the second starting opening winnings storing counter when the starting opening winnings designated value is "2". . In step AKS444, after setting the second starting opening winning memory counter address in the memory pointer, a starting opening winning winning check process is executed, and if the starting opening winning designation value is "1", the first starting opening winning memory counter address is set to the memory pointer. After setting an address in the memory pointer, it is possible to obtain the count value of the first starting opening winning memory counter or the second starting opening winning memory counter by using a transfer command to read the memory data of the address set in the memory pointer. do it.

After step AKS444, distribution determination value comparison processing P_HANTEI is executed (step AKS445). In the distribution judgment value comparison process P_HANTEI in step AKS445, the counted value of the first starting opening winning memory counter or the second starting opening winning memory counter acquired in step AKS444 is set as a comparison value, and the pending loss determined in step AKS443 is set as a comparison value. Designation data corresponding to the distribution determination value exceeding the comparison value is read out from the storage data of the performance distribution selection table.

When the distribution judgment value comparison process P_HANTEI of step AKS445 is completed, a losing performance distribution table is determined (step AKS446). In step AKS446, the address of the losing performance distribution table to be used is set in the pointer by adding the specified data read by the distribution judgment value comparison process P_HANTEI of step AKS445 to the start address of the losing performance distribution table. By doing so, it becomes possible to determine the losing performance distribution table.

After step AKS446, the losing effect selection buffer with buffer number "0" is loaded (step AKS447). The losing effect selection buffer with buffer number "0" is the first losing effect selection buffer included in the first pending storage buffer with buffer number "0" in the first special symbol pending buffer, or the second special symbol pending. This is a second losing effect selection buffer included in the second pending storage buffer with buffer number "0" in the buffer. In step AKS447, after setting the address of the second losing effect selection buffer with the buffer number "0", if the starting opening winning designation value is "1" in the starting opening winning prize check process, the buffer number "0" is set. After setting the address of the first losing effect selection buffer, a transfer command is issued to read the stored data at the set address. It is sufficient if the random number MR3-2 can be read out.

When the random number MR3-2 for selecting a losing effect is read out in step AKS447, a distribution judgment value comparison process P_HANTEI is executed (step AKS448). The distribution judgment value comparison process P_HANTEI of step AKS448 uses the losing performance distribution table determined in step AKS446 and the random number MR3-2 for selecting a losing performance read out in step AKS447, and uses the fluctuation pattern type distribution table. The offset value of can be determined. In this case, the random number MR3-2 for selecting a losing performance read out in step AKS447 is set as a comparison value, and the distribution judgment value exceeds the comparison value based on the stored data of the losing performance distribution table determined in step AKS446. The offset value of the variation pattern type distribution table indicated by the specified data corresponding to can be read.

When the distribution determination value comparison process P_HANTEI in step AKS448 ends, a fluctuation pattern type distribution table is determined (step AKS449), and the fluctuation pattern type table selection process P_TPATH at the time of loss ends. In step AKS449, the fluctuation pattern type distribution table to be used is added by adding the offset value indicated by the specified data read by the distribution judgment value comparison process P_HANTEI in step AKS448 to the start address of the fluctuation pattern type distribution table. By setting the address in the pointer, the fluctuation pattern type distribution table can be determined.

FIG. 10-28 (B1) shows an example AKD21 of the loss performance distribution table determination corresponding to the first special symbol loss. The first special figure loss means that the special figure display result in the special figure game using the first special figure by the first special symbol display device 4A corresponds to the starting opening winning designation value being "1". This is the case. When the starting opening winning designation value is "1", the count value of the first starting opening winning storage counter can be acquired in step AKS444 of the losing time variation pattern type table selection process P_TPATH. The count value of the first starting opening winning memory counter indicates the first pending memory number. Then, by the distribution judgment value comparison process P_HANTEI in step AKS445, the specified data corresponding to the count value of the first starting opening winning memory counter is read out, and in step AKS446, the losing effect distribution table corresponding to the first pending memory number is read. can be determined. In the losing performance distribution table determination example AKD21, one of the losing performance distribution tables AKV01 to AKV04 can be determined in accordance with the first pending storage number "0" to "3".

FIG. 10-28 (B2) shows an example AKD22 of the loss performance distribution table determination corresponding to the second special symbol loss. The second special figure loss means that the special figure display result in the special figure game using the second special figure by the second special symbol display device 4B corresponds to the starting opening winning designation value being "2". This is the case. When the starting opening winning designation value is "2", the count value of the second starting opening winning counter can be acquired in step AKS444 of the losing time variation pattern type table selection process P_TPATH. The count value of the second starting opening winning memory counter indicates the second pending memory number. Then, by the distribution judgment value comparison process P_HANTEI in step AKS445, the specified data corresponding to the count value of the second starting opening winning memory counter is read out, and in step AKS446, the losing effect distribution table corresponding to the second pending memory number is read. can be determined. In the losing performance distribution table determination example AKD22, only the common losing performance distribution table AKV11 can be determined corresponding to the second pending storage number "0" to "3".

FIG. 10-28(C) shows a variation pattern type distribution table determination example AKD23 in the case of the losing effect distribution table AKV01. The losing performance distribution table AKV01 can be determined when the starting opening winning designation value is "1" and the first pending storage number is "0" in the losing performance distribution table determination example AKD21. When the starting opening winning designation value is "1", in step AKS447 of the losing time variation pattern type table selection process P_TPATH, the random number MR3- for selecting a losing performance is selected from the first losing performance selection buffer with buffer number "0". 2 can be read. Then, by the distribution determination value comparison process P_HANTEI in step AKS448, the specified data corresponding to the random number MR3-2 for selecting a losing effect is read, and in step AKS449, a variation pattern type distribution table can be determined. In the variation pattern type distribution table determination example AKD23, one of the variation pattern type distribution tables AKU21 to AKU25 can be determined in accordance with the random number MR3-2 for selecting a losing effect.

FIG. 10-29 is a diagram for explaining a configuration example of a variation pattern type distribution table. When the winning time fluctuation pattern type table selection process P_TPATA shown in FIG. 10-27(A) is executed in step AKS365 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26, the jackpot symbol specified value Corresponding to the determination result of FIG. 10-27 (B1), one of the fluctuation pattern type distribution tables AKU01 to AKU03 in the fluctuation pattern type distribution table determination example AKD11 is selected from among the plurality of fluctuation pattern type distribution tables. It is possible to decide either one. The winning time fluctuation pattern type table selection process P_TPATA shown in FIG. 10-27(A) is used to specify the small winning symbol when executed in step AKS370 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26. Corresponding to the value determination result, a plurality of fluctuation pattern type distribution tables, such as either of the fluctuation pattern type distribution tables AKU11 and AKU12 in the fluctuation pattern type distribution table determination example AKD12 shown in FIG. 10-27 (B2), are selected. It is possible to decide on one of them. Step AKS449 of the losing fluctuation pattern type table selection process P_TPATH shown in FIG. 10-28(A) is the fluctuation pattern type distribution table in the fluctuation pattern type distribution table determination example AKD23 shown in FIG. 10-28(C). Any one of a plurality of variation pattern type distribution tables, such as any one of AKU21 to AKU25, can be determined. Then, the variation pattern distribution table selection process P_TPATTBL executed in step AKS373 of the variation pattern setting process P_TPATSET shown in FIG. 10-26 uses the random number MR3-3 for variation pattern type selection read out in step AKS372. The variable pattern type can be selected by referring to the variable pattern type distribution table using the variable pattern type distribution table, and the variable pattern distribution table corresponding to the selection result can be selected.

FIG. 10-29(A) shows a configuration example of the variation pattern type distribution table AKU01. The variable pattern type distribution table AKU01 is included in a plurality of variable pattern type distribution tables that can be determined in accordance with the specified jackpot symbol value. The fluctuation pattern type distribution table AKU01 in FIG. 10-29(A) is configured with table data so that one of the fluctuation pattern types CPA01 to CPA05 can be determined in accordance with the random number MR3-3 for selecting the fluctuation pattern type. is configured.

FIG. 10-29 (B1) shows a configuration example of the variation pattern type distribution table AKU11. The fluctuating pattern type distribution table AKU11 is included in a plurality of fluctuating pattern type distribution tables that can be determined in accordance with the small winning symbol designation value. The fluctuation pattern type distribution table AKU11 in FIG. 10-29 (B1) is a table so that only the common fluctuation pattern type CPB01 can be determined corresponding to the random number MR3-3 for all the fluctuation pattern type selections. Data is configured.

FIG. 10-29 (B2) shows a configuration example of the variation pattern type distribution table AKU12. The fluctuating pattern type distribution table AKU12 is included in a plurality of fluctuating pattern type distribution tables that can be determined in accordance with the small winning symbol designation value. The fluctuation pattern type distribution table AKU12 in FIG. 10-29 (B2) is a table so that only the common fluctuation pattern type CPB02 can be determined corresponding to the random number MR3-3 for all the fluctuation pattern type selections. Data is configured.

FIG. 10-29 (C1) shows a configuration example of the variation pattern type distribution table AKU21. The variation pattern type distribution table AKU21 is included in a plurality of variation pattern type distribution tables that can be determined in accordance with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type distribution table AKU21 in FIG. 10-29 (C1) is configured with table data such that the fluctuation pattern type CPC01 or CPC02 can be determined in accordance with the random number MR3-3 for selecting the fluctuation pattern type. is configured.

FIG. 10-29 (C2) shows a configuration example of the variation pattern type distribution table AKU22. The variation pattern type distribution table AKU22 is included in a plurality of variation pattern type distribution tables that can be determined in accordance with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type distribution table AKU22 in FIG. 10-29 (C2) is a table so that only the common fluctuation pattern type CPC03 can be determined in response to the random number MR3-3 for all the fluctuation pattern type selections. Data is configured.

FIG. 10-29 (C3) shows a configuration example of the variation pattern type distribution table AKU23. The variation pattern type distribution table AKU23 is included in a plurality of variation pattern type distribution tables that can be determined in accordance with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type distribution table AKU23 in FIG. 10-29 (C3) is a table so that only the common fluctuation pattern type CPC04 can be determined corresponding to the random number MR3-3 for all the fluctuation pattern type selections. Data is configured.

FIG. 10-29 (C4) shows a configuration example of the variation pattern type distribution table AKU24. The variation pattern type distribution table AKU24 is included in a plurality of variation pattern type distribution tables that can be determined in accordance with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type distribution table AKU24 in FIG. 10-29 (C4) is configured with table data so that one of the fluctuation pattern types CPC05 to CPC07 can be determined in accordance with the random number MR3-3 for selecting the fluctuation pattern type. is configured.

FIG. 10-29 (C5) shows a configuration example of the variation pattern type distribution table AKU25. The variation pattern type distribution table AKU25 is included in a plurality of variation pattern type distribution tables that can be determined in accordance with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type distribution table AKU25 in FIG. 10-29 (C5) is a table so that only the common fluctuation pattern type CPC08 can be determined corresponding to the random number MR3-3 for all the fluctuation pattern type selections. Data is configured.

FIGS. 10-30 to 10-32 are diagrams for explaining configuration examples of variation pattern distribution tables that can be used in accordance with variation pattern types. In the fluctuation pattern distribution table selection process P_TPATTBL executed in step AKS373 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26, the fluctuation pattern type selection result using the random number MR3-3 for fluctuation pattern type selection is Correspondingly, a variation pattern distribution table is selected. Thereafter, the second distribution judgment value comparison process P_HANTEI2 in step AKS375 uses the random numbers MR3-4 for the variation pattern read out in step AKS374 to make it possible to determine the variation pattern by referring to the variation pattern distribution table. .

FIG. 10-30 (A1) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPA01. The variation pattern type CPA01 can be determined at a predetermined rate corresponding to the random number MR3-3 for selection of the variation pattern type when using the variation pattern type distribution table AKU01 that can be determined in accordance with the designated value of the jackpot symbol. In the configuration example of FIG. 10-30 (A1), the fluctuation pattern distribution table is configured such that one of the fluctuation patterns PA01 to PA03, PA51, and PA52 can be determined in accordance with the random number MR3-4 for the fluctuation pattern. , the table data is configured. In this way, the distribution determination value is set for the variation pattern type CPA01 based on the data stored in the variation pattern distribution table so that it can be determined as one of the variation patterns PA01 to PA03, PA51, and PA52.

FIG. 10-30 (A2) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPA02. The variation pattern type CPA02 can be determined at a predetermined rate corresponding to the random number MR3-3 for selection of the variation pattern type when using the variation pattern type distribution table AKU01 which can be determined in accordance with the specified jackpot symbol value. In the configuration example shown in FIG. 10-30 (A2), the variation pattern distribution table can determine one of the variation patterns PA04 to PA11, PA21 to PA23, and PA54 in accordance with the random number MR3-4 for variation patterns. The table data is structured as follows. In this way, the distribution determination value is set for the variation pattern type CPA02 by the data stored in the variation pattern distribution table so that it can be determined as any of the variation patterns PA04 to PA11, PA21 to PA23, and PA54.

FIG. 10-30 (A3) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPA03. The variation pattern type CPA03 can be determined at a predetermined rate corresponding to the random number MR3-3 for selection of the variation pattern type when using the variation pattern type distribution table AKU01 that can be determined in accordance with the specified jackpot symbol value. In the configuration example shown in FIG. 10-30 (A3), the variation pattern distribution table can determine one of the variation patterns PA31 to PA38, PA24 to PA26, and PA55 in accordance with the random number MR3-4 for variation patterns. The table data is structured as follows. In this way, the distribution determination value is set for the variation pattern type CPA03 by the data stored in the variation pattern distribution table so that it can be determined as any of the variation patterns PA31 to PA38, PA24 to PA26, and PA55.

FIG. 10-30 (A4) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPA04. The variation pattern type CPA04 can be determined at a predetermined rate corresponding to the random number MR3-3 for selection of the variation pattern type when using the variation pattern type distribution table AKU01 which can be determined in accordance with the specified jackpot symbol value. In the configuration example of FIG. 10-30 (A4), the fluctuation pattern distribution table is configured with table data so that only the common fluctuation pattern PA41 can be determined corresponding to the random numbers MR3-4 for all fluctuation patterns. is configured. In this way, the distribution determination value is set for the variation pattern type CPA04 based on the data stored in the variation pattern distribution table so that only the variation pattern PA41 can be determined.

FIG. 10-30 (A5) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPA05. The variation pattern type CPA05 can be determined at a predetermined rate corresponding to the random number MR3-3 for selection of the variation pattern type when using the variation pattern type distribution table AKU01 that can be determined in accordance with the designated value of the jackpot symbol. In the configuration example of FIG. 10-30 (A5), the fluctuation pattern distribution table is configured with table data so that only the common fluctuation pattern PA42 can be determined corresponding to the random numbers MR3-4 for all fluctuation patterns. is configured. In this way, the distribution determination value is set for the variation pattern type CPA05 based on the data stored in the variation pattern distribution table so that only the variation pattern PA42 can be determined.

FIG. 10-30 (B1) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPB01. The variation pattern type CPB01 can be determined corresponding to the random number MR3-3 for all variation pattern type selections when using the variation pattern type distribution table AKU11 that can be determined in accordance with the specified value of the small winning symbol. . In the configuration example of FIG. 10-30 (B1), the fluctuation pattern distribution table is configured with table data so that only the common fluctuation pattern PB01 can be determined corresponding to the random numbers MR3-4 for all fluctuation patterns. is configured. In this way, the distribution determination value for the variation pattern type CPB01 is set based on the data stored in the variation pattern distribution table so that only the variation pattern PB01 can be determined.

FIG. 10-30 (B2) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPB02. The variation pattern type CPB02 can be determined corresponding to the random number MR3-3 for selecting all variation pattern types when using the variation pattern type distribution table AKU12, which can be determined in accordance with the specified value of the small winning symbol. . In the configuration example shown in FIG. 10-30 (B2), the fluctuation pattern distribution table has table data such that one of the fluctuation patterns PB11 to PB14 can be determined corresponding to the random number MR3-4 for the fluctuation pattern. It is configured. In this way, a distribution determination value is set for the variation pattern type CPB02 based on the data stored in the variation pattern distribution table so that it can be determined as one of the variation patterns PB11 to PB14.

FIG. 10-31(A) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPC01. The variation pattern type CPC01 is determined at a predetermined rate corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU21 that can be determined corresponding to the random number MR3-2 for selecting the losing effect. Determinable. In the configuration example of FIG. 10-31(A), the fluctuation pattern distribution table is configured with table data so that only the common fluctuation pattern PC01 can be determined corresponding to the random numbers MR3-4 for all fluctuation patterns. is configured. In this way, the distribution determination value for the variation pattern type CPC01 is set based on the data stored in the variation pattern distribution table so that only the variation pattern PC01 can be determined.

FIG. 10-31(B) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPC02. The variation pattern type CPC02 is determined at a predetermined rate corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU21 which can be determined corresponding to the random number MR3-2 for selecting the losing effect. Determinable. In the configuration example shown in FIG. 10-31(B), the variation pattern distribution table is configured to select one of the variation patterns PC12, PC13, PC15, PC16, PC24, PC27, PC33, and PC49, corresponding to the random number MR3-4 for variation patterns. The table data is structured so that it can be determined exactly. In this way, the variation pattern type CPC02 has a distribution determination value based on the data stored in the variation pattern distribution table so that it can be determined as one of the variation patterns PC12, PC13, PC15, PC16, PC24, PC27, PC33, and PC49. Set.

FIG. 10-31(C) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPC03. The variation pattern type CPC03 corresponds to the random number MR3-3 for selecting all the variation pattern types when using the variation pattern type distribution table AKU22 which can be determined corresponding to the random number MR3-2 for selecting a losing effect. Determinable. In the configuration example shown in FIG. 10-31(C), the variation pattern distribution table is configured so that one of the variation patterns PC11 to PC18 and PC101 can be determined corresponding to the random number MR3-4 for variation patterns. Data is configured. In this way, the distribution determination value is set for the variation pattern type CPC03 based on the data stored in the variation pattern distribution table so that it can be determined as one of the variation patterns PC11 to PC18 and PC101.

FIG. 10-31(D) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPC04. The variation pattern type CPC04 corresponds to the random number MR3-3 for selecting all the variation pattern types when using the variation pattern type distribution table AKU23 which can be determined corresponding to the random number MR3-2 for selecting a losing effect. Determinable. In the configuration example shown in FIG. 10-31(D), the fluctuation pattern distribution table is configured so that one of the fluctuation patterns PC19 to PC27 and PC102 can be determined in accordance with the random number MR3-4 for the fluctuation pattern. Data is configured. In this way, the distribution determination value is set for the variation pattern type CPC04 based on the data stored in the variation pattern distribution table so that it can be determined as one of the variation patterns PC19 to PC27 and PC102.

FIG. 10-32(A) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPC05. The variation pattern type CPC05 is the first ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU24 which can be determined corresponding to the random number MR3-2 for selecting the losing effect. It can be determined by In the configuration example shown in FIG. 10-32(A), the fluctuation pattern distribution table has table data such that one of the fluctuation patterns PC28 to PC43 can be determined corresponding to the random number MR3-4 for the fluctuation pattern. It is configured. In this way, the distribution determination value is set for the variation pattern type CPC05 based on the data stored in the variation pattern distribution table so that it can be determined as one of the variation patterns PC28 to PC43.

FIG. 10-32(B) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPC06. The variation pattern type CPC06 is the first ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU24 which can be determined corresponding to the random number MR3-2 for selecting the losing performance. can be determined at a second rate different from . The second ratio is a lower ratio than the first ratio. In the configuration example shown in FIG. 10-32(B), the fluctuation pattern distribution table has table data such that one of the fluctuation patterns PC44 to PC59 can be determined corresponding to the random number MR3-4 for the fluctuation pattern. It is configured. In this way, the distribution determination value is set for the variation pattern type CPC06 based on the data stored in the variation pattern distribution table so that it can be determined as any of the variation patterns PC44 to PC59.

FIG. 10-32(C) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPC07. The variation pattern type CPC07 is the first ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU24 that can be determined corresponding to the random number MR3-2 for selecting the losing effect. and a third ratio different from the second ratio. The third ratio is lower than the first ratio and the second ratio. In the configuration example shown in FIG. 10-32(C), the fluctuation pattern distribution table has table data such that one of the fluctuation patterns PC60 to PC75 can be determined corresponding to the random number MR3-4 for the fluctuation pattern. It is configured. In this way, a distribution determination value is set for the variation pattern type CPC07 based on the data stored in the variation pattern distribution table so that it can be determined as one of the variation patterns PC60 to PC75.

FIG. 10-32(D) shows a configuration example of a variation pattern distribution table corresponding to variation pattern type CPC08. The variation pattern type CPC08 corresponds to the random number MR3-3 for selecting all the variation pattern types when using the variation pattern type distribution table AKU25, which can be determined corresponding to the random number MR3-2 for selecting a losing effect. Determinable. In the configuration example shown in FIG. 10-32(D), the fluctuation pattern distribution table is configured with table data so that only the common fluctuation pattern PC02 can be determined corresponding to the random numbers MR3-4 for all fluctuation patterns. is configured. In this way, the distribution determination value is set for the variation pattern type CPC08 based on the data stored in the variation pattern distribution table so that only the variation pattern PC02 can be determined.

FIG. 10-33(A) is a flowchart showing an example of normal symbol process processing P_FPROC. The normal symbol process process P_FPROC is included in the process that can be called from the game control timer interrupt process P_PCT shown in FIG. 5, and can be executed in step AKS59 every time a timer interrupt occurs. When the CPU 103 executes the normal symbol process process P_FPROC, the CPU 103 sets the gate switch passage correspondence flag (step AKS501). Setting the gate switch passage correspondence flag reflects the state of the gate switch 21 included in the switch-on buffer in the flag register of the CPU 103 by executing a logical operation instruction or the like. At this time, the fact that the zero flag in the flag register is in the on state indicates that the gate switch passage correspondence flag is in the off state. On the other hand, the fact that the zero flag is in the OFF state indicates that the gate switch passage support flag is in the ON state. Thereafter, it is determined whether the gate switch passage support flag is on (step AKS502). If the gate switch passage support flag is on (step AKS502; Yes), gate switch passage processing P_FZU_ON is executed (step AKS503).

If the gate switch passage support flag is off in response to step AKS502 (step AKS502; No), or after the gate switch passage processing P_FZU_ON in step AKS503, the normal symbol process processing jump table is set by a transfer command that sets a pointer. Set (step AKS504). The normal symbol process processing jump table is an address management table that makes it possible to select and execute the process corresponding to the read value of the normal symbol process code. The normal pattern process code can be updated to any one of 00 [H] to 04 [H] in accordance with the progress of game control in the pachinko game machine 1, and is also referred to as the normal pattern process code.

Following step AKS504, a normal symbol process code is loaded by a transfer command for reading stored data (step AKS505). Next, by executing the 2-byte data selection process P_ABXEXEC (step AKS506), the address of the process selected in response to the normal symbol process code is acquired. The address obtained at this time is set to a pointer. Thereafter, by executing the process pointed to by the pointer using the subroutine call command (step AKS507), the process selected in response to the normal symbol process code becomes executable. When the selected process ends and returns to the normal symbol process process P_FPROC by the return command, this normal symbol process process P_FPROC also ends, and returns to the game control timer interrupt process P_PCT by the return command.

FIG. 10-33(B) shows an example of the configuration of the normal symbol process processing jump table AKT51 used in the normal symbol process process P_FPROC. The normal symbol process processing jump table is configured to include table data that can set the address of the process selected corresponding to the normal symbol process code in the internal register of the CPU 103 used as a pointer. The normal symbol process processing jump table of configuration example AKT51 is normal symbol normal processing P_FNORM when the normal symbol process code is 00 [H], and normal symbol fluctuation processing P_FSCRL when the normal symbol process code is 01 [H]. , the normal pattern stop processing P_FSTOP when the normal pattern process code is 02[H], the normal electric accessory activation preprocessing P_FINT when the normal pattern process code is 03[H], and the normal pattern process code 04 [H], and table data that can set the corresponding address value as a pointer is included.

Normal symbol normal processing P_FNORM determines whether or not to start the common symbol game based on the presence or absence of stored normal symbol reservation information, determines the fixed normal symbol to be stopped and displayed in the variable display of normal symbols, and To enable determination of a normal symbol variation pattern which is a symbol variation pattern. The normal symbol fluctuation process P_FSCRL measures the elapsed time after the normal symbol starts to fluctuate on the normal symbol display 20, and can determine whether or not the regular symbol fluctuation time corresponding to the normal symbol fluctuation pattern has elapsed. Make it. The normal symbol stop process P_FSTOP measures the elapsed time after the normal symbol stops fluctuating on the normal symbol display 20, and makes it possible to determine whether the normal symbol stop time has elapsed. When the normal symbol stop time has elapsed, the normal symbol process code can be updated and various settings can be made in accordance with the ordinary symbol display result. In this embodiment, it is sufficient if the normal symbol process code can be updated to 03 [H] in response to all ordinary symbol display results. The normal electric accessory actuation preprocessing P_FINT and the normal electric accessory actuation process P_FOPEN control the normal electric accessory solenoid 81 to change the second starting prize opening formed in the variable prize winning ball device 6B from the closed state to the open state. This is a process to make it changeable.

FIG. 10-34 is a diagram for explaining an example of the use of a data structure related to control of a normal symbol game, which is a variable display of normal symbols. For example, the normal symbol process process P_FPROC shown in FIG. 10-33(A) is executed in step AKS507 by executing the 2-byte data selection process P_ABXEXEC in step AKS506 using the normal symbol process code loaded in step AKS505. The process selected in response to the normal pattern process code is made executable. The normal symbol process code is provided in the normal symbol control data area, and the stored value can be updated in accordance with the control state of the common symbol game and the second starting prize opening. The gate switch passing process P_FZU_ON of step AKS503 can read the random number MR2-1 for the symbol per normal symbol, and store the numerical data indicating the value of the read random number MR2-1 in the buffer for the symbol per normal symbol. Store and make saveable. The buffer for symbols per normal symbol is provided in the buffer area for symbols per normal symbol, and is capable of storing numerical data indicating the value of the read random number MR2-1 until the number of stored normal symbols reaches the upper limit. . In this way, the process that can be executed in the normal symbol process process P_FPROC and the normal symbol process process P_FPROC is the variable display of normal symbols using the storage data in the normal symbol control data area and the buffer area for symbols per normal symbol. Allows control over the Fuzu game.

FIG. 10-34(A) shows a configuration example AKB51 of the normal symbol control data area. The normal symbol control data area of the configuration example AKB51 is used for ordinary symbol process processing P_FPROC, such as the ordinary symbol game which is a variable display of ordinary symbols, and the closed state and open state of the second starting prize opening that can be controlled based on the display result. It is possible to store various data related to control, etc. This normal symbol control data area contains the normal symbol process code at address F03E[H], the gate passing memory counter at address F03F[H], the normal symbol buffer at address F040[H], and the normal symbol at address F041[H]. The electric accessory release pattern timer, the normal electric accessory release pointer at address F043[H], the ordinary electric accessory winning number counter at address F045[H], and the normal symbol process timer at address F04A[H]. Contains.

The normal symbol process code can specify the process selected in the normal symbol process process P_FPROC. The gate passage storage counter is capable of storing a count value corresponding to the number of game balls detected by the gate switch 21. The normal symbol buffer can store data corresponding to the normal symbol designation value. The normal symbol designation value is a designation value corresponding to the confirmed normal symbol that is the display result in the variable display of the normal symbol by the normal symbol display 20, and includes a symbol designation value per normal symbol. The design designation value per normal symbol is a designated value corresponding to the confirmed normal symbol displayed by the normal symbol display 20 when the display result is "per common symbol" in the variable display of the normal symbol. The normal electric accessory opening pattern timer can store a timed value corresponding to the remaining time to control the second starting prize opening to the open state. The normal electric accessory opening pointer can specify the storage address of the normal electric accessory opening pattern table in which the time to control the second starting prize opening to the open state is set. The normal electric accessory winning number counter can store a count value corresponding to the number of game balls detected by the second starting port switch 22B. The normal symbol process timer can store a timed value corresponding to the control time by the normal symbol process process P_FPROC.

FIG. 10-34(B) shows a configuration example AKB52 of the symbol buffer area per normal symbol. The buffer area for symbols per normal symbol of the configuration example AKB52 can store numerical data indicating the value of the random number MR2-1 for symbols per normal symbol read when the game ball passes through the passage gate 41. be. This buffer area for symbols per normal symbol includes buffer numbers "1" to "4" for symbols per normal symbol at addresses F046[H] to F049[H]. The buffer numbers "1" to "4" for normal symbols are the buffers for symbols per normal symbol to which buffer numbers "1" to "4" are assigned, and the random numbers MR2 are assigned in the order in which the game balls pass through the passage gate 41. A value of -1 can be stored. As a result, the storage information of the symbol buffer per normal symbol indicates the number of game balls that have passed through the passage gate 41, and also indicates the value of the random number MR2-1 read in response to each passage.

FIG. 10-35 is a flowchart illustrating an example of gate switch passage processing P_FZU_ON. The gate switch passage process P_FZU_ON is included in the processes that can be called from the normal symbol process process P_FPROC shown in FIG. 10-33 (A), and when the gate switch passage support flag is on in step AKS502, it is It is executable. When the CPU 103 executes the gate switch passage process P_FZU_ON, the CPU 103 sets the gate passage storage counter address by a transfer command for setting a pointer (step AKS601). The gate passage storage counter address is the address of a gate passage storage counter provided in the game work area of the RAM 102. Subsequently, the gate passage storage counter is loaded by a transfer command for reading the storage data at the address pointed to by the pointer (step AKS602).

After step AKS602, it is determined whether the count value of the gate passage storage counter is greater than or equal to the maximum value of the counter (step AKS603). For example, by using a comparison return instruction that can compare the value loaded in step AKS602 and a counter maximum value such as "4", if the value is greater than or equal to the counter maximum value (step AKS603; Yes), gate switch passage processing P_FZU_ON is executed. Finish and return to normal pattern process processing P_FPROC. On the other hand, if it is less than the maximum value of the counter (step AKS603; No), the count value of the gate passage storage counter is updated by adding 1 (step AKS604). In this case, an arithmetic and logic operation instruction that increments the stored data at the address pointed to by the pointer makes it possible to update the count value of the gate passing storage counter by adding one.

After step AKS604, a symbol buffer address for each normal symbol is set by a transfer command for setting a pointer (step AKS605). In this case, the address of the normal symbol per symbol buffer with buffer number "0" provided in the game work area of the RAM 102 is set in the pointer. Then, the value loaded in step AKS602 is added to the value stored in the pointer. As a result, in the buffer area for symbols per normal symbol, the address of the buffer for symbols per normal symbol in which the random number MR2-1 for symbols per normal symbol is stored can be set in the pointer. Following this, the random number counter for symbols per normal symbol is stored (step AKS606), and the gate switch passage process P_FZU_ON is completed. In step AKS606, a random number for symbols per normal symbol is sent by a transfer command to write the value read out by specifying the lower address of the random number counter for symbols per normal symbol in the gaming work area of the RAM 102 to the storage area of the address pointed to by the pointer. It is sufficient if the value of the random number MR2-1 obtained from the counter can be stored in the symbol buffer for each normal symbol.

FIG. 10-36 is a flowchart showing an example of normal symbol normal processing P_FNORM. The normal pattern normal process P_FNORM is included in the process that can be called from the normal pattern process process P_FPROC shown in FIG. 10-33 (A), and when the normal pattern process code loaded by step AKS505 is 00[H] This can be executed in step AKS507. When the CPU 103 executes the normal symbol normal processing P_FNORM, the CPU 103 loads the gate passing memory counter (step AKS621). In this case, it is only necessary to obtain the count value of the gate passing memory counter by a transfer instruction for specifying the lower address of the gate passing memory counter in the game work area of the RAM 102 and setting the read value in the internal register of the CPU 103. . Then, it is determined whether or not the count value of the gate passage storage counter is "0" by an operation return instruction that returns the process when the second zero flag in the flag register of the CPU 103 is in the on state (step AKS622). At this time, if the second zero flag is in the on state, corresponding to the count value of the gate passing memory counter being "0" (step AKS622; Yes), the normal symbol normal process P_FNORM is completed, and the normal symbol process Return to processing P_FPROC.

Corresponding to step AKS622, if the count value of the gate passing memory counter is not "0" (step AKS622; No), a table address for setting a symbol per normal symbol is set by a transfer command for setting a pointer ( step AKS623). The symbol setting table address per normal symbol is the address of the table for symbol setting per normal symbol stored in the game data area of the ROM 101. Thereafter, the normal symbol per symbol buffer with buffer number "1" is loaded (step AKS624). In step AKS624, a transfer instruction for setting the value read out by specifying the lower address of the symbol buffer for each normal symbol with buffer number "1" in the game work area of the RAM 102 in the internal register of the CPU 103 is executed with the buffer number "1". It is only necessary that the random number MR2-1 for symbols per normal symbol stored in the buffer for symbols per normal symbol of "1" can be read out.

When the random number MR2-1 for the symbol per normal symbol is read out in step AKS624, the second distribution determination value comparison process P_HANTEI2 is executed (step AKS625). The second distribution judgment value comparison process P_HANTEI2 in step AKS625 is performed by setting the value of the random number MR2-1 read out in step AKS624 as a comparison value, and using the stored data of the symbol setting table per normal symbol whose address has been set in step AKS623. , the symbol designation value per normal symbol indicated by the distribution result data can be determined as the display result by the normal symbol display 20. When the symbol designation value per normal symbol is determined by the second distribution determination value comparison process P_HANTEI2 of step AKS625, the symbol designation value per normal symbol is stored in the normal symbol buffer (step AKS626). The normal symbol buffer is provided in the normal symbol control data area shown in FIG. 10-34(A), and is assigned address F040[H]. In step AKS626, the symbol designation value per normal symbol may be stored by a transfer command for writing to the storage area of the designated address in the game work area of the RAM 102.

After step AKS626, the count value of the gate passage storage counter is subtracted by 1 (step AKS627). Then, the symbol buffer for each normal symbol is shifted (step AKS628). In this case, in the normal symbol per symbol buffer area provided in the game work area of the RAM 102, the address of the normal symbol per symbol buffer with buffer number "2" is set to the pointer specifying the transfer source. Further, the address of the symbol buffer for each normal symbol with buffer number "1" is set in the buffer pointer that specifies the transfer destination. Furthermore, the number of transfers corresponding to the data size of the symbol buffer area per normal symbol is set. Thereafter, by using a block transfer command, the stored contents of the symbol buffer for each normal symbol may be sequentially transferred and shifted. At this time, the normal symbol per symbol buffer with buffer number "4" is cleared and the stored contents are initialized.

After step AKS628, the first normal symbol variation pattern distribution table address is set by a transfer command for setting a pointer (step AKS629). The first normal symbol variation pattern distribution table address is the address of the first normal symbol variation pattern distribution table stored in the game data area of the ROM 101. Further, through the time saving check process, it is confirmed that the time saving function flag is not the time saving operation designated value (step AKS630). At this time, if the time-saving function flag is the time-saving operation specified value (step AKS630; No), the second normal symbol variation pattern distribution table address is set by the transfer command for setting the pointer (step AKS631). The second normal symbol variation pattern distribution table address is the address of the second normal symbol variation pattern distribution table stored in the game data area of the ROM 101.

Corresponding to step AKS630, if the time saving function flag is not the time saving operation specified value (step AKS630; Yes), or after step AKS631, the RS3 soft latch random value register is loaded (step AKS632). In this case, the random number MR3-1 for the normal symbol fluctuation pattern is transferred by a transfer command to set the stored value read by specifying the address of the RS3 soft latch random value register in the function control register area in the internal register of the CPU 103. You can enable it as . Then, the second distribution determination value comparison process P_HANTEI2 is executed (step AKS633). In the second distribution judgment value comparison process P_HANTEI2 of step AKS633, the value of random number MR3-1 read in step AKS632 is set as a comparison value, and the first normal symbol fluctuation pattern distribution table whose address is set in step AKS629 or step AKS631 The normal symbol variation pattern indicated by the distribution result data can be determined by the stored data of the second normal symbol variation pattern distribution table whose address is set by .

When the normal symbol fluctuation pattern is determined by the second distribution determination value comparison process P_HANTEI2 in step AKS633, a normal symbol fluctuation time corresponding to the normal symbol fluctuation pattern is set (step AKS634). In step AKS634, by executing time data development processing using the normal symbol variation time table and the normal symbol variation pattern specification data, it is possible to set the normal symbol variation time corresponding to the determination result of the normal symbol variation pattern. do. Next, a transfer command for setting a pointer is used to set a work table address at the time of normal symbol variation (step AKS635). The normal symbol variation work table address is the address of the normal symbol variation work table stored in the game data area of the ROM 101. Next, data set processing P_DATASET is executed (step AKS636), and normal symbol normal processing P_FNORM is ended. The data set process P_DATASET in step AKS636 uses the normal symbol variation work table whose address has been set in step AKS635 to set the normal symbol process code to 01[H], which is the normal symbol variation processing specified value, and The stored value of the display buffer during fluctuation is set to 01[H], which is the display data during normal symbol fluctuation. In addition, initialization is enabled by clearing the normal symbol display update timer.

FIG. 10-37 is a diagram for explaining a usage example of the data structure regarding normal symbol normal processing P_FNORM. In the normal symbol normal process P_FNORM, the design specification value per normal symbol is determined by executing the second distribution judgment value comparison process P_HANTEI2 in step AKS625 using the table for setting the symbol per normal symbol whose address has been set in step AKS623. Make it decidable. Also, using the first normal symbol variation pattern distribution table whose address is set in step AKS629 or the second normal symbol variation pattern distribution table whose address is set in step AKS631, the second distribution judgment value comparison process P_HANTEI2 of step AKS633 is performed. By executing this, it becomes possible to determine the normal symbol fluctuation pattern. In step AKS634, using the normal symbol variation time table, it is possible to set the normal symbol variation time corresponding to the determination result of the normal symbol variation pattern. Also, in step AKS507 of the normal symbol process process P_FPROC shown in FIG. , the opening time of the normal electric accessory provided corresponding to the second starting prize opening can be determined by using a work setting table when the ordinary electric accessory is activated.

In this way, the normal symbol normal processing P_FNORM enables the symbol designation value per normal symbol to be determined using the symbol setting table per normal symbol. In addition, the normal symbol normal processing P_FNORM enables the normal symbol variation pattern to be determined using the first normal symbol variation pattern distribution table or the second normal symbol variation pattern distribution table. Furthermore, the normal symbol normal processing P_FNORM enables the normal symbol variation time to be determined using the normal symbol variation time table. The normal electric accessory activation preprocessing P_FINT, which is executed in response to the execution result of the ordinary figure game, can determine the opening time of the ordinary electric accessory.

FIG. 10-37(A) shows a configuration example AKT61 of a table for setting symbols per normal symbol. In the configuration example AKT61, the table for setting symbols per normal symbol stores the value 00[H] corresponding to the first symbol designation value per normal symbol at the top address 1B54[H], and stores the number of processing at the next address 1B55[H]. The indicated value 03[H] is stored. The stored data after address 1B56[H] indicates the allocation determination value corresponding to the symbol designation value for each of the first to third normal symbols. The second distribution judgment value comparison process P_HANTEI2 in step AKS625 is performed in the first to third distributions corresponding to the random number MR2-1 for symbols per normal symbol when using the table for setting symbols per normal symbol in the configuration example AKT61. Normally, it can be determined to any of the specified symbol values per symbol. In the configuration example AKT61, the design designation value per first normal symbol is 00 [H], the design designation value per second normal symbol is 01 [H], and the design designation value per third normal symbol is 02 [H]. It is. For example, when the random number MR2-1 for the symbol per normal symbol is 00[H] corresponding to the minimum random number value "0", the first symbol designation value per normal symbol is determined.

FIG. 10-37 (B1) shows a configuration example AKT62 of the first normal symbol variation pattern distribution table. In the first normal symbol variation pattern distribution table of the configuration example AKT62, the value 00[H] corresponding to the specified value of the normal symbol variation pattern FPZ1 is stored in the first address 1B59[H], and the number of processing is stored in the next address 1B5A[H]. The indicated value 04[H] is stored. The stored data after address 1B5B[H] indicates the distribution determination value corresponding to the normal symbol variation patterns FPZ1 to FPZ4. The second distribution judgment value comparison process P_HANTEI2 of step AKS633 is performed by using the normal symbol variation pattern corresponding to the random number MR3-1 for the normal symbol variation pattern when using the first normal symbol variation pattern distribution table of the configuration example AKT62. Any one of FPZ1 to FPZ4 can be determined.

FIG. 10-37 (B2) shows a configuration example AKT63 of the second normal symbol variation pattern distribution table. In the second normal symbol variation pattern distribution table of the configuration example AKT63, the value 04[H] corresponding to the specified value of the normal symbol variation pattern FPZ5 is stored in the first address 1B5F[H], and the number of processing is stored in the next address 1B60[H]. The indicated value 04[H] is stored. The stored data after address 1B61[H] indicates the distribution determination value corresponding to the normal symbol variation patterns FPZ5 to FPZ8. The second distribution judgment value comparison process P_HANTEI2 of step AKS633 is performed by using the normal symbol variation pattern corresponding to the random number MR3-1 for the normal symbol variation pattern when using the second normal symbol variation pattern distribution table of the configuration example AKT63. Any one of FPZ5 to FPZ8 can be determined.

FIG. 10-37(C) shows a normal symbol variation time determination example AKD61. In the determination example AKD61, the normal symbol variation time is determined to be 1000 [ms] corresponding to the normal symbol variation patterns FZP1 to FZP4, and the normal symbol variation time is determined to be 100 [ms] corresponding to the normal symbol variation patterns FZP5 to FZP8. It is determined. In step AKS634, a normal symbol fluctuation time corresponding to the normal symbol fluctuation pattern determined by the second distribution determination value comparison process P_HANTEI2 of step AKS633 is set. The normal symbol fluctuation patterns FZP1 to FZP4 can be determined using the first normal symbol fluctuation pattern distribution table of the configuration example AKT61 when the time saving function flag is off. The normal symbol fluctuation patterns FZP5 to FZP8 can be determined using the second normal symbol fluctuation pattern distribution table of the configuration example AKT62 when the time saving function flag is on. As a result, the normal symbol fluctuation time, which is the variable display time of the normal symbol, can be set to be shorter when the time saving control is being performed than when the time saving control is not being performed.

FIG. 10-37(D) shows an example AKD62 of determining the opening time of a normal electric accessory. In the normal electric accessory activation preprocessing P_FINT, it is possible to determine the normal electric accessory opening time in accordance with the time saving operation specified value and the symbol specified value per normal symbol. Normal electric accessory release time is the value 00 [H] corresponding to the "x" indicating that the time saving operation specified value is not in the time saving state, the symbol specified value 00 [H] to 02 [ per normal symbol. H], it is determined to be 16 ms. On the other hand, when the normal electric accessory activation time is the value 01 [H] corresponding to "○" indicating that the time saving operation specified value is in the time saving state, the specified symbol value 00 [H] for all normal symbols. ] to 02[H], and is determined to be 5000 ms.

In this way, the normal electric accessory release time can be determined to be a different time in accordance with the time saving operation specified value, regardless of the value of the symbol specified value per normal symbol. The symbol designation value per normal symbol can be determined in accordance with the random number MR2-1 for the symbol per normal symbol read from the buffer for symbols per normal symbol. If the time saving operation specified value is the same value, the random number MR2-1 for symbols per normal symbol will be the same in both cases where the random number MR2-1 is the minimum random number value "0" and when it is other than the minimum random number value. Determined by the operating time of the electric accessories. Therefore, corresponding to the special pattern game in which the normal pattern is variablely displayed on the normal pattern display 20, when the random number MR2-1 for the pattern per normal pattern is the minimum random number value "0", if the random number MR2-1 is the minimum random number value, The display result is not determined to be more advantageous than the case where . As a result, when the random number MR2-1 for symbols per normal symbol is used as the second random number, it becomes possible to update the random number appropriately so as to prevent fraudulent acts due to defects in the second random number.

In the game control microcomputer 100 shown in FIG. 10-1, a 16-bit random number circuit 104A and an 8-bit random number circuit 104B select a random number MR1- for special symbol determination among the random numbers included in the gaming random number. 1. Numerical values indicating the respective values of the random number MR3-2 for selecting a losing effect, the random number MR3-3 for selecting the variation pattern type, the random number MR3-4 for the variation pattern, and the random number MR3-1 for the normal symbol variation pattern. Data can be updated. In addition, when the CPU 103 executes the random number update process P_RANDOM etc. shown in FIG. 10-12, the random numbers MR1-2 for winning symbols among the random numbers included in the gaming random numbers become the initial value for winning symbols. Numerical data indicating the respective values can be updated for the random number MR1-3, the random number MR2-1 for symbols per normal symbol, and the random number MR2-2 which becomes the initial value for symbols per normal symbol.

When the special symbol determination process P_TDECISION shown in FIG. 10-20 is executed in step AKS248 of the special symbol normal process shown in FIG. 10-18, the special symbol jackpot determination process of step AKS304 or the special symbol jackpot determination process of step AKS305 The symbol small hit determination process makes it possible to determine whether or not the special symbol display result is a "big hit" or a "small win" using the random number MR1-1 for special symbol determination. Then, when the special symbol information setting process P_TZU_SET shown in FIG. 10-22 is executed in step AKS308 of the special symbol determination process P_TDECISION, the winning symbol Using the random numbers MR1-2, it becomes possible to determine the jackpot design designation value and small win design designation value corresponding to the confirmed special symbol that becomes the display result of the special symbol. In addition, when the second distribution judgment value comparison process P_HANTEIS is executed in step AKS625 of the normal symbol normal process shown in FIG. 10-36, the random number MR2-1 for the symbol per normal symbol is used to It becomes possible to determine the symbol designation value per normal symbol corresponding to the confirmed normal symbol that becomes the display result. The jackpot symbol designation value determined using the random number MR1-2 for the winning symbol is determined in step AKS330 of the special symbol information setting process P_TZU_SET to the maximum number of openings of the jackpot opening shown in FIG. 10-24(C). As in example AKD01, it is possible to set the maximum value of the number of openings of the big prize opening. The design specification value per normal symbol determined using the random number MR2-1 for the symbol per normal symbol is determined by the normal symbol process code in step AKS507 of the normal symbol process process P_FPROC shown in FIG. 10-33 (A). When the normal electric accessory activation preprocessing P_FINT is executed in response to 03[H], the normal electric accessory is It is possible to set the object release time. Therefore, the random numbers MR1-2 for winning symbols are used to determine the display results by the first special symbol display device 4A and the second special symbol display device 4B, and it is possible to set the type of jackpot game state that is advantageous for the player. do. The random number MR2-1 for the symbol per normal symbol is used to determine the display result by the normal symbol display 20, and is used to change the change mode to a guiding state in which the game ball can easily pass through the second starting prize opening, which is the starting area. Make it configurable.

In this way, it is possible to execute processing related to game control using random numbers that serve as random numbers for various games, and the random numbers MR1-2 for winning symbols that serve as the first random numbers and the second random numbers that serve as the second random numbers. Each update range is changed by a common update process such as the initial value change random number update process P_RANCP that can be executed by calling the random number MR2-1 for each normal symbol by the random number update process P_RANDOM shown in Figure 10-12. It can be updated in Here, the random number MR2-1 for symbols per normal symbol has an update range of "0" to "198", and the total number of random numbers included in the update range is "199", so the random number MR2-1 for the symbol per normal symbol is The total number of numbers is a prime number. Therefore, for at least one of the first random number value and the second random number value that can be updated by a common update process, the total number of random numbers included in the update range is a prime number. In this way, the common update process prevents an increase in program capacity, and since the total number of random numbers included in the update range is a prime number, it suppresses the occurrence of synchronous random numbers, making it possible to update appropriate random numbers. Become.

In addition, the random number MR1-2 for the winning symbol, which is the first random number, has an update range of "0" to "199", and the total number of random numbers included in the update range is "200", so the update range is The total number of random numbers included is not a prime number. The random numbers MR1-2 for winning symbols are used to determine the designated jackpot symbol value in the confirmed special symbol, and it is determined whether or not the probability variable state will occur after the end of the jackpot gaming state, corresponding to the designated jackpot symbol value. In some cases. In this case, the determination ratio of the designated jackpot symbol value corresponds to the probability change entry rate which is the ratio controlled to the probability change state. The variable entry rate is included in the important specifications of the pachinko game machine 1, and it is desirable to set it to a value that is clearly easy to recognize. However, if the total number of random numbers included in the update range for random numbers MR1-2 for winning symbols is a prime number, the denominator of the probability of entering into a variable probability will be a prime number, and it will be difficult to express it as a percentage. It may become difficult to recognize the rate. Therefore, among the random number MR1-2 for winning symbols and the random number MR2-1 for symbols per normal symbol that can be updated by a common update process, the random number MR2-1 for the symbol per normal symbol is a random number that is included in the update range. While the total number of numerical values is a prime number, the random number MR1-2 for the winning symbol may be such that the total number of random values included in the update range is not a prime number. This makes it possible to update the random number values appropriately so that the specifications of the pachinko gaming machine 1 can be clearly recognized while suppressing the occurrence of synchronized random numbers.

Regarding the random numbers MR1-2 for winning symbols, which are the first random numbers, the total number of random numbers included in the update range may be a prime number. This makes it possible to more reliably suppress the synchronous occurrence of random numbers that can be updated by a common update process, and to update the random numbers appropriately.

In the random number update process P_RANDOM shown in FIG. 10-12, steps AKS61 to AKS64 can update the random number MR1-2 that becomes the first random value, and steps AKS65 to AKS68 update the random number MR2-2 that becomes the second random value. can be updated. Then, the random number update process P_RANDOM stores the random numbers MR1-2, which is the first random value, and the random number MR2-1, which is the second random value, into the HL register, B register, and DE register of the CPU 103, which are common internal storage means. It can be updated using In this way, it is possible to stably update the first random number value and the second random number value using a common internal storage means, and to update the appropriate random number value.

The CPU 103 that executes the random number update process P_RANDOM shown in FIG. 10-12 sets the random number MR1-2 for winning symbols as the first random number and the random number MR2-1 for the normal symbol as the second random number. In this case, the first updating means is capable of updating the first random number value and the second random number value in their respective update ranges by random number update processing. In addition, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B include a random number MR1-1 for special symbol determination, a random number MR3-2 for selecting a losing effect, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-3 for selecting a variation pattern. When the third and fourth random numbers are set from among the random numbers MR3-4, the third and fourth random numbers are updated by the system clock input that serves as the random number clock signal. This serves as a second update means that can update within the range. For example, the random number MR2-1 for the symbol per normal symbol has an update range of "0" to "198", and the total number of random numbers included in the update range is "199", so the second random number is updated. The total number of random numbers in the range becomes a prime number. On the other hand, for example, the random number MR3-2 for selecting a loss effect has an update range of "0" to "65518", a total number of random numbers included in the update range is "65519", and a variation pattern type selection. The random number MR3-3 for the fluctuation pattern has an update range of "0" to "240", and the total number of random numbers included in the update range is "241", and the random number MR3-4 for the fluctuation pattern Since the range is "0" to "250" and the total number of random numbers included in the update range is "251", at least one of the third random number and fourth random number is included in the update range. The total number of random numbers is a prime number. In this way, even if the update methods are different between the first update means and the second update means, and the update methods are the same, at least one of the random values suppresses the occurrence of synchronization because the total number of random values included in the update range is a prime number. This makes it possible to update appropriate random values.

The 16-bit random number circuit 104A and the 8-bit random number circuit 104B include a random number MR1-1 for special symbol determination, a random number MR3-2 for selecting a losing effect, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-3 for selecting a variation pattern. When random numbers MR3-4 are set as the first random value and the second random value, the first random value and the second random value can be updated by the system clock input that serves as the random number clock signal. This is a means of updating. The CPU 103 that executes the random number update process P_RANDOM shown in FIG. 10-12 sets the third random number from among the random numbers MR1-2 for winning symbols and the random numbers MR2-1 for normal symbols. In this case, it becomes a second updating means that can update the third random number value by random number updating processing. Based on the start of power supply in the pachinko gaming machine 1, the CPU 103 that executes the main process P_MAIN for game control shown in FIG. 4 executes the power supply start corresponding process P_POWER_ON shown in FIG. 10-7 in step S1. When executed, the value stored in the function setting register area is set by the function setting register store instruction in step AKS13. At this time, by setting the stored value of the maximum value setting register provided corresponding to the 16-bit random number circuit 104A or the 8-bit random number circuit 104B, the 16-bit random number circuit 104A or the 8-bit random number circuit 104B can be set. It is possible to execute maximum value setting processing for setting the maximum random number value of the random numbers updated by. Then, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B, which serve as the first updating means, start updating the first random number when the maximum random number value of the first random number value is set in the maximum value setting process. After that, updating of the second random number is started because the maximum random number value of the second random number is set. The CPU 103 that executes the main process P_MAIN for game control shown in FIG. Correspondingly, the game control timer interrupt process P_PCT shown in FIG. 5 can be executed, and in step S56, the random number update process P_RANDOM is executed to start updating the third random number value. In this way, the CPU 103 that executes the random number update process P_RANDOM serving as the second update means can update the third random number value after executing the maximum value setting process in the power supply start corresponding process P_POWER_ON. Uncertainty is increased by starting to update a random number highly related to gaming value, such as the random number MR1-1 for symbol determination, thereby making it possible to update the random number appropriately.

In the bit data RAP of the RWM access protection register shown in FIG. 10-9(B), bit data RAM0 with bit number “0” has an initial value corresponding to the start of power supply to the pachinko gaming machine 1. It is set to 0 [B]. As a result, access to the RAM 102 serving as RWM is prohibited in response to the fact that the stored value of the RWM access protect register, which is a specific storage area, is set to the first stored value. The CPU 103 that has executed the power supply start corresponding process P_POWER_ON shown in FIG. Store the permission output value in . In this way, after setting a stored value in the function setting register area, which is a storage area related to functions, it is possible to set a second stored value that allows access to the RAM 102 as a storage means in the RWM access protection register, which is a specific storage area. It is. Then, as the next process after setting the second stored value, by executing the RWM check process P_RWM_CHK in step S2 in the main process P_MAIN process for game control shown in FIG. Based on the content, it is possible to execute a confirmation process to confirm whether or not the control state can be restored. In this way, the contents stored in the storage means are not changed unnecessarily, the confirmation process can be executed reliably, and the random value can be updated appropriately.

The CPU 103 that executes the power-off process P_POWER_OFF shown in FIG. Correspondingly, it is possible to perform a stop storage process in which checksum data serving as recovery information for restoring the control state is stored in a storage area such as a checksum buffer of the RAM 102, which is a storage means. After such a stop storage process is executed, the clear data set in the output value data in step AKS41 is stored in the RWM access protect register in step AKS42, thereby setting the first stored value in a specific storage area. It is possible to execute storage processing when stopped. After the stop storage process is executed, a loop process of steps AKS48 and AKS49 causes a transition to a standby state in which no game control is executed. In response to the restoration of power supply during this standby state, if the power confirmation signal input bit is not "0" in step AKS49, the vector table address at power-off recovery is set in the stack pointer in step AKS50. Then, by terminating the power-off process P_POWER_OFF using an interrupt return command, the main process P_MAIN for game control shown in FIG. 4 is executed from the beginning as a startup process based on the startup of the pachinko game machine 1. enable. This prevents unstable operation when power supply is restored, and allows appropriate updating of random values.

In the address map in the gaming control microcomputer 100 shown in FIG. The function control register area of the built-in registers to which addresses FF00[H] to FFFF[H] are assigned is the first area for setting functions using various circuits included in the game control microcomputer 100. This is the second area for functional control using . Among these, the RWM access protect register at address FF00[H] is a specific storage area in which a stored value indicating whether or not to permit access to the RAM 102, which is RWM, can be set. Based on the start of power supply in the pachinko gaming machine 1, the CPU 103 that executes the main process P_MAIN for game control shown in FIG. 4 executes the power supply start corresponding process P_POWER_ON shown in FIG. 10-7 in step S1. When executed, steps AKS5 to AKS7 make it possible to execute control storage processing for setting the storage value of the function control register area, which is the second area. After such a control storage process is executed, a setting storage process for setting the stored value of the function setting register area, which is the first area, can be executed in steps AKS11 to AKS13. After such setting storage processing is executed, in step AKS14, a stored value that permits access to the RAM 102, which is a storage means, can be set in the RWM access protection register as a specific storage area. In this way, it is possible to prevent the contents stored in the storage means from changing unnecessarily and to update the random value appropriately.

(Problem solving means and effects of characteristic part 01AK)
(1-1) A gaming machine that can be controlled to an advantageous state advantageous to the player,
an updating means capable of updating random values;
a first display means capable of variably displaying special identification information;
a second display means capable of variably displaying ordinary identification information,
The type of advantageous state is determined in accordance with the display result by the first display means,
In response to the display result by the second display means, a change mode is determined to change the starting area to a guiding state through which the game medium can easily pass;
The update method is
A first random number value used to determine a display result by the first display means and a second random number value used to determine a display result by the second display means can be updated in each update range by a common update process,
The first random value and the second random value can be updated using a common internal storage means,
The first random value is such that the total number of random values included in the update range is not a prime number,
For the second random number, the total number of random numbers included in the update range is a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, the CPU 103 that executes the random number updating process P_RANDOM. The special identification information may be, for example, a special symbol. The first display means may be, for example, the first special symbol display device 4A and the second special symbol display device 4B. The normal identification information may be, for example, a normal pattern. The second display means may be, for example, the normal symbol display 20 or the like. The display result by the first display means may be, for example, a confirmed special symbol that is a display result of a special symbol. The display result by the second display means may be, for example, a confirmed normal symbol that is a display result of a normal symbol. The type of advantageous state may be, for example, the maximum number of times the big winning opening is opened. The mode of change may be, for example, the normal electric accessory opening time. The first random number may be, for example, a random number MR1-2. The second random number may be, for example, a random number MR2-1. The update process may be, for example, initial value change random number update process P_RANCP. The internal storage means may be, for example, the HL register, B register, DE register, etc. of the CPU 103. The total number of first random numbers may be, for example, if the size of random numbers MR1-2 is "65536". The total number of second random numbers may be, for example, if the size of random number MR2-1 is "199".
According to such a configuration, the common update process prevents an increase in program capacity, and since the total number of random values included in the update range is a prime number, synchronization between the first random value and the second random value is prevented. This makes it possible to update appropriate random values.

(1-2) When executing the update process, the update means updates the random number to be updated and changes the initial random number after setting the random number to be updated, the maximum random number value, and the initial random number value. and may be executable.
Here, the settings for executing the update process may be, for example, steps AKS61 to AKS63 and AKS65 to AKS67. The update of the random number value to be updated and the change of the random number initial value may be performed by, for example, the part that executes the initial value change random number update process P_RANCP in steps AKS64 and AKS68.
In such a configuration, it is possible to update the random value appropriately by updating the set random value to be updated.

(1-3) The updating means may update the second random number value after updating the first random number value by specific update processing.
Here, the specific update process may be, for example, random number update process P_RANDOM.
In such a configuration, by updating the first random value used to determine the display result that attracts a high degree of player attention before the second random value, occurrence of a malfunction is suppressed, and an appropriate random value is updated. can be updated.

(1-4) The updating means updates the first random number value and the second random number value by calling a common update process corresponding to the first random number value and the second random number value by a specific update process, The initial values of the first random number value and the second random number value may be changeable.
Here, the common update process may be, for example, the initial value change random number update process P_RANCP of steps AKS64 and AKS68 in the random number update process P_RANDOM.
In such a configuration, the common update process prevents an increase in program capacity, stably updates the first random number value and the second random number value, and makes it possible to update the appropriate random number value.

(1-5) The updating means may be capable of updating the first random number value and the second random number value using a common internal storage means by specific update processing.
For example, in the random number update process P_RANDOM, the HL register is set in steps AKS61 and AKS65, the B register is set in steps AKS62 and AKS66, the DE register is set in steps AKS63 and AKS67, and then the initial value is changed in steps AKS64 and AKS68. It may be sufficient to execute the random number update process P_RANCP.
In such a configuration, it is possible to stably update the first random number value and the second random number value using a common internal storage means, thereby making it possible to update the appropriate random number value.

(1-6) When the reference destination information is stored in the internal storage means by the specific update process before the common update process, the update means becomes common in correspondence with the first random value and the second random value. It may be possible to set different reference destination information in the internal storage means using a command.
Here, the internal storage means may be, for example, an HL register, a B register, a DE register, or the like. The common command may be a transfer command such as an LD command or an LDQ command. The different reference destination information is, for example, the address F081 [H] of the random number counter for winning symbols, the address F052 [H] of the random number counter for regular symbols, the address F050 [H] of the random number initial value data buffer for winning symbols, and the normal number counter. It may be the address F053[H] of the random number initial value data buffer for symbols per symbol.
In such a configuration, by making it possible to update the first random value and the second random value using a common instruction, the first random value and the second random value can be stably updated and appropriate. Random values can be updated.

(1-7) When executing the update process, the updating means can change the initial random number value in response to the fact that the random number value to be updated matches the random number initial value after updating the random number value to be updated. be,
For example, in the initial value change random number update process P_RANCP, after the random number to be updated is updated in step AKS101, in response to the match with the value stored in the random number initial value data buffer in step AKS105, a new random number initial value is updated in step AKS108. It can be anything such as storing a value.
In such a configuration, by updating the random number value to be updated or changing the initial random number value, it is possible to update the random number value appropriately.

(1-8) When the updating means executes the updating process to update the random number value to be updated,
Comparing the random number to be updated with the maximum random number,
If the comparison result is less than the maximum random number value, add 1 to the random number to be updated;
If the comparison result is greater than or equal to the maximum random number value, a single comparison and addition instruction may be executed first, which includes changing the random number value to be updated to the minimum random number value.
Here, the comparison and addition instruction may be the part of step AKS101, for example.
In such a configuration, by first executing the comparison and addition instruction, it is possible to suppress the occurrence of defects and update the random value appropriately.

(1-9) The updating means may first execute the comparison and addition instruction both when updating the first random value and when updating the second random value.
For example, it may be the part of step AKS101 in the initial value change random number update process P_RANCP of steps AKS64 and AKS68.
In such a configuration, by first executing the comparison and addition instruction, it is possible to suppress the occurrence of defects in the first random value and the second random value, and to update the random value appropriately.

(1-10) When determining the display result by the first display means, when the first random number value is the minimum random number value, the display result is more advantageous than when the first random number value is other than the minimum random number value. not determined,
When determining the display result by the second display means, when the second random number value is the minimum random number value, the display result must not be determined to be more advantageous than when the second random number value is other than the minimum random number value. Good too.
Here, the display result that is not determined to be highly advantageous may be, for example, the example AKD01 of determining the number of openings of the big winning opening or the example AKD02 of determining the opening mode of the opening of the big winning opening.
In such a configuration, it is possible to appropriately update the random number value so as to prevent fraudulent acts due to malfunctions in the first random number value and the second random number value.

(1-11) The update method is
It is possible to perform an initial value update process that can update the initial random value used when changing the initial random number value,
After executing the comparison and addition instruction, comparing the updated random number value updated by the comparison and addition instruction with the random number initial value,
If the random number to be updated after updating does not match the initial random number value, store the random number to be updated after updating as the current random number,
If the random number to be updated after updating matches the initial random number value, the random number for initial value obtained by the initial value update process is stored as the current random number value, and also as the new initial random number value. good.
Here, the random number for initial value may be, for example, random number MR1-3 or random number MR2-2. The initial value update process may be, for example, initial value determination random number update process P_TFINIT. The comparison with the initial random number value may be performed, for example, at step AKS105. If the random number does not match the initial value, it is sufficient if the answer in step AKS105 is Yes, for example. If it matches the random number initial value, it may be the part of steps AKS106 to AKS108 when the result of step AKS105 is No, for example.
In such a configuration, by setting a new random number initial value, the uncertainty of the random value is increased, and by storing it as the current random number, it is possible to prevent an increase in data capacity and update the random value appropriately. becomes possible.

(1-12) The update method is
a first initial value update process of updating a first initial value random number used when changing the random number initial value in response to a case where the update target random number is a first random number;
an initial value including a second initial value update process of updating a second initial value random value used when changing the random number initial value in response to a case where the random number to be updated is a second random value; It may also be possible to execute update processing.
Here, the first initial value random number may be, for example, a random number MR1-3. The first initial value update process may be, for example, steps AKS81 and AKS82 in the initial value determination random number update process P_TFINIT. The second initial value random number may be, for example, a random number MR2-2. The second initial value update process may be, for example, steps AKS83 and AKS84 in the initial value determination random number update process P_TFINIT.
In such a configuration, by updating the first initial value random value and the second initial value random value, it is possible to update the random value appropriately.

(1-13) The updating means may update the random number value for the second initial value after updating the random number value for the first initial value by the initial value update process.
For example, in the initial value determining random number update process P_TFINIT, steps AKS83 and AKS84 may be executed after steps AKS81 and AKS82.
In such a configuration, by updating the random number for the first initial value, which has a higher priority, before the random number for the second initial value, which has a lower priority, it is possible to suppress the occurrence of problems and update the random number for the first initial value to an appropriate random value. can be updated.

(1-14) When executing the initial value update process, the update means, based on the settings regarding the random number value for the initial value to be updated and the maximum random number value for the initial value,
comparing the random number value for the initial value to be updated with the maximum random number value for the initial value;
If the comparison result is less than the maximum initial value random number, add 1 to the initial value random number to be updated;
If the comparison result is greater than or equal to the maximum random number value for initial values, a single comparison and addition instruction may be executed that includes changing the random number value for initial values to be updated to the minimum random number value.
Here, the comparison and addition instruction may be, for example, steps AKS82 and AKS84.
In such a configuration, by updating the random number value for the initial value to be updated using the comparison addition instruction, it is possible to suppress the occurrence of defects and update the random number value appropriately.

(1-15) The update method is
Random number update processing that can update random numbers to be updated;
An initial value random number update process capable of updating an initial value random number used when changing a random number initial value corresponding to an update target random number value,
The first process that can be executed in response to a timer interrupt due to the passage of a predetermined time includes a random number update process and an initial value random number update process,
The second process, which can be repeatedly executed until the first process is executed, may not include the random number update process, but may include the initial value random number update process.
Here, the random number to be updated may be, for example, random number MR1-2 or random number MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The initial value random number may be, for example, random number MR1-3 or random number MR2-2. The initial value random number update process may be, for example, the initial value determination random number update process P_TFINIT. The first process may be, for example, a timer interrupt process P_PCT for game control. The second process may be, for example, steps S8 to S10 in the main process P_MAIN for game control.
In such a configuration, the uncertainty of the initial value random number value is increased by the initial value random number update process, and it becomes possible to update the random number value appropriately.

(1-16) The update process is
Random number update processing that can update random numbers to be updated;
Initial value random number update processing capable of updating the initial value random number used when changing the random number initial value corresponding to the random number to be updated;
The random number update process and the initial value random number update process can be called and executed in the timer interrupt process that controls the progress of the game,
The initial value random number update process may be called and executed during a standby process that is repeated after a startup process that is executed based on the start of power supply.
Here, the random number to be updated may be, for example, random number MR1-2 or random number MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The random number for initial value may be, for example, random number MR1-3 or random number MR2-2. The initial value random number update process may be, for example, the initial value determination random number update process P_TFINIT. The timer interrupt process may be, for example, a timer interrupt process P_PCT for game control. The startup process may be, for example, steps S1 to S7 in the main process P_MAIN for game control. The standby process may be, for example, steps S8 to S10 in the main process P_MAIN for game control.
In such a configuration, the uncertainty of the initial value random number value is increased by the initial value random number update process, and it becomes possible to update the random number value appropriately.

(2-1) A gaming machine that can be controlled to an advantageous state advantageous to the player,
an updating means capable of updating random values;
A processing means capable of executing processing related to game control using the random value updated by the updating means,
The updating means is capable of updating a first random number value for determining whether to control to an advantageous state and a second random number value different from the first random number value,
The first random number is composed of a specific number of bytes, and the total number of random numbers included in the update range is a specific number,
The second random number is a predetermined number consisting of a specific number of bytes, and the total number of random numbers included in the update range is smaller than the specific number,
The update speed of the first random value may be faster than that of the second random value.
Here, the advantageous state may be, for example, a jackpot game state. The gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process processing P_TPROC. The first random number may be, for example, a random number MR1-1. The second random number may be, for example, a random number MR3-2. The specific number of bytes may be, for example, 2 bytes. The specific number may be, for example, "65536" which is the size of the random number MR1-1. The predetermined number may be, for example, "65519" which is the size of the random number MR3-2. The update speed may be fast if, for example, the update speed of the random number MR1-1 in the random value comparison example AKA23 is 15000 [times/ms] and the update speed of the random number MR3-2 is 469 [times/ms].
In such a configuration, it is possible to appropriately update the random number value so that intentional control of the advantageous state becomes difficult due to the fast update speed of the first random number value regarding the advantageous state.

(2-2) A gaming machine capable of playing games,
an updating means capable of updating random values;
A processing means capable of executing processing related to game control using the random value updated by the updating means,
The updating means is capable of updating the first random value and a second random value different from the first random value,
The first random value has an update speed of the first speed,
The second random value is a second speed at which the update speed is an integer multiple of the first speed,
The first random number value and the second random number value may have different total numbers of random numbers included in each update range, and the total number of random numbers included in both update ranges may be a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process processing P_TPROC. The first random number may be, for example, a random number MR3-2. The second random number may be, for example, random numbers MR3-3, MR3-4, etc. The first speed may be, for example, 469 times/ms. The second speed may be, for example, 938 times/ms. The total number of random numbers may be, for example, "65519" which is the size of random number MR3-2, "241" which is the size of random number MR3-3, "251" which is the size of random number MR3-4, etc. .
In such a configuration, even if the update speed is an integral multiple, the total number of random values included in the update range is a different prime number, thereby suppressing the occurrence of synchronization between the first random value and the second random value, It becomes possible to update appropriate random values.

(2-3) A gaming machine capable of playing games,
an updating means capable of updating random values;
A processing means capable of executing processing related to game control using the random value updated by the updating means,
The updating means is capable of updating a first random value, a second random value different from the first random value, and a third random value different from the first random value and the second random value,
The processing means can extract the first random number, the second random number, and the third random number by satisfying a common extraction condition,
The first random value has an update speed of the first speed,
The second random value and the third random value are a second rate at which the update rate is an integral multiple of the first rate,
The first random number, the second random number, and the third random number may have different total numbers of random numbers included in each update range, and the total number of random numbers included in each update range may be a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process processing P_TPROC. The first random number may be, for example, a random number MR3-2. The second random number may be, for example, a random number MR3-3. The third random number may be, for example, a random number MR3-4. The first speed may be, for example, 469 times/ms. The second speed may be, for example, 938 times/ms. The total number of random numbers may be, for example, "65519" which is the size of random number MR3-2, "241" which is the size of random number MR3-3, "251" which is the size of random number MR3-4, etc. .
In such a configuration, even if the update speed is an integral multiple, the total number of random values included in the update range is a different prime number, so the synchronization of the first random value, second random value, and third random value can occur. This makes it possible to update appropriate random values.

(2-4) A gaming machine capable of playing games,
an updating means capable of updating random values;
A processing means capable of executing processing related to game control using the random value updated by the updating means,
The update method is
a first updating means capable of updating the first random number value and the second random number value in their respective update ranges by random number update processing;
a second updating means capable of updating the third random number value and the fourth random number value in their respective update ranges using a random number clock signal;
At least one of the first random value and the second random value is such that the total number of random values included in the update range is a prime number,
For at least one of the third random number and the fourth random number, the total number of random numbers included in the update range may be a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, the 16-bit random number circuit 104A, the 8-bit random number circuit 104B, or the CPU 103 that executes the random number updating process P_RANDOM. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC or the normal symbol process P_FPROC. The first random number may be, for example, a random number MR2-1. The second random number may be, for example, a random number MR1-2. The random number update process may be, for example, random number update process P_RANDOM. The third random number may be, for example, a random number MR3-3. The fourth random number may be, for example, a random number MR3-4. The random number clock signal may be, for example, a system clock. The total number of random numbers included in the update range is, for example, "199" which is the size of random number MR2-1, "200" which is the size of random number MR1-2, and "241" which is the size of random number MR3-3. , "251" which is the size of the random number MR3-4.
In such a configuration, the first updating means and the second updating means use different updating methods, and even if the updating methods are the same, at least one of the random numbers is a prime number because the total number of random numbers included in the update range is a prime number. It is possible to suppress the occurrence of synchronization and update appropriate random values.

(3-1) A gaming machine capable of playing games,
an updating means capable of updating random values;
A processing means capable of executing processing related to game control using the random value updated by the updating means;
storage means including a storage area for the functions of the updating means and the processing means;
The processing means performs a maximum value setting process for setting a random number maximum value of the random values updated by the updating means when setting a stored value in a storage area related to a function by a startup process executed based on the start of power supply. is executable,
The update method is
a first updating means capable of updating a first random value composed of a specific number of bytes;
a second updating means capable of updating a second random number composed of a predetermined number of bytes smaller than the specific number of bytes;
When executing the maximum value setting process, the processing means may set the maximum random number value of the second random number value after setting the maximum random number value of the first random number value.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, the random number circuit 104. The processing means may be, for example, the CPU 103 that executes the special symbol process processing P_TPROC. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The startup process may be, for example, the main process P_MAIN for game control. The maximum value setting process may be, for example, steps AKS11 to AKS13 in the power supply start support process P_POWER_ON. The specific number of bytes may be, for example, 2 bytes. The first random number may be, for example, a random number MR3-2. The first updating means may be, for example, a 16-bit random number circuit 104A. The predetermined number of bytes may be, for example, 1 byte. The second random number may be, for example, random numbers MR3-3, MR3-4, etc. The second updating means may be, for example, an 8-bit random number circuit 104B. Setting the maximum random number value of the first random number value and setting the maximum random number value of the second random number value may be performed by executing step AKS13 using the function setting register storage value table AKT01.
In such a configuration, the first random value and the second random value are stably updated by setting the first random value of a specific number of bytes and then setting the second random value of a predetermined number of bytes. It becomes possible to update appropriate random values.

(3-2) The updating means may start updating in order from the random number value to which the maximum random number value is set.
For example, using the function setting register storage value table AKT01, 16-bit random number circuit channel RL0 with channel number "0", 16-bit random number circuit channel RL2 with channel number "2", and 8-bit random numbers with channel numbers "1" to "3" Any portion may be used as long as the maximum value is set for the circuit channels RS1 to RS3.
In such a configuration, the uncertainty of the random value is increased depending on the timing at which updating of the random value is started, the processing load is reduced, and the random value can be updated appropriately.

(3-3) A gaming machine capable of playing games,
an updating means capable of updating random values;
A processing means capable of executing processing related to game control using the random value updated by the updating means;
storage means including a storage area for the functions of the updating means and the processing means;
The processing means performs a maximum value setting process for setting a random number maximum value of the random values updated by the updating means when setting a stored value in a storage area related to a function by a startup process executed based on the start of power supply. is executable,
The update method is
a first updating means capable of updating the first random number value and the second random number value using a random number clock signal;
a second updating means capable of updating the third random number value by random number updating processing;
In the maximum value setting process executed by the processing means, the first updating means updates the random number maximum value of the second random value value after starting updating of the first random value value due to the setting of the random number maximum value of the first random value value. is set, starts updating the second random value,
The second updating means may start updating the third random number value after the processing means executes the maximum value setting process.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, the random number circuit 104 or the CPU 103 that executes the random number updating process P_RANDOM. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC or the normal symbol process P_FPROC. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The startup process may be, for example, the main process P_MAIN for game control. The maximum value setting process may be, for example, steps AKS11 to AKS13 in the power supply start support process P_POWER_ON. The first random number may be, for example, random numbers MR1-1, MR3-2, etc. The second random number may be, for example, random numbers MR3-3, MR3-4, etc. The first updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The third random number may be, for example, random numbers MR1-2, MR2-1, etc. The random number update process may be, for example, random number update process P_RANDOM. The second updating means may be, for example, the CPU 103 that executes the random number updating process P_RANDOM in step S56. To start updating the first random number value, for example, use the function setting register storage value table AKT01 to set the maximum value to the 16-bit random number circuit channel RL0 with channel number "0" and the 16-bit random number circuit channel RL2 with channel number "2". It is sufficient if it is a part to be set. To start updating the second random value, for example, use the function setting register storage value table AKT01 to set the maximum value to the 8-bit random number circuit channels RS1 to RS3 of channel numbers "1" to "3". good. The update of the third random number value may be started by executing the random number update process P_RANDOM in step S56 in the game control timer interrupt process P_PCT after the power supply start corresponding process P_POWER_ON in step S1 is executed, for example. .
In such a configuration, uncertainty is increased by starting to update the random number MR1-1, etc., which is highly related to the gaming value, and it becomes possible to update the random number appropriately.

(4-1) Storage means capable of storing information regarding game control;
storage means including a storage area for the functions of the updating means and the processing means;
A specific storage area of the function-related storage areas can be set to a first storage value that prohibits access to the storage means in response to the start of power supply;
The processing means are
After setting the stored value in the storage area related to the function, a second stored value that allows access to the storage means can be set in the specific storage area,
As the next process after setting the second stored value in the specific storage area, it may be possible to perform a confirmation process to confirm whether or not the control state can be restored based on the contents stored in the storage means.
Here, the storage means may be, for example, the RAM 102 or the like. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The specific storage area may be, for example, an RWM access protection register. The first stored value may be, for example, 00[H]. The second stored value may be, for example, 01[H]. The second storage value can be set in the specific storage area by, for example, executing step AKS14 in the power supply start support process P_POWER_ON. The confirmation process may be, for example, the RWM check process P_RWM_CHK in step S2.
In such a configuration, the contents stored in the storage means are not changed unnecessarily, the confirmation process can be executed reliably, and the random value can be updated appropriately.

(4-2) The processing means is
In response to a power supply stop, it is possible to perform a stop storage process in which recovery information for restoring the control state is stored in the storage means;
After the stop storage process is executed, a stop storage process for setting the first storage value in a specific storage area can be executed;
After the stop storage process is executed, the game machine is moved to a standby state in which no game control is executed, and in response to the power supply being restored while in the standby state, the game machine is started at the beginning of the start-up process. It may be executable from
The recovery information may be, for example, checksum data. The stop storage process may be, for example, the checksum calculation process in step AKS39 or the part in step AKS40 in the power-off process P_POWER_OFF. The stop storage process may be, for example, steps AKS41 and AKS42 in the power-off process P_POWER_OFF. Shifting to the standby state may be accomplished by, for example, executing steps AKS48 and AKS49 in the power-off process P_POWER_OFF. What can be executed from the beginning of the startup process may be, for example, executing the RET command after executing step AKS50 in the power-off process P_POWER_OFF.
In such a configuration, unstable operation can be prevented when power supply is restored, and an appropriate random value can be updated.

(4-3) Storage means capable of storing information regarding game control;
storage means including a storage area for the functions of the updating means and the processing means;
The storage means is a storage area for functions,
A first area for setting functions;
a second area for functional control;
The second area includes a specific storage area in which a storage value indicating whether or not access to the storage means is permitted can be set;
In the startup process executed based on the start of power supply, the processing means includes:
It is possible to execute a control storage process that sets a storage value in the second area,
After the control storage process is executed, a setting storage process for setting a stored value in the first area can be executed,
After the setting storage process is executed, it may be possible to set a storage value that permits access to the storage means in a specific storage area.
Here, the storage means may be, for example, the RAM 102 or the like. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The first area may be, for example, the function setting register area of setting example AKA01. The second area may be, for example, the function control register area of setting example AKA02. The specific storage area may be, for example, an RWM access protection register. The startup process may be, for example, the main process P_MAIN for game control. The control storage process may be, for example, steps AKS5 to AKS7 in the power supply start support process P_POWER_ON. The setting storage process may be, for example, steps AKS11 to AKS13 in the power supply start support process P_POWER_ON. The storage value can be set in the specific storage area by, for example, executing step AKS14 in the power supply start corresponding process P_POWER_ON.
In such a configuration, it is possible to prevent the contents stored in the storage means from being changed unnecessarily, and to update the random number value appropriately.

(SKY2021-664) A gaming machine that can be controlled to an advantageous state advantageous to the player,
an updating means capable of updating random values;
The random value includes a first random value and a second random value different from the first random value,
The determination result of the first random number has a greater influence on the ball payout rate than the determination result of the second random number,
The updating means includes:
The first random value and the second random value can be updated in their respective update ranges by a common update process,
After updating the first random value, updating the second random value,
Before updating the first random number value by an update process, setting reference information for the first random number value in an internal storage means using a specific instruction,
Before updating the second random number value by the update process, reference information for the second random number value is set in the internal enabling means using the specific command.
Here, the ball output rate is a rate calculated using the number of game balls hit into the gaming machine as the denominator and the game balls paid out to the player as the numerator. It is determined as a design value for each gaming machine. If it exceeds 100%, it indicates that the number of game balls paid out to the player is greater than the number of game balls hit into the game machine.
Here, the first random number corresponds to the random number for winning symbols (MR1-2), and the second random number corresponds to the random number for normal symbols (MR2-1). The random number for the winning symbol is a random number used to determine the number of jackpot rounds that is the trigger for acquiring game balls (a random number for determining the display result of the special symbol that is linked to the number of jackpot rounds) (Fig. 10-24(C)). The random number for symbols per normal symbol is a random number used to determine the opening time of the normal electric accessory (a random number for determining the display result of the normal symbol associated with the opening time of the ordinary electric accessory) (Fig. 10-37(D)). The random numbers for winning symbols are used to determine the number of jackpot rounds, and the random numbers for regular symbols are used to determine the opening time of normal electric accessories. has a large influence on the number of game balls acquired. The number of game balls that can be won by entering the ball into the grand prize opening is 15 balls, while the number of game balls that can be obtained by entering the ball into the normal electric accessory is one ball.
In such a configuration, the first random number has a greater influence on the player's ball output, so by performing the processing first, the random number may become constant due to a malfunction (it may not be updated). Stable updating can be achieved by preventing as much as possible the occurrence of unbalanced times and updating random numbers using a common command.

(SKY2021-665) A gaming machine that can be controlled to an advantageous state advantageous to the player,
an updating means capable of updating random values;
The random value includes a first random value and a second random value different from the first random value,
The updating means includes:
The first random value and the second random value can be updated in their respective update ranges by a common update process,
Comparing the random number with the maximum random number, adding 1 to the random number if the comparison result is less than the maximum random number, and adding 1 to the random number if the comparison result is greater than or equal to the maximum random number, changing the random number to the minimum random number. A single comparison and addition instruction including changing to is the first process of the update process on the first random value and the update process on the second random value,
When the first random number value is the minimum random number value, the decision result is not more advantageous than when the first random number value is other than the minimum random number value,
When the second random number value is the minimum random number value, the decision result is not more advantageous than when the second random number value is other than the minimum random number value.
Here, the display result that is not determined to be highly advantageous may be, for example, the example AKD01 of determining the number of openings of the big winning opening or the example AKD02 of determining the opening mode of the opening of the big winning opening. In addition, the normal electric accessory opening time in the normal electric accessory opening time determination example in Figure 10-37 (D) is uniformly 16 ms in the normal state (time saving operation specified value ×), and in the special condition (time saving operation specified value 〇). Although it is designed so that there is no advantage or disadvantage, such as 5000ms uniformly, the normal electric accessory opening time with the specified symbol value "00" per normal symbol in the example of determining the opening time of the ordinary electric accessory shown in Figure 10-37 (D) are set to 16 ms and 5000 ms, but may be set to 10 ms and 3000 ms to make them relatively disadvantageous compared to other open times. By doing so, the number of times the big winning hole is opened is the result of the first random number (random number for winning symbols (MR1-2)), and the number of times the big winning hole is opened is the result of the first random number (random number for normal symbols (MR2-1)). If both of the resulting normal electric accessory opening times are the minimum random number value (00H), an advantageous decision result (10 times for the number of openings for the big winning hole, and 10 times for the normal electric accessory opening time) 5000ms).
In such a configuration, by executing the compare and add instruction first, it is possible to suppress the occurrence of defects and update the random value appropriately. If a defect occurs, the random value can be updated to the minimum value. Although the random numbers will be slightly biased, in that case, the design does not result in a highly advantageous decision result, so it is possible to prevent problems from being caused, and as a result, the appropriate random numbers can be used. can be updated.

(SKY2021-708) A gaming machine that can be controlled to an advantageous state advantageous to the player,
an updating means capable of updating random values;
The random value includes a first random value used for processing regarding whether to control to the advantageous state, and a second random value different from the first random value,
The first random number is composed of a specific number of bytes, and the total number of random numbers included in the update range is a specific number,
The second random number is a predetermined number that is composed of the specific number of bytes, and the total number of random numbers included in the update range is smaller than the specific number,
The update speed of the first random number value by the update means is faster than the update speed of the second random number value by the update means.
Here, the advantageous state may be, for example, a jackpot game state. The gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process processing P_TPROC. The first random number may be, for example, a random number MR1-1. The second random number may be, for example, a random number MR3-2. The specific number of bytes may be, for example, 2 bytes. The specific number may be, for example, "65536" which is the size of the random number MR1-1. The predetermined number may be, for example, "65519" which is the size of the random number MR3-2. The update speed may be fast if, for example, the update speed of the random number MR1-1 in the random value comparison example AKA23 is 15000 [times/ms] and the update speed of the random number MR3-2 is 469 [times/ms].
In such a configuration, it is possible to appropriately update the random number value so that intentional control of the advantageous state becomes difficult due to the fast update speed of the first random number value regarding the advantageous state.

(SKY2021-709) A gaming machine that can be controlled to an advantageous state advantageous to the player,
an updating means capable of updating random values;
The random value includes a first random value and a second random value different from the first random value,
The first random value has an update speed at a first speed,
The second random value is a second speed at which the update speed is an integral multiple of the first speed,
The first random value and the second random value are random values obtained at the same opportunity,
The first random value and the second random value differ in the total number of random values included in their respective update ranges,
The first random number is such that the total number of random numbers included in the update range is a prime number,
In the second random number, the total number of random numbers included in the update range is a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process processing P_TPROC. The first random number may be, for example, a random number MR3-2. The second random number may be, for example, random numbers MR3-3, MR3-4, etc. The first speed may be, for example, 469 times/ms. The second speed may be, for example, 938 times/ms. The total number of random numbers may be, for example, "65519" which is the size of random number MR3-2, "241" which is the size of random number MR3-3, "251" which is the size of random number MR3-4, etc. .
In such a configuration, even if the update speed is an integral multiple, the total number of random values included in the update range is a different prime number, thereby suppressing the occurrence of synchronization between the first random value and the second random value, It becomes possible to update appropriate random values.

(SKY2021-710) A gaming machine that can be controlled to an advantageous state advantageous to the player,
an updating means capable of updating random values;
The random value includes a first random value, a second random value different from the first random value, and a third random value different from the first random value and the second random value,
The first random value has an update speed at a first speed,
The second random value and the third random value are a second rate at which the update rate is an integral multiple of the first rate,
The first random value, the second random value, and the third random value are random values obtained at the same opportunity,
The first random number, the second random number, and the third random number have different total numbers of random numbers included in their respective update ranges,
The first random number is such that the total number of random numbers included in the update range is a prime number,
The second random number is such that the total number of random numbers included in the update range is a prime number,
In the third random number, the total number of random numbers included in the update range is a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process processing P_TPROC. The first random number may be, for example, a random number MR3-2. The second random number may be, for example, a random number MR3-3. The third random number may be, for example, a random number MR3-4. The first speed may be, for example, 469 times/ms. The second speed may be, for example, 938 times/ms. The total number of random numbers may be, for example, "65519" which is the size of random number MR3-2, "241" which is the size of random number MR3-3, "251" which is the size of random number MR3-4, etc. .
In such a configuration, even if the update speed is an integral multiple, the total number of random values included in the update range is a different prime number, so the synchronization of the first random value, second random value, and third random value can occur. This makes it possible to update appropriate random values.

(SKY2021-711) A gaming machine that can be controlled to an advantageous state advantageous to the player,
a first updating means capable of updating the first random number value and the second random number value in their respective update ranges by random number update processing;
a second updating means capable of updating the third random number value and the fourth random number value in their respective update ranges using a random number clock signal;
At least one of the first random value and the second random value is such that the total number of random values included in the update range is a prime number,
For at least one of the third random number and the fourth random number, the total number of random numbers included in the update range is a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, the 16-bit random number circuit 104A, the 8-bit random number circuit 104B, or the CPU 103 that executes the random number updating process P_RANDOM. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC or the normal symbol process P_FPROC. The first random number may be, for example, a random number MR2-1. The second random number may be, for example, a random number MR1-2. The random number update process may be, for example, random number update process P_RANDOM. The third random number may be, for example, a random number MR3-3. The fourth random number may be, for example, a random number MR3-4. The random number clock signal may be, for example, a system clock. The total number of random numbers included in the update range is, for example, "199" which is the size of random number MR2-1, "200" which is the size of random number MR1-2, and "241" which is the size of random number MR3-3. ,
Any value such as "251", which is the size of the random number MR3-4, may be used.
In such a configuration, the first updating means and the second updating means use different updating methods, and even if the updating methods are the same, at least one of the random numbers is a prime number because the total number of random numbers included in the update range is a prime number. It is possible to suppress the occurrence of synchronization and update appropriate random values.

(SKY2021-712) A gaming machine that can play games,
a game control means for controlling the game;
a first updating means capable of updating the first random number value and the second random number value using a random number clock signal;
a second updating means capable of updating the third random number value by random number updating processing;
The game control means sets a maximum random number value of the first random number value and the second random number value when setting a stored value in the storage area by a start-up process executed based on the start of power supply. It is possible to execute value setting processing,
In the maximum value setting process, the first updating means updates the random number maximum value of the second random number value after starting updating of the first random number value due to the setting of the random number maximum value of the first random number value. is set, it is possible to start updating the second random value,
The second updating means can start updating the third random number value after updating the first random number value and updating the second random number value are started.
Here, the gaming machine may be, for example, the pachinko gaming machine 1. The updating means may be, for example, the random number circuit 104 or the CPU 103 that executes the random number updating process P_RANDOM. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC or the normal symbol process P_FPROC. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The startup process may be, for example, the main process P_MAIN for game control. The maximum value setting process may be, for example, steps AKS11 to AKS13 in the power supply start support process P_POWER_ON. The first random number may be, for example, random numbers MR1-1, MR3-2, etc. The second random number may be, for example, random numbers MR3-3, MR3-4, etc. The first updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The third random number may be, for example, random numbers MR1-2, MR2-1, etc. The random number update process may be, for example, random number update process P_RANDOM. The second updating means may be, for example, the CPU 103 that executes the random number updating process P_RANDOM in step S56. To start updating the first random number value, for example, use the function setting register storage value table AKT01 to set the maximum value to the 16-bit random number circuit channel RL0 with channel number "0" and the 16-bit random number circuit channel RL2 with channel number "2". It is sufficient if it is a part to be set. To start updating the second random value, for example, use the function setting register storage value table AKT01 to set the maximum value to the 8-bit random number circuit channels RS1 to RS3 of channel numbers "1" to "3". good. The update of the third random number value may be started by executing the random number update process P_RANDOM in step S56 in the game control timer interrupt process P_PCT after the power supply start corresponding process P_POWER_ON in step S1 is executed, for example. .
In such a configuration, uncertainty is increased by starting to update the random number MR1-1, etc., which is highly related to the gaming value, and it becomes possible to update the random number appropriately.

(SKY2021-713) A gaming machine that can play games,
a game control means for controlling the game;
a storage means capable of storing information regarding game control;
A storage means including a storage area related to the function of controlling the game,
The storage means, as a storage area regarding functions,
a first area for setting functions related to game control;
a second area for functional control related to game control;
The second area includes a specific storage area in which a storage value indicating whether or not access to the storage means is permitted can be set;
In the startup process executed based on the start of power supply, the game control means includes:
control storage processing for setting a storage value in the second area;
After the control storage process is executed, a setting storage process for setting a stored value in the first area can be executed,
After the setting storage process is executed, a storage value that permits access to the storage means can be set in the specific storage area.
Here, the storage means may be, for example, the RAM 102 or the like. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The first area may be, for example, the function setting register area of setting example AKA01. The second area may be, for example, the function control register area of setting example AKA02. The specific storage area may be, for example, an RWM access protection register. The startup process may be, for example, the main process P_MAIN for game control. The control storage process may be, for example, steps AKS5 to AKS7 in the power supply start support process P_POWER_ON. The setting storage process may be, for example, steps AKS11 to AKS13 in the power supply start support process P_POWER_ON. The storage value can be set in the specific storage area by, for example, executing step AKS14 in the power supply start corresponding process P_POWER_ON.
In such a configuration, it is possible to prevent the contents stored in the storage means from being changed unnecessarily, and to update the random number value appropriately.

The various embodiments described above are not limited to pachinko gaming machines, but can also be applied to slot machines and the like.

1... Pachinko gaming machine 4A... First special symbol display device 4B... Second special symbol display device 11... Main board 12... Production control board 100... Game control microcomputer 101... ROM
102...RAM
103...CPU
104, 104A, 104B...Random number circuit

Claims (1)

A gaming machine capable of playing games,
a game control means for controlling the game;
a first updating means capable of updating the first random number value and the second random number value using a random number clock signal;
a second updating means capable of updating the third random number value by random number updating processing;
The game control means performs a first maximum value setting process for setting a random number maximum value of the first random number values when setting a stored value in the storage area by a start-up process executed based on the start of power supply. is executable, and is capable of executing a second maximum value setting process of setting a random number maximum value of the second random number value,
The first updating means starts updating the first random number value when the random number maximum value of the first random number values is set in the first maximum value setting process , and starts updating the first random number value in the second maximum value setting process. Starting to update the second random number by setting the maximum random number of the second random number,
The game control means executes the first maximum value setting process to start updating the first random value, and executes the first maximum value setting process to start updating the first random value. After that, execute the second maximum value setting process to start updating the second random value,
The second updating means can start updating the third random number value after the first random number value update and the second random number number update are started.
A gaming machine characterized by:

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