JP7381514B2 - Information communication system and information communication device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an information communication system and information communication apparatus that synchronizes a plurality of information communication apparatuses through communication.

As a general time synchronization method between a plurality of information communication devices, for example, IEEE1588 Precision Time Protocol (PTP) of Non-Patent Document 1 is known. In Non-Patent Document 1, a master device that has a reference time and a slave device that synchronizes with the time of the master device are defined, and time synchronization packets are periodically exchanged between the master device and the slave device. Correct the time of the slave device.

Specifically, the master device's transmission time and the slave device's reception time of a packet sent from the master device to the slave device, as well as the slave device's transmission time and the master device's reception time of the packet sent from the slave device to the master device. Using the time, the slave device estimates and corrects the time offset, which is the time difference between the master device and the slave device.

“IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems.”IEEE Standa rd 1588-2008.

In a PTP system, even if synchronization is established between a master device and a slave device, the synchronization state may transition from a synchronized state to an asynchronous state due to some factor, resulting in loss of synchronization. Examples of factors that cause synchronization to be lost include the following.
(a) The synchronization phase, which is the difference in time between the master device and the slave device, becomes excessive (b) The master device switches (c) It becomes impossible to receive synchronization information from the master device (d) The state of the master device and Settings change (e) An error occurs in the external interface or communication path that communicates synchronization information.

Here, even if the synchronization state with respect to the master device is lost, the subsystem that refers to the timing information for synchronization can maintain steady and stable operation, and the synchronization phase will be in a continuous state. , called synchronous continuity. Once the synchronized state has transitioned to the asynchronous state, synchronization continuity is not guaranteed, and resynchronization will occur discontinuously, even if the cause of the out-of-synchronization is resolved.

For example, when a subsystem that uses synchronized timing information, such as a timing information reference unit, is transmitting an audio signal, discontinuous resynchronization may cause problems such as noise in the audio or interruptions in the audio. This results in a decrease in operational quality.

However, if these factors are resolved within a predetermined period, there are cases in which the synchronization can be treated as being maintained within the range where subsystem operation quality does not deteriorate, even if the subsystem does not transition to an asynchronous state.

Therefore, there is a need for a system that can maintain continuity in synchronization, achieve seamless synchronization between devices with the same clock performance, and allow subsystems that refer to synchronized timing information to operate continuously. ing.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an information communication system and an information communication device that can maintain synchronization continuity.

The present invention is an information communication system in which a plurality of information communication devices communicate information as a master device or a slave device, wherein the information includes synchronization information for synchronizing time between the master device and the slave device. a synchronization control unit that controls the synchronization phase between the master device and the slave device based on the synchronization information to bring them into a synchronized state; and timing information that indicates the synchronized timing output from the synchronization control unit. , a timing information reference unit that performs processing in synchronization with the timing information, and a timing information reference unit that performs processing in synchronization with the timing information; and when a factor that causes synchronization to be lost occurs, while the timing information reference unit performs processing in synchronization with the timing information, the timing information reference unit performs processing in synchronization with the timing information; and an inertial synchronization processing unit that suspends transition from the synchronized state to an asynchronous state in which synchronization is lost and causes the transition to an inertial synchronization state in which continuous synchronization is maintained.

An information communication device of the present invention is an information communication device that communicates information with other information communication devices as a master device or a slave device , and the information is used to synchronize time with other information communication devices. a synchronization control unit that includes synchronization information of the information communication device and sets the synchronization state by controlling a synchronization phase with another information communication device based on the synchronization information; and a timing indicating the synchronized timing output from the synchronization control unit. a timing information reference unit that refers to information and performs processing in synchronization with the timing information; and when a factor causing synchronization to be lost occurs, while the timing information reference unit performs processing in synchronization with the timing information; an inertial synchronization processing unit that suspends transition from the synchronized state to an asynchronous state in which synchronization is lost based on the synchronization phase and transitions to an inertial synchronization state that maintains continuous synchronization; and a synchronization phase change for synchronization. and a variation control section that limits the speed within a predetermined range and controls the acceleration of the synchronous phase change to vary according to a continuous function.

According to the present invention, it is possible to obtain an information communication system and an information communication device that can maintain synchronization continuity.

1 is a schematic diagram of an information communication system according to an embodiment. FIG. 1 is a functional block diagram of an information communication device that constitutes an information communication system according to an embodiment. It is a functional block diagram of a control part concerning an embodiment. FIG. 2 is a diagram showing a mode of communication for synchronizing the information communication system according to the embodiment. FIG. 2 is a state transition diagram including an inertial synchronization state and a quasi-synchronization state of the information communication system according to the embodiment. It is a flowchart which shows the procedure of the process at the time of transitioning from a semi-synchronous state to a synchronous state or an asynchronous state. FIG. 2 is a state transition diagram including an inertial synchronization state, a quasi-synchronization state, and a quasi-time distribution state of the information communication system according to the embodiment.

An information communication system and an information communication device according to embodiments will be described below with reference to the drawings.

[composition]
FIG. 1 is a schematic diagram of an information communication system 100 according to an embodiment. FIG. 2 is a functional block diagram of the information communication device 1 that constitutes the information communication system 100 according to the embodiment. FIG. 3 is a functional block diagram of the control unit 70 in FIG. 2.

The information communication system 100 according to this embodiment includes a plurality of information communication devices 1, and each information communication device 1 attempts to synchronize through information communication. The information communication device 1 that is a slave device is synchronized with the information communication device 1 that is a master device. A master device is an information communication device 1 that is a target to be synchronized with other information communication devices 1 in the information communication system 100. A slave device is an information communication device 1 that is synchronized with another information communication device 1 that is a master device in the information communication system 100. The slave device synchronizes with the master device through the transmission and reception of synchronization information, which is information for time synchronization from the master device to the slave device.

In the following, the information communication device 1 serving as a master device will be referred to as a master device 1a, and the information communication device 1 serving as a slave device will be referred to as a slave device 1b. It is sufficient that at least one slave device 1b exists for the master device 1a, but as shown in FIG. 1, the system may include a plurality of slave devices 1b.

The master device 1a and the slave device 1b communicate information by wire or wirelessly. Here, an example will be described in which the information communication device 1 achieves synchronization by transmitting and receiving information by wire.

Note that the information communication device 1 may be configured as a synchronous relay device having the functions of both the master device 1a and the slave device 1b. A synchronous relay device corresponds to a boundary clock in PTP. In this case, the network connected to the slave device 1b side is the upper synchronous network, and the network connected to the master device 1a side is the lower synchronous network. Timing information synchronized in the upper synchronous network on the slave device 1b side is transmitted to the lower synchronous network via the master device 1a.

(Information communication device)
The information communication device 1 includes a computer, and a processor including a CPU executes a program stored in advance in a storage unit such as an HDD or SSD, thereby performing necessary calculations in a control unit described below. .

Specifically, as shown in FIG. 2, the information communication device 1 includes a communication section 10, a clock 20, a timepiece 30, a storage section 50, an external interface 60, and a control section 70. For example, each section 10 to 70 is configured as hardware. Each part of the control unit 70 may be configured by software including programs and data. The design of which part of the control unit 70 is configured as software can be changed as appropriate.

The communication unit 10 transmits and receives information to and from other information communication devices 1 . The communication section 10 includes a transmitter 11, a receiver 12, a transmission timing detection section 13, and a reception timing detection section 14.

The transmitter 11 is a device that transmits input information. Specifically, the transmitter 11 disassembles the information into minimum constituent elements in time series and transmits the information to the outside. The information packet length (communication information amount) is arbitrary and may be different for each communication. For example, an input unit that converts an audio signal input from a microphone into audio data is connected to the information communication device 1, and audio data as information is input to the information communication device 1 from the input unit.

The receiver 12 is a device that receives information from the outside. Specifically, the receiver 12 reconstructs information received from outside the information communication device 1 and decomposed in time series into the minimum constituent elements, and outputs the reconstructed information to other components within the information communication device 1. For example, a playback unit such as an ear receiver or a speaker that outputs audio is connected to the information communication device 1, and the receiver 12 converts audio data into an audio signal and outputs it to the playback unit.

Here, the information communicated by the information communication device 1, that is, the information transmitted by the transmitter 11 and the information received by the receiver 12, includes synchronization information, timing information, and clock quality information, which will be described later.

The information communication device 1 has both a transmitter 11 and a receiver 12. Note that when performing wireless communication, the transmitter 11 and the receiver 12 may each be provided with an antenna, or a changeover switch may be provided to share one antenna.

The transmission timing detection unit 13 detects transmission timing. The transmission timing is the timing at which a predetermined information element position of the information transmitted by the transmitter 11 is transmitted to the outside of the information communication device 1. This transmission timing is detected based on the clock cycle of the clock 20 (in other words, the cycle of the pulses oscillated by the clock 20), which will be described later. That is, the transmission timing is expressed based on an integral multiple of the clock period.

Further, the transmission timing detection unit 13 outputs the detection result to other components within the information communication device 1. The information referred to here is, for example, a packet, and in this case, a predetermined information element position (hereinafter referred to as a predetermined information element position) is a bit position. For example, when information is decomposed into eight minimum constituent bits in time series, the transmission timing detection unit 13 detects the timing at which the third information element position (bit position) is transmitted, and The timing at which the information element position (bit position) is transmitted is output to the outside.

The reception timing detection unit 14 detects a reception timing at which a predetermined information element position of the information received by the receiver 12 is received from outside the information communication device 1 . This reception timing is detected based on the clock cycle of a clock 20, which will be described later. That is, the reception timing is expressed as an integral multiple of the clock cycle.

Further, the reception timing detection unit 14 outputs the detection result to other components within the information communication device 1. For example, when information is decomposed into bits, which are eight minimum constituent elements, in time series, the reception timing detection unit 14 detects the timing at which the third information element position (bit position) is received, and detects the timing at which the third information element position (bit position) is received. The timing at which the information element position (bit position) of is received is output to the outside.

Note that in the above examples of transmission timing and reception timing, the position of the same minimum component is detected in both cases, but for example, the transmission timing detection unit 13 of the information communication device 1 serving as a transmitter detects the position of the fifth element. , and the reception timing detection unit 14 of the information communication device 1 serving as a receiver detects the eighth element. )), it is not necessary to detect the same position.

Furthermore, the transmission timing may be detected a predetermined time later than the actual transmission timing. The reception timing may be detected a predetermined time later than the actual reception timing. These default values may be fixed within the communication unit, or may be set statically or dynamically from the outside. Note that "regulation" is synonymous with "preset" and "predetermined".

The clock 20 oscillates at a predetermined frequency and outputs a signal for giving operation timing to each part of the information communication device 1. As a result, each part within the information communication device 1 operates in synchronization with the clock 20. The entire information communication device 1 may be synchronized with a single clock 20 all at once, or each of a plurality of functional units may be independently synchronized with a plurality of clocks 20. This clock 20 has an inherent finite oscillation frequency tolerance. That is, the clock 20 has an error (for example, 20 ppm) with respect to a predetermined oscillation frequency (for example, 10 MHz). As the clock 20, for example, a fixed frequency oscillator such as a crystal resonator can be used.

Even if the nominal frequency of the clock 20 is the same between the master device 1a and the slave device 1b, there are actually individual differences. That is, there is a frequency deviation between the frequencies of the clocks 20 of the master device 1a and the slave device 1b. A frequency control signal may be inputted to the clock 20 from the outside, and the oscillation frequency may be variably controlled in response to the signal.

The clock 30 clocks using the output signal of the clock 20 as a source oscillation, and outputs the relative time from the start of the information communication device 1. The clock may be synchronized with the frequency-divided wave of the input clock signal. Further, the timing may be variable in advance width per clock, or the driving frequency of the clock may be intermittently controllable even if the clock frequency is fixed. Although the time is referred to in a specified unit, this specified value may be fixed within the clock, or may be set statically or dynamically from the outside. The relative time of the clock 30 is output, for example, in response to an external reference request.

The storage unit 50 is a recording medium such as an HDD, SSD, memory, or register. The storage unit 50 stores information necessary for the control unit 70 to perform calculations. It is preferable that the time of the clock 30 corresponding to the transmission timing or reception timing, which will be described later, be held in a recording medium that can be held by access only by hardware without using the CPU or software. This is because jitter caused by software can be eliminated. Note that it is important that the correspondence between the transmission/reception timing and the time is not affected by software jitter, and after the transmission/reception timing and the time are correlated, it may be stored in a low-speed access area.

The memory serving as the storage unit 50 inputs and outputs arbitrary information and stores the information in a designated storage area. Information is stored in response to an external storage request, and at that time the information to be stored and the storage area are input. Information is referenced by a reference request from the outside, and at that time, the storage area of the reference information is input, and the information of the storage area specified by the input is output. The storage of information may be maintained only while the device is in operation, or permanently, including when the device is stopped.

The external interface 60 (hereinafter also referred to as external I/F 60) connects the inside of the information communication device 1 and the outside, and inputs and outputs arbitrary information. The information includes transmitted and received data and the time of the clock 30. For example, the external I/F 60 acquires information to be stored in the storage unit 50 from the outside. Further, the external I/F 60 may acquire the time from the outside from the reception timing detected by the reception timing detection unit 14 to the transmission timing detected by the transmission timing detection unit 13, and use the time in the scheduler 77 described later. .

Note that the master device 1a has an external I/F 60 that transmits at least synchronization information. The slave device 1b has an external I/F 60 that receives at least synchronization information. However, the master device 1a may have an external I/F 60 that receives synchronization information, and the slave device 1b may have an external I/F 60 that transmits synchronization information. Further, the information communication device 1 may have a user interface such as a display device that can control and display internal states.

The control section 70 controls the overall operation of each section of the information communication device 1. FIG. 3 is a functional block diagram of the control unit 70. As shown in FIG. 3, the control unit 70 includes a main control unit 71, a transmission/reception data I/F 72, a communication control unit 73, a time recording unit 74, a scheduler 77, a frequency deviation calculation unit 78, a synchronization control unit 79, a timing information reference 80 , an inertial synchronization processing section 81 , a quasi-synchronization processing section 82 , a fluctuation control section 83 , a clock quality information output section 84 , a selection section 85 , a suppression section 86 , and a reselection section 87 .

The main control section 71 is linked with each section within the control section 70 and controls the operation of each section within the control section 70 . The transmission/reception data I/F 72 converts the information in the storage unit 50 and the external I/F 60 into a format that can be transmitted to the outside of the device. Further, the transmission/reception data I/F 72 converts information received from outside the apparatus into a format suitable for the control section 70 and the storage section 50 .

The communication control unit 73 controls the operation of the communication unit 10. The communication control section 73 inputs and outputs information to be transmitted and received between the communication section 10 and the control section 70 .

The time recording unit 74 associates the transmission timing of the predetermined information element position of the information transmitted by the transmission timing detection unit 13 with the time of the clock 30 at the transmission timing, and stores them in the memory of the storage unit 50. For example, the time recording unit 74 receives a signal from the transmission timing detection unit 13 indicating that the transmission timing of a predetermined information element position of the transmitted information has been detected, and refers to the time on the clock 30. , associate the relevant time with the transmission timing.

Further, the time recording unit 74 is also a time adding unit that adds a time corresponding to the transmission timing to the information to be transmitted. Similarly to the transmission, the time recording section 74 associates the reception timing of the predetermined element position of the information received by the reception timing detection section 14 with the time of the clock 30 at the reception timing and stores it in the memory. Further, the time recording unit 74 causes the transmitter 11 to include the time corresponding to the reception timing in the information and transmit it.

As described above, in the present embodiment, "time" refers to the time of the clock 30 corresponding to the detected transmission timing or reception timing of a predetermined information element position of information, and "time" refers to the difference between the times. .

Scheduler 77 controls the schedule (time) for transmitting or receiving information. For example, when communicating information in one direction, the scheduler 77 on the transmitting side controls the information transmission interval and sets a schedule in which the information transmission timing is detected at a predetermined time. Furthermore, the scheduler 77 may control the time from when information is received until it is transmitted. When transmitting information, the communication control unit 73 can include in the information a time corresponding to a transmission timing according to a preset schedule or a detected transmission timing.

The frequency deviation calculation unit 78 calculates the difference between the clock frequency of the information communication device 1 to be synchronized (master device 1a) and the clock frequency of the information communication device 1 to be synchronized (slave device 1b). This difference in clock frequency (hereinafter also simply referred to as "frequency") is a frequency ratio or frequency deviation. The frequency deviation calculation unit 78 of this embodiment calculates the frequency ratio or frequency deviation from the time difference between the clocks 20 between the information communication devices 1 and the propagation time of information between the information communication devices 1.

In the present embodiment, the frequency ratio is the ratio r of the clock frequency of the slave device to the clock frequency of the master device (hereinafter referred to as clock frequency ratio, sometimes simply referred to as frequency ratio). The frequency deviation is the difference between the clock frequency of the master device and the clock frequency of the slave device, and the frequency deviation e can be determined by e=r−1.

The synchronization control section 79 controls the clock 20 or the timepiece 30 based on the frequency ratio or frequency deviation obtained by the frequency deviation calculation section 78.

In other words, the synchronization control unit 79 calculates the time difference with the information communication device 1 serving as the synchronized device (master device) based on the frequency ratio or frequency deviation obtained by the frequency deviation calculation unit 78, and corrects the time difference. Based on this, the value ticked by the clock 30 is corrected. For example, the time may be corrected by controlling the clock 30 itself. Alternatively, the time may be corrected based on the time difference when the clock 30 outputs the time. That is, the clock 30 may not be corrected, but the clock 30 may be controlled so that when the clock 30 outputs the time, it outputs a time with the deviation corrected.

The timing information reference section 80 refers to the timing information output from the synchronization control section 79 and executes desired processing in synchronization with this timing information. The timing information is composed of a periodic timing signal and time information that uniquely corresponds to the specified timing. The synchronization control unit 79 can synchronize with other information communication devices 1 based on timing information. In the synchronous relay device, synchronized timing information of the upper synchronous network is transmitted to the lower synchronous system.

When a factor causing loss of synchronization occurs, the inertial synchronization processing unit 81 changes from a synchronous state to an asynchronous state in which synchronization is lost based on the synchronization phase while the timing information reference unit 80 is performing processing synchronized with timing information. The transition to is suspended and the transition is made to an inertial synchronization state that maintains continuous synchronization. The inertial synchronization state is a state in which the synchronization phase required by the system cannot be maintained, but there is no transition to an asynchronous state. The inertial synchronization processing unit 81 controls the mutual state transition between the synchronous state and the inertial synchronous state, and the mutual state transition between the inertial synchronous state and the asynchronous state.

The quasi-synchronous processing unit 82 sets the asynchronous state to a quasi-synchronous state in which transition to the synchronous state is suspended until a predetermined synchronization phase is reached after the synchronization control unit 79 starts synchronization control. The quasi-synchronized state is a state in which a synchronized state is waited until the synchronized phase becomes stable. In other words, the quasi-synchronized state is a state in which the above four measurement values necessary for time synchronization can be received and the clock frequency can be controlled without problems, but the synchronization accuracy required by the system has not been reached. It is a transitional state. The quasi-synchronous processing unit 82 controls mutual state transition between the asynchronous state and the quasi-synchronous state, and mutual state transition between the quasi-synchronous state and the synchronous state.

The fluctuation control unit 83 limits the speed of the synchronization phase change for synchronization within a predetermined range, and controls the acceleration of the synchronization phase change to vary according to a continuous function. That is, the fluctuation control unit 83 avoids discontinuous switching of the synchronization phase by imposing constraints on the speed and acceleration of fluctuation of the synchronization phase.

Clock quality information output section 84 outputs clock quality information. The clock quality information is a set of statically set values such as clock accuracy and priority, and corresponds to the PTP ANNOUNCE packet.

The selection unit 85 selects one of the information communication devices 1 as at least one of the master device 1a and the slave device 1b based on the clock quality information. The suppression unit 86 suppresses switching of the master device 1a to the slave device 1b due to selection by the selection unit 85 by causing the clock quality information output unit 84 of the information communication device 1 to suspend output of clock quality information at the time of startup. do. When the re-selection unit 87 detects the departure of the master device 1a from the information communication system 100, the re-selection unit 87 causes the master device 1a to transition to the synchronization state or the inertial synchronization state, and re-selects one of the information communication devices 1 as the master device 1a. .

[motion]
The operation of the information communication system 100 having the above configuration will be explained. The information communication system 100 of this embodiment uses information communication to measure the time difference between clocks between the information communication devices 1 and the propagation time of information communication between the information communication devices 1, and corrects this time difference. Time synchronization between information communication devices 1 is realized.

Furthermore, basic synchronization continuity in environments where there are disturbances to synchronization quality, synchronization continuity when switching roles between master and slave devices, and maintenance of synchronization continuity between synchronization systems in synchronization relay equipment. is possible.

[Time synchronization]
First, an example of time synchronization by the frequency deviation calculation section 78 and the synchronization control section 79 will be described. This time synchronization is performed by measuring the time difference between the clocks 20 between the information communication devices 1 and the propagation time of information between the information communication devices 1, and correcting this time difference.

As shown in FIG. 4, the master device 1a transmits synchronization information to the slave device 1b, the slave device 1b receives the information after a propagation time, and after receiving the information, sends another synchronization information to the master device 1a. Considering a situation where data is transmitted and received by the master device 1a after the same propagation time, the propagation time and time difference will be formulated. Note that the synchronization information transmitted by the master device 1a and the other synchronization information transmitted by the slave device 1b are for the purpose of timing for synchronization, and the synchronization information includes the synchronization information transmitted by the master device 1a. The transmission time of the synchronization information may be included, but the contents of the synchronization information and the other synchronization information are arbitrary.

In FIG. 4, information is transmitted from the master device 1a at time _tm,T , and is received by the slave device 1b at time _ts,R after a propagation time _td . The operation timing is shown in which another information is transmitted from the slave device 1b at time t _s,T after Δt _s , and received at time t _m,R by the master device after the same propagation time t _d .

なお、伝搬時間ｔ_ｄは、情報通信の方向において、対照的であることを前提としている。 Here, the interval from transmission to reception in the master device 1a is Δt _m , the interval from reception to transmission in the slave device 1b is Δt _s , and the same timing as the transmission timing t _m,T of the master device 1a is the timing for the slave device 1a. It is assumed that the observation is made as t _{' m,T} in the device 1b. Therefore, the time difference t ₀ between the clock 20 and the slave device 1b based on the master device 1a can be determined as shown in equation (1).

It is assumed that the propagation time _td is symmetrical in the direction of information communication.

From these conditions, the propagation time t _d can be determined as shown in equation (2).

Therefore, the time difference t ₀ between the clocks 20 can be calculated as shown in equation (3) using equation (2).

The synchronization control unit 79 of the slave device 1b can synchronize the time with the master device 1a by repeatedly adjusting the clock frequency and time so that t0 becomes ₀ .

If the clock frequencies of the master device 1a and the slave device 1b are the same, that is, if the clock domain is single, time synchronization is possible by simply adjusting the time once, but generally there is a frequency difference between the two clocks. Because of the deviation, clock frequency adjustment is essential for time synchronization. Even in systems where the clock frequency cannot be directly adjusted, the driving frequency of the clock can be controlled and time synchronization can be achieved by repeatedly adjusting the advance width of each clock.

For these frequency adjustments, closed-loop control is periodically performed in which the synchronization phase is input and the frequency adjustment value is output, and the output value is controlled so that the input synchronization phase becomes zero.

Note that the propagation time and internal delay between transmission and reception timings can be ignored or corrected depending on system requirements. Furthermore, instead of starting the transmission of synchronization information from the master device 1a, the synchronization information may be transmitted from the slave device 1b. Furthermore, although one interface is necessary and sufficient for information communication, a configuration may be adopted in which multiple interfaces are used simultaneously, for example, by implementing transmitting and receiving interfaces independently.

[Synchronization in which subsystems cooperate]
(inertial synchronization)
The synchronization performed by the subsystems in cooperation will be explained with reference to the state transition diagram of FIG. 5. This synchronization includes an inertial synchronization state. Note that the quasi-synchronous state will be described later. The subsystem is a system that is part of the information communication system 100 and includes hardware and application programs that perform time synchronization and information output. In this embodiment, in the information communication device 1, a system that performs time synchronization and transmits audio corresponds to a subsystem.

In addition, in the following explanation, a state machine is a logic circuit that determines the next state depending on input conditions and the current state, and whose state changes according to the input conditions. It is carried out by functioning. In this embodiment, the synchronization control unit 79 and the like in the slave device 1b function as a state machine that switches between various states depending on the factors that have occurred.

FIG. 5 is a state transition diagram modeling a state machine for time synchronization control executed by cooperation of subsystems. This cooperation is performed by state transition between two states of the upper layer: a timing information non-reference state and a timing information reference state. Transition to one of the states is triggered by a subsystem timing information reference start/end event.

The state in which timing information is not referenced shown in the upper frame of FIG. 5 corresponds to a normal operating state in which the PTP is simply operating. The timing information reference state shown in the lower frame of FIG. 5 differs from the timing information non-reference state in that it includes an inertia synchronization state by the inertia synchronization processing unit 81. When the inertia synchronization processing unit 81 transitions to the inertia synchronization state, even if the synchronization phase is unstable or cannot be calculated, it recovers in a short time and immediately changes to an asynchronous state and loses synchronization continuity. This is the case when a factor occurs that makes it unnecessary to do so. In such a case, there may be noise in the communication of synchronization information, a cable connection failure, etc. In this case as well, transmission of timing information continues.

In the inertial synchronization state, when these factors are resolved and the synchronization phase becomes stable, the inertia synchronization processing unit 81 transitions to synchronization without passing through the asynchronous state. This prevents the audio from being interrupted due to a transition to an asynchronous state, and allows communication to continue while maintaining synchronization continuity. If the permissible conditions of the subsystem are exceeded in the inertial synchronization state, the time synchronization control information is reset and the system transitions to the asynchronous state.

More specifically, for example, even if the synchronization phase (time difference) exceeds a threshold value that would result in an asynchronous state in PTP, the inertial synchronization processing unit 81 does not set the asynchronous state but sets the inertial synchronization state. However, if the synchronization phase exceeding the threshold continues for a predetermined period of time, it is assumed to be in an asynchronous state. The predetermined time is the time required for the synchronization phase exceeding the threshold to become zero.

Each state in the upper layer includes a state machine in the lower layer mainly for time synchronization control, and states with the same name are transparent. That is, if the lower layer in the timing information non-reference state is in the synchronous state, even if the state transitions to the timing information reference state, the lower layer will be in the synchronous state. However, when the lower layer is in the inertial synchronization state and the upper layer transitions to the timing information non-reference state, the time synchronization control information is reset and the transition to the asynchronous state occurs. When the device is started, the state machine in the lower layer performs initialization such as waiting for information transmitted from other devices, and transitions to an asynchronous state.

In the synchronous state, from the viewpoint of synchronous continuity, state transition operations differ depending on the state of the upper layer. In a synchronized state, if the synchronization phase becomes unstable to the extent that it cannot satisfy the synchronization accuracy requirements, or if the synchronization phase cannot be determined due to some reason such as not being able to receive synchronization information, if the subsystem is referring to timing information, Transition to inertial synchronization state. At this time, transmission of timing information continues in order to maintain synchronization continuity.

On the other hand, if the subsystem is not referencing timing information, for example, if it is not outputting audio, there is no need to maintain synchronization continuity, so the time synchronization control information is reset like normal PTP. and transition to an asynchronous state.

In the inertial synchronization state, when the synchronization phase becomes stable enough to satisfy the synchronization accuracy requirement again, a transition is made to the synchronization state.

In this way, by performing time synchronization control according to the state machine of FIG. 5, synchronization continuity can be ensured and the subsystem can be stably operated.

Even if the subsystem references timing information, it will transition to an asynchronous state if it falls outside of the allowable conditions for synchronous continuity. This allowable condition is set by defining an abnormal state in which the subsystem cannot maintain stable operation even if synchronization continuity is ensured. For example, an abnormal state such as an unstable synchronization state lasting longer than a specified period or a synchronization phase shift exceeding a specified value is defined and established.

(semi-synchronous)
In this embodiment, before transitioning from the asynchronous state to the synchronous state, the quasi-synchronous processing unit 82 causes the transition to the quasi-synchronous state so that the synchronization phase is adjusted to an extent that satisfies the synchronization accuracy requirements of the subsystem that refers to the timing information. When stable, transition to synchronous state. For example, if an incorrect propagation time is determined and synchronization control is performed to set the synchronization phase to zero, synchronization continuity cannot be maintained even if synchronization is performed using the incorrect propagation time or synchronization phase.

Immediately after the transition to the quasi-synchronized state, there is a possibility that an incorrect propagation time is obtained due to burst noise in the communication of synchronization information, and an incorrect synchronization phase is calculated based on this. If the transition to the synchronized state continues as it is, the synchronized state will be entered with an incorrect synchronization phase. In such a case, when the burst noise is eliminated, the synchronization phase changes discontinuously to the original synchronization phase, making it impossible to ensure synchronization continuity. Once synchronized, it takes a long time to regain synchronization with the correct synchronization phase.

In order to avoid such a transition to an erroneous synchronization state, the quasi-synchronization processing section 82 assigns a weighting value according to the synchronization phase controlled by the synchronization control section 79, and calculates the cumulative value of the weighting values. When the value reaches a predetermined value, the semi-synchronous state is transitioned to the synchronous state.

More specifically, the quasi-synchronization processing unit 82 operates the processing flow shown in FIG. 6 as a function that is called every time the synchronization phase is determined based on the propagation time in the quasi-synchronization state. That is, a variable called cumulative synchronization phase is set, and the process is started every time a synchronization phase is determined based on four propagation times, and it is determined whether or not the cumulative synchronization phase exceeds a specified value (step S101).

If the cumulative synchronization phase is less than or equal to the specified value (NO in step S101), it is ranked according to the value of the synchronization phase, and the weight value set according to the rank is added to a variable called cumulative synchronization phase. (Steps S102 to S104, S107 to S109), the process ends. In other words, for example, with zero as the value of the correct synchronization phase, values larger than this are distinguished by ranks separated by a predetermined value width, and each rank is given a weight of 1 to N in the order of being closest to the correct synchronization phase. Set.

If the cumulative synchronous phase exceeds the specified value (YES in step S101), it is determined that the synchronous phase has been obtained based on an incorrect propagation time, the cumulative synchronous phase is cleared (step S110), and a transition is made to the asynchronous state ( Step S111). In other words, the synchronous phase is discarded and the state transitions to an asynchronous state. When the synchronization phase zero based on the correct propagation time is found (NO in step S104), the accumulated synchronization phase is cleared (step S105), and the state transitions to the synchronization state (step S106).

[Synchronous phase fluctuation control]
Even if synchronization continuity is ensured by introducing principles related to synchronization state transitions, depending on the size of the synchronization phase, there may be cases where the synchronization phase may appear to have changed discontinuously from the subsystem that refers to timing information. be. This is because the fluctuation speed and fluctuation acceleration of the synchronization phase change rapidly.

For example, if timing information is input to a PLL in a subsystem, a sudden change in the fluctuation speed or fluctuation acceleration of the synchronization phase will cause the PLL to unlock if the allowable range of the input frequency fluctuation speed of the PLL is exceeded. , leading to abnormality in the subsystem.

To deal with this, it is conceivable to set an upper limit on the synchronous phase fluctuation speed and control it so that it falls within the permissible range of the subsystem. However, since the continuity of the synchronous phase fluctuation acceleration is not taken into account, there remains a possibility that this will lead to abnormalities in the subsystem.

In this embodiment, in addition to limiting the range of the synchronous phase fluctuation speed, the synchronous phase fluctuation acceleration is configured to be a continuous function. That is, when performing synchronous control from the current synchronous phase φ _S to the target synchronous phase φ _D , for example, the synchronous phase fluctuation function f _φ (t) is used as shown in equation (4), which is a sigmoid function that continues up to the second derivative. to continuously control the synchronization phase.

Here, V in equation (4) is set to be a positive number less than or equal to the maximum absolute value of the synchronous phase variation speed defined by the subsystem. In other words, by maintaining the continuity of acceleration while limiting the speed, discontinuous switching is avoided.

Note that the synchronous phase variation function is not limited to Equation (4), and may be any function as long as the second-order derivative of time t is continuous and a parameter for controlling the range of the first-order derivative can be set. Furthermore, if the subsystem allows it, the amount of computation of the synchronization phase may be reduced by applying polygonal approximation to the synchronization phase variation function.

[Synchronization continuity when switching roles]
For example, when the device that was originally the master device 1a is lost and another device that was the slave device 1b becomes the master device 1a, switching between the master device 1a and the slave device 1b is performed. One of the slave devices 1b with good conditions becomes the master device 1a, and the others become slave devices 1b again and synchronize with the master device 1a. That is, after the overall synchronization is reset, a new master device 1a and slave device 1b are determined.

In a system in which the roles of the master device 1a and the slave device 1b are switched in this way, it is desirable to ensure specific synchronization continuity when the roles are switched. However, in PTP, when the roles of the master device 1a and the slave device 1b are switched, the synchronization phase changes discontinuously through a transition to an asynchronous state, so synchronization continuity cannot be ensured. Synchronous continuity in this embodiment includes the property that a subsystem that refers to timing information operates steadily and stably when switching roles from slave device 1b to master device 1a.

In a system in which multiple devices of the same or the same type form a synchronous network and perform time synchronization, one of the devices dynamically operates as the master device 1a during a given period, and all other devices operate as the slave devices 1b. Consider operational cases.

At this time, even if the clock performance of each device is the same, generality is essential. That is, from the aspect of clock performance, it can be considered that the synchronization quality will be the same no matter what device operates as the master device 1a. Here, the synchronization quality is expressed by combining the average value and variance of the synchronization phase over a certain period of time. Furthermore, reception quality (error rate, number of missing information, etc.) such as clock quality information may be combined. If the objective is to ensure synchronization continuity when switching the roles of devices, there is no problem even if a plurality of various devices form a synchronization network.

(simultaneous startup)
FIG. 7 shows a state machine for time synchronization control to ensure synchronization continuity in each device whose role can be switched. Although FIG. 7 shows the state machine of the master device 1a, which is a lower layer, with the slave device 1b in the upper layer in the timing information reference state, the same applies to the case in which the timing information is not referenced. Omitted. Further, in FIG. 7, the asynchronous state, quasi-synchronous state, synchronous state, and inertial synchronous state are the same as described above.

If the role of the own device is undetermined at startup, the own device waits for clock quality information output from the clock quality information output unit 84 of the other device in an asynchronous state, but the own device does not distribute the clock quality information by the suppression unit 86. is suppressed. If the clock quality information is received within the specified period, it starts operating as the slave device 1b and transitions to a semi-synchronized state, thereby maintaining the existing master device 1a. In other words, since the own device does not distribute clock quality information that triggers switching of the master device 1a, it can continue to operate as the master device 1a.

The value of the ANNOUNCE packet is an indicator of whether the device will become the best master. Depending on its superiority or inferiority, even if it is currently operating as the master device 1a, it will switch to the slave device 1b, and a better device will switch to the master device 1a based on static information, regardless of the state of the subsystem. Therefore, when the master device 1a is selected by distributing clock quality information from its own device at startup and comparing it with the received clock quality information, the existing master device 1a is switched to the slave device 1b, and synchronization continuity is maintained. may be lost.

Therefore, in this embodiment, at startup, by waiting for clock quality information from other devices and not distributing clock quality information from the own device, the existing master device 1a Prevent switching to the own device.

If the clock quality information is not received even after the specified period has elapsed, each device continues to wait for the clock quality information, starts periodically transmitting the clock quality information, and transitions to the quasi-time distribution state. do.

In the quasi-time distribution state, if the clock quality information is not received after a specified period, the own device starts operating as the master device 1a, starts sending timing information to the subsystem, and returns to the time distribution state. Transition to.

If the clock quality information is received within the specified period, the selection unit 85 compares all the received clock quality information with the clock quality information of its own device, and selects the best master device 1a. After the prescribed period has passed, if the selected best master device 1a is its own device, it starts operating as the master device 1a, starts transmitting timing information to the subsystem, and transitions to a time distribution state. If the other device is the best master device 1a, the own device starts operating as the slave device 1b and transitions to an asynchronous state.

Due to this state transition, only the own device starts up independently, and when no other device is connected to the synchronous network, operates as the master device 1a. When the self-device is started after being connected to a synchronous network in which an already operating master device 1a exists, the self-device operates as the slave device 1b. Therefore, synchronization continuity can be maintained without the master device 1a being in operation being switched inadvertently.

Furthermore, when the master device 1a of synchronous network A is connected to the master device 1a of synchronous network B, that is, when synchronous network A and synchronous network B are combined, there is no state transition in the time distribution state or synchronous state. , the re-selection unit 87 re-selects the best master device 1a. If another device is selected as the master device 1a, the role is switched to the slave device 1b, and the device transitions to a semi-synchronized state. Although the means for selecting the best master device 1a is arbitrary, for example, BMCA of PTP can be used.

When the master device 1a is switched as a result of re-election, synchronization is re-established with respect to the new master device 1a, and synchronization continuity is ensured at this time as well. That is, as described above, the synchronization phase is continuously varied. However, if there is a time difference between the master devices 1a to the extent that the subsystem tolerance conditions cannot be satisfied, either the synchronization continuity is abandoned and resynchronization is performed, or it is interpreted as an abnormal event and the system transitions to an abnormal state. Good too.

Note that since the synchronization network connection between the operating master devices 1a is a hot-line insertion, some time synchronization systems may interpret this as an abnormal event and transition to an abnormal state. Further, even after the own device becomes the master device 1a and enters the time distribution state, the role may be switched from the master device 1a to the slave device 1b by a specific command. For example, in a synchronous network, a case may be considered in which the frequency deviation from the nominal frequency is averaged by periodically switching the master device 1a.

(Change of master device)
In a single synchronous network, when the master device 1a leaves the synchronous network or when the master device 1a changes its role to the slave device 1b, the re-selection unit 87 re-selects the master device 1a and selects one of the slaves. The device 1b switches its role to the master device 1a, and the other slave devices 1b need to resynchronize with the new master device 1a. The state transition in this case will also be explained according to the state machine shown in FIG.

When operating normally and in synchronization, the subsystems are controlled to maintain the required synchronization phase. For example, the average frequency deviation between devices is zero or near zero. Therefore, even if the master device 1a is absent for a certain period of time and the slave device 1b becomes free running, the synchronization phase is maintained at approximately zero. Even if it takes a long time to be re-elected, there is a high probability that synchronization will be maintained. In other words, even if a new master device 1a is selected, the synchronization phase is unlikely to shift significantly. However, in PTP, the state is UNCALIBRATED, the state is reset, the state is changed to an asynchronous state, and synchronization is performed again.

Here, since the own device is synchronized with the old master device 1a that left, even if the synchronization control is temporarily stopped, the synchronization phase will remain within the synchronization phase range allowed by the subsystem. Continuously fluctuate. Therefore, even if the own device resynchronizes with a different master device 1a, synchronization continuity can be ensured as long as the state transition through the asynchronous state is not performed.

Therefore, if the clock quality information is no longer received due to the departure of the master device 1a or the like, a transition is made from the synchronization state or the inertial synchronization state to the re-selection state. At this time, in order to maintain synchronization continuity, the timing information continues to be transmitted and does not transition to an asynchronous state.

In the re-selection state, the re-selection unit 87 receives clock quality information of other devices and selects the master device 1a by means such as BMCA of PTP. When the own device is selected as the master device 1a, it transits to the time distribution state. When another device is selected as the master device 1a, the device is resynchronized as the master device 1a, and the state changes to the state before transitioning to the re-selected state, that is, the synchronized state or the inertial synchronized state. At this time, in order to maintain synchronization continuity, timing information continues to be transmitted and does not transition to an asynchronous state.

If it takes time to select the master device 1a and the subsystem tolerance conditions cannot be satisfied, synchronization continuity may be abandoned and resynchronized, or it may be interpreted as an abnormal event and transitioned to an abnormal state.

In a synchronization network where the synchronization phase is stable, even when the master device 1a switches the role to the slave device 1b, if you want to ensure synchronization continuity, it is necessary to continue sending timing information without resetting the time synchronization control information. , it may transition to an asynchronous state.

[Synchronous continuity between synchronous systems]
In a synchronous relay device where one device functions simultaneously as a master device 1a and a slave device 1b, such as a boundary clock in a PTP system, it is necessary to ensure unique synchronization continuity between synchronous systems. is desirable.

In a conventional synchronous relay device, an upper synchronous network and a lower synchronous network independently manage the synchronous state. For example, when starting up a synchronous relay device, the master device 1a and slave device 1b start up simultaneously, and each performs synchronous control independently. Therefore, the slave device 1b must synchronize with the master device 1a, which takes time.

In other words, the boundary clock functions as a master device 1a for the lower synchronous system. Since the master device 1a has already established its position as the master device 1a, it is sufficient to send an ANNOUNCE packet or the like to synchronize the lower synchronization network. When the boundary clock is activated in this manner, the synchronization phase of the lower synchronization network system is determined by the function as the master device 1a. On the other hand, since the slave device 1b needs to determine the synchronization phase with respect to the master of the higher-level synchronization network closer to the grandmaster clock, it takes time to determine the synchronization phase.

However, the synchronization information transmitted to the lower synchronization network is generated based on the timing information of the upper synchronization network. Therefore, if the lower synchronization network establishes the synchronization state in advance, the synchronization phase of the lower synchronization network becomes discontinuous during the process of determining the synchronization state of the upper synchronization network, and the synchronization continuity of the lower synchronization network may not be able to be maintained.

Therefore, the information communication device 1 serving as a synchronous relay device manages the synchronization state in cooperation between the synchronous networks, and suspends the transmission of timing information to the lower synchronous network until the synchronous state of the upper synchronous network is determined. , and suspends the distribution of clock quality information and synchronization information on the lower-level synchronization network. That is, after the slave device 1b of the synchronous relay device establishes synchronization in the upper synchronous network, the master device 1a of the synchronous relay device controls the synchronization in the lower synchronous network by transmitting the synchronized timing information to the lower synchronous network. . As a result, in the master device 1a connected to the lower synchronization network, f phase fluctuation is eliminated and synchronization continuity is ensured.

[effect]
(1) This embodiment is an information communication system 100 in which a plurality of information communication devices 1 communicate information as a master device 1a or a slave device 1b, and information is transmitted between the master device 1a and the slave device 1b. Contains synchronization information, which is information communicated to synchronize time.

A synchronization control unit 79 that controls the synchronization phase between the master device 1a and the slave device 1b based on the synchronization information to achieve a synchronized state in which the time is synchronized, and a timing indicating the synchronized timing output from the synchronization control unit 79. The timing information reference unit 80 refers to the timing information and performs processing in synchronization with the timing information, and when a factor that causes synchronization to be lost occurs, the timing information reference unit 80 performs processing in synchronization with the timing information. and an inertial synchronization processing unit 81 that suspends transition from a synchronized state to an asynchronous state in which synchronization is lost, and causes a transition to an inertial synchronization state in which continuous synchronization is maintained.

Further, the present embodiment is an information communication device 1 that communicates information with another information communication device 1, and the time is changed by controlling the synchronization phase with the other information communication device 1 based on synchronization information. A synchronization control unit 79 brings the synchronized state into a synchronized state, a timing information reference unit 80 refers to timing information indicating synchronized timing outputted from the synchronization control unit 79, and performs processing in synchronization with the timing information, and causes the synchronization to be lost. When a factor occurs, while the timing information reference unit 80 is performing synchronized processing, transition from a synchronized state to an asynchronous state where synchronization is lost is suspended based on the synchronization phase to maintain continuous synchronization. It has an inertia synchronization processing section 81 that causes the transition to an inertia synchronization state.

In this way, while the timing information reference section 80 is performing synchronized processing, even if a factor that causes synchronization to be lost occurs in the synchronized state, the inertial synchronization processing section 81 transitions to the inertial synchronization state according to the synchronization phase. By doing so, it is possible to suspend transition to an asynchronous state and maintain continuous synchronization. Therefore, it is possible to reduce situations in which the synchronization becomes discontinuous, resulting in a deterioration in operation quality, such as phase noise occurring in the audio or interruptions in the audio.

(2) In the asynchronous state, after the synchronization control unit 79 starts synchronization control, it has a quasi-synchronization processing unit 82 that puts the transition to the synchronization state on hold until a predetermined synchronization phase is reached. Therefore, since the synchronization state can be established after the synchronization phase is stabilized, it is possible to reduce the possibility that the synchronization phase will switch discontinuously due to an incorrect propagation time and the synchronization phase based thereon.

(3) It has a fluctuation control unit 83 that limits the speed of synchronization phase change for synchronization within a predetermined range and controls the acceleration of synchronization phase change to vary according to a continuous function. Therefore, it is possible to prevent a situation where the varying speed and varying acceleration exceed the permissible range of the device and an abnormality occurs.

(4) A clock quality information output unit 84 that outputs clock quality information, and a selection unit 85 that selects one of the information communication devices 1 as at least one of the master device 1a and the slave device 1b based on the clock quality information. , Suppression that suppresses switching of the existing master device 1a to the slave device 1b due to selection by the selection unit 85 by causing the clock quality information output unit 84 of the information communication device 1 to suspend output of clock quality information at the time of startup. It has a section 86. Therefore, even if there is an information communication device 1 newly connected to the system, there is a high possibility that the existing master device 1a can maintain its status as a master, and the possibility that synchronization continuity will be lost can be reduced.

(5) When the slave device 1b detects the separation of the master device 1a from the information communication system 100, re-selecting one of the information communication devices 1 as the master device 1a from the synchronized state or the inertial synchronized state. It has a re-selection unit 87 for transitioning to the state. Therefore, when the master device 1a is re-selected, the synchronization state or the inertial synchronization state is maintained, which increases the possibility that synchronization continuity will be maintained.

(6) Any of the information communication devices 1 includes an information communication device 1 that is a synchronous relay device having the functions of both a master device 1a and a slave device 1b, and the slave device 1b side is connected to an upper synchronous network, and the master device 1a side is connected to an upper synchronous network. When the lower synchronization network is assumed to be a lower synchronization network, after synchronization is established in the upper synchronization network by the slave device 1b, the master device 1a controls synchronization in the lower synchronization network by transmitting synchronized timing information to the lower synchronization network. Therefore, after the lower synchronization network establishes synchronization first, the lower synchronization network establishes synchronization again in accordance with the synchronization established by the upper synchronization network, thereby reducing the possibility that synchronization continuity will be lost.

[Other embodiments]
The present invention is not limited to the above-mentioned embodiments as they are, and in the implementation stage, the constituent elements can be modified and embodied without departing from the spirit of the invention. Moreover, various inventions can be formed by appropriately combining the plurality of components disclosed in the above embodiments.

1 Information communication device 1a Master device 1b Slave device 10 Communication section 11 Transmitter 12 Receiver 13 Transmission timing detection section 14 Reception timing detection section 20 Clock 30 Clock 50 Storage section 60 External interface 70 Control section 71 Main control section 72 Transmission/reception data I /F
73 Communication control section 74 Time recording section 77 Scheduler 78 Frequency deviation calculation section 79 Synchronization control section 80 Timing information reference section 81 Inertial synchronization processing section 82 Quasi-synchronization processing section 83 Fluctuation control section 84 Clock quality information output section 85 Selection section 86 Suppression section 87 Re-selection section 100 Information communication system

Claims (6)

An information communication device that communicates information with other information communication devices as a master device or a slave device,
The information includes synchronization information for synchronizing time with other information communication devices,
a synchronization control unit that achieves a synchronized state by controlling a synchronization phase with another information communication device based on the synchronization information;
a timing information reference unit that refers to timing information indicating synchronized timing output from the synchronization control unit and performs processing in synchronization with the timing information;
When a factor that causes a loss of synchronization occurs, while the timing information reference unit is performing processing in synchronization with the timing information, a transition from the synchronous state to an asynchronous state in which synchronization is lost is caused based on the synchronous phase. an inertial synchronization processing unit that suspends and transitions to an inertial synchronization state in which continuous synchronization is maintained;
a fluctuation control unit that limits the speed of synchronization phase change for synchronization within a predetermined range, and controls the acceleration of the synchronization phase change to vary according to a continuous function;
An information communication device comprising: In the asynchronous state, the device is characterized by having a quasi-synchronization processing unit that sets a quasi-synchronization state to a quasi-synchronization state in which transition to the synchronization state is suspended until a predetermined synchronization phase is reached after the synchronization control unit starts synchronous control. The information communication device according to claim 1. a clock quality information output unit that outputs its own clock quality information to another information communication device;
a selection unit that selects itself as at least one of a master device and a slave device based on the clock quality information;
a suppression unit that suspends outputting the own clock quality information to other information communication devices;
The information communication device according to claim 1 or 2, characterized in that the information communication device has: A network connecting the slave devices is defined as an upper synchronization network, a network connecting the master devices is defined as a lower synchronization network, and when the slave device detects the departure of the master device from the lower synchronization network, The information communication device according to any one of claims 1 to 3, further comprising a reselection unit that transitions from the synchronization state or the inertial synchronization state to a reselection state in which the information communication device reselects itself as a master device. An information communication system comprising a plurality of information communication devices according to any one of claims 1 to 4 , and configured such that the information communication device serving as a slave device is synchronized with the information communication device serving as a master device. including a synchronous relay device that communicates information as the master device and the slave device,
When the network connecting the slave devices is defined as an upper synchronization network, and the network connecting the master devices is defined as a lower synchronization network,
After the slave device of the synchronous relay device establishes synchronization in the upper synchronous network, the master device of the synchronous relay device establishes synchronization in the lower synchronous network by transmitting synchronized timing information to the lower synchronous network. The information communication system according to claim 5 , characterized in that:

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