JP7296609B2 - DIGITAL PROCESSING DEVICE, METHOD AND PROGRAM FOR MANUFACTURING DIGITAL PROCESSING DEVICE - Google Patents

Description

The present invention relates to a digital processing device, a method of manufacturing a digital processing device, and a program.

It is known that products using LSIs (Large Scale Integrated Circuits) such as ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Arrays) are used in digital processing devices that require table lookup processing. Examples of such a digital processing device include a signal processing device that performs filter processing by referring to a table of filter coefficients, and a security (encryption processing) device that performs nonlinear conversion processing by table reference processing. Hard macros and soft macros are used in programmable logic devices such as FPGAs. In the soft macro, circuit design for table reference processing is performed using a hardware description language (HDL) (see, for example, Patent Document 1).

Description methods using a hardware description language include a description method using a look-up table (LUT), a description method using Boolean algebra, and a description method using an extension field in finite field theory. There is In the description method using Boolean algebra, it is necessary to describe uniquely in Boolean algebra, and due to its complexity, the description method using Boolean algebra is rarely used. A description method using extension fields in finite field theory can be expected to greatly improve performance, but it is not practical due to the difficulty of theory. In such a situation, a description method using a lookup table is frequently used from the viewpoint of simplicity.

Japanese Patent Application Laid-Open No. 2003-323117

However, there is room for improvement in terms of performance in a digital processing device in which circuit design for table lookup processing is performed only by a description method using a lookup table.

The present invention provides a digital processing device capable of improving performance, a method for manufacturing the digital processing device, and a program.

A digital processing device according to one aspect of the present invention is a digital processing device created using a programmable logic device, and converts first data having a first number of bits into second data having a first number of bits. and a linear processing unit that performs linear processing on the second data. The processing unit has a plurality of first conversion circuits created based on a lookup table description method and a plurality of second conversion circuits created based on a Boolean algebra description method, and a plurality of first conversion circuits and each of the plurality of second conversion circuits converts first partial data having a second number of bits of the first data into second partial data having a second number of bits of the second data . The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more). For each unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are assigned.

In this digital processing device, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, in the processing unit, conversion circuits created based on different description methods coexist, and N conversion circuits created based on the same description method are used for each processing unit of the unit processing circuit of the linear processing unit. assigned. Various circuits created in a programmable logic device are basically randomly distributed and arranged, but circuits based on the same description method tend to be arranged together. Therefore, by allocating N conversion circuits created based on the same description method for each processing unit, the possibility that N conversion circuits are arranged together increases. As a result, the mounting area of the circuit created in the programmable logic device can be reduced, or the processing speed of the circuit can be increased, so that the performance of the digital processing device can be improved.

The unit processing circuit may change the arrangement order of the N pieces of second partial data included in the unit data. Since the N conversion circuits that supply the N second partial data processed by the unit processing circuits tend to be arranged together, the total wiring length of the wiring from the N conversion circuits to the unit processing circuits is is likely to become smaller. This reduces the mounting area of the circuit created in the programmable logic device and increases the possibility of increasing the processing speed.

The unit processing circuit may shift the unit data by a predetermined number of bits. Since the N conversion circuits that supply unit data to be processed by the unit processing circuits tend to be arranged together, the total wiring length from the N conversion circuits to the unit processing circuits may be reduced. increases. This reduces the mounting area of the circuit created in the programmable logic device and increases the possibility of increasing the processing speed.

A digital processing device according to one aspect of the present invention is a digital processing device created using a programmable logic device, which performs linear processing of predetermined data and outputs first data having a first number of bits. A processing unit and a processing unit that converts first data into second data having a first number of bits. The processing unit has a plurality of first conversion circuits created based on a lookup table description method and a plurality of second conversion circuits created based on a Boolean algebra description method, and a plurality of first conversion circuits and each of the plurality of second conversion circuits converts first partial data having a second number of bits of the first data into second partial data having a second number of bits of the second data . The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more). For each unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are assigned.

In this digital processing device, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it is possible to improve the performance of the digital processing device as in the case of the digital processing device described above.

The unit processing circuit may perform an exclusive OR operation between the unit data and the data having the third number of bits. Since the N conversion circuits supplied with data based on the processing results of the unit processing circuits tend to be arranged together, the total wiring length from the unit processing circuit to the N conversion circuits is reduced. more likely. This reduces the mounting area of the circuit created in the programmable logic device and increases the possibility of increasing the processing speed.

Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits may perform nonlinear conversion processing. In this case, it is possible to make it difficult to guess the input data of the digital processing device from the output data of the digital processing device.

A method of manufacturing a digital processing device according to another aspect of the present invention includes a plurality of first conversion circuits and a plurality of second conversion circuits, and converts first data having a first number of bits to A method of manufacturing a digital processing device comprising a processing unit that converts to second data and a linear processing unit that performs linear processing on the second data, the circuits of the processing unit and the linear processing unit according to the programmable logic device A description step of describing the function and a creation step of creating the processing units and the linear processing units in the programmable logic device based on the circuit functions. Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits converts the first partial data having the second number of bits of the first data to the second data having the second number of bits of the second data. The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer equal to or greater than 2) as a processing unit. . In the processing unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are assigned for each processing unit, and in the description step, The lookup table description system describes the circuit functions of the plurality of first conversion circuits, and the Boolean algebra description system describes the circuit functions of the plurality of second conversion circuits.

In this digital processing device manufacturing method, the circuit functions of the plurality of first conversion circuits are described by the lookup table description method, and the circuit functions of the plurality of second conversion circuits are described by the Boolean algebra description method. Furthermore, in the processing unit, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it is possible to improve the performance of the digital processing device as in the case of the digital processing device described above.

A method of manufacturing a digital processing device according to another aspect of the present invention includes a linear processing unit that performs linear processing on predetermined data and outputs first data having a first number of bits; and a processing unit that converts first data into second data having a first number of bits, the method for manufacturing a digital processing device according to a programmable logic device. a description step of describing the circuit functions of the units and the linear processing units; and a creation step of creating the processing units and the linear processing units in the programmable logic device based on the circuit functions. Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits converts the first partial data having the second number of bits of the first data to the second data having the second number of bits of the second data. The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer equal to or greater than 2) as a processing unit. . In the processing unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are assigned for each processing unit, and in the description step, The lookup table description system describes the circuit functions of the plurality of first conversion circuits, and the Boolean algebra description system describes the circuit functions of the plurality of second conversion circuits.

In this digital processing device manufacturing method, the circuit functions of the plurality of first conversion circuits are described by the lookup table description method, and the circuit functions of the plurality of second conversion circuits are described by the Boolean algebra description method. Furthermore, in the processing unit, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it is possible to improve the performance of the digital processing device as in the case of the digital processing device described above.

A program according to still another aspect of the present invention has a plurality of first conversion circuits and a plurality of second conversion circuits, and converts first data having a first number of bits to second data having a first number of bits. A program for causing a programmable logic device to function as a digital processing device comprising a processing unit for conversion and a linear processing unit for linearly processing second data, wherein a plurality of first conversion circuits are created in the programmable logic device. and a second portion for creating a plurality of second conversion circuits in the programmable logic device. The first part is described using a lookup table description method, the second part is described using a Boolean algebra description method, and each of the plurality of first conversion circuits and each of the plurality of second conversion circuits are: First partial data having a second number of bits of the first data is converted into second partial data having a second number of bits of the second data. The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more). For each unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are assigned.

In this program, the first part is described using the lookup table description method, and the second part is described using the Boolean algebra description method. Furthermore, in the processing unit, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it is possible to improve the performance of the digital processing device as in the case of the digital processing device described above.

According to yet another aspect of the present invention, there is provided a program comprising: a linear processing unit that performs linear processing on predetermined data and outputs first data having a first number of bits; a plurality of first conversion circuits; a plurality of second conversion circuits; A program for causing a programmable logic device to function as a digital processing device, the program for causing a programmable logic device to function as a digital processing device, the program comprising: and a second portion for creating a plurality of second translation circuits in the programmable logic device. The first part is described using a lookup table description method, the second part is described using a Boolean algebra description method, and each of the plurality of first conversion circuits and each of the plurality of second conversion circuits are: First partial data having a second number of bits of the first data is converted into second partial data having a second number of bits of the second data. The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more). For each unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are assigned.

In this program, the first part is described using the lookup table description method, and the second part is described using the Boolean algebra description method. Furthermore, in the processing unit, N first conversion circuits or N second conversion circuits are assigned to each processing unit. Therefore, it is possible to improve the performance of the digital processing device as in the case of the digital processing device described above.

According to the present invention, it is possible to improve the performance of a digital processing device.

FIG. 1 is a diagram showing the configuration of a digital processing device according to the first embodiment. FIG. 2 is a diagram showing the detailed configuration of the linear processing unit in FIG. FIG. 3 shows a modification of the digital processing device according to the first embodiment. FIG. 4 is a diagram showing the configuration of a digital processing device according to the second embodiment. FIG. 5 is a diagram for explaining array conversion processing of the array conversion circuit in FIG. FIG. 6 is a diagram showing a modification of the digital processing device according to the second embodiment.

Hereinafter, details of embodiments of the present invention will be described with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are used for the same or equivalent elements, and overlapping descriptions are omitted.

FIG. 1 is a diagram showing the configuration of a digital processing device according to the first embodiment. FIG. 2 is a diagram showing the detailed configuration of the linear processing unit in FIG. A digital processing device 1 shown in FIG. 1 is a device for performing cryptographic processing conforming to the BORON standard. The digital processing device 1 is made using programmable logic devices. FPGAs and PLDs (Programmable Logic Devices), for example, are used as programmable logic devices.

The digital processing device 1 includes an encrypted data generator 2 , a processor 3 and a linear processor 4 . The digital processing device 1 digitally processes input data having a first bit number (64 bits in FIG. 1) by means of an encrypted data generating unit 2, a processing unit 3, and a linear processing unit 4, thereby converting the first bit number into Output the output data that has Although FIG. 1 shows one encrypted data generator 2, one processor 3, and one linear processor 4, the digital processing device 1 includes the encrypted data generator 2, processor 3, and linear processor 4. A plurality of circuit units 10 are provided with the processing unit 4 as one circuit unit 10 . The plurality of circuit units 10 are connected in series, and in two circuit units 10 adjacent to each other, data Dout output from the preceding circuit unit 10 is input to the subsequent circuit unit 10 as data Din. be. Each bit included in the data Din is assigned a bit number in ascending order from LSB (Least Significant Bit) to MSB (Most Significant Bit). In this embodiment, the bit number of the LSB is 0 and the bit number of the MSB is 63rd. The same applies to data Dout and data D1, D2, D3, and D4, which will be described later.

The encrypted data generator 2 is a circuit that logically operates data Din based on the encrypted key data. Specifically, the encrypted data generator 2 calculates XOR (exclusive OR) of the data Din and the encrypted key data. Data Din is data having a first number of bits. The cipher key data is stored in advance in a memory (not shown), and is input to the cipher data generator 2 from the memory. The encryption key data may be sequentially generated by an encryption key generation circuit (not shown) and input to the encryption data generation unit 2 from the encryption key generation circuit. The encryption key data has a first number of bits. The encrypted data generation unit 2 outputs the calculation result to the processing unit 3 as data D1 (first data). Data D1 is data having a first number of bits.

The processing unit 3 is a circuit that converts data D1 into data D2 (second data). Data D2 is data having the first number of bits. Specifically, the processing unit 3 generates the data D2 by performing nonlinear conversion processing on the data D1. The processor 3 outputs data D2 to the linear processor 4 . The processing unit 3 includes a plurality of conversion circuits 31 (a plurality of first conversion circuits) and a plurality of conversion circuits 32 (a plurality of second conversion circuits). A plurality of conversion circuits 31 and a plurality of conversion circuits 32 are arranged in parallel, and data d1 (first partial data) is input to each conversion circuit 31 and each conversion circuit 32 . Data d1 is part of data D1 and has a second number of bits (4 bits in FIG. 1). Data d1 is data obtained by dividing all the data from LSB to MSB of data D1 in units of the second number of bits in order of bit numbers. In FIG. 1, data D1 is composed of 16 data d1. Each of the plurality of conversion circuits 31 and each of the plurality of conversion circuits 32 converts input data d1, whereby the processing unit 3 converts the data D1 into data D2.

The conversion circuit 31 is a circuit created based on a description method using a lookup table (lookup table description method). The conversion circuit 32 is a circuit created based on a description system using Boolean algebra (Boolean algebra description system). The conversion circuit 31 and the conversion circuit 32 have functions equivalent to each other.

Conversion circuits 31 and 32 are circuits for converting data d1. Specifically, conversion circuits 31 and 32 convert data d1 into data d2 (second partial data). Data d2 is part of data D2 and has a second number of bits. Data d2 is data obtained by dividing all the data from LSB to MSB of data D2 in units of the second number of bits in the order of bit numbers. In FIG. 1, data D2 is composed of 16 data d2. The conversion circuits 31 and 32 are logical operation circuits that implement table lookup circuits based on a truth table or the like defining the relationship between the data d1 and the data d2. The conversion circuits 31 and 32 are also called S-BOX (substitution box).

In the processing unit 3, N of the plurality of conversion circuits 31 are converted for each data having a third bit number (16 bits in FIG. 1) which is N times the second bit number (N is an integer of 2 or more) of the data D1. N conversion circuits 32 out of the conversion circuits 31 or the plurality of conversion circuits 32 are assigned. Note that N=4 in this embodiment. Specifically, in the processing unit 3, the conversion circuit 32 is assigned to each of the four data d1 from the LSB to the 15th bit of the data D1. Conversion circuits 31 are assigned to the four data d1 from the 16th to 31st bits of the data D1. Conversion circuits 32 are assigned to the four data d1 from the 32nd to 47th bits of the data D1. Conversion circuits 31 are assigned to four pieces of data d1 from the 48th bit to the MSB of data D1.

The linear processor 4 is a circuit that linearly processes the data D2. The linear processor 4 linearly processes the data D2 to generate the data Dout. Data Dout is data having a first number of bits. The linear processing section 4 outputs the data Dout as output data from the circuit section 10 . The linear processing unit 4 has a shuffle circuit 41 , a shift circuit 42 and an XOR execution circuit 43 .

The shuffle circuit 41 is a circuit that shuffles the data D2. The shuffle process is a process of changing the arrangement order of a plurality of data d2 arranged in parallel and included in the data D2. The shuffle circuit 41 shuffles data D2 to generate data D3. Shuffle circuit 41 outputs data D3 to shift circuit 42 . Data D3 is data having the first number of bits. The shuffle circuit 41 has a plurality (here, four) of shuffle circuits 41a to 41d (unit processing circuits), as shown in FIG. Each of the shuffle circuits 41a to 41d is a circuit that performs shuffle processing (linear processing) using unit data having the third bit number as a processing unit. Each of the shuffle circuits 41a to 41d changes the arrangement order of the N (here, N=4) data d2 included in the unit data. The shuffle circuits 41a-41d are arranged in parallel, and each of the shuffle circuits 41a-41d is assigned to one of the four conversion circuits 31 and the four conversion circuits 32. FIG.

Specifically, the shuffle circuit 41a is assigned to four conversion circuits 32, and shuffles four data d2 from the LSB to the 15th bit of the data D2 as unit data. The shuffle circuit 41a outputs the shuffle processing result as data d3a to the shift circuit 42a, which will be described later. The shuffle circuit 41a arranges the data d2 from the LSB to the 3rd bit of the data D2 in the 8th to 11th bit positions of the data d3a, and arranges the 4th to 7th bits of the data D2. are placed in the 12th to 15th bit positions in the data d3a. The shuffle circuit 41a arranges the data d2 of the 8th to 11th bits of the data D2 to the 3rd bit position from the LSB in the data d3a, and arranges the 12th to 15th bits of the data D2. are placed in the fourth to seventh bit positions in the data d3a.

The shuffle circuit 41b is assigned to the four conversion circuits 31, and shuffles the four data d2 from the 16th to 31st bits of the data D2 as unit data. The shuffle circuit 41b outputs the shuffle processing result as data d3b to the shift circuit 42b, which will be described later. The shuffle circuit 41c is assigned to the four conversion circuits 32, and shuffles the four data d2 from the 32nd to 47th bits of the data D2 as unit data. The shuffle circuit 41c outputs the shuffle processing result as data d3c to the shift circuit 42c, which will be described later. The shuffle circuit 41d is assigned to the four conversion circuits 31, and shuffles the four data d2 from the 48th bit to the MSB of the data D2 as unit data. The shuffle circuit 41d outputs the shuffle processing result as data d3d to the shift circuit 42d, which will be described later.

The data d3a to d3d are part of the data D3 and have the third bit number. Data d3a to d3d are data obtained by dividing all the data from LSB to MSB of data D3 in the order of the bit numbers in units of the third number of bits. In FIG. 2, data D3 is composed of data d3a to d3d. The shuffle circuits 41b to 41d change the arrangement order of the plurality of data d2 in the same manner as the shuffle circuit 41a, except that the plurality of (here, four) data d2 to be shuffled are different, so detailed description is omitted. do. In addition, in the shuffle circuits 41a to 41d shown in FIG. 2, 4-bit data are displayed together in one line.

The shift circuit 42 is a circuit that shifts the data D3. Shift processing is processing for shifting each of data d3a to d3d included in data D3 by a predetermined number of bits. The shift circuit 42 shifts the data D3 to generate the data D4. Shift circuit 42 outputs data D4 to XOR execution circuit 43 . Data D4 is data having the first number of bits. The shift circuit 42 has a plurality (here, four) of shift circuits 42a to 42d (unit processing circuits). Shift circuits 42a-42d are arranged in parallel and assigned to data d3a-d3d, respectively. Each of the shift circuits 42a to 42d performs left shift processing (linear processing) using unit data having the third bit number as a processing unit.

Specifically, the shift circuit 42a shifts the data d3a by 1 bit (left shift) using the data d3a as unit data. The left shift is a process of cyclically shifting all bits included in data to be shifted upward by a predetermined number of bits. The shift circuit 42a outputs the shift processing result as data d4a to the XOR operation circuits 43a and 43c, which will be described later. In the shift processing of the shift circuit 42a, for example, the bit located at the LSB in the data d3a is shifted to the first bit position in the data d4a, and the first bit in the data d3a is shifted to the second bit in the data d4a. and the 15th bit of data d3a is shifted to the LSB bit position of data d4a.

The shift circuit 42b shifts the data d3b to the left by 4 bits using the data d3b as unit data. The shift circuit 42b outputs the shift processing result as data d4b to the XOR operation circuit 43b, which will be described later. The shift circuit 42c shifts the data d3c to the left by 7 bits using the data d3c as unit data. The shift circuit 42c outputs the shift processing result as data d4c to the XOR operation circuit 43c, which will be described later. The shift circuit 42d shifts the data d3d to the left by 9 bits using the data d3d as unit data. The shift circuit 42d outputs the shift processing result as data d4d to the XOR operation circuits 43b and 43d, which will be described later. Data d4a to d4d are part of data D4 and have a third bit number. Data d4a to d4d are data obtained by dividing all the data from LSB to MSB of data D4 in the order of the bit numbers in units of the third number of bits. In FIG. 2, data D4 is composed of data d4a to d4d. In FIG. 2, data d3a to d3d and data d4a to d4d are shown by grouping 16-bit data into one line.

The XOR execution circuit 43 is a circuit that performs XOR operation processing on the data D4. The XOR execution circuit 43 generates data Dout by XORing data D4. The XOR execution circuit 43 outputs the data Dout as output data from the circuit section 10 . The XOR execution circuit 43 has a plurality (here, four) of XOR operation circuits 43a to 43d. The XOR operation circuits 43a-43d are arranged in parallel and assigned to data d4a-d4d, respectively. Each of the XOR operation circuits 43a-43d performs XOR operation processing (linear processing) on the data d4a-d4d.

Specifically, the XOR operation circuit 43c XORs the data d4a and the data d4c. The XOR operation circuit 43c outputs the operation result as data of the 32nd to 47th bits of the data Dout, and also outputs the operation result to the XOR operation circuit 43d. The XOR operation circuit 43b XORs the data d4b and the data d4d. The XOR operation circuit 43b outputs the operation result as data of the 16th to 31st bits of the data Dout, and also outputs the operation result to the XOR operation circuit 43a. The XOR operation circuit 43a XORs the data d4a and the operation result of the XOR operation circuit 43b. The XOR operation circuit 43a outputs the operation result as data from the LSB to the 15th bit of the data Dout. The XOR operation circuit 43d XORs the data d4d and the operation result of the XOR operation circuit 43c. The XOR operation circuit 43d outputs the operation result as data from the 48th bit to the MSB of the data Dout.

FIG. 3 is a diagram showing a modification of the digital processing device according to the first embodiment. A digital processing device 1A shown in FIG. 3 differs from the digital processing device 1 shown in FIG. Specifically, in the digital processing device 1A, the conversion circuits 31 are assigned to the four data d1 from the LSB to the 15th bit of the data D1. Conversion circuits 32 are assigned to the four data d1 from the 16th to 31st bits of the data D1. Conversion circuits 31 are assigned to the four data d1 from the 32nd to 47th bits of the data D1. Conversion circuits 32 are assigned to the four data d1 from the 48th bit to the MSB of the data D1.

Next, a method for manufacturing the digital processing device 1 will be described. Here, the case of using an FPGA as a programmable logic device will be described. A circuit unit 10 included in the digital processing device 1 is created using an FPGA. In manufacturing the digital processing device 1, first, a user such as a circuit designer creates a program in which the circuit functions of the circuit section 10 are described in a hardware description language. Then, the circuit section 10 is created on the FPGA by writing the circuit functions of the circuit section 10 to the FPGA based on a program using a dedicated tool or the like. Note that FPGAs in which circuit functions are not written are manufactured in advance. The manufacturing method of the digital processing device 1 includes a description process and a creation process.

The description step is a step of describing the functions of the circuit section 10 included in the digital processing device 1 according to the FPGA. Specifically, the circuit functions of the encrypted data generation unit 2, the processing unit 3, and the linear processing unit 4 are described in a hardware description language compatible with FPGA. A program describing circuit functions includes a first part for creating a plurality of conversion circuits 31 in FPGA and a second part for creating a plurality of conversion circuits 32 in FPGA. The circuit functions of the conversion circuit 31 and the conversion circuit 32 are described so that an output value is uniquely determined for an input value based on a truth table or the like.

Circuit functions of the plurality of conversion circuits 31 are described by a lookup table description method. That is, the first part of the program is described using the lookup table description method. Specifically, the value of 4-bit data d1 (input value) and the value of data d2 (output value) are expressed in hexadecimal, and all hexadecimal input values 0 to F (0000 to 1111 in binary) , the circuit function of each conversion circuit 31 is described so as to uniquely associate hexadecimal output values 0 to F with each. For example, the circuit function of each conversion circuit 31 is such that an input value of 2 (0010 in binary) is associated with an output value of B (1011 in binary), and an input value of 3 (0011 in binary) is associated with is described so as to correspond to 1 (0001 in binary) as an output value. Note that the input value and the output value may be uniquely associated by expressing the input value and the output value in decimal numbers.

Circuit functions of the plurality of conversion circuits 32 are described by a Boolean algebra description method. That is, the second part of the program is described using the Boolean algebra description method. Specifically, the circuit function of each conversion circuit 32 is described so that each bit of data d2 is represented by a Boolean algebra (logic operation expression) including a plurality of bits of data d1. Let data d1 be (x3, x2, x1, x0) in binary notation and data d2 be (y3, y2, y1, y0) in binary notation. is described by Boolean algebra as here,! represents negation (NOT) of xn (where n is 0 to 3), & represents a logical product (AND) operation, and | represents a logical sum (OR) operation. Similarly, the other bits y1, y2, and y3 of the output value are also described by Boolean algebra uniquely determined from each bit (x0, x1, x2, x3) of data d1.
y0=(!x3&!x2&x1)|(!x2&x1&x0)|(!x3&x2&!x1)|(x2&!x1&x0)|(x3&!x2&!x1&!x0)|(x3&x2&x1&!x0)...(1)

The circuit functions of the conversion circuit 31 and the conversion circuit 32 are described to output the same value of data d2 if the value of data d1 is the same. A program containing descriptions of circuit functions of the plurality of conversion circuits 31 and the plurality of conversion circuits 32 is also called a source file. A program describing circuit functions is stored in a storage medium such as a flexible disk, a CD-ROM (Compact Disc-Read only memory), a DVD (Digital Versatile Disc) or a ROM, or a semiconductor memory. Also, the above program may be provided via a network as a computer data signal superimposed on a carrier wave.

Subsequently, the circuit section 10 is created in the FPGA based on the circuit functions described in the above program (creation step). In the creation process, for example, a dedicated tool converts the above-described program into a netlist obtained by translating the hardware description language into an intermediate language. Then, write data (object file) for writing to the FPGA is created from the netlist. Then, by writing data for writing into the FPGA using a writing tool (configuration), the circuit section 10 including the processing section 3 and the linear processing section 4 is created in the FPGA. The digital processing device 1A is also manufactured in the same manner as the digital processing device 1. FIG.

Next, verification results of the effects of the digital processing apparatuses 1 and 1A according to the first embodiment will be described. Tables 1 and 2 show the verification results when sp6 (product name) manufactured by Xilinx was used as the FPGA. The first verification example is the verification result of the digital processing device 1 shown in FIG. The second verification example is the verification result of the digital processing device 1A shown in FIG. The first comparative example is a comparison result when all the conversion circuits of the processing unit 3 are created based on the lookup table description method. It is a comparison result when created based on the method. Each of the digital processing devices in the first verification example, the second verification example, the first comparative example, and the second comparative example includes 24 circuit units. Table 1 shows the verification results when each bit of the input data and output data of the digital processing device is not assigned to a specific input/output terminal on the FPGA (IO-Floated). Also, Table 2 shows the verification results when each bit of the input data and output data of the digital processing device is assigned to a specific input/output terminal on the FPGA (IO-Stuck). As an optimization option for circuit synthesis, in the case of IO-Floated, select the option that emphasizes operation speed, and in the case of IO-Stuck, select the option that emphasizes operation speed but also considers the balance with the mounting area. , verified.

Regarding the evaluation items in Table 1, "LUTs" are lookup tables that configure the logic blocks of the FPGA in order to realize the circuit configurations of the first verification example, the second verification example, the first comparative example, and the second comparative example. is used, and the unit is pcs. The "mounting area" indicates the mounting area of the circuit created in the FPGA, here, the number of used slices composed of a predetermined number of lookup tables and flip-flops of the FPGA, and the unit is the number of slices. "Operating speed" is the maximum frequency at which a digital processing device can operate, and is measured in megahertz (MHz). "Power consumption" indicates the power consumed by the circuit created on the FPGA at an operating speed of 10 MHz, and its unit is milliwatts (mW).

As shown in Tables 1 and 2, the number of lookup tables used on the FPGA was the same in the first verification example, the second verification example, the first comparative example, and the second comparative example. In the case of IO-Floated, the verification result of the first verification example shows that the mounting area is smaller than those of the first and second comparative examples, and the verification result of the second verification example shows that the operation speed is lower than that of the first and second comparative examples. It became faster than the second comparative example. On the other hand, in the case of IO-Stuck, the verification result of the first verification example shows that the mounting area is smaller than that of the first and second comparative examples, and the operating speed is lower than that of the first and second comparative examples. faster. Further, in the verification result of the second verification example, the mounting area was smaller than those of the first and second comparative examples, and the operating speed was faster than those of the first and second comparative examples.

In the case of IO-Floated, the verification results of the first verification example and the second verification example show that the power consumption is smaller than that of the first comparative example and the second comparative example, which consumes more power. On the other hand, in the case of the IO-Stuck, the verification result of the first verification example showed that the power consumption was smaller than that of the first comparative example and the second comparative example, which consumed a large amount of power. In the verification result of the second verification example, the power consumption was smaller than those of the first and second comparative examples. From the above, it can be seen that in the first verification example and the second verification example, the performance was improved without causing a large increase in power consumption as compared with the first comparative example and the second comparative example.

In such a digital processing device 1, 1A, each of the shuffle circuits 41a to 41d (unit processing circuits) and each of the shift circuits 42a to 42d (unit processing circuits) is four times the second number of bits (4 bits). Linear processing is performed using unit data having a certain third bit number (16 bits) as a processing unit. In the processing unit 3, four conversion circuits 31 or four conversion circuits 32 are assigned for each processing unit. In the processing unit 3, conversion circuits 31 and 32 created based on different description methods are mixed, and four conversion circuits 31 and 32 created based on the same description method are assigned to each processing unit. Various circuits created in FPGAs (programmable logic devices) are basically randomly distributed and arranged, but circuits based on the same description method tend to be arranged together. Therefore, by allocating the four conversion circuits 31 and 32 created based on the same description method for each processing unit, the possibility that the four conversion circuits 31 and 32 are arranged together increases. As a result, the mounting area of the circuit created in the FPGA can be reduced, or the processing speed of the circuit can be increased, so that the performance of the digital processing device can be improved.

The shuffle circuits 41a to 41d (unit processing circuits) change the arrangement order of the four data d2 (second partial data) included in the unit data. When the four conversion circuits 32 that supply the four pieces of data d2 processed by the shuffle circuit 41a are arranged in a distributed manner, the total wiring length from the four conversion circuits 32 to the shuffle circuit 41a is It can grow. On the other hand, since the four conversion circuits 32 that supply the four data d2 processed by the shuffle circuit 41a tend to be arranged together, the total wiring length is more likely to be reduced. As a result, the mounting area of the circuit created in the FPGA can be reduced, increasing the possibility of increasing the processing speed. The same applies to the shuffle circuits 41b-41d.

The shift circuits 42a-42d (unit processing circuits) shift the data d3a-d3d (unit data) by a predetermined number of bits. When the four conversion circuits 32 that supply the data d3a to be processed by the shift circuit 42a through the shuffle circuit 41a are arranged in a distributed manner, the data d3a from the four conversion circuits 32 are transmitted through the shuffle circuit 41a to the shift circuit 42a. There is a possibility that the total wiring length of the wiring up to is large. On the other hand, since the four conversion circuits 32 tend to be arranged together, the total wiring length is more likely to be reduced. As a result, the mounting area of the circuit created in the FPGA can be reduced, increasing the possibility of increasing the processing speed. The same applies to the shift circuits 42b-42d.

Each of the plurality of conversion circuits 31 (first conversion circuit) and each of the plurality of conversion circuits 32 (second conversion circuit) perform nonlinear conversion processing. Therefore, it is possible to make it difficult to guess the input data of the digital processing devices 1 and 1A from the output data of the digital processing devices 1 and 1A.

FIG. 4 is a diagram showing the configuration of a digital processing device according to the second embodiment. FIG. 5 is a diagram for explaining the array conversion processing of the array processing circuit of FIG. The digital processing device 5 shown in FIG. 4 is a device for performing cryptographic processing conforming to the PRINTcipher standard. The digital processing device 5 differs from the digital processing device 1 according to the first embodiment in that the first bit numbers of the input data and the output data are 48 bits, and instead of the processing unit 3 and the linear processing unit 4, , the processing unit 7 and the linear processing unit 6 are provided.

In the digital processing device 5, the encrypted data generation unit 2 XORs the data Din and the encryption key data, and outputs the operation result to the linear processing unit 6 as data D1. Data Din and D1 have a first number of bits. In this embodiment, the bit number of MSB in data Din is 47th. The same applies to data D1 and data D5, D6, D7, and Dout, which will be described later. The linear processing unit 6 linearly processes the data D1 and outputs the linear processing result to the processing unit 7 as data D7 (first data). Data D7 is data having the first number of bits. The linear processing unit 6 has an array conversion circuit 61 , an XOR execution circuit 62 and a permutation circuit 63 .

The array conversion circuit 61 is a circuit that performs array conversion processing (linear processing) on the data D1. Array conversion processing is processing for changing the array of a plurality of bits included in data D1. The array conversion circuit 61 generates data D5 by performing array conversion processing on the data D1. Array conversion circuit 61 outputs data D5 to XOR execution circuit 62 . Data D5 is data having the first number of bits.

As shown in FIG. 5, the array conversion circuit 61 arranges each bit from the 0th bit to the 15th bit number m in the data D1 at the (3×m)th bit position in the data D5. The array conversion circuit 61 arranges each bit of bit number m from 16th to 31st in data D1 to the {3×(m−16)+1}th bit position in data D5. The array conversion circuit 61 arranges each bit from the 32nd to 47th bit numbers m in the data D1 at the {3×(m−32)+2}th bit position in the data D5.

The XOR execution circuit 62 is a circuit that performs XOR operation processing on the data D5. The XOR execution circuit 62 generates data D6 by XORing data D5. XOR execution circuit 62 outputs data D6 to replacement circuit 63 . Data D6 is data having the first number of bits. The XOR execution circuit 62 has an XOR operation circuit 62a. The XOR operation circuit 62a is assigned to the data d51 from the LSB to the fifth bit of the data D5. The XOR operation circuit 62a performs XOR operation processing (linear processing) on the data d51. The XOR operation circuit 62a outputs the operation result to the replacement circuit 63 as data d61. The XOR execution circuit 62 outputs the data d52 from the 6th bit to the MSB of the data D5 as the data d62 to the replacement circuit 63 without changing the value.

Data d51 is a part of data D5 and has a third number of bits (here, 6 bits). Data d52 is a part of data D5. Data D5 is composed of data d51 and data d52. Data d61 is part of data D6 and has a third bit number. Data d62 is a part of data D6. Data D6 is composed of data d61 and data d62. Data d52 and data d62 have the same number of bits (here, 42 bits).

The XOR operation circuit 62a (unit processing circuit) XORs the data d51 and the round constant data. The XOR operation circuit 62a performs XOR operation processing (linear processing) using data d51 having a third bit number that is N times the second bit number (N is an integer equal to or greater than 2) as unit data. Note that N=2 in this embodiment. The round constant data is stored in advance in a memory (not shown), and is input from the memory to the XOR operation circuit 62a. The round constant data may be sequentially generated by a round constant generation circuit (not shown) and input from the round constant generation circuit to the XOR operation circuit 62a. Round constant data has a third bit number. The round constant data may have different values for each of the plurality of circuit units 10 included in the digital processing device 5 .

The replacement circuit 63 is a circuit that performs replacement processing on the data D6. The replacement process is a process of replacing the bit position of each bit included in the data having the second number of bits (here, 3 bits) in the data D6. The replacement circuit 63 replaces the data D6 to generate the data D7. The replacement circuit 63 outputs the data D7 to the processing section 7. FIG. Data D7 is data having the first number of bits. The replacement circuit 63 has a plurality of (here, 16) individual replacement circuits 64 . The plurality of individual replacement circuits 64 are arranged in parallel, and each of the plurality of individual replacement circuits 64 is assigned to each data having the second bit number in data D6 in order from the LSB. The individual replacement circuit 64 performs replacement processing (linear processing) on the data having the second number of bits in the data D6.

Specifically, the individual replacement circuit 64 replaces the bit position of each bit of the data input to the individual replacement circuit 64 according to the 2-bit round key. The round key is stored in advance in a memory (not shown) and is input to each individual permutation circuit 64 from the memory. The round key may be sequentially generated by a round key generation circuit (not shown) and input to each individual permutation circuit 64 from the round key generation circuit. The round key may have a different value for each of the multiple circuit units 10 included in the digital processing device 5 . The individual permutation circuit 64 changes how to permute the bit position of each bit according to the value of the round key. For example, if the value of the 2-bit round key is (0, 1), the individual permutation circuit 64 replaces the 3-bit data (p2, p1, p0) input to the individual permutation circuit 64 with the bit position of each bit. are replaced with the data (p1, p2, p0) that have been exchanged. When the value of the round key is (1, 0), the individual replacement circuit 64 replaces data (p2, p1, p0) with data (p2, p0, p1).

Each individual replacement circuit 64 performs replacement processing to generate data d7 (first partial data). Each individual replacement circuit 64 outputs the data d7 to the conversion circuit 31 or the conversion circuit 32 . Note that the data d7 is part of the data D7 and has the second number of bits. A plurality of data d7 is data obtained by dividing all data from LSB to MSB of data D7 in units of the second number of bits in order of bit numbers. In FIG. 4, data D7 is composed of 16 data d7.

The processing unit 7 is a circuit that converts data D7 into data Dout (second data). Data Dout is data having a first number of bits. Specifically, the processing unit 7 generates the data Dout by performing nonlinear conversion processing on the data D7. The processing unit 7 outputs the data Dout as output data from the circuit unit 10 . In the processing unit 7, a plurality of conversion circuits 31 (a plurality of first conversion circuits) and a plurality of conversion circuits 32 (a plurality of second conversion circuits) are arranged in parallel. Data d7 is input to each conversion circuit 31 and each conversion circuit 32 . Each of the plurality of conversion circuits 31 and each of the plurality of conversion circuits 32 converts the data d7 input thereto, whereby the processing unit 7 converts the data D7 into the data Dout.

Each conversion circuit 31 and each conversion circuit 32 generate data dout (second partial data) by performing conversion processing on data d7. Data dout has a second number of bits. The data dout is part of the data Dout. A plurality of data douts are data obtained by dividing all data from LSB to MSB of data Dout in units of the second number of bits in order of bit numbers. In FIG. 4, the data Dout is composed of 16 data douts.

In the processing unit 7, N (here, N=2) conversion circuits 31 out of the plurality of conversion circuits 31 for each data of a third bit number that is N times (here, N=2) the second bit number in the data D7 , or N (here, N=2) conversion circuits 32 out of the plurality of conversion circuits 32 are assigned. Specifically, in the processing unit 7, the conversion circuit 31 is assigned to each of the two data d7 from the LSB to the fifth bit of the data D7. A conversion circuit 31 is assigned to each of the two data d7 from the 6th to 11th bits of the data D7. A conversion circuit 31 is assigned to each of the two data d7 from the 12th to 17th bits of the data D7. Conversion circuits 31 are assigned to two pieces of data d7 from the 18th to 23rd bits of the data D7.

In the processing unit 7, the conversion circuit 32 is assigned to each of the two data d7 from the 24th to 29th bits of the data D7. Conversion circuits 32 are assigned to two pieces of data d7 from the 30th bit to the 35th bit of data D7. Conversion circuits 32 are assigned to two pieces of data d7 from the 36th to 41st bits of data D7. Conversion circuits 32 are assigned to two pieces of data d7 from the 42nd bit to the MSB of data D7.

FIG. 6 is a diagram showing a modification of the digital processing device according to the second embodiment. A digital processing device 5A shown in FIG. 6 differs from the digital processing device 5 shown in FIG. Specifically, in the digital processing device 5A, the conversion circuit 31 is assigned to each of the two data d7 from the LSB to the fifth bit of the data D7. A conversion circuit 32 is assigned to each of the two data d7 from the 6th to 11th bits of the data D7. A conversion circuit 31 is assigned to each of the two data d7 from the 12th to 17th bits of the data D7. Conversion circuits 32 are assigned to two data d7 from the 18th to 23rd bits of the data D7.

In the digital processing device 5A, conversion circuits 31 are assigned to two data d7 from the 24th to 29th bits of the data D7. Conversion circuits 32 are assigned to two pieces of data d7 from the 30th to 35th bits of data D7. Conversion circuits 31 are assigned to two pieces of data d7 from the 36th to 41st bits of data D7. Conversion circuits 32 are assigned to two pieces of data d7 from the 42nd bit to the MSB of data D7.

The digital processing devices 5 and 5A according to the second embodiment are manufactured using FPGAs, like the digital processing devices 1 and 1A according to the first embodiment. In the manufacture of the digital processing devices 5 and 5A, similarly to the manufacture of the digital processing devices 1 and 1A according to the first embodiment, the circuit functions of the circuit section 10 including the linear processing section 6 and the processing section 7 are described in a hardware description language. A written program is created.

Next, verification results of the effects of the digital processing devices 5 and 5A according to the second embodiment will be described. Tables 3 and 4 show the verification results when sp6 (product name) manufactured by Xilinx was used as the FPGA. The third verification example is the verification result in the digital processing device 5 shown in FIG. The fourth verification example is the verification result of the digital processing device 5A shown in FIG. The third comparative example is a comparison result when all the conversion circuits provided in the processing unit 7 are created based on the lookup table description method. It is a comparison result when created based on the method. Each of the digital processing devices in the third verification example, the fourth verification example, the third comparative example, and the fourth comparative example includes 48 circuit units. Table 3 shows the verification results for the IO-Floated case, and Table 4 shows the verification results for the IO-Stuck case. For both IO-Floated and IO-Stuck as optimization options for circuit synthesis, an option that emphasizes operation speed but also considers the balance with mounting area was selected and verified.

As shown in Tables 3 and 4, the number of lookup tables used on the FPGA was the same in the third verification example, the fourth verification example, the third comparative example, and the fourth comparative example. In the case of IO-Floated, the verification result of the third verification example shows that the mounting area is smaller than that of the third and fourth comparative examples, and the operation speed is faster than that of the third and fourth comparative examples. became. In the verification result of the fourth verification example, the mounting area was smaller than those of the third and fourth comparative examples, and the operating speed was faster than those of the third and fourth comparative examples. On the other hand, in the case of IO-Stuck, the verification result of the third verification example shows that the mounting area is smaller than that of the third and fourth comparative examples, and the operating speed is lower than that of the third and fourth comparative examples. faster. Also, in the verification result of the fourth verification example, the operating speed was faster than those of the third and fourth comparative examples.

In the case of IO-Floated, the verification result of the third verification example shows that the power consumption is smaller than that of the third comparative example and the fourth comparative example, which consumes a large amount of power. In the verification result of the fourth verification example, the power consumption was smaller than those of the third and fourth comparative examples. On the other hand, in the case of the IO-Stuck, the verification results of the third verification example and the fourth verification example showed that the power consumption was smaller than that of the third comparative example and the fourth comparative example. From the above, it can be seen that in the third verification example and the fourth verification example, the performance was improved without causing a large increase in power consumption as compared with the third comparative example and the fourth comparative example.

In such a digital processing device 5, 5A, the XOR operation circuit 62a (unit processing circuit) converts unit data having a third bit number (6 bits) which is twice the second bit number (3 bits) into a processing unit. Perform linear processing as In the processing unit 7, two conversion circuits 31 (first conversion circuits) or two conversion circuits 32 (second conversion circuits) are assigned for each processing unit in the XOR operation circuit 62a (unit processing circuit). In the processing unit 7, conversion circuits 31 and 32 created based on different description methods are mixed, and two conversion circuits 31 and 32 created based on the same description method are assigned to each processing unit. Various circuits created in FPGAs (programmable logic devices) are basically randomly distributed and arranged, but circuits based on the same description method tend to be arranged together. Therefore, by allocating two conversion circuits 31 and 32 created based on the same description method for each processing unit, the possibility that the two conversion circuits 31 and 32 are arranged together increases. As a result, the mounting area of the circuit created in the FPGA can be reduced, or the processing speed of the circuit can be increased, so that the performance of the digital processing device can be improved.

The XOR arithmetic circuit 62a (unit processing circuit) XORs the unit data and the data having the third bit number (round key). Data based on the processing result of the XOR operation circuit 62a is input to two conversion circuits 31 assigned for each processing unit. When these two conversion circuits 31 are arranged in a distributed manner, there is a possibility that the total wiring length of the wiring from the XOR operation circuit 62a to the two conversion circuits 31 via the replacement circuit 63 becomes large. be. On the other hand, since the two conversion circuits 31 tend to be arranged together, the total wiring length is more likely to be reduced. As a result, the mounting area of the circuit created in the FPGA can be reduced, increasing the possibility of increasing the processing speed.

Note that the digital processing device, the method for manufacturing the digital processing device, and the program according to the present invention are not limited to the above embodiments.

In the first embodiment and the second embodiment, the same total number of conversion circuits 31 and conversion circuits 32 are assigned to the processing units 3 and 7, but the present invention is not limited to this. If the processing units 3 and 7 include a plurality of conversion circuits 31 and a plurality of conversion circuits 32, the number of conversion circuits 31 and the number of conversion circuits 32 may not be the same.

Although the processing units 3 and 7 perform nonlinear conversion processing, the present invention is not limited to this. The processing unit 3 may perform linear conversion processing on the data D1, and the processing unit 7 may perform linear conversion processing on the data D7.

The unit processing circuits such as the shuffle circuits 41a to 41d may perform linear processing with unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more) as a processing unit, In the processing units 3 and 7, N conversion circuits 31 or N conversion circuits 32 may be assigned to each processing unit.

The digital processing devices 1, 1A, 5, and 5A are devices for performing cryptographic processing, but are not limited to this. The digital processors 1, 1A, 5, 5A may be signal processors that read the filter coefficients using a table lookup circuit. In addition, the digital processing devices 1, 1A, 5, and 5A may be devices provided with a circuit that performs table lookup processing for converting the value of input data into output data having a value different from the value of the input data.

1, 5... Digital processing unit, 3, 7... Processing unit, 4, 6... Linear processing unit, 31... Conversion circuit, 32... Conversion circuit.

Claims (10)

A digital processing device that is created using a programmable logic device and performs data conversion of input data,
a processing unit that converts first data having a first number of bits into second data having the first number of bits;
a linear processing unit that performs linear processing on the second data;
with
The processing unit includes a plurality of first conversion circuits created based on a program describing circuit functions using a lookup table, and a plurality of first conversion circuits created based on a program describing circuit functions using Boolean algebra. a second conversion circuit;
In the processing unit, at least a portion of the plurality of first conversion circuits and at least a portion of the plurality of second conversion circuits each use a different description method for various circuits created in a programmable logic device. are arranged together on the programmable logic device due to the property that circuits based on the same description method tend to be arranged together when they are mixed ,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits converts first partial data having a second number of bits of the first data to the second data of the second data. convert to second partial data having a number of bits;
The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more) as a processing unit,
In the processing unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are allocated for each processing unit,
Digital processing equipment. wherein the unit processing circuit changes the arrangement order of the N pieces of the second partial data included in the unit data;
2. Digital processing apparatus according to claim 1. The unit processing circuit shifts the unit data by a predetermined number of bits.
2. Digital processing apparatus according to claim 1. A digital processing device that is created using a programmable logic device and performs data conversion of input data,
a linear processing unit that performs linear processing on predetermined data and outputs first data having a first number of bits;
a processing unit that converts the first data into second data having the first number of bits;
with
The processing unit includes a plurality of first conversion circuits created based on a program describing circuit functions using a lookup table, and a plurality of first conversion circuits created based on a program describing circuit functions using Boolean algebra. a second conversion circuit;
In the processing unit, at least a portion of the plurality of first conversion circuits and at least a portion of the plurality of second conversion circuits each use a different description method for various circuits created in a programmable logic device. are arranged together on the programmable logic device due to the property that circuits based on the same description method tend to be arranged together when they are mixed ,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits converts first partial data having a second number of bits of the first data to the second data of the second data. convert to second partial data having a number of bits;
The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more) as a processing unit,
In the processing unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are allocated for each processing unit,
Digital processing equipment. wherein the unit processing circuit calculates an exclusive OR of the unit data and the data having the third number of bits;
5. Digital processing apparatus according to claim 4. Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits perform nonlinear conversion processing;
6. A digital processing apparatus according to any one of claims 1-5. a processing unit that has a plurality of first conversion circuits and a plurality of second conversion circuits and converts first data having a first number of bits into second data having the first number of bits; A method for manufacturing a digital processing device comprising a linear processing unit that performs linear processing,
a description step of describing circuit functions of the processing unit and the linear processing unit by a program according to a programmable logic device;
a creation step of creating the processing unit and the linear processing unit in the programmable logic device based on the circuit function;
with
The digital processing device is a device that performs data conversion of input data,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits converts first partial data having a second number of bits of the first data to the second data of the second data. convert to second partial data having a number of bits;
The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more) as a processing unit,
In the processing unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are allocated for each processing unit;
In the processing unit, at least a portion of the plurality of first conversion circuits and at least a portion of the plurality of second conversion circuits each use a different description method for various circuits created in a programmable logic device. are arranged together on the programmable logic device due to the property that circuits based on the same description method tend to be arranged together when they are mixed ,
In the description step, the circuit functions of the plurality of first conversion circuits are described by a program describing circuit functions using a lookup table, and the plurality of second conversion circuits are described by a program describing the circuit functions using Boolean algebra. the circuit function of the circuit is described,
A method of manufacturing a digital processing device. a linear processing unit that performs linear processing on predetermined data and outputs first data having a first number of bits; a plurality of first conversion circuits; and a plurality of second conversion circuits; A method of manufacturing a digital processing device comprising: a processing unit that converts to second data having a first number of bits,
a description step of describing circuit functions of the processing unit and the linear processing unit by a program according to a programmable logic device;
a creation step of creating the processing unit and the linear processing unit in the programmable logic device based on the circuit function;
with
The digital processing device is a device that performs data conversion of input data,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits converts first partial data having a second number of bits of the first data to the second data of the second data. convert to second partial data having a number of bits;
The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more) as a processing unit,
In the processing unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are allocated for each processing unit;
In the processing unit, at least a portion of the plurality of first conversion circuits and at least a portion of the plurality of second conversion circuits each use a different description method for various circuits created in a programmable logic device. are arranged together on the programmable logic device due to the property that circuits based on the same description method tend to be arranged together when they are mixed ,
In the description step, the circuit functions of the plurality of first conversion circuits are described by a program describing circuit functions using a lookup table, and the plurality of second conversion circuits are described by a program describing the circuit functions using Boolean algebra. the circuit function of the circuit is described,
A method of manufacturing a digital processing device. a processing unit that has a plurality of first conversion circuits and a plurality of second conversion circuits and converts first data having a first number of bits into second data having the first number of bits; A program for causing a programmable logic device to function as a digital processing device comprising a linear processing unit that performs linear processing,
a first portion for creating the plurality of first conversion circuits in the programmable logic device;
a second portion for creating the plurality of second translation circuits in the programmable logic device;
with
the first part describes circuit functions of the plurality of first conversion circuits using a lookup table;
wherein the second part describes circuit functions of the plurality of second transform circuits using Boolean algebra;
The digital processing device is a device that performs data conversion of input data,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits converts first partial data having a second number of bits of the first data to the second data of the second data. convert to second partial data having a number of bits;
The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more) as a processing unit,
In the processing unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are allocated for each processing unit;
In the processing unit, at least a portion of the plurality of first conversion circuits and at least a portion of the plurality of second conversion circuits each use a different description method for various circuits created in a programmable logic device. are arranged together on the programmable logic device due to the property that circuits based on the same description method tend to be arranged together when mixed;
program. a linear processing unit that performs linear processing on predetermined data and outputs first data having a first number of bits; a plurality of first conversion circuits; and a plurality of second conversion circuits; A program for causing a programmable logic device to function as a digital processing device, comprising a processing unit that converts to second data having a first bit number,
a first portion for creating the plurality of first conversion circuits in the programmable logic device;
a second portion for creating the plurality of second translation circuits in the programmable logic device;
with
the first part describes circuit functions of the plurality of first conversion circuits using a lookup table;
wherein the second part describes circuit functions of the plurality of second transform circuits using Boolean algebra;
The digital processing device is a device that performs data conversion of input data,
Each of the plurality of first conversion circuits and each of the plurality of second conversion circuits converts first partial data having a second number of bits of the first data to the second data of the second data. convert to second partial data having a number of bits;
The linear processing unit has a unit processing circuit that performs linear processing on unit data having a third bit number that is N times the second bit number (N is an integer of 2 or more) as a processing unit,
In the processing unit, N first conversion circuits out of the plurality of first conversion circuits or N second conversion circuits out of the plurality of second conversion circuits are allocated for each processing unit;
In the processing unit, at least a portion of the plurality of first conversion circuits and at least a portion of the plurality of second conversion circuits each use a different description method for various circuits created in a programmable logic device. are arranged together on the programmable logic device due to the property that circuits based on the same description method tend to be arranged together when mixed;
program.

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