JP7242360B2 - Receiver and test system - Google Patents

Description

An embodiment of the present invention relates to a receiver and a test system.

2. Description of the Related Art There is known a receiver that forms a reception beam pattern by a digital beam forming (DBF) method. A receiver that forms a receive beam pattern in the DBF method performs digital signal processing on each of the received signals received by a plurality of antenna elements. As one of tests to determine whether such a receiver operates normally, an operation test is performed to confirm whether or not digital signal processing for each received signal is operating in synchronism.

When performing an operation test by supplying test signals from the outside, it is necessary to branch the test signals in order to prepare the same number of test signals as the number of signals received by the receiver. The branching of the test signal and the amplification for compensating for the drop in signal level due to the branching may cause a phase shift between the test signals, which may affect the result of the operation test. A circuit such as a phase shifter is required to correct the phase shift caused by branching and amplification in order to suppress the influence on the operation test. As the number of signals received by the receiver increases, the scale of the circuit required for correction also increases, and the operation test may be burdensome and costly.

JP 2013-242151 A

A problem to be solved by the present invention is to provide a receiving device and a testing system that can more easily perform an operation test on a receiving device that forms a receiving beam pattern using the DBF method.

A receiver according to an embodiment has a plurality of demodulators, a test signal generator, a switch, and a memory. A plurality of demodulators demodulate each of the plurality of received signals. The test signal generator divides a test signal used for an operation test for determining whether or not the respective operations of the plurality of demodulators are synchronized by frequency-dividing a clock signal indicating the timing at which the demodulators operate . The phase of the test signal is initialized according to the input of the reference signal that generates the signal and synchronizes the operation of each of the plurality of demodulators. The switch switches whether to supply the test signal as a received signal to the plurality of demodulators. When the storage section and the switch supply the test signal to the plurality of demodulation sections, the demodulation results output from each of the plurality of demodulation sections are stored in synchronization with the clock signal.

1 is a block diagram showing a configuration example of a test system according to a first embodiment; FIG. FIG. 4 is a waveform diagram showing an operation example of the receiving device during an operation test in the first embodiment; FIG. 11 is a block diagram showing a configuration example of a test system according to a second embodiment; FIG.

Hereinafter, a receiving device and a test system according to embodiments will be described with reference to the drawings. In the following embodiments, it is assumed that constituent elements with the same reference numerals perform the same operations, and overlapping descriptions will be omitted as appropriate.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of a test system according to the first embodiment. The test system includes a receiving device 1 and a determining device 2 . The receiving device 1 includes a plurality of RF (Radio Frequency) switches 11 (11-1, ..., 11-N), a plurality of orthogonal demodulation units 12 (12-1, ..., 12-N), a reception beam combining unit 13, It comprises a filter 14 , an attenuator 15 , a test signal generator 16 and a data storage section 17 . The determination device 2 determines whether or not the operations of the plurality of quadrature demodulators 12 are synchronized based on the data stored in the data storage unit 17 of the receiver 1 .

A plurality of analog signals #1 to #N, a test signal, a clock signal CLK, a reference timing signal SYSREF, a trigger signal, and a save enable signal are input to the receiver 1 . The plurality of analog signals #1 to #N are signals obtained by subjecting signals received by the array antenna to signal processing including attenuation, amplification, and predetermined amount of phase shift of frequency components in unnecessary bands. be. For example, the analog signal corresponds to multiple antenna elements provided in an array antenna. The receiver 1 is provided with an RF switch 11 and a quadrature demodulator 12 corresponding to each of the analog signals #1 to #N input to the receiver 1 . Note that the method of acquiring the analog signal input to the receiving device 1 is not limited to these.

The test signal is a signal used for an operation test to determine whether the operations of the quadrature demodulators 12-1 to 12-N are synchronized. The clock signal CLK is a signal that indicates the timing at which the quadrature demodulator 12, the reception beam combiner 13, and the data storage unit 17 operate. The reference timing signal SYSREF is a signal that instructs to align operation timings in the receiver 1 . For example, the reference timing signal SYSREF instructs each quadrature demodulator 12 to initialize a frequency-divided clock signal (NCO) obtained by frequency-dividing the clock signal CLK. When the initialization is performed, the phase difference between the frequency-divided clock signals (NCO) of each quadrature demodulator 12 becomes 0 degree. The trigger signal and the storage enable signal are signals that control the operation of the data storage unit 17 .

The test signal generator 16 supplies the clock signal CLK and the reference timing signal SYSREF input from the outside of the receiver 1 to the quadrature demodulator 12 , the reception beam combiner 13 and the data storage 17 . Further, the test signal generator 16 divides the frequency of the clock signal CLK to generate test signals. The test signal generator 16 outputs the generated test signal to the outside via an output terminal provided in the receiver 1 . The test signal output to the outside is input to the receiver 1 through an input terminal provided in the receiver 1 and supplied to the filter 14 . That is, the generated test signal is supplied to the filter 14 after being output to the outside of the receiver 1 once.

By passing the test signal through the outside of the receiving device 1, the observability of the test signal used when performing the operation test of the receiving device 1 is improved, and monitoring during the operation test and verification of the operation test result can be easily performed. can be done. Note that the test signal generator 16 may directly supply the generated test signal to the filter 14 . Moreover, the test signal generator 16 may output the test signal to the outside and supply the test signal to the filter 14 without passing through the outside of the receiver 1 .

When the reference timing signal SYSREF is input, the test signal generator 16 initializes the phase of the test signal to a predetermined phase and then generates the test signal. The test signal generator 16 determines that the reference timing signal SYSREF has been input when the reference timing signal SYSREF changes to a predetermined level.

Filter 14 accepts a test signal input from the outside via an input terminal provided in receiver 1 . Filter 14 suppresses, in the test signal, harmonic components generated when clock signal CLK is frequency-divided, and supplies the test signal with the suppressed harmonic components to attenuator 15 . The attenuator 15 attenuates the signal level of the test signal supplied from the filter 14 to a predetermined signal level or less, and then supplies the test signal to each of the RF switches 11-1 to 11-N.

Note that the receiver 1 may not include the attenuator 15 when the signal level of the test signal supplied from the filter 14 is equal to or lower than a predetermined signal level. Further, in the configuration example shown in FIG. 1, the receiving device 1 has a configuration including one filter 14 and one attenuator 15, but the receiving device 1 corresponds to each of the RF switches 11-1 to 11-N. A filter 14 and an attenuator 15 may be provided. When the attenuator 15 is provided for each RF switch 11 , the amount of attenuation in the attenuator 15 may be variable, and variations in signal level between test signals supplied to each RF switch 11 may be reduced.

RF switch 11 - 1 receives analog signal # 1 and the test signal supplied from attenuator 15 . The RF switch 11-1 supplies the analog signal and the test signal to the quadrature demodulator 12-1. The RF switch 11-1 switches between the analog signal and the test signal to be supplied to the quadrature demodulator 12-1. The RF switch 11-1 mixes the analog signal and the test signal and supplies it to the quadrature demodulator 12-1, or supplies the analog signal to the quadrature demodulator 12-1 without mixing the test signal. can be switched. Each RF switch 11 operates similarly to the RF switch 11-1. Each RF switch 11 may switch whether or not to supply the test signal to the quadrature demodulator 12 according to the presence or absence of input of the test signal or according to the setting from the outside.

The quadrature demodulator 12 - 1 includes an NCO (Numerical Control Oscillator) 121 , an AD (Analog-Digital) converter 122 , a quadrature demodulator 123 and a thinning section 124 . The NCO 121 , AD converter 122 , quadrature demodulator 123 and thinning section 124 receive the clock signal CLK and the reference timing signal SYSREF supplied from the test signal generator 16 . The NCO 121 generates a frequency-divided clock signal (NCO) by frequency-dividing the clock signal CLK, and supplies the frequency-divided clock signal (NCO) to the quadrature demodulator 123 .

The AD converter 122 samples the signal supplied from the RF switch 11-1 in synchronization with the clock signal CLK. The AD converter 122 quantizes the sampled signal to generate a digital signal and supplies the digital signal to the quadrature demodulator 123 .

The quadrature demodulator 123 multiplies the digital signal by the frequency-divided clock signal (NCO) supplied from the NCO 121 and a signal obtained by shifting the phase of the frequency-divided clock signal (NCO) by 90 degrees, passes it through a low-pass filter, quadrature demodulation of an I (In-phase) signal and a Q (Quadrature-phase) signal that are different by 90 degrees. The quadrature demodulator 123 supplies the I signal and Q signal, which are demodulation results, to the thinning section 124 . The decimation unit 124 performs decimation according to the signal rate of the I signal and the Q signal required in the reception beam synthesis unit 13 in the subsequent stage, and the I signal and the Q signal are sent to the reception beam synthesis unit 13 and the data storage unit 17. supply to Each quadrature demodulator 12 has the same configuration as the quadrature demodulator 12-1 and operates in the same manner.

The reception beam synthesizing unit 13 forms a reception beam pattern using the DBF method. The reception beam synthesizing unit 13 multiplies the I and Q signals supplied from the quadrature demodulators 12-1 to 12-N by reception weights and synthesizes the signals. The reception weight is determined for each orthogonal demodulator 12-1 to 12-N according to the reception beam pattern formed by the array antenna. The reception beam synthesizing unit 13 multiplies the I signal and the Q signal by the reception weight and synthesizes them, thereby generating a reception beam signal corresponding to the reception beam pattern. The reception beam synthesizing unit 13 may simultaneously generate a plurality of reception beam signals corresponding to a plurality of beam patterns. The reception beam synthesizing unit 13 outputs the generated reception beam signals to the outside.

The data storage unit 17 includes an input I/F (Interface) 171 , a storage unit 172 and an output I/F 173 . The input I/F 171 receives the clock signal CLK, the reference timing signal SYSREF, the trigger signal and the save enable signal. The save enable signal is a signal for switching whether to record the I signal and the Q signal supplied from each quadrature demodulator 12 in the storage unit 172 . The trigger signal is a signal for instructing start of recording of the I signal and the Q signal.

When the storage enable signal instructs recording of the I and Q signals, the trigger signal instructs recording start, and the reference timing signal SYSREF instructs phase synchronization, the input I/F 171 is connected to each quadrature demodulator. 12 is stored in the storage unit 172 including the I signal and the Q signal. The input I/F 171 adds an identifier that uniquely identifies the quadrature demodulator 12 that supplies the I signal and the Q signal to the data stored in the storage unit 172 . That is, the storage unit 172 stores the I signal and the Q signal for each quadrature demodulator 12 so that they can be distinguished. The output I/F 173 outputs data stored in the storage unit 172 to the determination device 2 in response to a request from the determination device 2 . The input I/F 171 stores data including the I and Q signals when the save enable signal instructs recording of the I and Q signals and the reference timing signal SYSREF instructs phase synchronization. 172 may be stored.

The determination device 2 compares the I signal and Q signal of the quadrature demodulator 12 included in the data acquired via the output I/F 173 with the I signal and Q signal of the other quadrature demodulator 12, and determines the I signal and Determine whether the Q signals match. This determination is made for each quadrature demodulator 12 . If all the I and Q signals match, the decision device 2 decides that all the quadrature demodulators 12 are operating synchronously. That is, the determination device 2 determines that all the quadrature demodulators 12 are operating normally, and outputs information indicating that each quadrature demodulator 12 is operating normally as an operation test result.

If there are I and Q signals that do not match other I and Q signals, the determination device 2 determines that there is a quadrature demodulator 12 that does not operate in synchronization with other quadrature demodulators 12 . The determination device 2 acquires from the data the identifier of the quadrature demodulator 12 that outputs the I and Q signals that do not match the other I and Q signals. The determination device 2 outputs an identifier indicating the quadrature demodulator 12 that is not synchronized with other quadrature demodulators 12 as an operation test result.

The output of the operation test result by the determination device 2 may be in any format as long as the user using the test system can recognize the operation test result. For example, the determination device 2 displays a text indicating normal operation or a text indicating an identifier on the screen, or displays an image representing the quadrature demodulator 12 indicated by the identifier.

FIG. 2 is a waveform diagram showing an operation example of the receiver 1 during an operation test in the first embodiment. In the operation example shown in FIG. 2, the test signal is a signal obtained by dividing the frequency of the clock signal CLK by eight. The frequency-divided clock signal (NCO) supplied from the NCO 121 to the quadrature demodulator 123 in each quadrature demodulator 12 is a signal obtained by dividing the frequency of the clock signal CLK by four. Further, in the operation example, the operation is performed at the rising edge of the clock signal CLK. Note that the frequency division ratio for generating the test signal and the frequency-divided clock signal (NCO) may be other values. The frequency division ratio of the frequency-divided clock signal (NCO) may be determined according to the operating speed required of the receiver 1 and the like. The frequency division ratio of the test signal may be determined according to the frequency band of the analog signals #1 to #N to be processed by the receiving device 1. FIG.

When the reference timing signal SYSREF is input, the NCO 121 initializes the phase of the divided clock signal (NCO), and the test signal generator 16 initializes the phase of the test signal. The initialization of the phase starts synchronization (synchronization start) in which the phase of the frequency-divided clock signal (NCO) and the phase of the test signal have a fixed phase relationship. That is, the input of the reference timing signal SYSREF uniquely determines the phase relationship between the frequency-divided clock signal (NCO) and the test signal. When the input of the reference timing signal SYSREF is finished and the initialization of the phases of the frequency-divided clock signal (NCO) and the test signal is released (synchronization release), the operation starts at the timing indicated by the clock signal CLK.

After time t0, the test signal supplied from the RF switch 11 is converted into a digital signal by the AD converter 122. FIG. The digital signal is quadrature demodulated in a quadrature demodulator 123 using a divided clock signal (NCO). The I signal and Q signal obtained by orthogonal demodulation are supplied to the reception beam combining unit 13 and the data storage unit 17 after a predetermined number of signals are thinned out by the thinning unit 124 . In the operation example shown in FIG. 2, the thinning unit 124 performs thinning (decimation=4) to output one I/Q signal for every four I/Q signals.

When the trigger signal is input after the reference timing signal SYSREF has been input (time t0 to t1), the input I/F 171 receives signals from the quadrature demodulators 123 of the quadrature demodulators 12-1 to 12-N. The I signal and the Q signal obtained are stored in the storage unit 172 . In the operation example shown in FIG. 2, the I signal and Q signal (IQ1, IQ2, IQ3, . . . ) supplied after time t1 are stored in the storage unit 172 . In the operation example, the input I/F 171 causes the storage unit 172 to store the I signal and the Q signal that are continuous on the time axis. Note that the input I/F 171 may select the I signal and the Q signal to be stored in the storage unit 172 according to the trigger signal.

As illustrated in FIG. 2, the operations of the quadrature demodulators 12 are synchronized by initializing the phase of the frequency-divided clock signal (NCO) at the timing when the reference timing signal SYSREF is input. At the timing when the reference timing signal SYSREF is input, the phase of the test signal is also initialized, and the phase relationship between the test signal and the frequency-divided clock signal (NCO) becomes fixed. If each quadrature demodulator 12 operates synchronously, the I signal and the Q signal supplied at the same timing by each quadrature demodulator 12 match. The I signal and Q signal supplied by each quadrature demodulator 12 may change periodically according to the combination of the frequency division ratio of the test signal and the frequency division ratio of the frequency-divided clock signal (NCO). Even in this case, if each quadrature demodulator 12 operates synchronously, the I signal and Q signal of each quadrature demodulator 12 match.

Whether or not the quadrature demodulators 12 are operating synchronously can be determined by comparing the I and Q signals obtained at the same timing. The determination device 2 compares the I signal and the Q signal supplied at the same timing from each quadrature demodulation unit 12 stored in the storage unit 172 to determine whether each quadrature demodulation unit 12 is operating synchronously. judge.

In the test system according to the first embodiment, the test signal generator 16 initializes the phase of the test signal obtained by dividing the clock signal CLK used in the receiver 1 with the reference timing signal SYSREF. By using the test signal generated in this way, it becomes unnecessary to consider the phase shift of the test signal between the quadrature demodulators 12-1 to 12-N, and the operation of the quadrature demodulators 12-1 to 12-N is eliminated. It is possible to reduce the labor and cost required for the operation test to determine whether or not the devices are synchronized. In addition, the test system records and compares the demodulation results (I signal and Q signal) of each quadrature demodulator 12 to determine whether the operations of each quadrature demodulator 12 are synchronized. In order to perform such determination, even if the period of the test signal and the period of operation of each quadrature demodulator 12 are different and the demodulation result is different for each demodulation, the true value of the demodulation result is not required in advance. An operation test for each quadrature demodulator 12 can be performed. As described above, according to the test system of the first embodiment, it is possible to easily perform an operation test on the receiver 1 that forms a receive beam pattern using the DBF method.

Also, the test signal generator 16 can generate a test signal in a frequency band corresponding to the frequency band of the analog signal to be demodulated by the receiver 1 by changing the frequency division ratio when generating the test signal. Even if the frequency band of the test signal is changed, there is no need to change the configurations and operations of the quadrature demodulator 12, the data storage unit 17, and the determination device 2, and the operation test can be performed according to the usage conditions of the receiver 1. It can be done easily.

The function of synchronizing the quadrature demodulators 12 with the reference timing signal SYSREF is also used in the operation of the receiver 1 to generate a receive beam signal corresponding to the receive beam pattern. By using it, it is possible to suppress an increase in the circuit scale required for the operation test.

Note that in the first embodiment, as the determination of whether the quadrature demodulators 12 are operating in synchronism, the determination device 2 determines whether the I and Q signals of the quadrature demodulators 12 match. explained how it works. However, the determination is not limited to this, and other operations may be used for determination. For example, the determination device 2 may calculate the phase indicated by the combination of the I signal and the Q signal, and determine whether or not the phase difference between the quadrature demodulators 12 is equal to or less than a predetermined threshold. If there is another phase and a phase exceeding the threshold, the determination device 2 determines that the quadrature demodulator 12 corresponding to the phase is not synchronized with the other quadrature demodulators 12 .

Further, the determination device 2 adds a plurality of phases calculated from a plurality of I signals and Q signals for each quadrature demodulation unit, and determines whether the difference between the addition results of each quadrature demodulation unit 12 is equal to or less than a predetermined threshold. may be determined. If there is an addition result whose difference from other addition results exceeds the threshold, the determination device 2 determines that the quadrature demodulator 12 corresponding to the addition result is not synchronized with the other quadrature demodulators 12 . Since the deviation in the operation of the quadrature demodulator 12 is emphasized by phase addition (accumulation), the determination device 2 can improve the determination accuracy of the operation test.

Although the case where quadrature demodulation is performed as demodulation for analog signals and test signals has been described, a demodulator that performs demodulation other than quadrature demodulation may be provided in place of the quadrature demodulator 123 . Also, the receiving device 1 may include a data storage unit 17 for each orthogonal demodulation unit 12 .

(Second embodiment)
In the second embodiment, the handling of the test signal input by the receiver 1 is different from that in the first embodiment. In the first embodiment, as shown in FIG. 1, a configuration has been described in which the test signal generated by the test signal generator 16 of the receiver 1 is once output to the outside and then input. In the second embodiment, a signal output to the outside by another receiving device 1 is input.

FIG. 3 is a block diagram showing a configuration example of a test system according to the second embodiment. The test system in the second embodiment comprises a plurality of receivers 1 (1-1, 1-2, . . . , 1-N) and a determination device 2a. Each receiver 1 has the same configuration as the receiver 1 in the first embodiment. As described above, each receiving device 1 receives a test signal generated by another receiving device 1 instead of a test signal generated by itself. As shown in FIG. 3, receiver 1-1 supplies test signal #1 to receiver 1-2 and receives test signal #N from receiver 1-N.

Even if a test signal generated by another receiver 1 is used, by inputting the clock signal CLK and the reference timing signal SYSREF to each receiver 1, according to the input of the reference timing signal SYSREF, The phase of each test signal is initialized. When the reference timing signal SYSREF is input to each receiver 1, the phase difference between the test signals generated by each receiver 1 becomes zero. Furthermore, according to the input of the reference timing signal SYSREF, the phase of the frequency-divided clock signal (NCO) in each quadrature demodulator 12 of each of the receivers 1-1 to 1-N is initialized, and the frequency-divided clock signal (NCO) and the phase of each test signal have a definite phase relationship. Since the phases of the frequency-divided clock signal (NCO) and the test signal are initialized according to the input of the reference timing signal SYSREF, each receiver 1 operates in the same way as in the first embodiment even in the operation test. , the I signal and the Q signal supplied from each quadrature demodulation unit 12 are stored in the storage unit 172 .

The determining device 2a compares the I signal and the Q signal stored in the storage unit 172 of each receiving device 1 to determine whether or not the quadrature demodulators 12 in the plurality of receiving devices 1 are operating in synchronization. judge. For example, when the receiving device 1 is configured on one substrate and a large-scale receiving device using a plurality of substrates is configured, test signals are connected between the substrates (receiving device 1) as shown in FIG. By doing so, it is possible to determine whether or not the substrates are operating in synchronization with each other with higher accuracy. Further, by temporarily outputting the test signal to the outside, the observability of each test signal used in the operation test is enhanced and verification of the validity of the operation test is facilitated.

The receiving device 1 and the determining devices 2 and 2a in each of the above embodiments may be implemented by a hardware processor such as a DSP (Digital Signal Processor) or a CPU (Central Processing Unit) executing a program (software). . Some or all of the components included in the receiving device 1 and the determining devices 2 and 2a are LSI (Large Scale Integration circuit), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device) ) and the like.

According to at least one embodiment described above, the test signal is generated by dividing the clock signal indicating the timing at which the demodulator (the quadrature demodulator 12) operates, and the reference signal for synchronizing the operations of the plurality of demodulators is generated. A test signal generator (test signal generator 16) that initializes the phase of the test signal according to the input of (reference timing signal SYSREF), and switches whether to supply the test signal as a received signal to a plurality of demodulators. Having a switch (RF switch 11) and a storage unit for storing demodulation results output from each of the plurality of demodulators in synchronization with a clock signal when the switch supplies the test signal to the plurality of demodulators. Therefore, it is possible to more easily perform an operation test on a receiver that forms a reception beam pattern using the DBF method.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, as well as the scope of the invention described in the claims and equivalents thereof.

REFERENCE SIGNS LIST 1 receiver, 2 determination device, 11 RF switch, 12 quadrature demodulator, 13 reception beam combiner, 14 filter, 15 attenuator, 16 test signal generator, 17 data storage unit, 121... NCO, 122... AD converter, 123... Quadrature demodulator, 124... Decimation unit, 171... Input I/F, 172... Storage unit, 173... Output I/F

Claims (6)

a plurality of demodulation units that demodulate each of the plurality of received signals;
generating a test signal used in an operation test for determining whether or not the operations of the plurality of demodulators are synchronized by dividing a clock signal indicating timings at which the demodulators operate; a test signal generator for initializing the phase of the test signal according to the input of a reference signal for synchronizing the operations of the demodulators;
a switch for switching whether to supply the test signal as the received signal to the plurality of demodulators;
a storage unit that stores demodulation results output from each of the plurality of demodulators in synchronization with the clock signal when the switch supplies the test signal to the plurality of demodulators;
receiving device. The switch switches whether to supply the test signal once output to the outside of the receiving device as the received signal to the plurality of demodulators.
The receiving device according to claim 1. a frequency-divided clock signal generator that generates a frequency-divided clock signal obtained by frequency-dividing the clock signal, and initializes a phase of the frequency-divided clock signal according to the input of the reference signal;
The plurality of demodulators demodulate the plurality of received signals using the frequency-divided clock signal.
3. The receiver according to claim 1 or 2. a receiving device according to any one of claims 1 to 3 ;
comparing the demodulation results of the plurality of demodulation units stored in the storage unit, and determining whether or not there is a demodulation unit whose operation is not synchronized with other demodulation units among the plurality of demodulation units based on the comparison result a judgment device for judging;
A test system with a plurality of receivers according to claim 1;
comparing the demodulation results of each of the plurality of demodulators stored in the storage units of the plurality of receivers, and determining whether or not there is a demodulator whose operation is not synchronized with other demodulators among the plurality of demodulators a determination device that determines based on the result of the comparison;
with
The test signal generator supplies the generated test signal to another receiving device,
The switches of the plurality of receiving devices switch whether to supply the test signal supplied from another receiving device as the received signal to the plurality of demodulators of the own device,
test system. The storage unit stores a plurality of demodulation results for each demodulation unit,
The determination device adds the plurality of demodulation results for each of the demodulators, compares the addition results of each of the plurality of demodulators, and determines that operation of the plurality of demodulators is not synchronized with other demodulators. determining the presence or absence of the demodulator based on the result of the comparison;
6. A test system according to claim 4 or claim 5 .

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