JP7107436B2 - How to apply dicing tape - Google Patents

How to apply dicing tape Download PDF

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JP7107436B2
JP7107436B2 JP2021520024A JP2021520024A JP7107436B2 JP 7107436 B2 JP7107436 B2 JP 7107436B2 JP 2021520024 A JP2021520024 A JP 2021520024A JP 2021520024 A JP2021520024 A JP 2021520024A JP 7107436 B2 JP7107436 B2 JP 7107436B2
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wafer
dicing tape
mount stage
protective film
water
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一男 吉田
泰弘 松尾
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping

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  • Condensed Matter Physics & Semiconductors (AREA)
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Description

本発明はダイシングテープの貼付方法に関する。 The present invention relates to a method of attaching a dicing tape.

半導体ウエハを個々のデバイスにダイシングする際には、ウエハを裏返した後、マウントステージ上でウエハの位置合わせを行い、ウエハをマウントステージに真空吸着する。その後、ウエハとダイシングテープをローラーを用いて貼り合わせる。特許文献１には、一種類の表面保護テープで、外周余剰領域の幅が異なるウエハに汎用的に適用可能とすることができる表面保護テープの貼着方法が開示されている。 When the semiconductor wafer is diced into individual devices, after the wafer is turned over, the wafer is aligned on the mount stage and vacuum-sucked to the mount stage. After that, the wafer and the dicing tape are pasted together using a roller. Patent Literature 1 discloses a method of attaching a surface protection tape that can be applied to wafers having different widths of peripheral surplus regions with one type of surface protection tape.

日本特開２０１３－２４３３０８号公報Japanese Patent Application Laid-Open No. 2013-243308

ウエハにダイシングテープを貼り付ける際には、ウエハはマウントステージの方向に押し付けられる力を受ける。このとき、ウエハのうち回路パターンなどが形成されたデバイス面がマウントステージと接触すると、そのデバイス面がマウントステージに押し付けられ、ウエハの回路パターンが損傷したり、外観歩留が生じたり、信頼性が低下したりするおそれがあった。 When the dicing tape is attached to the wafer, the wafer receives a pressing force toward the mount stage. At this time, if the device surface of the wafer, on which circuit patterns and the like are formed, comes into contact with the mount stage, the device surface is pressed against the mount stage, damaging the circuit pattern of the wafer, reducing appearance yield, and reducing reliability. was likely to decline.

本発明は、上述のような課題を解決するためになされたもので、弊害を抑制しつつウエハにダイシングテープを貼り付けることができるダイシングテープの貼付方法を提供することを目的とする。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a dicing tape applying method capable of applying a dicing tape to a wafer while suppressing adverse effects.

本願の発明に係るダイシングテープの貼付方法は、回路パターンが形成された上面と、下面とを有するウエハの該上面の外縁部分に保護ブロックを貼り付けることと、該保護ブロックがマウントステージに接し、該上面が該マウントステージに接しない状態で、該下面にダイシングテープを貼り付けることと、を備え、前記保護ブロックは、前記上面の外縁に沿って複数設けられたことを特徴とする。
A method of attaching a dicing tape according to the invention of the present application includes attaching a protective block to an outer edge portion of the upper surface of a wafer having an upper surface on which a circuit pattern is formed and a lower surface, the protective block being in contact with a mount stage, affixing a dicing tape to the lower surface while the upper surface is not in contact with the mount stage; and a plurality of the protective blocks are provided along the outer edge of the upper surface .

本発明のその他の特徴は以下に明らかにする。 Other features of the invention will become apparent below.

本発明によれば、ウエハの上面がマウントステージに対向し、ウエハの上面がマウントステージに接しない状態でウエハの下面にダイシングテープを貼り付けるので、弊害を抑制しつつウエハにダイシングテープを貼り付けることができる。 According to the present invention, the dicing tape is applied to the lower surface of the wafer in a state in which the upper surface of the wafer faces the mount stage and the upper surface of the wafer does not touch the mount stage. be able to.

実施の形態１に係るウエハの平面図である。1 is a plan view of a wafer according to Embodiment 1; FIG. 実施の形態１に係るダイシングテープの貼付け方法を示す図である。FIG. 4 is a diagram showing a method of applying a dicing tape according to Embodiment 1; 実施の形態２に係るウエハの平面図である。8 is a plan view of a wafer according to Embodiment 2; FIG. 実施の形態２に係るダイシングテープの貼付け方法を示す図である。FIG. 10 is a diagram showing a method of attaching a dicing tape according to Embodiment 2;

本発明の実施の形態に係るダイシングテープの貼付方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。 A method of attaching a dicing tape according to an embodiment of the present invention will be described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and repetition of description may be omitted.

実施の形態１．
図１は、実施の形態１に係るウエハ１０の平面図である。ウエハ１０は、セル領域１０Ａと、セル領域１０Ａを囲む外縁部分１０Ｂを備えている。セル領域１０Ａと外縁部分１０Ｂの境界は破線で示されている。一例によれば、セル領域１０Ａに複数のデバイスが形成され、外縁部分１０Ｂにはデバイスが形成されない。ウエハ１０の上面１０ａには、回路パターンが形成され得る。ウエハ１０の上面１０ａには回路パターン又は回路パターンを覆う絶縁膜が露出し得る。Embodiment 1.
FIG. 1 is a plan view of a wafer 10 according to Embodiment 1. FIG. The wafer 10 comprises a cell area 10A and an outer edge portion 10B surrounding the cell area 10A. A boundary between the cell region 10A and the outer edge portion 10B is indicated by a dashed line. According to one example, multiple devices are formed in the cell area 10A and no devices are formed in the outer edge portion 10B. A circuit pattern may be formed on the upper surface 10 a of the wafer 10 . A circuit pattern or an insulating layer covering the circuit pattern may be exposed on the upper surface 10a of the wafer 10. FIG.

このようなウエハ１０の上面１０ａの外縁部分１０Ｂに保護ブロック１２を貼り付ける。保護ブロック１２は、上面１０ａの外縁に沿って複数設けることができる。図１には、複数の保護ブロック１２が上面１０ａの外縁に沿って等間隔に８個設けられたことが図示されている。別の例によれば、保護ブロック１２は環状の１つの部材とすることもできる。 A protective block 12 is attached to the outer edge portion 10B of the upper surface 10a of the wafer 10 as described above. A plurality of protection blocks 12 can be provided along the outer edge of the upper surface 10a. FIG. 1 shows that eight protective blocks 12 are provided at regular intervals along the outer edge of the upper surface 10a. According to another example, the protective block 12 can be an annular one-piece member.

図２は、図１のウエハ１０へのダイシングテープの貼付け方法を示す図である。まず、ウエハ１０の上面１０ａをマウントステージ２０に対向させつつ、ウエハ１０をマウントステージ２０にのせる。具体的には、保護ブロック１２がマウントステージ２０に接し、上面１０ａがマウントステージ２０に接しない。ウエハ１０をマウントステージ２０に乗せる際には必要に応じてウエハ１０の位置決めを行う。保護ブロック１２がマウントステージ２０に接した状態で、ウエハ１０の下面１０ｂにダイシングテープ２２を貼り付ける。ダイシングテープ２２を下面１０ｂに貼り付ける際には、貼付けローラー２４がダイシングテープ２２の上面を移動することで、ダイシングテープ２２を下面１０ｂに押し付ける。ダイシングテープ２２が貼り付けられたウエハ１０は、周知の方法でダイシングされる。 FIG. 2 is a diagram showing a method of attaching a dicing tape to the wafer 10 of FIG. First, the wafer 10 is placed on the mount stage 20 while the upper surface 10a of the wafer 10 faces the mount stage 20 . Specifically, the protection block 12 is in contact with the mount stage 20 and the upper surface 10 a is not in contact with the mount stage 20 . When the wafer 10 is placed on the mount stage 20, the wafer 10 is positioned as necessary. A dicing tape 22 is attached to the lower surface 10 b of the wafer 10 while the protective block 12 is in contact with the mount stage 20 . When applying the dicing tape 22 to the lower surface 10b, the application roller 24 moves on the upper surface of the dicing tape 22 to press the dicing tape 22 against the lower surface 10b. The wafer 10 to which the dicing tape 22 is attached is diced by a well-known method.

ダイシングテープ２２をウエハ１０に貼り付けるときに、保護ブロック１２がマウントステージ２０に接し、上面１０ａがマウントステージに接しない状態とすることで、ウエハ１０のセル領域１０Ａがマウントステージ２０に押し付けられることを回避できる。そのため、ウエハ１０の回路パターンが損傷したり、外観歩留が生じたり、信頼性が低下したりする弊害を抑制できる。 When the dicing tape 22 is attached to the wafer 10, the cell region 10A of the wafer 10 is pressed against the mount stage 20 by keeping the protection block 12 in contact with the mount stage 20 and the upper surface 10a not in contact with the mount stage 20. can be avoided. Therefore, it is possible to suppress adverse effects such as damage to the circuit pattern of the wafer 10, occurrence of appearance yield, and deterioration of reliability.

以下に実施の形態にかかるダイシングテープの貼付方法は実施の形態１との共通点が多いので実施の形態１との相違点を中心に説明する。 Since the dicing tape applying method according to the embodiment has many points in common with the first embodiment, differences from the first embodiment will be mainly described below.

実施の形態２．
図３は、実施の形態２に係るウエハ１０の平面図である。ウエハ１０の上面には、回路パターンが形成され得る。実施の形態２に係るダイシングテープの貼付方法では、ウエハ１０の上面に水溶性保護膜３０をコーティングする。図３には、ウエハ１０の上面の全体に水溶性保護膜３０が設けられたことが図示されている。ウエハ１０の上面の一部に水溶性保護膜をコーティングしてもよい。図３の円形の破線は、セル領域と外縁部分の境界を表す。水溶性保護膜３０は例えば、（株）ディスコ製のＨＯＧＯＭＡＸ（登録商標）、東京応化工業（株）製のＴＬＤＰ３００、又は日化精工（株）製のナノシェルターを採用し得る。水溶性保護膜３０としては、ウエハ１０より柔らかい任意の材料を採用し得る。Embodiment 2.
FIG. 3 is a plan view of wafer 10 according to the second embodiment. A circuit pattern may be formed on the upper surface of the wafer 10 . In the method of attaching the dicing tape according to the second embodiment, the upper surface of the wafer 10 is coated with the water-soluble protective film 30 . FIG. 3 illustrates that a water-soluble protective film 30 is provided over the entire top surface of the wafer 10 . A portion of the upper surface of the wafer 10 may be coated with a water-soluble protective film. A circular dashed line in FIG. 3 represents the boundary between the cell area and the outer edge portion. For the water-soluble protective film 30, for example, HOGOMAX (registered trademark) manufactured by DISCO Corporation, TLDP300 manufactured by Tokyo Ohka Kogyo Co., Ltd., or Nano Shelter manufactured by Nikka Seiko Co., Ltd. can be used. Any material that is softer than the wafer 10 can be used as the water-soluble protective film 30 .

図４は、図３のウエハ１０へのダイシングテープの貼付け方法を示す図である。水溶性保護膜３０がマウントステージ２０に接した状態で、ウエハ１０をマウントステージ２０にのせる。したがって、ウエハ１０とマウントステージ２０は直接接触していない。この状態で、ウエハ１０の下面１０ｂにダイシングテープ２２を貼り付ける。ダイシングテープ２２を下面１０ｂに貼り付ける際には、貼付けローラー２４がダイシングテープ２２の上面を移動することで、ダイシングテープ２２を下面１０ｂに押し付ける。このとき、ウエハ１０とマウントステージ２０の間には水溶性保護膜３０があるので、ウエハがマウントステージに接することで生じ得る回路パターンの損傷、外観歩留低下、又は信頼性低下を抑制できる。 4A and 4B are diagrams showing a method of attaching a dicing tape to the wafer 10 of FIG. The wafer 10 is placed on the mount stage 20 while the water-soluble protective film 30 is in contact with the mount stage 20 . Therefore, wafer 10 and mount stage 20 are not in direct contact. A dicing tape 22 is attached to the lower surface 10b of the wafer 10 in this state. When applying the dicing tape 22 to the lower surface 10b, the application roller 24 moves on the upper surface of the dicing tape 22 to press the dicing tape 22 against the lower surface 10b. At this time, since the water-soluble protective film 30 is present between the wafer 10 and the mount stage 20, it is possible to suppress damage to the circuit pattern, reduction in appearance yield, or reduction in reliability that may occur due to contact between the wafer and the mount stage.

水溶性保護膜３０がコーティングされたウエハ１０は、ダイシングテープ２２の貼付け後、例えばレーザダイシングによって複数のチップにダイシングされる。レーザダイシングでは、例えば、ウエハ１０の上面１０ａ側からウエハ１０にレーザ光を照射し、ウエハをダイシングする。このとき、ウエハ１０の上面１０ａが水溶性保護膜３０でコーティングされているため、当該上面１０ａの回路パターン等へのデブリを抑制できる。デブリとは、レーザダイシング中に被切断材料の表面材料が飛散して被切断材料の表面に異物として付着することである。 After the dicing tape 22 is attached, the wafer 10 coated with the water-soluble protective film 30 is diced into a plurality of chips by laser dicing, for example. In laser dicing, for example, laser light is applied to the wafer 10 from the upper surface 10a side of the wafer 10 to dice the wafer. At this time, since the upper surface 10a of the wafer 10 is coated with the water-soluble protective film 30, debris on the circuit pattern and the like on the upper surface 10a can be suppressed. Debris means that the surface material of the material to be cut scatters during laser dicing and adheres to the surface of the material to be cut as foreign matter.

レーザダイシングの後に、水溶性保護膜３０を液体で除去する。例えば水溶性保護膜３０が形成されたウエハ１０を水洗することで、水溶性保護膜３０を除去する。水溶性保護膜３０の除去をダイシング工程の一部に組み入れることができる。 After laser dicing, the water-soluble protective film 30 is removed with a liquid. For example, the water-soluble protective film 30 is removed by washing the wafer 10 on which the water-soluble protective film 30 is formed. Removal of the water-soluble protective film 30 can be incorporated as part of the dicing process.

別の例によれば、ウエハ１０の下面１０ｂにダイシングテープ２２を貼り付けた後に、水溶性保護膜３０を液体で除去することができる。水溶性保護膜３０を除去するタイミングは任意である。例えば、ダイシングソーを使ったダイシングを行う場合はデブリの問題がない。そのため、ダイシングテープ２２をウエハ１０に貼り付けた後、ダイシング前又はダイシング中に、水溶性保護膜３０を除去し得る。 According to another example, after applying the dicing tape 22 to the underside 10b of the wafer 10, the water-soluble protective film 30 can be removed with a liquid. The timing of removing the water-soluble protective film 30 is arbitrary. For example, when performing dicing using a dicing saw, there is no problem of debris. Therefore, after the dicing tape 22 is attached to the wafer 10, the water-soluble protective film 30 can be removed before or during dicing.

１０ ウエハ、 １０Ａ セル領域、 １０Ｂ 外縁部分、 １０ａ 上面、 １０ｂ 下面、 １２ 保護ブロック、 ２０ マウントステージ、 ２２ ダイシングテープ、 ２４ 貼付けローラー、 ３０ 水溶性保護膜 10 wafer 10A cell region 10B outer edge portion 10a upper surface 10b lower surface 12 protective block 20 mounting stage 22 dicing tape 24 pasting roller 30 water-soluble protective film

Claims (1)

回路パターンが形成された上面と、下面とを有するウエハの前記上面の外縁部分に保護ブロックを貼り付けることと、
前記保護ブロックがマウントステージに接し、前記上面が前記マウントステージに接しない状態で、前記下面にダイシングテープを貼り付けることと、を備え、
前記保護ブロックは、前記上面の外縁に沿って複数設けられたことを特徴とするダイシングテープの貼付方法。 affixing a protection block to an outer edge portion of the upper surface of a wafer having an upper surface on which a circuit pattern is formed and a lower surface;
affixing a dicing tape to the lower surface while the protective block is in contact with the mount stage and the upper surface is not in contact with the mount stage ;
A method of attaching a dicing tape , wherein a plurality of the protective blocks are provided along the outer edge of the upper surface .
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Citations (6)

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JP2003332271A (en) 2002-05-15 2003-11-21 Renesas Technology Corp Semiconductor wafer and method of manufacturing semiconductor device
JP2006135309A (en) 2004-10-07 2006-05-25 Showa Denko Kk Manufacturing method of semiconductor device
JP2006310338A5 (en) 2005-04-26 2008-04-10
WO2009147954A1 (en) 2008-06-06 2009-12-10 リンテック株式会社 Apparatus and method for attaching sheet
JP2011222843A (en) 2010-04-13 2011-11-04 Renesas Electronics Corp Method of manufacturing semiconductor device
JP2012174956A (en) 2011-02-23 2012-09-10 Mitsubishi Electric Corp Semiconductor device manufacturing method

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Publication number Priority date Publication date Assignee Title
JPH0536827A (en) * 1991-07-25 1993-02-12 Miyagi Oki Denki Kk Wafer stage
JP4143623B2 (en) * 2005-04-26 2008-09-03 Ｎｅｃエンジニアリング株式会社 Tape applicator
JP4808458B2 (en) * 2005-09-28 2011-11-02 株式会社ディスコ Wafer processing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003332271A (en) 2002-05-15 2003-11-21 Renesas Technology Corp Semiconductor wafer and method of manufacturing semiconductor device
JP2006135309A (en) 2004-10-07 2006-05-25 Showa Denko Kk Manufacturing method of semiconductor device
JP2006310338A5 (en) 2005-04-26 2008-04-10
WO2009147954A1 (en) 2008-06-06 2009-12-10 リンテック株式会社 Apparatus and method for attaching sheet
JP2011222843A (en) 2010-04-13 2011-11-04 Renesas Electronics Corp Method of manufacturing semiconductor device
JP2012174956A (en) 2011-02-23 2012-09-10 Mitsubishi Electric Corp Semiconductor device manufacturing method

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