JP7102482B2 - Memory system and control method - Google Patents

Description

An embodiment of the present invention relates to a technique for controlling a non-volatile memory.

In recent years, memory systems including non-volatile memory have become widespread.

As one of such memory systems, a solid state drive (SSD) based on NAND flash technology is known.

SSDs are also used as storage in data center servers. High I / O performance is required for storage used in a host computer such as a server. For this reason, new interfaces between hosts and storage have recently begun to be proposed.

Yiying Zhang, Outside, "De-indirection for flash-based SSDs with nameless writes." FAST. 2012, [online], [Search September 13, 2017], Internet <URL: https://www.usenix. org / system / files / conference / fast12 / zhang.pdf>

However, in general, the control of NAND flash memory is complicated, so when realizing a new interface for improving I / O performance, consider the appropriate division of roles between the host and storage (memory system). Is required to do.

An object to be solved by the present invention is to provide a memory system and a control method capable of improving I / O performance.

According to the embodiment, the memory system connectable to the host includes a non-volatile memory including a plurality of blocks, each of which is a unit of erasing operation, and a controller electrically connected to the non-volatile memory. The controller requests the writing of the first data, specifies the identifier of the domain to which the first data is to be written, and the logical address corresponding to the first data, and the first data is written. When a write command that does not specify the identifier of the block to be specified is received from the host, the domain associated with the specified identifier is selected from the plurality of domains, and the block belonging to the selected domain is selected. A first block in which the first data is to be written is assigned, and the first data is written in the first storage position in the first block. The controller notifies the host of the first storage position by using the identifier of the first block and the offset address in the first block.

The block diagram which shows the relationship between the host and the memory system (flash storage device) of embodiment. The figure for demonstrating the division of roles between a conventional SSD and a host, and the division of roles between a flash storage device and a host of the same embodiment. A block diagram showing a configuration example of a computer system in which data transfer between a plurality of hosts and a plurality of flash storage devices is executed via network devices. The block diagram which shows the configuration example of the memory system of the same embodiment. The block diagram which shows the relationship between the NAND interface provided in the memory system of the same embodiment, and a plurality of NAND type flash memory dies. The figure which shows the composition example of the super block constructed by the set of a plurality of blocks. The figure for demonstrating the write command applied to the memory system of the same embodiment. The figure for demonstrating the response to the write command of FIG. The figure for demonstrating the Trim command applied to the memory system of the same embodiment. The figure for demonstrating the block number and offset which define the physical address included in the response of FIG. The figure for demonstrating the relationship between the write operation executed in response to a write command and the return value contained in the response to this write command. The figure for demonstrating the writing operation which skips a bad page. Diagram to illustrate another example of a write operation that skips bad pages. Diagram to illustrate the operation of writing a logical address / data pair to a page in a block. The figure for demonstrating the operation of writing data to the user data area of a page in a block, and writing the logical address of this data to the redundant area of this page. The figure for demonstrating the relationship between a block number and an offset when a super block is used. A sequence chart showing a sequence of write operation processes executed by the host and the memory system of the same embodiment. The figure which shows the data update operation which writes the update data for the data which has already been written. The figure for demonstrating the operation of updating the block management table managed by the memory system of the same embodiment. The figure for demonstrating the operation of updating the look-up table (logical-physical address translation table) managed by a host. The figure for demonstrating the operation of updating the block management table in response to the notification from the host which shows the physical address corresponding to the data to be invalidated. The figure for demonstrating the read command applied to the memory system of the same embodiment. The figure for demonstrating the read operation performed by the memory system of the same embodiment. The figure for demonstrating the operation of reading the data part stored in each of the different physical storage positions according to the read command from a host. A sequence chart showing the sequence of read processing performed by the host and the memory system of the same embodiment. The figure for demonstrating the garbage collection (GC) control command applied to the memory system of the same embodiment. The figure for demonstrating the callback command for GC applied to the memory system of the same embodiment. A sequence chart showing the procedure of garbage collection (GC) operation performed by the memory system of the same embodiment. The figure for demonstrating the example of the data copy operation performed for garbage collection (GC). FIG. 29 is a diagram for explaining the contents of the host lookup table updated based on the result of the data copy operation of FIG. 29. The figure for demonstrating the relationship between the response to a write command and the callback processing for GC. The figure for demonstrating another example of the garbage collection (GC) control command applied to the memory system of the same embodiment. The figure for demonstrating another example of the callback command for GC applied to the memory system of the same embodiment. The figure for demonstrating the write / read / GC operation performed by the memory system of the same embodiment. The figure which shows the configuration example of the block management table for managing the reference count. The figure for demonstrating the duplicate command applied to the memory system of the same embodiment. The figure for demonstrating the Trim command for decrementing a reference count by one. A sequence chart showing reference count increment / decrement processing performed by the host and the memory system of the same embodiment.

Hereinafter, embodiments will be described with reference to the drawings.

First, the configuration of the computer system including the memory system according to the embodiment will be described with reference to FIG.

This memory system is a semiconductor storage device configured to write data to a non-volatile memory and read data from the non-volatile memory. This memory system is realized as a flash storage device 3 based on the NAND flash technology.

This computer system may include a host (host device) 2 and a plurality of flash storage devices 3. The host 2 may be a server configured to use a flash array composed of a plurality of flash storage devices 3 as storage. The host (server) 2 and the plurality of flash storage devices 3 are interconnected via the interface 50 (internal interconnection). The interface 50 for this internal interconnection is not limited to, but is limited to PCI Express (PCIe) (registered trademark), NVM Express (NVMe) (registered trademark), Ethernet (registered trademark), NVMe over Fabrics (NVMeOF). Etc. can be used.

A typical example of a server that functions as host 2 is a server in a data center.

In the case where the host 2 is realized by a server in the data center, the host (server) 2 may be connected to a plurality of end user terminals (clients) 61 via the network 51. The host 2 can provide various services to these end-user terminals 61.

Examples of services that can be provided by the host (server) 2 include (1) a platform as a service (PaaS) that provides a system development platform to each client (each end user terminal 61), and (2) a virtual server. There is an infrastructure as a service (IAaS), etc. that provides such an infrastructure to each client (each end user terminal 61).

A plurality of virtual machines may be executed on a physical server that functions as the host (server) 2. Each of these virtual machines running on the host (server) 2 can function as a virtual server configured to provide various services to a number of corresponding clients (end-user terminals 61).

The host (server) 2 includes a storage management function for managing a plurality of flash storage devices 3 constituting a flash array, and a front-end function for providing various services including storage access to each of the end user terminals 61. ..

In a conventional SSD, the block / page hierarchy of the NAND flash memory is hidden by the flash translation layer (FTL) in the SSD. That is, the FTL of the conventional SSD is (1) a function of managing the mapping between each logical address and each physical address of the NAND flash memory by using a lookup table that functions as a logical physical address conversion table. It has (2) a function for concealing read / write in page units and erasing operation in block units, and (3) a function for executing garbage collection (GC) of NAND flash memory. The mapping between each logical address and the physical address of the NAND flash memory is invisible to the host. The block / page structure of NAND flash memory is also invisible to the host.

On the other hand, a kind of address translation (application level address translation) may be performed on the host as well. This address translation uses an application-level address translation table to manage the mapping between each logical address for an application and each logical address for an SSD. Also, on the host, a kind of GC (application level GC) for changing the data arrangement on the logical address space is executed in order to eliminate the fragments generated on the logical address space for SSD.

However, in a redundant configuration in which the host and the SSD each have an address translation table (the SSD has a lookup table that functions as a logical physical address translation table, and the host has an application level address translation table), these address translations. A huge amount of memory resources are consumed to hold the table. Further, the double address translation including the address translation on the host side and the address translation on the SSD side also becomes a factor of lowering the I / O performance.

Further, the application level GC on the host side is a factor that increases the amount of data written to the SSD to several times (for example, twice) the amount of actual user data. Such an increase in the amount of data written does not increase the write amplification of the SSD, but it reduces the storage performance of the entire system and shortens the life of the SSD.

In order to solve such a problem, a measure has been proposed in which all the FTL functions of the conventional SSD are transferred to the host.

However, in order to implement this countermeasure, it is necessary for the host to directly handle the blocks and pages of the NAND flash memory. The capacity of the NAND flash memory is increasing for each generation of the NAND flash memory, and the block size / page size of the NAND flash memory is also different for each generation. Therefore, it is conceivable that the host 2 uses NAND flash memories having different block sizes and page sizes in a mixed manner. Dealing with different block / page sizes is difficult for the host. In addition, there may be an unpredictable number of bad pages (bad pages) that occur due to various manufacturing reasons, so the number of pages that can be practically used in a block differs from block to block. Is assumed, and the block size in the NAND flash memory may differ from block to block. Handling bad pages and non-uniform block sizes is even more difficult for hosts.

Therefore, in the present embodiment, the role of FTL is shared between the host 2 and the flash storage device 3. The host 2 manages a look-up table that functions as a logical-physical address translation table, but the selection of blocks to be used for writing is performed by the flash storage device 3 instead of the host 2. Also, GC is executed by the flash storage device 3 instead of the host 2. Hereinafter, the FTL function transferred to the host 2 will be referred to as a global FTL.

The global FTL of host 2 has a function to execute a storage service, a function to manage a look-up table (LUT), a wear control function, a function to realize high availability, and multiple duplicate data parts having the same contents in the storage. It may have a deduplication function, etc. that prevents it from being stored.

On the other hand, the flash storage device 3 can perform low level abstraction (LLA). LLA is a function for abstraction of NAND flash memory. LLA includes absorption of block size non-uniformity, absorption of block / page structure, functions to assist data placement, and the like. Functions that assist data placement include a function that determines the copy source block and copy destination block for garbage collection, a function that notifies the copy destination position of valid data to the upper layer (host 2), and a user data write destination. A function to determine the position (block number, position in this block), a function to notify the higher layer (host 2) of this writing destination position (block number, position in this block) in which user data is written, etc. include. In addition, LLA has a function of executing GC. Further, the LLA also has a QoS control function that executes resource management of the flash storage device 3 for each domain (QoS domain).

The QoS control function includes a function of determining an access unit for each QoS domain (or each block). The access unit indicates the minimum data size (Grain) that the host 2 can write / read. The flash storage device 3 supports a single or multiple access units (Grain), and the host 2 hosts each QoS domain (or block) if the flash storage device 3 supports multiple access units. ), The access unit to be used can be instructed to the flash storage device 3.

In addition, the QoS control function includes a function for preventing performance interference between QoS domains as much as possible. This function is basically a function for maintaining a stable latency.

In order to realize this, the flash storage device 3 classifies a large number of blocks in the NAND flash memory into a plurality of groups so that each of the large number of blocks in the NAND flash memory belongs to only one group. May be good. In this case, each group contains a plurality of blocks, but the same block is not shared by different groups. These plurality of groups function as the plurality of QoS domains described above.

Alternatively, the flash storage device 3 has a plurality of NAND flash memories in the flash storage device 3 so that each of the plurality of NAND flash memory dies in the flash storage device 3 belongs to only one group (one QoS domain). The dies may be classified into a plurality of groups (plurality of QoS domains). In this case, each group (QoS domain) contains a plurality of dies, but the same die is not shared by different QoS domains.

FIG. 2 shows the division of roles between the conventional SSD and the host and the division of roles between the flash storage device 3 and the host 2 of the present embodiment.

The left part of FIG. 2 shows the hierarchical structure of the entire computer system including the conventional SSD and the host that executes the virtual disk service.

On the host (server), the virtual machine service 101 for providing a plurality of virtual machines to a plurality of end users is executed. In each virtual machine on the virtual machine service 101, the operating system and user application 102 used by the corresponding end user is executed.

Further, on the host (server), a plurality of virtual disk services 103 corresponding to the plurality of user applications 102 are executed. Each virtual disk service 103 allocates a part of the capacity of the storage resource in the conventional SSD as a storage resource (virtual disk) for the corresponding user application 102. In each virtual disk service 103, application-level address conversion that converts an application-level logical address into an SSD logical address is also executed by using the application-level address conversion table. In addition, application level GC104 is also executed on the host.

The transmission of commands from the host (server) to the conventional SSD and the return of the command completion response from the conventional SSD to the host (server) are performed by the I / O queue 200 existing in each of the host (server) and the conventional SSD. Is executed through.

The conventional SSD includes a write buffer (WB) 301, a look-up table (LUT) 302, a garbage collection function 303, and a NAND flash memory (NAND flash array) 304. The conventional SSD manages only one look-up table (LUT) 302, and the resources of the NAND flash memory (NAND flash array) 304 are shared by a plurality of virtual disk services 103.

In this configuration, the write amplification is increased by the overlapping GC including the application level GC 104 under the virtual disk service 103 and the garbage collection function 303 (LUT level GC) in the conventional SSD. Further, in the conventional SSD, the frequency of GC increases due to an increase in the amount of data written from a certain end user or a certain virtual disk service 103, which causes I / O performance for another end user or another virtual disk service 103. Can cause a noisy neighbor problem of deterioration.

Also, the presence of duplicate resources, including the application level address translation table in each virtual disk service and the LUT 302 in the conventional SSD, consumes a lot of memory resources.

The right part of FIG. 2 shows the hierarchical structure of the entire computer system including the flash storage device 3 and the host 2 of the present embodiment.

On the host (server) 2, the virtual machine service 401 for providing a plurality of virtual machines to a plurality of end users is executed. Each virtual machine on the virtual machine service 401 runs the operating system and user application 402 used by the corresponding end user.

Further, on the host (server) 2, a plurality of I / O services 403 corresponding to the plurality of user applications 402 are executed. These I / O services 403 may include LBA-based block I / O services, key-value store services, and the like. Each I / O service 403 includes a look-up table (LUT) that manages the mapping between each logical address and each physical address of the flash storage device 3. Here, the logical address means an identifier that can identify the data to be accessed. This logical address may be a logical block address (LBA) that specifies a position in the logical address space, or it may be a key (tag) of a key value store.

In the LBA-based block I / O service, a LUT that manages the mapping between each logical address (LBA) and each physical address of the flash storage device 3 may be used.

In a key-value store service, the physical address of the flash storage device 3 in which each logical address (that is, a key-like tag) and the data corresponding to these logical addresses (that is, a key-like tag) are stored. A LUT that manages the mapping between each may be used. In this LUT, the correspondence between the tag, the physical address in which the data identified by the tag is stored, and the data length of this data may be managed.

Each end user can choose which addressing method to use (LBA, key-value store key, etc.).

Each of these LUTs does not translate each of the logical addresses from the user application 402 into each of the logical addresses for the flash storage device 3, but translates each of the logical addresses from the user application 402 into each of the physical addresses of the flash storage device 3. .. That is, each of these LUTs is a table in which a table for converting the logical address for the flash storage device 3 into a physical address and an application level address translation table are integrated (merged).

In the host (server) 2, the I / O service 403 exists for each of the above-mentioned QoS domains. The I / O service 403 belonging to a certain QoS domain is between each of the logical addresses used by the user application 402 in the corresponding QoS domain and each of the physical addresses of the blocks belonging to the resource group assigned to the corresponding QoS domain. Manage the mapping of.

The transmission of the command from the host (server) 2 to the flash storage device 3 and the return of the command completion response from the flash storage device 3 to the host (server) 2 are sent to each of the host (server) 2 and the flash storage device 3. It is executed via the existing I / O queue 500. These I / O queues 500 may also be classified into a plurality of queue groups corresponding to a plurality of QoS domains.

The flash storage device 3 includes a plurality of write buffers (WB) 601 corresponding to a plurality of QoS domains, a plurality of garbage collection (GC) functions 602 corresponding to a plurality of QoS domains, and a NAND flash memory (NAND flash array) 603. include.

In the configuration shown on the right side of FIG. 2, the LUT 302 in the conventional SSD and the application level address conversion table are merged as one LUT in the I / O service 403, so that the address conversion information can be stored. The amount of memory resources consumed by the service can be reduced. Further, since the number of address translation stages is reduced, the I / O performance can be improved.

Further, only the flash storage device 3 performs the data copy for the GC (Unified GC), not the duplicate GC including the application level GC and the LUT level GC. Therefore, it is possible to significantly reduce the write amplification of the entire system as compared with the configuration in which duplicate GCs are executed. As a result, the I / O performance can be improved and the life of the flash storage device 3 can be maximized.

FIG. 3 shows a modified example of the system configuration of FIG.

In FIG. 3, data transfer between the plurality of hosts 2A and the plurality of flash storage devices 3 is executed via the network device (here, the network switch 1).

That is, in the computer system of FIG. 3, the storage management function of the server 2 of FIG. 1 is transferred to the manager 2B, and the front-end function of the server 2 is transferred to a plurality of hosts (hosts for end user services) 2A. ..

The manager 2B manages a plurality of flash storage devices 3 and, in response to a request from each host (end user service host) 2A, supplies the storage resources of these flash storage devices 3 to each host (end user service host) 2A. Assign to.

Each host (end user service host) 2A is connected to one or more end user terminals 61 via a network. Each host (host for end user service) 2A manages a look-up table (LUT), which is the above-mentioned integrated (merged) logical and physical address translation table. Each host (host for end-user service) 2A uses its own LUT to manage only the mapping between each logical address used by the corresponding end user and each physical address of the resource assigned to it. do. Therefore, this configuration allows the system to be easily scaled out.

The global FTL of each host 2A has a function of managing a look-up table (LUT), a function of realizing high availability, a deduplication function, a QoS policy control function, and the like.

The manager 2B is a dedicated device (computer) for managing a plurality of flash storage devices 3. The manager 2B has a global resource reservation function for reserving storage resources for the capacity requested by each host 2A. Further, the manager 2B has a wear monitoring function for monitoring the degree of consumption of each flash storage device 3, a NAND resource allocation function for allocating reserved storage resources (NAND resources) to each host 2A, a QoS policy control function, and a global clock. It has a management function, etc.

Each flash storage device 3 has a local FTL. This local FTL is a function for coordinating with the global FTL of each host 2A. This local FTL has a QoS control function, a function to manage the write buffer of each QoS domain, a function to execute GC data copy within or between QoS domains, a LUT copy function for recovery, and deduplication (De-). It may include a function for managing the reference count used for deduplication), a workload analysis function, a housekeeping function, and the like.

According to the system configuration of FIG. 3, since the management of each flash storage device 3 is executed by the manager 2B, each host 2A sends an I / O request to one or more flash storage devices 3 assigned to itself. It is only necessary to execute the operation of performing the operation and the operation of receiving the response from the flash storage device 3. That is, the data transfer between the plurality of hosts 2A and the plurality of flash storage devices 3 is executed only through the switch 1, and the manager 2B is not involved in this data transfer. Further, as described above, the contents of the LUT managed by each of the hosts 2A are independent of each other. Therefore, since the number of hosts 2A can be easily increased, a scale-out type system configuration can be realized.

FIG. 4 shows a configuration example of the flash storage device 3.

The flash storage device 3 includes a controller 4 and a non-volatile memory (NAND flash memory) 5. The flash storage device 3 may also include a random access memory, for example, a DRAM 6.

The NAND flash memory 5 includes a memory cell array including a plurality of memory cells arranged in a matrix. The NAND flash memory 5 may be a NAND flash memory having a two-dimensional structure or a NAND flash memory having a three-dimensional structure.

The memory cell array of the NAND flash memory 5 includes a plurality of blocks BLK0 to BLKm-1. Each of the blocks BLK0 to BLKm-1 is organized by a large number of pages (here, pages P0 to Pn-1). The blocks BLK0 to BLKm-1 function as erasing units. Blocks are sometimes referred to as "erased blocks," "physical blocks," or "physical erase blocks." Each of pages P0 to Pn-1 contains a plurality of memory cells connected to the same word line. Pages P0 to Pn-1 are units of data writing operation and data reading operation.

The controller 4 is electrically connected to the NAND flash memory 5, which is a non-volatile memory, via a NAND interface 13 such as a Toggle or an open NAND flash interface (ONFI). The controller 4 is a memory controller (control circuit) configured to control the NAND flash memory 5.

As shown in FIG. 5, the NAND flash memory 5 includes a plurality of NAND flash memory dies. Each NAND flash memory die is a non-volatile memory die including a memory cell array including a plurality of blocks BLK and peripheral circuits for controlling the memory cell array. The individual NAND flash memory dies can operate independently. Therefore, the NAND flash memory die functions as a parallel operation unit. The NAND flash memory die is also referred to as a "NAND flash memory chip" or a "nonvolatile memory chip". In FIG. 5, 16 channels Ch1, Ch2, ... Ch16 are connected to the NAND interface 13, and the same number (for example, 2 dies per channel) of NAND type is connected to each of these channels Ch1, Ch2, ... Ch16. The case where each flash memory die is connected is illustrated. Each channel includes a communication line (memory bus) for communicating with the corresponding NAND flash memory die.

The controller 4 controls the NAND flash memory dies # 1 to # 32 via channels Ch1, Ch2, ... Ch16. The controller 4 can drive channels Ch1, Ch2, ... Ch16 at the same time.

The 16 NAND flash memory dies # 1 to # 16 connected to channels Ch1 to Ch16 may be organized as a first bank, and the remaining 16 NAND flashes connected to channels Ch1 to Ch16. Memory dies # 17 to # 32 may be organized as a second bank. A bank functions as a unit for operating a plurality of memory modules in parallel by bank interleave. In the configuration example of FIG. 5, a maximum of 32 NAND flash memory dies can be operated in parallel by 16 channels and bank interleave using two banks.

In the present embodiment, the controller 4 may manage a plurality of blocks (hereinafter, referred to as super blocks) each of which is composed of a plurality of blocks BLK, or may execute an erasing operation in units of super blocks. ..

The super block may include, but is not limited to, a total of 32 blocks BLK selected one by one from the NAND flash memory dies # 1 to # 32. Each of the NAND flash memory dies # 1 to # 32 may have a multiplane configuration. For example, when each of the NAND flash memory dies # 1 to # 32 has a multi-plane configuration including two planes, one super block corresponds to the NAND flash memory dies # 1 to # 32 64. It may contain a total of 64 block BLKs selected one by one from the planes. In FIG. 6, one super block SB is selected one by one from NAND flash memory dies # 1 to # 32, for a total of 32 blocks BLK (block BLK surrounded by a thick frame in FIG. 5). The case where it is composed of is illustrated.

As shown in FIG. 4, the controller 4 includes a host interface 11, a CPU 12, a NAND interface 13, a DRAM interface 14, and the like. The CPU 12, the NAND interface 13, and the DRAM interface 14 are interconnected via the bus 10.

The host interface 11 is a host interface circuit configured to execute communication with the host 2. The host interface 11 may be, for example, a PCIe controller (NVMe controller). The host interface 11 receives various requests (commands) from the host 2. These requests (commands) include write requests (write commands), read requests (read commands), and various other requests (commands).

The CPU 12 is a processor configured to control the host interface 11, the NAND interface 13, and the DRAM interface 14. The CPU 12 loads the control program (firmware) from the NAND flash memory 5 or a ROM (not shown) into the DRAM 6 in response to the power-on of the flash storage device 3, and executes the firmware to perform various processes. The firmware may be loaded on an SRAM (not shown) in the controller 4. The CPU 12 can execute command processing and the like for processing various commands from the host 2. The operation of the CPU 12 is controlled by the above-mentioned firmware executed by the CPU 12. Note that part or all of the command processing may be executed by the dedicated hardware in the controller 4.

The CPU 12 can function as a write operation control unit 21, a read operation control unit 22, and a GC operation control unit 23. The write operation control unit 21, the read operation control unit 22, and the GC operation control unit 23 are equipped with an application program interface (API) for realizing the system configuration shown on the right side of FIG.

The write operation control unit 21 receives a write request (write command) for specifying a logical address from the host 2. The logical address is an identifier that can identify the data to be written (user data), and may be, for example, an LBA or a tag such as a key of a key-value store. When the write command is received, the write operation control unit 21 first determines a block to write data from the host 2 (write destination block) and a position in this block (write destination position). Next, the write operation control unit 21 writes the data (write data) from the host 2 to the write destination position of the write destination block. In this case, the write operation control unit 21 can write not only the data from the host 2 but also both this data and the logical address of this data to the write destination block.

Then, the write operation control unit 21 returns the designated logical address and the physical address indicating the position (physical storage position) in the NAND flash memory 5 in which the data (write data) is written to the host 2.

In this case, the physical address is represented by (1) the block number of the write-destination block and (2) an offset within the block indicating the write-destination position in the write-destination block. The block number is an identifier that specifies the block in which the data is written. As the block number, various values that can uniquely identify any one in a plurality of blocks can be used.

The in-block offset indicates the offset from the beginning of the write-destination block to the write-destination position, that is, the offset of the write-destination position with respect to the beginning of the write-destination block. The size of the offset from the beginning of the write-to block to the write-to position is indicated by a multiple of the grain size having a size different from the page size. Particle size is the above-mentioned access unit. The maximum size of the grain size is limited to the block size. In other words, the intra-block offset indicates the offset from the beginning of the write-to block to the write-to position as a multiple of the particle size having a size different from the page size.

The grain size may have a size smaller than the page size. For example, if the page size is 16 Kbytes, the grain size may be 4 Kbytes. In this case, in one block, a plurality of offset positions each having a size of 4 Kbytes are defined. The in-block offset corresponding to the first offset position in the block is, for example, 0, and the in-block offset corresponding to the next offset position in the block is, for example, 1, which corresponds to the next offset position in the block. The offset within the block to be used is, for example, 2.

Alternatively, the grain size may have a size larger than the page size. For example, the grain size may be several times the page size. If the page size is 16 Kbytes, the particle size may be 32 Kbytes in size.

In this way, the write operation control unit 21 determines both the block to which the data should be written and the position in the block by itself, and as a physical address indicating the position where the data (user data) from the host 2 is written. , Notify host 2 of block number and intra-block offset, not block number and page number. As a result, the host 2 can write the user data to the NAND flash memory 5 without being aware of the block size, the page write order constraint, the bad page, the page size, etc., and further, by the block number and the offset in the block. The represented physical address can be mapped to the logical address of this user data.

When the read operation control unit 22 receives a read request (read command) for specifying a physical address (that is, a block number and an intra-block offset) from the host 2, the NAND flash memory is based on the block number and the intra-block offset. Read the data from 5. The block to be read is specified by the block number. The physical storage position of the read target in this block is specified by the offset in the block. By using this intra-block offset, the host 2 does not need to handle different page sizes for each generation of NAND flash memory.

In order to obtain the physical storage position of the read target, the read motion control unit 22 first divides this offset in the block by the number of grain sizes representing the page size (here, 4), and then the quotient obtained by this division. And the remainder may be determined as the page number of the read target and the in-page offset of the read target, respectively.

When the GC operation control unit 23 executes garbage collection of the NAND flash memory 5, the copy source block (GC source block) and copy destination block (GC destination block) for the garbage collection are converted into the NAND flash memory 5 by the NAND flash memory 5. Choose from a large number of blocks in. In this case, the GC operation control unit 23 usually selects a plurality of copy source blocks (GC source blocks) and one or more copy destination blocks (GC destination blocks). The condition (GC policy) for selecting the copy source block (GC source block) may be specified by the host 2. For example, a GC policy may be used in which the block having the smallest amount of valid data is preferentially selected as a copy source block (GC source block), or another GC policy may be used. As described above, the selection of the copy source block (GC source block) and the copy destination block (GC destination block) is executed not by the host 2 but by the controller 4 (GC operation control unit 23) of the flash storage device 3. The controller 4 may manage the amount of effective data of each block by using each block management table.

When a command (GC control command) for specifying a copy source group (source QoS domain) and a copy destination group (destination QoS domain) of garbage collection is received from the host 2, the GC operation control unit 23 belongs to the copy source group. Select the copy source block of the garbage collection from the block group, and select the copy destination block of the garbage collection from the block group belonging to the copy destination group.

Management of valid / invalid data may be performed using the block management table 32. The block management table 32 may exist for each block, for example. In the block management table 32 corresponding to a certain block, a bitmap flag indicating valid / invalidity of each data in the block is stored. Here, the valid data means the data referred to by the LUT (that is, the data associated with the latest data from the logical address), which may be read from the host 2 later. .. Invalid data means data that can no longer be read from host 2. For example, data associated with a logical address is valid data, and data not associated with any logical address is invalid data.

The GC operation control unit 23 determines the position (copy destination position) in the copy destination block (GC destination block) to which the valid data stored in the copy source block (GC source block) should be written, and determines the position (copy destination position) of the valid data. Copy to this determined position (copy destination position) of the copy destination block (GC destination block). In this case, the GC operation control unit 23 may copy both the valid data and the logical address of the valid data to the copy destination block (GC destination block). The GC operation control unit 23 may specify valid data in the GC source block by referring to the block management table 32 corresponding to the copy source block (GC source block). Alternatively, in another embodiment, management of valid / invalid data may be performed by host 2. In this case, the GC operation control unit 23 receives information indicating the validity / invalidity of each data in the GC source block from the host 2, and identifies the valid data in the GC source block based on the received information. You may.

Then, the GC operation control unit 23 includes the logical address of the copied valid data, the block number of the copy destination block (GC destination block), and the copy destination block (GC destination block) from the beginning to the copy destination position. The host 2 is notified of the in-block offset, which indicates the offset as a multiple of the above-mentioned grain size.

In the present embodiment, as described above, the write operation control unit 21 can write both the data (write data) from the host 2 and the logical address from the host 2 to the write destination block. Therefore, the GC operation control unit 23 can easily obtain the logical address of each data in the copy source block (GC source block) from the copy source block (GC source block), so that the copied valid data can be obtained. The logical address of is easily notified to the host 2.

The NAND interface 13 is a memory control circuit configured to control the NAND flash memory 5 under the control of the CPU 12. The DRAM interface 14 is a DRAM control circuit configured to control the DRAM 6 under the control of the CPU 12. A part of the storage area of the DRAM 6 is used for storing the write buffer (WB) 31. In addition, the other part of the storage area of the DRAM 6 is used for storing the block management table 32. The write buffer (WB) 31 and the block management table 32 may be stored in an SRAM (not shown) in the controller 4.

FIG. 7 shows a write command applied to the flash storage device 3.

The write command is a command that requests the flash storage device 3 to write data. This write command may include a command ID, a QoS domain ID, a logical address, a length, and the like.

The command ID is an ID (command code) indicating that this command is a write command, and the write command includes a command ID for the write command.

The QoS domain ID is an identifier that can uniquely identify the QoS domain to which the data should be written. The write command sent from the host 2 in response to a write request from an end user may include a QoS domain ID that specifies the QoS domain corresponding to this end user. The namespace ID may be treated as a QoS domain ID.

The logical address is an identifier for identifying the write data to be written. This logical address may be an LBA or a key-value store key, as described above. When the logical address is LBA, the logical address (start LBA) included in this write command indicates the logical position (first logical position) in which the write data should be written.

The length indicates the length of the write data to be written. This length (data length) may be specified by the number of grains, the number of LBAs, or its size may be specified by bytes.

As described above, the controller 4 groups a large number of blocks in the NAND flash memory 5 into a plurality of groups (a plurality of QoS domains) so that each of the large number of blocks in the NAND flash memory 5 belongs to only one group. Can be classified into. Then, the controller 4 can manage the free block list (free block pool) and the active block list (active block pool) for each group (QoS domain).

The state of each block is roughly divided into an active block that stores valid data and a free block that does not store valid data. Each block that is an active block is managed by the active block list. On the other hand, each block that is a free block is managed by a free block list.

When a write command is received from the host 2, the controller 4 determines a block in which data from the host 2 should be written (write destination block) and a position in the write destination block (write destination position). The controller 4 may determine one of the free block groups belonging to the QoS domain corresponding to the QoS domain ID as the write destination block. The writing destination position is determined in consideration of the restrictions on the page writing order, bad pages, and the like. Then, the controller 4 writes the data from the host 2 to the write destination position in the write destination block.

If the entire write-destination block is filled with user data, the controller 4 moves the write-destination block to the active block list (active block pool). Then, the controller 4 selects the free block again from the free block list corresponding to the QoS domain, and assigns the selected free block as a new write destination block.

If the number of remaining free blocks managed by the free block list drops below the threshold set by a predetermined policy, or if host 2 instructs to perform garbage collection, the controller 4 will be in this QoS domain. Garbage collection may be started.

In this QoS domain garbage collection, the controller 4 selects a copy source block (GC source block) and a copy destination block (GC destination block) from the active block group corresponding to this QoS domain. Which block is selected as the GC candidate (copy source block) may be determined according to the above-mentioned policy specified by the host 2, or may be specified by the host 2. When the policy is also based, for example, the block with the smallest amount of valid data may be selected as the GC candidate (copy source block).

FIG. 8 shows the response to the write command of FIG.

This response includes a logical address, a physical address, and a length.

The logical address is the logical address included in the write command of FIG.

The physical address indicates the physical storage position in the NAND flash memory 5 in which the data is written in response to the write command of FIG. 7. In the present embodiment, this physical address is specified not by the combination of the block number and the page number but by the combination of the block number and the offset (intra-block offset) as described above. The block number is an identifier that can uniquely identify any one of all the blocks in the flash storage device 3. If different block numbers are assigned to all blocks, these block numbers may be used directly. Alternatively, the block number may be represented by a combination of the die number and the block number in the die. The length indicates the length of the write data to be written. This length (data length) may be specified by the number of grains, the number of LBAs, or its size may be specified by bytes.

FIG. 9 shows a Trim command applied to the flash storage device 3.

This Trim command is a command that includes a block number indicating a physical storage position in which data to be invalidated is stored and an offset within the block. That is, this Trim command can specify a physical address instead of a logical address like LBA. This Trim command includes a command ID, a physical address, and a length.

The command ID is an ID (command code) indicating that this command is a Trim command, and the Trim command includes a command ID for the Trim command.

The physical address indicates the first physical storage location where the data to be invalidated is stored. In the present embodiment, this physical address is specified by a combination of a block number and an offset (intra-block offset).

The length indicates the length of data to be invalidated. This length (data length) may be specified by the number of grain sizes or by bytes.

The controller 4 manages a flag (bitmap flag) indicating validity / invalidity of each data included in each of the plurality of blocks by using the block management table 32. When a Trim command including a block number indicating a physical storage position in which data to be invalidated is stored and an offset (intra-block offset) is received from the host 2, the controller 4 updates the block management table 32 and Trim. Change the flag (bitmap flag) corresponding to the data of the physical storage position corresponding to the block number and the offset in the block included in the command to a value indicating invalidity.

FIG. 10 shows the block numbers and offsets that define the physical address.

The block number specifies one block BLK. Each block BLK includes a plurality of pages (here, pages 0 to n) as shown in FIG.

In the case where the page size (user data storage area of each page) is 16 Kbytes and the particle size (Grain) is 4 KB, this block BLK is logically divided into 4 × (n + 1) areas. To.

Offset +0 indicates the first 4KB area of page 0, offset +1 indicates the second 4KB area of page 0, offset +2 indicates the third 4KB area of page 0, and offset +3 indicates the fourth 4KB area of page 0. The 4KB region is shown.

Offset +4 indicates the first 4KB area of page 1, offset +5 indicates the second 4KB area of page 1, offset +6 indicates the third 4KB area of page 1, and offset +7 indicates the fourth 4KB area of page 1. The 4KB region is shown.

FIG. 11 shows the relationship between the write operation executed in response to the write command and the return value included in the response to the write command.

The controller 4 of the flash storage device 3 manages a free block group that does not contain valid data by a free block list, selects one block (free block) from these free block groups, and writes the selected block to the write destination block. Assign as. Now, assume that block BLK # 1 is assigned as a write-destination block. The controller 4 writes data to the block BLK # 1 in the order of page 0, page 1, page 2, ... Page n.

In FIG. 11, a write command for specifying the logical address (LBAx) and the length (= 4) is received from the host 2 in a state where 16 Kbytes of data has already been written on page 0 of the block BLK # 1. Is expected. The controller 4 determines the page 1 of the block BLK # 1 as the write destination position, and writes the write data for 16 Kbytes received from the host 2 to the page 1 of the block BLK # 1. Then, the controller 4 returns a response (logical address, block number, offset (intra-block offset), length) to this write command to the host 2. In this case, the logical address is LBAx, the block number is BLK # 1, the offset (intra-block offset) is +5, and the length is 4.

FIG. 12 shows a writing operation for skipping a defective page (bad page).

In FIG. 12, a write command for specifying the logical address (LBAx + 1) and the length (= 4) is received from the host 2 while the data has already been written on the pages 0 and 1 of the block BLK # 1. The case is assumed. If the page 2 of the block BLK # 1 is a bad page, the controller 4 determines the page 3 of the block BLK # 1 as the write destination position, and blocks 16 Kbytes of write data received from the host 2 BLK. Write on page 3 of # 1. Then, the controller 4 returns a response (logical address, block number, offset (intra-block offset), length) to this write command to the host 2. In this case, the logical address is LBAx + 1, the block number is BLK # 1, the offset (intra-block offset) is +12, and the length is 4.

FIG. 13 shows another example of a write operation that skips bad pages.

In FIG. 13, it is assumed that data is written over two pages sandwiching a defective page. Now, it is assumed that the data has already been written to the pages 0 and 1 of the block BLK # 2, and the unwritten 8 Kbytes of write data remains in the write buffer 31. In this state, if a write command for specifying the logical address (LBAy) and length (= 6) is received, the controller 4 receives unwritten 8 Kbyte write data and 24K newly received from the host 2. 16K byte write data corresponding to the page size is prepared by using the first 8K byte write data in the byte write data. Then, the controller 4 writes the prepared 16 Kbyte write data on page 2 of the block BLK # 2.

If the next page 3 of the block BLK # 2 is a bad page, the controller 4 determines the page 4 of the block BLK # 2 as the next write destination position in the 24 Kbyte write data received from the host 2. The remaining 16 Kbyte write data of is written to page 4 of block BLK # 2.

Then, the controller 4 returns a response (logical address, block number, offset (intra-block offset), length) to this write command to the host 2. In this case, the response is LBAy, block number (= BLK # 2), offset (= +10), length (= 2), block number (= BLK # 2), offset (= +16), length. (= 4) may be included.

14 and 15 show an operation of writing a logical address / data pair to a page in a block.

In each block, each page may include a user data area for storing user data and a redundant area for storing management data. The page size is 16KB + alpha.

The controller 4 writes both the 4KB user data and the logical address (for example, LBA) corresponding to the 4KB user data in the writing destination block BLK. In this case, as shown in FIG. 14, four datasets, each containing LBA and 4KB user data, may be written to the same page. The offset within the block may indicate a set boundary.

Alternatively, as shown in FIG. 15, four 4KB user data are written to the user data area within the page, and four LBAs corresponding to these four 4KB user data are written to the redundant area within this page. You may.

FIG. 16 shows the relationship between the block number and the offset (intra-block offset) in the case where the super block is used. In the following, the offset within the block is also referred to simply as the offset.

Here, in order to simplify the illustration, it is assumed that one super block SB # 1 is composed of four blocks BLK # 11, BLK # 21, BLK # 31, and BLK # 41. The controller 4 includes block BLK # 11, page 0, block BLK # 21, page 0, block BLK # 31, page 0, block BLK # 41 page 0, block BLK # 11, page 1, and block BLK # 21 page. 1. Write data in the order of block BLK # 31 page 1, block BLK # 41 page 1, and so on.

Offset +0 indicates the first 4KB area of page 0 of block BLK # 11, offset +1 indicates the second 4KB area of page 0 of block BLK # 11, and offset +2 indicates the third of page 0 of block BLK # 11. 4KB region of, offset +3 indicates the fourth 4KB region of page 0 of block BLK # 11.

Offset +4 indicates the first 4KB area of page 0 of block BLK # 21, offset +5 indicates the second 4KB area of page 0 of block BLK # 21, and offset +6 indicates the third of page 0 of block BLK # 21. 4KB region of, offset +7 indicates the fourth 4KB region of page 0 of block BLK # 21.

Similarly, offset +12 indicates the first 4KB area of page 0 of block BLK # 41, offset +13 indicates the second 4KB area of page 0 of block BLK # 41, and offset +14 indicates page 0 of block BLK # 41. Indicates the third 4KB region of, and offset +15 indicates the fourth 4KB region of page 0 of block BLK # 41.

Offset +16 indicates the first 4KB area of page 1 of block BLK # 11, offset +17 indicates the second 4KB area of page 1 of block BLK # 11, and offset +18 indicates the third of page 1 of block BLK # 11. Indicates the 4KB region of, and offset +19 indicates the fourth 4KB region of page 1 of block BLK # 11.

Offset +20 indicates the first 4KB area of page 1 of block BLK # 21, offset +21 indicates the second 4KB area of page 1 of block BLK # 21, and offset +22 indicates the third of page 1 of block BLK # 21. 4KB region of, offset +23 indicates the fourth 4KB region of page 1 of block BLK # 21.

Similarly, offset +28 indicates the first 4KB area of page 1 of block BLK # 41, offset +29 indicates the second 4KB area of page 1 of block BLK # 41, and offset +30 indicates page 1 of block BLK # 41. Indicates the third 4KB region of, and offset +31 indicates the fourth 4KB region of page 1 of block BLK # 41.

For example, when 4 Kbyte data corresponding to a write command specifying a certain LBA (LBAx) is written at a position corresponding to offset +8, the controller 4 has a logical address (= LBAx) and a block number (= SB # 1). ), Offset (= +8), and length (= 1) may be returned to host 2 as a response to this write command.

FIG. 17 shows a sequence of write operation processes executed by the host 2 and the flash storage device 3.

The host 2 sends a write command including the QoS domain ID, LBA, and length to the flash storage device 3. When the controller 4 of the flash storage device 3 receives this write command, the controller 4 determines the write destination block to which the write data from the host 2 should be written and the position in the write destination block. More specifically, the controller 4 selects one free block from the free block list and assigns the selected free block as a write destination block (step S12). That is, the selected free block and the first available page within this selected free block are determined as the write destination block to which the write data from the host 2 should be written and the position within the write destination block. If the write-destination block has already been assigned, it is not necessary to execute the write-destination block allocation process in step 12. The next available next page within the already allocated write-to block is determined as the position within the write-to block to which the write data from host 2 should be written.

The controller 4 may manage a plurality of free block lists corresponding to a plurality of QoS domains. In the free block list corresponding to a certain QoS domain, only the block group reserved for this QoS domain may be registered. In this case, in step S12, the controller 4 selects a free block list corresponding to the QoS domain specified by the QoS domain ID of the write command, selects one free block from the selected free block list, and selects this. The free block may be assigned as the write destination block. This makes it possible to prevent data corresponding to different QoS domains from being mixed in the same block.

The controller 4 writes the write data received from the host 2 to the write destination block (step S12). In step S12, the controller 4 writes both the logical address (here, LBA) and the write data to the write destination block.

The controller 4 updates the block management table 32 to change the bitmap flag corresponding to the written data (that is, the bitmap flag corresponding to the physical address of the physical storage position where this data is written) from 0 to 1. Change (step S13). For example, as shown in FIG. 18, it is assumed that 16 Kbyte update data having a start LBA of LBAx is written to a physical storage position corresponding to offsets +4 to +7 of block BLK # 1. In this case, as shown in FIG. 19, in the block management table for block BLK # 1, each of the bitmap flags corresponding to the offsets +4 to +7 is changed from 0 to 1.

The controller 4 returns a response to this write command to the host 2 (step S14). For example, as shown in FIG. 18, if 16 Kbyte update data having a start LBA of LBAx is written to a physical storage position corresponding to offsets +4 to +7 of block BLK # 1, the LBAx, block number ( A response including = BLK1), offset (= +4), and length (= 4) is transmitted from the controller 4 to the host 2.

When the host 2 receives this response, the host 2 updates the LUT managed by the host 2 and maps the physical address to each of the logical addresses corresponding to the written write data. As shown in FIG. 20, the LUT contains a plurality of entries corresponding to each of the plurality of logical addresses (eg, LBA). In the entry corresponding to a certain logical address (for example, a certain LBA), the physical address PBA indicating the position (physical storage position) in the NAND flash memory 5 in which the data corresponding to this LBA is stored, that is, the block number and the offset. (Offset in block) is stored. As shown in FIG. 18, if 16 Kbyte update data with a starting LBA of LBAx is written to the physical storage location corresponding to offsets +4 to +7 of block BLK # 1, it is shown in FIG. As described above, the LUT is updated, BLK # 1 and offset +4 are stored in the entry corresponding to LBAx, BLK # 1 and offset +5 are stored in the entry corresponding to LBAx + 1, and BLK # 1 is stored in the entry corresponding to LBAx + 2. , Offset +6 is stored, and BLK # 1 and offset +7 are stored in the entry corresponding to LBAx + 3.

After that, the host 2 transmits a Trim command to the flash storage device 3 for invalidating the previous data that is no longer needed by writing the update data described above (step S21). As shown in FIG. 18, when the previous data is stored at the positions corresponding to the offset +0, offset +1, offset +2, and offset +3 of the block BLK # 0, as shown in FIG. A Trim command for specifying the block number (= BLK # 0), offset (= +0), and length (= 4) is transmitted from the host 2 to the flash storage device 3. The controller 4 of the flash storage device 3 updates the block management table 32 in response to this Trim command (step S15). In step S15, as shown in FIG. 21, in the block management table for block BLK # 0, the bitmap flags corresponding to the offsets +0 to +3 are changed from 1 to 0, respectively.

FIG. 22 shows a read command applied to the flash storage device 3.

The read command is a command that requests the flash storage device 3 to read data. This read command includes a command ID, a physical address PBA, a length, and a transfer destination pointer.

The command ID is an ID (command code) indicating that this command is a read command, and the read command includes a command ID for the read command.

The physical address PBA indicates the first physical storage location where the data should be read. The physical address PBA is specified by a block number and an offset (intra-block offset).

The length indicates the length of data to be read. This data length can be specified by the number of grains.

The transfer destination pointer indicates a position on the memory in the host 2 to which the read data should be transferred.

One read command can specify a plurality of pairs of physical address PBA (block number, offset) and length.

FIG. 23 shows the read operation.

Here, it is assumed that a read command for specifying the block number (= BLK # 2), offset (= +5), and length (= 3) is received from the host 2. The controller 5 of the flash storage device 4 reads data d1 to d3 from BLK # 2 based on the block number (= BLK # 2), offset (= +5), and length (= 3). In this case, the controller 4 reads data for one page size from page 1 of BLK # 2, and extracts data d1 to data d3 from the read data. Next, the controller 4 transfers the data d1 to the data d3 onto the host memory designated by the transfer destination pointer.

FIG. 24 shows an operation of reading a data unit stored in different physical storage positions in response to a read command from the host 2.

Here, a read that specifies the block number (= BLK # 2), offset (= +10), length (= 2), block number (= BLK # 2), offset (= +16), and length (= 4). It is assumed that the command is received from host 2. The controller 5 of the flash storage device 4 reads data for one page size from page 2 of BLK # 2 based on the block number (= BLK # 2), offset (= +10), and length (= 2). , Data d1 to data d2 are extracted from this read data. Next, the controller 5 receives data (data d3 to data d4) for one page size from page 4 of BLK # 2 based on the block number (= BLK # 2), offset (= +16), and length (= 4). ) Lead. Then, the controller 5 transfers the read data of the length (= 6) obtained by combining the data d1 to the data d2 and the data d3 to the data d4 on the host memory specified by the transfer destination pointer in the read command. Transfer to.

This makes it possible to read the data unit from a separate physical storage location without causing a read error, even if there are bad pages in the block. Further, even if the data is written over two blocks, this data can be read by issuing one read command.

FIG. 25 shows a sequence of read processing performed by the host 2 and the flash storage device 3.

The host 2 refers to the LUT managed by the host 2 and converts the logical address included in the read request from the user application into a block number and an offset. Then, the host 2 sends a read command for specifying the block number, the offset, and the length to the flash storage device 3.

When the controller 4 of the flash storage device 3 receives the read command from the host 2, the controller 4 determines the block corresponding to the block number specified by this read command as the block to be read, and also designates the block by this read command. The page to be read is determined based on the offset (step S31). In step S31, the controller 4 may first divide the offset specified by the read command by the number of particle sizes representing the page size (here, 4). Then, the controller 4 may determine the quotient and the remainder obtained by this division as the page number of the read target and the offset position in the page of the read target, respectively.

The controller 4 reads the data defined by the block number, the offset, and the length from the NAND flash memory 5 (step S32), and transmits this read data to the host 2.

FIG. 26 shows GC control commands applied to the flash storage device 3.

The GC control command may include a command ID, a policy, a source QoS domain ID, a destination QoS domain ID, and the like.

The command ID is an ID (command code) indicating that this command is a GC control command, and the GC control command includes a command ID for the GC control command.

The policy is a parameter that specifies a condition (GC policy) for selecting a GC candidate block (GC source block). The controller 4 of the flash storage device 3 supports a plurality of GC policies.

The GC policy supported by the controller 4 may include a policy (Greedy) in which a block having a small amount of valid data is preferentially selected as a GC candidate block (GC source block).

Further, in the GC policy supported by the controller 4, a block in which data having a low update frequency (cold data) is collected is more than a block in which data having a high update frequency (hot data) is collected. A policy of preferentially selecting as a GC candidate block (GC source block) may be included.

In addition, the GC policy may specify GC start conditions. The GC start condition may indicate, for example, the number of remaining free blocks.

The controller 4 manages a group of blocks including valid data by the active block list, and when executing GC, the blocks managed by the active block list based on the GC policy specified by the GC control command. Select one or more GC candidate blocks (GC source blocks) from the group.

The source QoS domain ID is a parameter that specifies which QoS domain should be the GC source. The controller 4 selects one or more GC candidate blocks (GC source blocks) from the block group belonging to the QoS domain specified by the source QoS domain ID, that is, the active block list corresponding to this QoS domain.

The destination QoS domain ID is a parameter that specifies which QoS domain should be the GC destination. The controller 4 can select one or more free blocks in the free block group belonging to the QoS domain specified by the destination QoS domain ID as the GC destination block.

The source QoS domain ID and the destination QoS domain ID may specify the same QoS domain or different QoS domains. That is, each of the source QoS domain ID and the destination QoS domain ID is a parameter that specifies any one of the plurality of QoS domains.

The controller 4 may start GC when the number of remaining free blocks corresponding to the source QoS domain falls below the threshold specified by the policy. If a GC control command including a policy specifying the forced execution of the GC is received, the controller 4 may start the GC immediately when the GC control command is received from the host 2.

FIG. 27 shows a GC callback command.

The GC callback command is used to notify the host 2 of the logical address of the valid data copied by the GC and the block number and offset indicating the copy destination position of the valid data.

The GC callback command may include a command ID, a logical address, a length, a destination physical address, and a source physical address (optional).

The command ID is an ID (command code) indicating that this command is a GC callback command, and the GC callback command includes a command ID for a GC callback command.

The logical address indicates the logical address of the valid data copied by the GC from the GC source block to the GC destination block.

The length indicates the length of this copied data. This data length may be specified by the number of grain.

The destination physical address indicates the location within the GC destination block where the valid data was copied. The destination physical address is specified by the block number and offset (intra-block offset).

The source physical address (optional) indicates the position in the GC source block where the valid data was stored. The source physical address is specified by the block number and offset (intra-block offset).

FIG. 28 shows the procedure of garbage collection (GC) operation.

The controller 4 of the flash storage device 3 is one or more GCs in which valid data and invalid data are mixed from a group of blocks belonging to the QoS domain specified by the source QoS domain ID based on the policy specified by the host 2. Select the source block (copy source block) (step S41). The controller 4 then selects one or more free blocks from the group of free blocks belonging to the QoS domain specified by the destination QoS domain ID and assigns the selected free blocks as GC destination blocks (copy destination blocks) ( Step S42).

The controller 4 copies all the valid data in the GC source block (copy source block) to the GC destination block (copy destination block) (step S44). In step S44, the controller 4 transfers not only the valid data in the GC source block (copy source block) but also both the valid data and the logical address corresponding to the valid data from the GC source block (copy source block) to GC. Copy to the destination block (copy destination block). As a result, a pair of data and a logical address can be held in the GC destination block (copy destination block).

Then, the controller 4 uses the logical address of the copied valid data and the destination physical address (block number, offset (offset in the block) indicating the position in the GC destination block (copy destination block) to which the valid data is copied. )) Is notified to the host 2 by using the GC callback command (step S44). In step S44, the controller 4 may notify the host 2 not only the logical address and the destination physical address of the copied valid data but also the source physical address.

When the host 2 receives this GC callback command, the host 2 updates the LUT managed by the host 2 and maps the destination physical address to each logical address corresponding to the copied valid data. (Step S51).

FIG. 29 shows an example of a data copy operation performed for GC.

In FIG. 29, the valid data (LBA = 10) stored at the position corresponding to the offset +4 of the GC source block (here, block BLK # 50) is the offset of the GC destination block (here, block BLK # 100). The valid data (LBA = 20) that is copied to the position corresponding to +0 and stored at the position corresponding to the offset +10 of the GC source block (here, block BLK # 50) is the GC destination block (here, block BLK). It is assumed that the data is copied to the position corresponding to the offset +1 of # 100). In this case, the controller 4 notifies the host of {LBA10, BLK # 100, offset (= + 0), LBA20, BLK # 100, offset (= + 1)} (GC callback process).

FIG. 30 shows the contents of the LUT of the host 2 which is updated based on the result of the data copy operation of FIG. 29.

In this LUT, the block number and offset corresponding to LBA10 are updated from BLK # 50, offset (= + 4) to BLK # 100, offset (= +0). Similarly, the block number and offset corresponding to LBA20 are updated from BLK # 50, offset (= +10) to BLK # 100, offset (= + 1).

After the LUT is updated, the host 2 sends a Trim command to specify the BLK # 50 and the offset (= + 4) to the flash storage device 3 and stores it in the position corresponding to the offset (= + 4) of the BLK # 50. You may invalidate the data that has been set. Further, the host 2 sends a Trim command for specifying the BLK # 50 and the offset (= +10) to the flash storage device 3, and sends the data stored at the position corresponding to the offset (= +10) of the BLK # 50. It may be invalidated.

FIG. 31 shows the relationship between the response to the write command and the GC callback process.

While the controller 4 is copying valid data corresponding to a certain logical address, a write command specifying this logical address may be received from the host 2.

In FIG. 31, it is assumed that a write command specifying the LBA 10 is received from the host 2 during the data copy operation (data copy operation corresponding to the LBA 10) of FIG. 29.

The controller 4 writes the write data received from the host 2 to the write destination block (here, it is written at the position corresponding to the offset +0 of BLK # 3). Then, the controller 4 notifies the host 2 of {LBA10, BLK # 3, offset (= + 0)}.

The host 2 updates the LUT to change the block number and offset corresponding to LBA10 from BLK # 50, offset (+4) to BLK # 3, offset (+0).

If the destination physical address of LBA10 is notified to host 2 from the controller 4 after this, the block number and offset (BLK # 3, offset (+0)) indicating the position where the latest data corresponding to LBA10 is stored. ) May be erroneously changed to the destination physical address corresponding to LBA10 (here, BLK # 100, offset (= +0)).

In the present embodiment, the controller 4 notifies the host 2 not only the LBA 10 and the destination physical address (BLK # 100, offset (= + 0)) but also the source physical address (BLK # 50, offset (= + 4)). be able to. The host 2 does not update the LUT if the source physical address (BLK # 50, offset (= +4)) does not match the block number or offset currently mapped to the LBA 10 by the LUT. As a result, the block number and offset (BLK # 3, offset (+0)) indicating the position where the latest data corresponding to LBA10 is stored are the destination physical addresses corresponding to LBA10 (here, BLK # 100, offset). It is possible to prevent it from being accidentally changed to (= + 0)).

FIG. 32 shows another example of a GC control command.

The GC control command of FIG. 32 may specify a pair of a source device ID and a source QoS domain ID instead of the source QoS domain ID. Further, the GC control command of FIG. 32 may specify a pair of a destination device ID and a destination QoS domain ID instead of the destination QoS domain ID. This makes it possible to operate one flash storage device 3 as a GC source and another flash storage device 3 as a GC destination. When the source device ID and the destination device ID are the same, GC is executed in one flash storage device 3.

FIG. 33 shows an example of a GC callback command corresponding to the GC control command of FIG. 32.

The GC callback command of FIG. 33 includes a destination device ID and a destination physical address pair instead of the destination physical address. Further, the GC callback command of FIG. 33 may include a pair (optional) of the source device ID and the source physical address instead of the source physical address (optional).

Now, it is assumed that the flash storage device 3 having a device ID of 1 is operated as a GC source and the flash storage device 3 having a device ID of 2 is operated as a GC destination. The host 2 may send a GC control command specifying the source device ID # 1 and the destination device ID # 2 to the flash storage device 3 of the device ID # 1 and the flash storage device 3 of the device ID # 2. ..

The flash storage device 3 of the device ID # 1 selects a GC source block from a group of blocks belonging to the QoS domain specified by the source QoS domain ID, and sets the valid data in the GC source block and the logical address of the valid data. The data is transmitted to the flash storage device (flash storage device of device ID # 2) specified by the destination device ID. The valid data in the GC source block and the logical address of the valid data are transferred from the flash storage device 3 of device ID # 1 to the flash storage device 3 of device ID # 2 via, for example, the switch 1 of FIG. ..

The flash storage device 3 of device ID # 2 selects a GC destination block from a group of free blocks belonging to the QoS domain specified by the destination QoS domain ID, and selects valid data and logical dress received via switch 1. Write (copy) to the GC destination block.

The flash storage device 3 of device ID # 2 notifies the host 2 of the logical address of the copied valid data and the destination physical address (block number, offset) to which the copied valid data is copied by a GC callback command. do.

The flash storage device 3 of device ID # 1 notifies the host 2 of the logical address of the copied valid data and the source physical address (block number, offset) in which the valid data is stored by a GC callback command. do.

FIG. 34 shows the write / read / GC operation.

First, a host write operation for writing data from the host 2 will be described.

(1) The controller 4 receives LBA and write data from the host 2.

(2) The controller 4 writes both the LBA and the write data to the write destination block. If the write-destination block is not assigned, the controller 4 selects one free block from the free block list and assigns the selected free block as a new write-destination block. Then, the controller 4 writes both the LBA and the write data to this new write destination block.

(3) The controller 4 notifies the host 2 of this LBA and the physical address PBA indicating the position in the writing destination block in which the write data is written. This physical address PBA is represented by a block number and an offset. When the entire write-destination block is filled with data, the controller 4 registers the write-destination block in the active block list.

Next, the read operation will be described.

(4) The host 2 refers to the LUT managed by the host 2 and converts the LBA included in the read request from the user application into the physical address PBA (block number, offset) for reading.

(5) Based on the read physical address PBA (block number, offset) received from the host 2, the controller 4 determines the block having this block number as the block to be read. The block to be read is any one of the blocks (active blocks) managed by the active block list, the current GC source block, or the current write destination block. Then, the controller 4 reads the data from the block to be read based on the offset.

Next, the GC operation will be described.

(6) The controller 4 selects a GC source block (copy source block) and a GC destination block (copy destination block), and GCs both the valid data stored in the GC source block and the LBA of this valid data. Copy to the destination block.

(7) The controller 4 notifies the host 2 of both the LBA of the copied valid data and the PBA (block number, offset) indicating the position in the GC destination block to which the valid data is copied.

Alternatively, the controller 4 has an LBA of the copied valid data, a PBA (block number, offset) indicating the position in the GC destination block to which the valid data has been copied, and a GC source in which the valid data is stored. The PBA (block number, offset) indicating the position in the block may be notified to the host 2.

FIG. 35 shows a configuration example of a block management table for managing reference counts.

Host 2 supports the deduplication function. Therefore, if duplicate data matching the data requested to be written by the user application already exists in the flash storage device 3 (NAND type flash memory 5), the host 2 does not write this data to the flash storage device 3. Only the pointer to the position (block number, offset) where this data is stored is associated with the LBA of the data requested to be written. Therefore, each 4 Kbyte data stored in the flash storage device 3 (NAND flash memory 5) may be referred not only from one logical address but also from a plurality of logical addresses.

In the present embodiment, the flash storage device 3 has a function of managing the reference count for each 4 Kbyte data. Here, the reference count corresponding to a certain data indicates the number of logical addresses that refer to this data.

In FIG. 35, a block management table for block BLK # 1 is illustrated.

The block management table for block BLK # 1 contains a plurality of entries corresponding to each of the plurality of offset values of block BLK # 1.

For example, the entry corresponding to the offset +0 stores the reference count corresponding to the 4KB data stored at the position corresponding to the offset +0 of the block BLK # 1. Similarly, the entry corresponding to offset +1 stores the reference count corresponding to the 4KB data stored at the position corresponding to offset +1 of block BLK # 1.

Data with a reference count of 1 or more is valid data, and data with a reference count of 0 is invalid data.

The flash storage device 3 increments / decrements the reference count based on the duplicate command / Ttim command received from the host 2.

FIG. 36 shows a duplicate command applied to the flash storage device 3 for reference counting management.

The duplicate command is a command that requests the flash storage device 3 to increase the reference count of the data stored at a certain physical address (block number, offset) by 1.

This duplicate command may include a command ID, physical address PBA, length, etc.

The command ID is an ID (command code) indicating that this command is a duplicate command, and the duplicate command includes a command ID for the duplicate command.

The physical address PBA indicates the first physical storage location in which the data whose reference count should be incremented by 1 is stored. The physical address PBA is specified by a block number and an offset (intra-block offset).

The length indicates the length of data for which the reference count should be incremented by one. This data length can be specified by the number of grain.

When the controller 4 receives from the host 2 a duplicate command including a block number indicating a physical storage position in which data for which the reference count should be increased is stored and an intra-block offset, the controller 4 updates the block management table 32 to the duplicate command. Increases the reference count corresponding to the data in the physical storage location corresponding to the included block number and intra-block offset by 1.

FIG. 37 shows a Trim command applied to the flash storage device 3 for reference counting management.

This Trim command is a command that requests the flash storage device 3 to decrement the reference count of the data stored at a certain physical address (block number, offset) by 1.

This Trim command may include a command ID, physical address PBA, length, and the like.

The command ID is an ID (command code) indicating that this command is a Trim command, and the Trim command includes a command ID for the Trim command.

The physical address PBA indicates the first physical storage location in which the data whose reference count should be decremented by 1 is stored. The physical address PBA is specified by a block number and an offset (intra-block offset).

Length indicates the length of data for which the reference count should be decremented by one. This data length can be specified by the number of grain.

When the controller 4 receives from the host 2 a Trim command including a block number indicating a physical storage position in which data for which the reference count should be reduced is stored and an intra-block offset, the controller 4 updates the block management table 32 to the Trim command. Decrease the reference count corresponding to the physical storage location data corresponding to the included block number and intra-block offset by 1.

FIG. 38 shows the reference count increment / decrement process.

When the controller 4 of the flash storage device 3 receives the duplicate command from the host 2, the controller 4 receives the reference count corresponding to the physical address PBA (block number, offset) specified by the duplicate command, that is, the block number and the offset. The reference count corresponding to the data stored in the physical storage position in the NAND flash memory 5 specified by is incremented by 1 (step S61). In this case, the controller 4 updates the block management table 32 corresponding to the block having the block number specified by the duplicate command. This update of the block management table 32 increments the reference count stored in the entry in the block management table 32 corresponding to the offset specified by the duplicate command. If the length specified by the duplicate command is 2 or more, not only the reference count corresponding to the offset specified by the duplicate command, but also the reference count corresponding to some offsets following this offset is incremented by 1. ..

When the controller 4 of the flash storage device 3 receives the Trim command from the host 2, the controller 4 receives the reference count corresponding to the physical address PBA (block number, offset) specified by the Trim command, that is, this block number and offset. The reference count corresponding to the data stored in the physical storage position in the NAND flash memory 5 specified by is decremented by 1 (step S62). In this case, the controller 4 updates the block management table 32 corresponding to the block having the block number specified by the Trim command. This update of the block management table 32 decrements the reference count stored in the entry in the block management table 32 corresponding to the offset specified by the Trim command. If the length specified by the Trim command is 2 or more, not only the reference count corresponding to the offset specified by the Trim command but also the reference count corresponding to some offsets following this offset is decremented by 1. ..

In the GC, the controller 4 refers to the block management table corresponding to the GC source block and determines whether the data in the GC source block is valid data or invalid data in units of data having a size of 4 KB. do. The controller 4 determines that the data having a reference count of 0 is invalid data, and determines that the data having a reference count of 1 or more is valid data. Then, the controller 4 copies the valid data (data having a reference count of 1 or more) and the logical address corresponding to the valid data from the GC source block to the GC destination block.

More specifically, when executing the garbage collection of the NAND flash memory 5, the controller 4 selects the copy source block and the copy destination block for the garbage collection. The controller 4 copies both the first data (valid data) having a reference count of 1 or more and the logical address of the first data stored in the copy source block to the copy destination block. Then, the controller 4 indicates the logical address of the first data, the block number of the copy destination block, and the offset position from the beginning of the copy destination block to which the first data is copied, which is an offset within the block indicating a multiple of the particle size. Is notified to the host 2.

As described above, according to the present embodiment, the flash storage device 3 instead of the host 2 is the write destination block to which the data (user data) from the host 2 should be written and the position (write destination) in the write destination block. Position) is determined. The flash storage device 3 writes the user data to the write destination position in the write destination block, and sets the block number of the write destination block and the offset from the beginning of the write destination block to the write destination position to a size different from the page size. The host 2 is notified of the offset in the block indicated by a multiple of the particle size. As a result, the host 2 can write the user data to the NAND flash memory 5 without being aware of the block size, the page write order constraint, the bad page, the page size, etc., and further, the block number and the block. The physical address represented by the offset (abstracted physical address) can be mapped to the logical address of this user data.

In this way, the flash storage device 3 determines the write-destination block and the position in the write-destination block, and returns the block number and the in-block offset to the host 2, so that the application in the upper layer (host 2) It is possible to merge the level address conversion table with the LUT level address conversion table of the conventional SSD, and the flash storage device 3 is a NAND type flash memory in consideration of the features / restrictions of the NAND type flash memory 5. It becomes possible to control 5. Therefore, it is possible to realize an appropriate division of roles between the host 2 and the flash storage device 3, thereby improving the I / O performance of the entire system including the host 2 and the flash storage device 3.

Further, according to the present embodiment, the flash storage device 3 selects the copy source block and the copy destination block for garbage collection, and is stored in the copy source block, instead of the host 2 that manages the address translation table. Copy valid data to the destination block. Then, the flash storage device 3 notifies the host 2 of the logical address of the copied valid data, the block number of the copy destination block, and the offset in the block indicating the position in the copy destination block to which the valid data is copied. do. In this way, the garbage collection is executed by the flash storage device 3, and the logical address, the block number, and the offset in the block are notified from the flash storage device 3 to the host 2, so that the host 2 can notify each of the logical addresses and the NAND type flash. The mapping between each physical address of memory 5 (ie, the pair of block number and offset within the block) can be managed correctly using the address translation table (LUT). Further, since the application level GC can be merged with the GC of the flash storage device 3, the write amplification can be significantly reduced.

The flash storage device 3 may be used as one of a plurality of flash storage devices 3 provided in the storage array. The storage array may be connected to an information processing device such as a server computer via a cable or a network. The storage array includes a controller that controls a plurality of flash storage devices 3 in the storage array. When the flash storage device 3 is applied to the storage array, the controller of this storage array may function as the host 2 of the flash storage device 3.

Further, in the present embodiment, a NAND flash memory is exemplified as the non-volatile memory. However, the function of this embodiment is, for example, MRAM (Magnetoresistive).
Random Access Memory), PRAM (Phase change)
It can also be applied to various other non-volatile memories such as Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Ramdom Access Memory).

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

2 ... Host, 3 ... Flash storage device, 4 ... Controller, 5 ... NAND flash memory, 21 ... Write operation control unit, 22 ... Read operation control unit, 23 ... GC operation control unit.

Claims (18)

A memory system that can be connected to a host
A non-volatile memory containing multiple blocks, each of which is a unit of erasing operation,
A controller electrically connected to the non-volatile memory is provided.
The plurality of blocks are classified into a plurality of domains, and the plurality of blocks are classified into a plurality of domains.
The controller
The identifier of the block that requests the writing of the first data and specifies the identifier of the domain to which the first data is to be written and the logical address corresponding to the first data, and the identifier of the block to which the first data is to be written. When a write command that does not specify is received from the host, the domain associated with the specified identifier is selected from the plurality of domains, and the first data is selected from the set of blocks belonging to the selected domain. Allocates a first block to be written, writes the first data to a first storage position in the first block,
A memory system configured to notify the host of the first storage location using the identifier of the first block and the offset address within the first block . Each of the plurality of blocks includes a plurality of pages, and each of the plurality of pages is a unit of data writing operation.
The memory system according to claim 1 , wherein the controller specifies the offset address using a multiple of the particle size having a size different from the size of each of the plurality of pages. When the controller receives a read command from the host that specifies the identifier of the first block and the offset address in the first block, the controller receives the first storage position in the first block. The memory system according to claim 1 , which is configured to read the first data from. The memory system according to claim 3 , wherein the read command does not specify the logical address corresponding to the first data. The first aspect of the present invention, wherein the controller is further configured to write the logical address corresponding to the first data to the first storage position in the first block together with the first data. Memory system. The controller
The first data and the logical address are copied from the first storage position in the first block to the second storage position in the second block of the non-volatile memory.
Further configured to notify the host of the second storage location and the logical address .
The memory system according to claim 5 , wherein the second storage position is notified to the host using the identifier of the second block and the offset address in the second block . The memory system according to claim 1, wherein each of the plurality of blocks belongs to only one domain among the plurality of domains. The memory system according to claim 1, wherein the non-volatile memory includes a plurality of memory dies, and each of the plurality of memory dies belongs to only one domain among the plurality of domains. A memory system that can be connected to a host
A non-volatile memory containing multiple blocks, each of which is a unit of erasing operation,
A controller electrically connected to the non-volatile memory is provided.
The controller
When a write command is received from the host that requests the writing of the first data, specifies the logical address corresponding to the first data, and does not specify the identifier of the block to which the first data should be written. The first data is written to the first storage location in the non-volatile memory, and the identifier of the block in which the first data is written and the offset address in the block in which the first data is written are used. Notify the host of the first storage position,
The host issues a read command that requests reading of the first data and specifies the identifier of the block in which the first data is written and the offset address in the block in which the first data is written. A memory system configured to read the first data from the first storage location in the non-volatile memory when received from. The plurality of blocks are classified into a plurality of domains, and the plurality of blocks are classified into a plurality of domains.
The write command further specifies the identifier of the domain in which the first data should be written.
The controller
From the plurality of domains, the domain associated with the specified identifier is selected, and the domain is selected.
9. The memory system of claim 9, further configured to allocate blocks from which the first data should be written from a set of blocks belonging to the selected domain. It is a control method in which a controller controls a non-volatile memory containing a plurality of blocks, each of which is a unit of erasing operation.
The plurality of blocks are classified into a plurality of domains, and the plurality of blocks are classified into a plurality of domains.
The identifier of the block that requests the writing of the first data and specifies the identifier of the domain to which the first data is to be written and the logical address corresponding to the first data, and the identifier of the block to which the first data is to be written. When a write command that does not specify is received from the host, the domain associated with the specified identifier is selected from the plurality of domains, and the first data is obtained from the set of blocks belonging to the selected domain. Allocating a first block to be written, writing the first data to a first storage position in the first block ,
A control method comprising notifying the host of the first storage position using the identifier of the first block and the offset address in the first block . Each of the plurality of blocks includes a plurality of pages, and each of the plurality of pages is a unit of data writing operation.
11. The control method of claim 11 , wherein the offset address is specified using a multiple of the particle size having a size different from the size of each of the plurality of pages. When a read command for specifying the identifier of the first block and the offset address in the first block is received from the host, the first storage position in the first block is used as the first storage position. 11. The control method according to claim 11 , further comprising reading the data of the above. 13. The control method according to claim 13 , wherein the read command does not specify the logical address corresponding to the first data. The control method according to claim 11 , further comprising writing the logical address corresponding to the first data to the first storage position in the first block together with the first data. Copying the first data and the logical address from the first storage position in the first block to a second storage position in the second block of the non-volatile memory.
Further comprising notifying the host of the second storage position and the logical address .
The control method according to claim 15 , wherein the second storage position is notified to the host using the identifier of the second block and the offset address in the second block . The control method according to claim 11 , wherein each of the plurality of blocks belongs to only one domain among the plurality of domains. The control method according to claim 11 , wherein the non-volatile memory includes a plurality of memory dies, and each of the plurality of memory dies belongs to only one domain among the plurality of domains.

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