JP7066672B2 - Semiconductor device - Google Patents

Description

One aspect of the present invention relates to a semiconductor device, a display device, and an electronic device using the display device.
Alternatively, one aspect of the present invention relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). One aspect of the present invention is a semiconductor device, a display device, an electronic device, a method for manufacturing the same, and the like.
Or related to their driving method. In particular, one aspect of the present invention relates to, for example, a semiconductor device including a transistor and a capacitive element.

Transistors used in many flat panel displays such as liquid crystal displays and light emitting display devices are composed of silicon semiconductors such as amorphous silicon, single crystal silicon, and polysilicon that are formed on a glass substrate. .. Transistors using the silicon semiconductor are also used in integrated circuits (ICs) and the like.

In recent years, a technique of using a metal oxide exhibiting semiconductor characteristics for a transistor instead of a silicon semiconductor has attracted attention. In the present specification, a metal oxide exhibiting semiconductor characteristics is referred to as an oxide semiconductor. For example, as an oxide semiconductor, zinc oxide or In-Ga-
A technique for producing a transistor using a Zn-based oxide and using the transistor as a switching element for pixels of a display device is disclosed (see Patent Document 1 and Patent Document 2).

Japanese Unexamined Patent Publication No. 2007-123861 Japanese Unexamined Patent Publication No. 2007-96055

One aspect of the present invention is to provide a semiconductor device provided with a conductive oxide semiconductor film. Alternatively, one aspect of the present invention is to provide a semiconductor device having an increased aperture ratio and an increased capacitance value. Alternatively, one aspect of the present invention is to provide a semiconductor device having a low manufacturing cost. Alternatively, one aspect of the present invention is to provide a new semiconductor device or the like.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc.
It is possible to extract problems other than these from the drawings, claims, and the like.

One aspect of the present invention is a semiconductor device including a transistor, a first insulating film, and a capacitive element including a third insulating film between a pair of electrodes, wherein the transistor is on the first insulating film. No. 1 of
Oxide semiconductor film, a second insulating film on the first oxide semiconductor film, and a second insulating film on the second insulating film.
The oxide semiconductor film is composed of a first oxide semiconductor film and a third insulating film on the second oxide semiconductor film, and the first oxide semiconductor film is a second oxide semiconductor. It has a channel region that overlaps with the film, a source region that is in contact with the third insulating film, and a drain region that is in contact with the third insulating film.
The source and drain regions have one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or rare gas, and one of the pair of electrodes of the capacitive element is a second oxide semiconductor. It is a semiconductor device including a film.

Further, it is a semiconductor device including a transistor, a first insulating film, and a capacitive element including a third insulating film between a pair of electrodes. The transistor is a gate electrode and the first insulating film on the gate electrode. The insulating film, the first oxide semiconductor film on the first insulating film, the second insulating film on the first oxide semiconductor film, and the second oxide semiconductor on the second insulating film. It has a film, a first oxide semiconductor film, and a third insulating film on the second oxide semiconductor film, and the first oxide semiconductor film has a channel that overlaps with the second oxide semiconductor film. It has a region, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film, and the source region and the drain region are hydrogen, boron, and so on.
A semiconductor device having one or more of carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a rare gas and one of a pair of electrodes of a capacitive element containing a second oxide semiconductor film is also of the present invention. This is one aspect.

Further, it is a semiconductor device including a transistor, a first insulating film, and a capacitive element including a third insulating film between a pair of electrodes. The transistor is a gate electrode and the first insulating film on the gate electrode. The insulating film, the first oxide semiconductor film on the first insulating film, the second insulating film on the first oxide semiconductor film, and the second oxide semiconductor on the second insulating film. It has a film and a first oxide semiconductor film and a third insulating film on the second oxide semiconductor film, and the gate electrode is electrically connected to the second oxide semiconductor film and has a second structure. The oxide semiconductor film 1 has a channel region overlapping the second oxide semiconductor film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film, and has a source region and a drain region. Drain regions are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus,
A semiconductor device having one or more of sulfur, chlorine, titanium, or a rare gas and one of a pair of electrodes of a capacitive element comprising a second oxide semiconductor film is also an aspect of the present invention.

Further, the transistor is electrically connected to the source region through the fourth insulating film on the third insulating film and the openings provided in the third insulating film and the fourth insulating film. The above-mentioned semiconductor device having the conductive film of the above and a second conductive film electrically connected to a drain region via an opening provided in the third insulating film and the fourth insulating film is also present. It is one aspect of the invention.

Further, it has a fourth insulating film, a fifth insulating film on the first conductive film and the second conductive film, and a third conductive film on the fifth insulating film, and is a pair of electrodes of a capacitive element. The above-mentioned semiconductor device, wherein the other of the above includes a third conductive film, is also an aspect of the present invention.

Further, the semiconductor device according to one aspect of the present invention is the above-mentioned semiconductor device in which the capacitive element has translucency in visible light.

Further, in the above semiconductor device, the first oxide semiconductor film and the second oxide semiconductor film are In—M—Zn oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Sn or Hf
Represents).

Further, in the above semiconductor device, it is preferable that the third insulating film contains nitrogen or hydrogen.

Further, in the above semiconductor device, it is preferable that the second insulating film contains oxygen.

A display device having the above-mentioned semiconductor device and a liquid crystal element is also an aspect of the present invention.

An electronic device having the above-mentioned semiconductor device, a switch, a speaker, a display unit, or a housing is also an aspect of the present invention.

According to one aspect of the present invention, it is possible to provide a semiconductor device provided with a conductive oxide semiconductor film. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device having an increased aperture ratio and an increased capacitance value. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device having a low manufacturing cost. Further, according to one aspect of the present invention, a novel semiconductor device or the like can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

Top view and sectional view showing one aspect of a semiconductor device. The cross-sectional view which shows one aspect of the semiconductor device. Top view and sectional view showing one aspect of a semiconductor device. Top view and sectional view showing one aspect of a semiconductor device. The cross-sectional view which shows one aspect of the semiconductor device. The cross-sectional view which shows one aspect of the semiconductor device. The cross-sectional view which shows one aspect of the semiconductor device. The cross-sectional view which shows one aspect of the semiconductor device. The figure explaining the band structure. The cross-sectional view which shows one aspect of the manufacturing method of a semiconductor device. The cross-sectional view which shows one aspect of the manufacturing method of a semiconductor device. The cross-sectional view which shows one aspect of the manufacturing method of a semiconductor device. The cross-sectional view which shows one aspect of the manufacturing method of a semiconductor device. The figure explaining the structural analysis of CAAC-OS and a single crystal oxide semiconductor by XRD, and the figure which shows the selected area electron diffraction pattern of CAAC-OS. A cross-sectional TEM image of the CAAC-OS, a planar TEM image, and an image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. The figure which shows the change of the crystal part by electron irradiation of In—Ga—Zn oxide. A top view showing one form of a display device and a circuit diagram showing one form of pixels. Top view showing one form of a pixel. Sectional drawing which shows one form of a pixel. Top view showing one form of a pixel. Sectional drawing which shows one form of a pixel. Top view showing one form of a pixel. Sectional drawing which shows one form of a pixel. Top view showing one form of a pixel. Sectional drawing which shows one form of a pixel. Top view showing one form of a pixel. Sectional drawing which shows one form of a pixel. Top view showing one form of a pixel. Sectional drawing which shows one form of a pixel. A block diagram and a timing chart diagram of the touch sensor. The figure explaining the pixel which has a touch sensor. The figure explaining the operation of a touch sensor and a pixel. Schematic diagram of a cross section showing a touch panel method. Schematic diagram of a cross section showing a touch panel method. Top view showing the arrangement of electrodes of a touch sensor. Top view showing one form of a pixel. Sectional drawing which shows one form of a pixel. A circuit diagram showing a form of a pixel. Top view showing one form of a display device. A cross-sectional view showing one form of a display device. A cross-sectional view showing one form of a display device. A cross-sectional view showing one form of a display device. The perspective view which shows the structure of a touch panel. Sectional drawing which shows the structure of a touch panel. Top view showing the configuration of the touch sensor. Top view showing the structure of a touch sensor electrode. Top view showing the configuration of the touch sensor. Top view showing the structure of a touch sensor electrode. The figure explaining the structure of a light emitting element. The figure explaining the display module. The figure explaining the electronic device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, one aspect of the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the gist of the present invention and its scope. To. Therefore, one aspect of the present invention is not construed as being limited to the description of the embodiments shown below.
Further, in the embodiments described below, the same reference numerals or the same hatch patterns are commonly used among different drawings for the same parts or parts having the same functions, and the repeated description thereof will be omitted.

In each of the figures described herein, the size, film thickness, or region of each configuration may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

Further, the first and second ordinal numbers used in the present specification and the like are attached to avoid mixing of the components, and are not limited numerically. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation.

Further, in the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Or, for example, the term "insulating film" is referred to as "insulating film".
It may be possible to change to the term.

Further, even when the term "semiconductor" is used in the present specification or the like, for example, if the conductivity is sufficiently low, it may have characteristics as an "insulator". Also, "semiconductor" and "
The boundary with "insulator" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in the present specification and the like may be paraphrased as an "insulator". Similarly, the "insulator" described in the present specification and the like may be paraphrased as "semiconductor". Alternatively, it may be possible to paraphrase the "insulator" described in the present specification or the like into a "semi-insulator".

Further, even when the term "semiconductor" is used in the present specification or the like, for example, if the conductivity is sufficiently high, the conductor may have characteristics as a "conductor". Also, "semiconductor" and "
The boundary with "conductor" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in the present specification and the like may be paraphrased as a "conductor". Similarly, the "conductor" described in the present specification and the like may be paraphrased as "semiconductor".

The "source" and "drain" functions of the transistor may be interchanged when a transistor having a different polarity is used or when the direction of the current changes in the circuit operation. Therefore, in the present specification, the terms "source" and "drain" may be used interchangeably.

In the present specification and the like, patterning uses a photolithography process. However, the patterning is not limited to the photolithography process, and a process other than the photolithography process can also be used. Further, the mask formed in the photolithography process shall be removed after the etching process.

In the present specification and the like, the silicon oxide film refers to a film having a higher oxygen content than nitrogen in its composition, preferably 55 atomic% or more and 65 atomic% or less of oxygen, and 1 nitrogen.
Atomic% or more and 20 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0.1 atomic% or more and 10 atomic% or less. The silicon nitride film refers to a film having a nitrogen content higher than that of oxygen in its composition, preferably having a nitrogen content of 55 atomic% or more 6
5 atomic% or less, oxygen is 1 atomic% or more and 20 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0.1 atomic% or more and 10 atomic% or less.

(Embodiment 1)
In the present embodiment, the semiconductor device of one aspect of the present invention will be described with reference to FIGS. 1 to 13.

<Semiconductor device configuration example 1>
1 (A) is a top view of the semiconductor device 100 according to one aspect of the present invention, and FIG. 1 (B) shows the alternate long and short dash line AB, the alternate long and short dash line CD of FIG. 1 (A), and FIG. 1 (B). It corresponds to the cross-sectional view of the cut surface between the alternate long and short dash lines EF. In FIG. 1A, a part of the components (gate insulating film, etc.) of the semiconductor device 100 is omitted in order to avoid complication. In the top view of the transistor, in the subsequent drawings, as in FIG. 1A, some of the components may be omitted.

The alternate long and short dash line AB in FIG. 1A shows the channel length direction of the transistor 150. Further, the alternate long and short dash line EF indicates the channel width direction of the transistor 150. In the present specification, the channel length direction of the transistor means the direction in which the carrier moves between the source (source region or source electrode) and the drain (drain region or drain electrode), and the channel width direction is the substrate. In a horizontal plane, it means the direction perpendicular to the channel length direction.

The semiconductor device 100 shown in FIGS. 1A and 1B includes a transistor 150 including a first oxide semiconductor film 108, and a capacitive element 160 including an insulating film between a pair of electrodes. note that,
In the capacitive element 160, one of the pair of electrodes is the second oxide semiconductor film 111b, and the other of the pair of electrodes is the conductive film 123.

The transistor 150 includes a gate electrode 106 on the substrate 102, an insulating film 104 that functions as a gate insulating film on the gate electrode 106, and a first oxide semiconductor film 10 on the insulating film 104.
8, the insulating film 110 on the first oxide semiconductor film 108, the second oxide semiconductor film 111a on the insulating film 110, the insulating film 104, the first oxide semiconductor film 108 and the second oxidation. It has an insulating film 116 on the material semiconductor film 111a. The first oxide semiconductor film 108 is
It has a channel region 108i that overlaps with the second oxide semiconductor film 111a, a source region 108s that is in contact with the insulating film 116, and a drain region 108d that is in contact with the insulating film 116.

In the transistor 150, the gate electrode 106 functions as a first gate electrode, and the second oxide semiconductor film 111a functions as a second gate electrode. The second oxide semiconductor film 111a is electrically connected to the gate electrode 106 via the insulating film 104 and the opening 142 provided in the insulating film 110. That is, the gate electrode 106 and the second oxide semiconductor film 111a have the same potential. In the transistor 150, the gate electrode 106 and the second
The oxide semiconductor film 111a of the above may operate independently and may be given different potentials. Further, the transistor 150 may be configured not to have the gate electrode 106 (FIG. 1).
(C)).

Further, the insulating film 116 has nitrogen or hydrogen. Insulating film 116 and source region 108
When s and the drain region 108d are in contact with each other, nitrogen or hydrogen in the insulating film 116 is added to the source region 108s and the drain region 108d. The carrier density of the source region 108s and the drain region 108d is increased by adding nitrogen or hydrogen.
In the first oxide semiconductor film 108, the source region 108s and the drain region 1
08d is shown by changing the hatching from the channel region 108i (see FIG. 1 (B)).

Further, the transistor 150 includes the insulating film 118 on the insulating film 116 and the insulating films 116 and 11.
The conductive film 120a electrically connected to the source region 108s via the opening 141a provided in 8, and electrically connected to the drain region 108d via the openings 141b provided in the insulating films 116 and 118. It may have a conductive film 120b to be connected.

In the present specification and the like, the insulating film 104 is the first insulating film, the insulating film 110 is the second insulating film, the insulating film 116 is the third insulating film, and the insulating film 118 is the fourth insulating film. The insulating film 122, which will be described later, may be referred to as a fifth insulating film. Further, the conductive film 112 has a function as a gate electrode, the conductive film 120a has a function as one of a source electrode or a drain electrode, and the conductive film 120b has a function as one of a source electrode or a drain electrode. Have.

Further, the insulating film 110 has a function as a gate insulating film. In addition, the insulating film 110 is
Has an excess oxygen region. Since the insulating film 110 has an excess oxygen region, excess oxygen can be supplied into the channel region 108i of the first oxide semiconductor film 108. Therefore, since the oxygen deficiency that can be formed in the channel region 108i can be compensated by the excess oxygen, a highly reliable semiconductor device can be provided.

In order to supply excess oxygen into the first oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the first oxide semiconductor film 108. however,
In this case, the excess oxygen contained in the insulating film 104 can also be supplied to the source region 108s and the drain region 108d of the first oxide semiconductor film 108. Source area 108s
, And when excess oxygen is supplied into the drain region 108d, the resistance of the source region 108s and the drain region 108d may increase.

On the other hand, by configuring the insulating film 110 formed above the first oxide semiconductor film 108 to have excess oxygen, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the source region 108s and the drain region 108d
By selectively increasing the carrier density of the source region 108s and the drain region 108
It is possible to suppress an increase in the resistance of d.

Further, the source region 108s and the drain region 10 of the first oxide semiconductor film 108
It is preferable that each of 8d has one or more elements forming an oxygen deficiency or the following elements that bind to oxygen deficiency. Typical examples of the element that forms the oxygen deficiency or the element that binds to the oxygen deficiency include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gas. Typical examples of rare gas elements include helium, neon, argon, krypton, xenon and the like. The element forming the oxygen deficiency is the insulating film 11.
The constituent elements of 6 are diffused into the source region 108s and the drain region 108d, or are added into the source region 108s and the drain region 108d by the impurity addition treatment.

When the impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is broken, and an oxygen deficiency is formed. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is combined with the impurity element, oxygen is desorbed from the metal element, and oxygen deficiency is formed. To. As a result, the carrier density of the oxide semiconductor film is increased and the conductivity is increased.

Further, the insulating film 122 and the conductive film 123 are formed on the insulating film 118, the conductive film 120a and the conductive film 120b in this order. An opening 143 that reaches the second oxide semiconductor film 111b is formed in the insulating film 116 and the insulating film 118, and the conductive film 120b and the second oxide semiconductor film 111b are electrically connected through the opening 143. It is connected to the. The second oxide semiconductor film 111b has a function as, for example, a pixel electrode. Further, the conductive film 123 has a function as, for example, a common electrode.

The second oxide semiconductor film 111b has a function as a common electrode, and the conductive film 123.
May have a function as a pixel electrode (see FIG. 2A). In FIG. 2 (A),
The conductive film 123 is electrically connected to the conductive film 120b via an opening 144 provided in the insulating film 122. Further, instead of the second oxide semiconductor film 111b, the first oxide semiconductor film 108b formed at the same time as the first oxide semiconductor film 108 may have a function as a pixel electrode (Fig.). 2 (B)). Further, the first oxide semiconductor film 108b may have a function as a common electrode, and the conductive film 123 may have a function as a pixel electrode (FIG. 2).
(C)).

Further, the auxiliary electrode may be connected to the conductive film 123 having the function of the common electrode. When the second oxide semiconductor film 111b functions as a pixel electrode of the transmissive liquid crystal display device, it is preferable that the auxiliary electrode is provided at a position where it does not overlap with the second oxide semiconductor film 111b. For example, a conductive film 124 that functions as an auxiliary electrode may be provided on the conductive film 123 (see FIGS. 3A and 3B). Further, the conductive film 1 that can be formed at the same time as the conductive films 120a and 120b.
20c may be provided as an auxiliary wiring of the conductive film 123 (see FIGS. 4A and 4B). In FIGS. 4A and 4B, the conductive film 120c is electrically connected to the conductive film 123 through the opening 145 provided in the insulating film 122. Note that FIGS. 3 (B) and 4 (B) correspond to cross-sectional views of the cut surfaces between the alternate long and short dash lines AB and the alternate long and short dash lines CG in FIGS. 3 (A) and 4 (A), respectively. ..

The capacitive element 160 includes a second oxide semiconductor film 111 that functions as one of a pair of electrodes on the insulating film 110, and an insulating film 116 that functions as a dielectric film on the second oxide semiconductor film 111. It has an insulating film 118 and an insulating film 122, and a conductive film 123 having a function as the other of a pair of electrodes on the insulating film 122. That is, the second oxide semiconductor film 111b has a function as a pixel electrode and a function as an electrode of a capacitive element. Further, the conductive film 123 has a conductive film 123.
It has a function as a common electrode and a function as an electrode of a capacitive element.

It is preferable that the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b have the same metal element. By configuring the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b to have the same metal element, a manufacturing apparatus (for example, a film forming apparatus, a processing apparatus, etc.) can be commonly used. Therefore, the manufacturing cost can be suppressed.

Further, the semiconductor device 100 shown in FIG. 1 has a second oxide semiconductor film 111a that functions as a gate electrode of the transistor 150 and a second oxide semiconductor film 11 that functions as a pixel electrode.
1b is formed simultaneously using the same material. With such a configuration, the number of steps for manufacturing the semiconductor device can be reduced, and the manufacturing cost can be suppressed.

Further, the capacitive element 160 has translucency. That is, the second capacitance element 160 has.
The oxide semiconductor film 111b, the conductive film 123, and the insulating films 116, 118, 122 are each made of a translucent material. In this way, since the capacitive element 160 has translucency, it can be formed large (in a large area) in a region other than the portion where the transistor is formed in the pixel, so that the capacitive value can be increased while increasing the aperture ratio. An increased semiconductor device can be obtained. As a result, a semiconductor device having excellent display quality can be obtained.

In the transistor 150, the channel region 10 of the first oxide semiconductor film 108
8i has a higher resistivity than the source region 108s and the drain region 108d. Further, since the second oxide semiconductor films 111a and 111b have a function as electrodes, the resistivity is lower than that of the channel region 108i of the first oxide semiconductor film 108.

Here, a method for controlling the resistivity of the first oxide semiconductor film 108 and the second oxide semiconductor film 111 will be described below.

<Method of controlling resistivity of oxide semiconductor>
The oxide semiconductor film that can be used for the first oxide semiconductor film 108 and the second oxide semiconductor film 111 has a resistance rate due to oxygen deficiency in the film and / or the concentration of impurities such as hydrogen and water in the film. It is a semiconductor material that can control. Therefore, the first oxide semiconductor film 108
By selecting a treatment for increasing the oxygen deficiency and / or the impurity concentration in the second oxide semiconductor film 111, or a treatment for reducing the oxygen deficiency and / or the impurity concentration, the resistance of each oxide semiconductor film can be determined. Can be controlled.

Specifically, the oxide semiconductor film in the region where low efficiency is desired to be reduced is subjected to plasma treatment to increase oxygen deficiency in the oxide semiconductor film, and / or hydrogen, water, etc. in the oxide semiconductor film. By increasing the impurities in the above, it is possible to obtain an oxide semiconductor film having a high carrier density and a low resistance. Further, by forming an insulating film containing hydrogen in contact with the oxide semiconductor film and diffusing hydrogen from the insulating film containing hydrogen, for example, the insulating film 116 to the oxide semiconductor film, the carrier density is high and the resistance is high. It can be a low oxide semiconductor film. At this time, the oxide semiconductor film functions as an oxide conductor (OC). For example, the second oxide semiconductor films 111a and 111b have a function as a semiconductor before the step of increasing oxygen deficiency in the membrane or diffusing hydrogen as described above, and after the step. Has a function as a conductor.

On the other hand, the channel region 108i of the first oxide semiconductor film 108 is configured not to come into contact with the insulating film 116 containing hydrogen by providing the insulating film 110. By applying an insulating film containing oxygen to at least one of the insulating films 104 and 110, in other words, an insulating film capable of releasing oxygen, oxygen is applied to the region of the oxide semiconductor film to be the channel region 108i. Can be supplied. The channel region 108i to which oxygen is supplied becomes an oxide semiconductor film having a high resistivity by compensating for oxygen deficiency in the film or at the interface. As the insulating film capable of releasing oxygen, for example, a silicon oxide film or a silicon nitride film can be used.

Further, in order to obtain an oxide semiconductor film having a low resistance, hydrogen, boron, phosphorus or nitrogen is injected into the oxide semiconductor film by using an ion implantation method, an ion doping method, a plasma implantation ion implantation method or the like. You may.

Further, in order to obtain an oxide semiconductor film having a low resistivity, the oxide semiconductor film may be subjected to plasma treatment. For example, the plasma treatment is typically a noble gas (He, Ne, A).
Plasma treatment using a gas containing one or more selected from r, Kr, Xe), hydrogen, and nitrogen can be mentioned. More specifically, plasma treatment in an Ar atmosphere, plasma treatment in an Ar and hydrogen mixed gas atmosphere, plasma treatment in an ammonia atmosphere, plasma treatment in an Ar and ammonia mixed gas atmosphere, or nitrogen. Plasma treatment in an atmosphere can be mentioned.

By the above plasma treatment, the oxide semiconductor film forms an oxygen deficiency in the oxygen-desorbed lattice (or the oxygen-desorbed portion). The oxygen deficiency may be a factor in generating carriers. Further, when hydrogen is supplied from the vicinity of the oxide semiconductor film, more specifically, from the insulating film in contact with the lower side or the upper side of the oxide semiconductor film, the oxygen deficiency and hydrogen are combined to form a carrier. May generate electrons.

On the other hand, the oxide semiconductor film in which the oxygen deficiency is compensated and the hydrogen concentration is reduced is highly pure and intrinsic.
Alternatively, it can be said that it is an oxide semiconductor film that has been substantially purified. Here, what is practically true?
The carrier density of the oxide semiconductor film is 8 × 10 ¹¹ pieces / cm ³ or less, preferably 1 × 10 ¹ .
It means less than ¹ / ^cm3 , more preferably less than 1 × 10 ¹⁰ pieces / ^cm3 . Oxide semiconductor films having high-purity intrinsics or substantially high-purity intrinsics have few carrier sources, so that the carrier density can be lowered. Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density can be reduced.

Further, an oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a remarkably small off-current, and even if it is an element having a channel width of 1 × ¹⁰⁶ μm and a channel length of L of 10 μm, it can be used as a source electrode. When the voltage between the drain electrodes (drain voltage) is in the range of 1 V to 10 V, it is possible to obtain the characteristic that the off current is not more than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ^-13 A or less. Therefore, the transistor 150 that uses the above-mentioned region of the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity for the channel region 108i is a highly reliable transistor with little variation in electrical characteristics.

As the insulating film 116, for example, an insulating film containing hydrogen, in other words, an insulating film capable of releasing hydrogen, typically a silicon nitride film, is used to form a first oxide semiconductor film 108 and a second. Hydrogen can be supplied to the oxide semiconductor films 111a and 111b of the above. As an insulating film capable of releasing hydrogen, the concentration of hydrogen contained in the film is 1 × 10 ²² atoms / c.
It is preferably m ³ or more. By forming such an insulating film in contact with the oxide semiconductor film, the oxide semiconductor film can be effectively contained with hydrogen. Thus, the first
The resistivity of the oxide semiconductor film can be controlled by changing the configuration of the insulating film in contact with the oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b.

The hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to become water, and at the same time, forms an oxygen deficiency in the oxygen-desorbed lattice (or the oxygen-desorbed portion). When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be bonded to oxygen, which is bonded to a metal atom, to generate an electron as a carrier.

It is preferable that hydrogen is reduced as much as possible in the channel region 108i of the first oxide semiconductor film 108. Specifically, in the channel region 108i, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹ .
⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, 5 ×
10 ¹⁸ atoms / cm less than ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, still more preferably 1 × 10 ¹⁶ at.
oms / cm ³ or less.

On the other hand, the hydrogen concentration contained in the source region 108s, drain region 108d and the second oxide semiconductor films 111a and 111b of the first oxide semiconductor film 108 is 8 × 10 ¹⁹ or more.
It is preferably 1 × 10 ²⁰ atoms / cm ³ or more, and more preferably 5 × 10 ²⁰ or more. Alternatively, the hydrogen concentration contained in these oxide semiconductor films is twice or more, preferably 10 times or more, as compared with the channel region 108i. Further, the resistivity of these oxide semiconductor films is preferably 1 × 10 ^-8 times or more and less than 1 × 10 ^-1 times the resistivity of the channel region 108i, and is typically 1 × 10 ^-3 Ωcm. It is preferable that the resistivity is 1 × 10 ^-3 Ωcm or more and more preferably less than 1 × ^{10 -1} Ωcm, more preferably less than 1 × 10 -3 Ωcm.

Here, the details of the other components of the semiconductor device 100 shown in FIGS. 1 (A) and 1 (B) will be described below.

<Board>
There are no major restrictions on the material of the substrate 102, but at least it must have heat resistance sufficient to withstand the subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Further, it is also possible to apply a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like, and a semiconductor element is provided on these substrates. May be used as the substrate 102. When a glass substrate is used as the substrate 102, the 6th generation (1500 mm × 1850 mm) and the 7th generation (1870 mm × 2200 mm) are used.
m), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800m)
m), a large-sized display device can be manufactured by using a large-area substrate such as the 10th generation (2950 mm × 3400 mm). Further, a flexible substrate may be used as the substrate 102, and the transistor 150, the capacitive element 160, and the like may be formed directly on the flexible substrate.

In addition to these, various substrates can be used as the substrate 102 to form transistors. The type of substrate is not limited to a specific one. Examples of the substrate include a plastic substrate, a metal substrate, a stainless still substrate, a substrate having a stainless still foil, a tungsten substrate, a substrate having a tungsten foil, and a flexible substrate.
There are laminated films, papers containing fibrous materials, base films, and the like. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of a flexible substrate, polyethylene terephthalate (PE)
There are flexible synthetic resins such as T), polyethylene naphthalate (PEN), plastics typified by polyether sulfone (PES), and acrylics. Examples of the laminated film include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride and the like. Examples of the base film include polyester, polyamide, polyimide, inorganic vapor-deposited film, paper and the like. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to manufacture a transistor having a high current capacity and a small size with little variation in characteristics, size, or shape. .. When a circuit is configured with such transistors, it is possible to reduce the power consumption of the circuit or increase the integration of the circuit.

A transistor may be formed using a certain substrate, then the transistor may be transposed to another substrate, and the transistor may be arranged on another substrate. As an example of the substrate on which the transistor is translocated, in addition to the substrate capable of forming the above-mentioned transistor, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, linen), etc. Synthetic fiber (nylon, polyurethane, polyester) or recycled fiber (acetate, cupra, rayon,
(Including recycled polyester), leather substrate, rubber substrate, etc. By using these substrates, it is possible to form a transistor having good characteristics, to form a transistor having low power consumption, to manufacture a device that is hard to break, to impart heat resistance, to reduce the weight, or to reduce the thickness.

<First insulating film>
The insulating film 104 includes a sputtering method, a CVD method, a vapor deposition method, and pulsed laser deposition (
It can be formed by appropriately using a PLD) method, a printing method, a coating method, or the like. In addition, the insulating film 104
For example, an oxide insulating film or a nitride insulating film can be formed as a single layer or laminated. In order to improve the interface characteristics with the oxide semiconductor film 108, it is preferable that at least the region of the insulating film 104 in contact with the oxide semiconductor film 108 is formed of the oxide insulating film. Further, by using an oxide insulating film that releases oxygen by heating as the insulating film 104, oxygen contained in the insulating film 104 can be transferred to the oxide semiconductor film 108 by heat treatment.

The thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By thickening the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108. 1
It is possible to reduce the oxygen deficiency contained in 08i.

As the insulating film 104, for example, silicon oxide, silicon nitride nitride, silicon nitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 104 may be provided in a single layer or in a laminated manner. In the present embodiment, a laminated structure of a silicon nitride film and a silicon oxide film is used as the insulating film 104. As described above, by using the insulating film 104 as a laminated structure, using the silicon nitride film on the lower layer side and using the silicon oxide nitride film on the upper layer side, oxygen can be efficiently introduced into the oxide semiconductor film 108.

<First oxide semiconductor film and second oxide semiconductor film>
The first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b have at least indium (In), zinc (Zn) and M (Al, Ti, Ga, Y, Zr, La, C).
It is preferable to include a film represented by an In—M—Zn oxide containing (a metal such as e, Sn or Hf). Further, in order to reduce variations in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to include a stabilizer together with them.

Stabilizers include, for example, gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr), including the metals described in M above.
And so on. Another stabilizer is lanthanum (La), which is a lanthanoid.
, Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Samarium (Sm),
Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (
Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu) and the like.

Examples of the oxide semiconductors constituting the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b include In—Ga—Zn-based oxides and In—Al—Zn-based oxides.
In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, I
n-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In
-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-
Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-E
r-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu
-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide,
In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf
-Zn-based oxides and In-Hf-Al-Zn-based oxides can be used.

Here, the In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn does not matter. In, Ga, and Z
A metal element other than n may be contained.

Further, the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b may have the same metal element among the above oxides. First oxide semiconductor film 108
By using the second oxide semiconductor film 111 as the same metal element, the manufacturing cost can be reduced. For example, the manufacturing cost can be reduced by using a metal oxide target having the same metal composition. Further, by using a metal oxide target having the same metal composition, an etching gas or an etching solution for processing an oxide semiconductor film can be commonly used. However, even if the first oxide semiconductor film 108 and the second oxide semiconductor film 111 have the same metal element, the composition may be different. For example, during the manufacturing process of a transistor and a capacitive element, the metal element in the film may be desorbed to have a different metal composition.

When the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b are In—M—Zn oxides, the atomic number ratio of In and M is 100, which is the sum of In and M.
When it is set to atomic%, In is preferably higher than 25 atomic% and M is 75a.
Less than tomic%, more preferably In is higher than 34atomic% and M is 66 at
It shall be less than omic%.

The channel region 108i has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. As described above, by using an oxide semiconductor having a wide energy gap, the off-current of the transistor 150 can be reduced.

The thickness of the first oxide semiconductor film 108 is 3 nm or more and 200 nm or less, preferably 3 nm.
It is 100 nm or less, more preferably 3 nm or more and 60 nm or less. The thickness of the second oxide semiconductor films 111a and 111b is 3 nm or more and 100 nm or less, preferably 30 nm or more and 70 nm or less, and more preferably 30 nm or more and 50 nm or less.

The oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b are In—MZ.
In the case of n oxide, it is preferable that the atomic number ratio of the metal element of the sputtering target used for forming the In—M—Zn oxide is satisfied with In ≧ M and Zn ≧ M. The atomic number ratio of the metal element of such a sputtering target is In: M: Zn = 1: 1: 1, I.
n: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2
1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M:
Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7, and the like are preferable. The atomic number ratio of the oxide semiconductor film 108 to be formed may fluctuate by about plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target. For example, when the atomic number ratio of In: Ga: Zn = 4: 2: 4.1 is used as the sputtering target,
The atomic number ratio of the oxide semiconductor film to be formed may be in the vicinity of In: Ga: Zn = 4: 2: 3. Further, as a sputtering target, the atomic number ratio is In: Ga: Zn = 5: 1.
When: 7 is used, the atomic number ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 5: 1.
: May be near 6.

As the channel region 108i, an oxide semiconductor film having a low carrier density is used. For example, the channel region 108i has a carrier density of 1 × 10 ¹⁷ pieces / cm ³ or less, preferably 1
An oxide semiconductor film having × 10 ¹⁵ pieces / cm ³ or less, more preferably 1 × 10 ¹³ pieces / cm ³ or less, and more preferably 1 × 10 ¹¹ pieces / cm ³ or less is used.

Not limited to these, a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, atomic number ratio between metal element and oxygen, interatomic distance, density, etc. of the first oxide semiconductor film 108 are appropriately selected. It is preferable to use the above.

If silicon or carbon, which is one of the Group 14 elements, is contained in the first oxide semiconductor film 108, oxygen deficiency increases in the first oxide semiconductor film 108, resulting in n-type formation.
Therefore, the concentration of silicon and carbon in the first oxide semiconductor film 108 (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 ×.
10 ¹⁷ atoms / cm ³ or less.

Further, in the channel region 108i, the concentration of the alkali metal or alkaline earth metal obtained by the secondary ion mass spectrometry is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. .. Alkali metals and alkaline earth metals are
When combined with an oxide semiconductor, carriers may be generated, which may increase the off-current of the transistor. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the first oxide semiconductor film 108.

Further, when nitrogen is contained in the channel region 108i, electrons as carriers are generated, the carrier density increases, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible in the oxide semiconductor film, for example, the nitrogen concentration obtained by the secondary ion mass spectrometry is preferably 5 × 10 ¹⁸ atoms / cm ³ or less. ..

Further, by reducing the impurity elements in the channel region 108i, the carrier density of the oxide semiconductor film can be reduced. Therefore, in the channel region 108i,
The carrier density can be 1 x 10 ¹⁷ pieces / cm ³ or less, or 1 x 10 ¹⁵ pieces / cm ³ or less, or 1 x 10 ¹³ pieces / cm ³ or less, or 1 x 10 ¹¹ pieces / cm ³ or less. ..

By using an oxide semiconductor film having a low impurity concentration and a low defect level density as the channel region 108i, a transistor having further excellent electrical characteristics can be manufactured.
Here, a low impurity concentration and a low defect level density (less oxygen deficiency) is referred to as high-purity intrinsic or substantially high-purity intrinsic. Alternatively, it is called true or substantially true. Oxide semiconductors with high-purity intrinsics or substantially high-purity intrinsics have few carrier sources, and therefore
It may be possible to reduce the carrier density. Therefore, the transistor in which the channel region is formed in the oxide semiconductor film tends to have an electric characteristic (also referred to as a normally-off characteristic) in which the threshold voltage is positive. Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.
Further, the oxide semiconductor film having high-purity intrinsicity or substantially high-purity intrinsicity can obtain the property that the off-current is remarkably small. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may be a highly reliable transistor with small fluctuations in electrical characteristics.

On the other hand, the source region 108s and the drain region 108d are in contact with the insulating film 116.
When the source region 108s and the drain region 108d are in contact with the insulating film 116, nitrogen or hydrogen is added from the insulating film 116 to the source region 108s and the drain region 108d, so that the carrier density is increased.

Further, the first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b may have a non-single crystal structure. The non-single crystal structure is, for example, CAAC-OS (CAx) described later.
is Defined-Crystalline Oxide Semiconduct
or), includes a polycrystalline structure, a microcrystal structure described later, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest defect level density, and CAAC-OS has the lowest defect level density.

The first oxide semiconductor film 108 and the second oxide semiconductor films 111a and 111b have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal region. It may be a single-layer film having two or more kinds of regions of a crystal structure, or a structure in which these films are laminated.

The first oxide semiconductor film 108 is a mixed film having two or more kinds of an amorphous structure region, a microcrystal structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure. May be. The mixed film may be, for example, an amorphous region, a microcrystal region, a polycrystalline region, CA.
It may have two or more regions, either an AC-OS region or a single crystal structure region. Further, the mixed film may be, for example, an amorphous region, a microcrystal region, a polycrystalline region, or CA.
It may have a laminated structure of two or more types of either an AC-OS region or a single crystal structure region.

In the first oxide semiconductor film 108, the channel region 108i and the source region 1
The crystallinity of 08s and the drain region 108d may be different. Specifically, in the oxide semiconductor film 108, the source region 108s and the drain region 108d may have lower crystallinity than the channel region 108i. This is because when an impurity element is added to the source region 108s and the drain region 108d, the source region 108s and the drain region 10
This is because 8d is damaged and the crystallinity is lowered.

<Second insulating film>
The insulating film 110 functions as a gate insulating film of the transistor 150. In addition, the insulating film 1
Reference numeral 10 has a function of supplying oxygen to the oxide semiconductor film 108, particularly the channel region 108i. For example, as the insulating film 110, an oxide insulating film or a nitride insulating film can be formed as a single layer or laminated. In order to improve the interface characteristics with the oxide semiconductor film 108, it is preferable that the region of the insulating film 110 in contact with the oxide semiconductor film 108 is formed by using at least the oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon nitriding, silicon nitride, silicon nitride, or the like may be used.

The thickness of the insulating film 110 is 5 nm or more and 400 nm or less, or 5 nm or more and 300 n.
It can be m or less, or 10 nm or more and 250 nm or less.

Further, the insulating film 110 preferably has few defects, and typically, it is preferable that the insulating film 110 has few signals observed by an electron spin resonance method (ESR: Electron Spin Resonance). For example, the above-mentioned signal includes an E'center where a g value is observed at 2.001. The E'center is due to the dangling bond of silicon. As the insulating film 110, the spin density due to the E'center is 3 × 10 ¹⁷ spi.
A silicon oxide film having an ns / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less, or a silicon nitride film may be used.

Further, in the insulating film 110, a signal caused by nitrogen dioxide (NO ₂ ) may be observed in addition to the above-mentioned signal. The signal is divided into three signals by the nuclear spin of N, and each g value is 2.037 or more and 2.039 or less (referred to as the first signal).
, G value is 2.001 or more and 2.003 or less (referred to as the second signal), and g value is 1.96.
It is observed at 4 or more and 1.966 or less (referred to as a third signal).

For example, as the insulating film 110, the spin density due to nitrogen dioxide (NO ₂ ) is 1 × 10 ¹ .
It is preferable to use an insulating film having ⁷ spins / cm ³ or more and 1 × 10 ¹⁸ spins / cm ³ or less.

The nitrogen oxide (NO _x ) containing nitrogen dioxide (NO ₂ ) forms a level in the insulating film 110. The level is located within the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxides (NOx) diffuse to the interface between the insulating film 110 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 110 side. As a result, the trapped electrons stay in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, the insulating film 11
As 0, if a film having a low nitrogen oxide content is used, the shift of the threshold voltage of the transistor can be reduced.

As the insulating film in which the amount of nitrogen oxide (NO _x ) released is small, for example, a silicon oxide film can be used. The silicon oxide film is subjected to a heated desorption gas analysis method (TDS: Th).
In the thermal Desorption Spectroscopy), it is a film in which the amount of ammonia released is larger than the amount of nitrogen oxides (NO _x ) released, and the amount of ammonia released is typically 1 × 10 ¹⁸ / cm ³ or more 5 × 10 ¹⁹ . / Cm ³ or less. The amount of ammonia released is the total amount in the range where the temperature of the heat treatment in TDS is 50 ° C. or higher and 650 ° C. or lower, or 50 ° C. or higher and 550 ° C. or lower.

Since nitrogen oxides (NO _x ) react with ammonia and oxygen in the heat treatment, nitrogen oxides (NO _x ) are reduced by using an insulating film that releases a large amount of ammonia.

When the insulating film 110 was analyzed by SIMS, the nitrogen concentration in the film was 6 × 10 ²⁰ ato.
It is preferably ms / cm ³ or less.

Further, as the insulating film 110, hafnium silicate (HfSiO _x ), nitrogen-added hafnium silicate ( _{HfSi xOyNz} ), nitrogen-added _{hafniumaluminate ( HfAl xOyNz} ), hafnium oxide, etc. High-k material may be used.
By using the high-k material, the gate leak of the transistor can be reduced.

<Third insulating film>
The insulating film 116 has nitrogen or hydrogen. Further, the insulating film 116 may have fluorine. Examples of the insulating film 116 include a nitride insulating film. The nitride insulating film can be formed by using silicon nitride, silicon nitride oxide, silicon nitride fluoride, silicon fluoride nitride, or the like. The hydrogen concentration contained in the insulating film 116 is 1 × 10 ²² a.
It is preferably toms / cm ³ or more. Further, the insulating film 116 is an oxide semiconductor film 108.
It is in contact with the source region 108s and the drain region 108d. Therefore, the insulating film 116
Impurities (nitrogen or hydrogen) in the source region 108s and drain region 108d in contact with
The concentration is increased, and the carrier density of the source region 108s and the drain region 108d can be increased.

<Fourth insulating film>
An oxide insulating film can be used as the insulating film 118. Further, as the insulating film 118, a laminated film of an oxide insulating film and a nitride insulating film can be used. As the insulating film 118, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, etc.
Hafnium oxide, gallium oxide, Ga-Zn oxide, etc. may be used.

Further, the insulating film 118 is preferably a film that functions as a barrier film for hydrogen, water, etc. from the outside.

The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 n.
It can be m or less.

<Conductor>
The conductive films 120a and 120b can be formed by using a sputtering method, a vacuum vapor deposition method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. In addition, the conductive film 120a
, 120b includes, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, an alloy containing the above-mentioned metal element as a component, or the above-mentioned metal element. It can be formed by using a combined alloy or the like. Further, a metal element selected from any one or more of manganese and zirconium may be used. Further, the conductive films 120a and 120b may have a single-layer structure or a laminated structure having two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, and nitrided. Two-layer structure in which a tungsten film is laminated on a titanium film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a titanium nitride film, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and a titanium film. A two-layer structure in which a copper film is laminated on a titanium film, a three-layer structure in which an aluminum film is laminated on the titanium film, and a titanium film is formed on the titanium film, and a copper film is laminated on a copper film containing manganese. Further, there is a three-layer structure in which a copper film containing manganese is formed on the copper film. Further, an alloy film or a nitride film in which one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be combined with aluminum may be used.

In particular, as the conductive films 120a and 120b, it is preferable to use a material containing copper. When a material containing copper is used for the conductive films 120a and 120b, the resistance can be lowered. For example, even when a large-area substrate is used as the substrate 102, signal delay and the like can be suppressed.

The conductive film 123 includes indium tin oxide (I).
TO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon (TO) It can be formed by using a translucent conductive material such as In—Sn—Si oxide: also referred to as ITSO). As the conductive films 120a and 120b, these conductive materials having translucency may be used. Further, the conductive films 120a and 120b may have a laminated structure of the conductive material having the translucency and the metal element.

As the conductive film 124 and the conductive film 120c, the same materials as those of the conductive film 120a and the conductive film 120b can be used.

<Fifth insulating film>
The insulating film 122 that functions as the protective insulating film of the transistor 150 is a plasma CV.
Silicon oxide film, silicon nitride film, silicon nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, etc. by the D method, sputtering method, etc. An insulating film containing one or more of a magnesium oxide film, a lanthanum oxide film, a cerium oxide film and a neodym oxide film can be used. Alternatively, as the insulating film 122, the same material as the third insulating film or the fourth insulating film can be used.

<Semiconductor device configuration example 2>
Next, a configuration different from the semiconductor device 100 shown in FIGS. 1A and 1B will be described with reference to FIG.

FIG. 5A is a cross-sectional view of the semiconductor device 100A, and FIG. 5B is a semiconductor device 100.
It is sectional drawing of B. Since the top views of the semiconductor device 100A and the semiconductor device 100B are the same as those of the semiconductor device 100 shown in FIG. 1A, the description thereof is omitted here.

The transistor 150A included in the semiconductor device 100A shown in FIG. 5A has a different shape from the transistor 150 included in the semiconductor device 100 shown above, the insulating film 110, and the second oxide semiconductor film 111a. Specifically, in the cross section of the transistor in the channel length (L) direction, the transistor 150 has the insulating film 110 and the second oxide semiconductor film 111a having a tapered shape, whereas the transistor 150A is insulated. The shapes of the film 110 and the second oxide semiconductor film 111a are rectangular. More specifically, in the transistor 150, the upper end portion of the second oxide semiconductor film 111a is formed inside the lower end portion of the insulating film 110 in the cross section in the channel length (L) direction of the transistor. In other words, the side end portion of the insulating film 110 is located outside the side end portion of the second oxide semiconductor film 111a. On the other hand, in the transistor 150A, the upper end portion of the second oxide semiconductor film 111a and the lower end portion of the insulating film 110 are formed at substantially the same position in the cross section in the channel length (L) direction of the transistor.

The transistor 150 can be formed by processing the second oxide semiconductor film 111a and the insulating film 110 with the same mask, and processing by combining a wet etching method and a dry etching method. The transistor 150A includes a second oxide semiconductor film 111a.
And the insulating film 110 can be formed by processing them with the same mask and collectively processing them using a dry etching method.

It is preferable to have a configuration like the transistor 150 because the covering property of the insulating film 116 is improved. On the other hand, by configuring the transistor 150A, the source region 108
It is preferable because the ends of the s and the drain region 108d and the second oxide semiconductor film 111a are formed at substantially the same position.

The transistor 150B included in the semiconductor device 100B shown in FIG. 5B is different from the transistor 150A shown above in the shapes of the second oxide semiconductor film 111a and the insulating film 110. Specifically, the transistor 150B has a different position between the lower end portion of the second oxide semiconductor film 111a and the upper end portion of the insulating film 110 in the cross section in the channel length (L) direction of the transistor. The lower end portion of the second oxide semiconductor film 111a is formed inside the upper end portion of the insulating film 110.

For example, the second oxide semiconductor film 111a and the insulating film 110 are processed with the same mask.
The structure of the transistor 150B can be obtained by processing the second oxide semiconductor film 111a by a wet etching method and the insulating film 110 by a dry etching method.

Further, by adopting the structure of the transistor 150B, in the first oxide semiconductor film 108,
Region 108f may be formed. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

The region 108f functions as either a high resistance region or a low resistance region. The high resistance region is a second region having a resistance equivalent to that of the channel region 108i and functioning as a gate electrode.
This is a region where the oxide semiconductor film 111a of the above is not superimposed. When the region 108f is a high resistance region,
The region 108f functions as a so-called offset region. When the region 108f functions as an offset region, the region 108f may be set to 1 μm or less in the cross section in the channel length (L) direction in order to suppress a decrease in the on-current of the transistor 150B.

Further, the low resistance region has a lower resistance than the channel region 108i and the source region 10
This is a region having a higher resistance than the 8s and the drain region 108d. When the region 108f is a low resistance region, the region 108f functions as a so-called LDD (Lightly Doped Drain) region. When the region 108f functions as the LDD region, the electric field in the drain region can be relaxed, so that the fluctuation of the threshold voltage of the transistor due to the electric field in the drain region can be reduced.

When the region 108f is used as the LDD region, for example, the insulating film 116 to the region 10
Nitrogen or hydrogen is supplied to 8f, or an impurity element is added from above the second oxide semiconductor film 111a and the insulating film 110 using the second oxide semiconductor film 111a and the insulating film 110 as a mask. The impurities pass through the insulating film 110, and the first oxide semiconductor film 10
It can be formed by being added to 8.

<Semiconductor device configuration example 3>
Next, a configuration different from the semiconductor device 100 shown in FIGS. 1A and 1B will be described with reference to FIGS. 6 to 8.

FIG. 6A is a cross-sectional view of the semiconductor device 100C, and FIG. 6B is a semiconductor device 100.
FIG. 7A is a cross-sectional view of D, FIG. 7A is a cross-sectional view of the semiconductor device 100E, and FIG. 7B is a cross-sectional view.
It is a cross-sectional view of the semiconductor device 100F, and FIG. 8 is a cross-sectional view of the semiconductor device 100G. The semiconductor device 100C, the semiconductor device 100D, the semiconductor device 100E, and the semiconductor device 100F.
, And the top view of the semiconductor device 100G is the same as that of the semiconductor device 100 shown in FIG. 1 (A), and thus the description thereof is omitted here.

The transistor 150C included in the semiconductor device 100C, the transistor 150D included in the semiconductor device 100D, the transistor 150E included in the semiconductor device 100E, the transistor 150F included in the semiconductor device 100F, and the transistor 150G included in the semiconductor device 100G are shown above. The structures of the transistor 150A and the first oxide semiconductor film 108 are different. Other than that, the configuration is the same as that of the transistor 150A shown above, and the same effect is obtained.

The first oxide semiconductor film 108 included in the transistor 150C shown in FIG. 6 (A) includes an oxide semiconductor film 108_1 on the insulating film 104, an oxide semiconductor film 108_1 on the oxide semiconductor film 108_1, and an oxide semiconductor. It has an oxide semiconductor film 108_3 on the film 108_2. Further, the channel region 108i, the source region 108s, and the drain region 108d are the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 1, respectively.
It is a three-layer laminated structure of 08_3.

The first oxide semiconductor film 108 included in the transistor 150D shown in FIG. 6B has an oxide semiconductor film 108_2 on the insulating film 104 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. Further, the channel region 108i, the source region 108s, and the drain region 108d are the oxide semiconductor film 108_2 and the oxide semiconductor film 10, respectively.
It is a two-layer laminated structure of 8_3.

The first oxide semiconductor film 108 included in the transistor 150E shown in FIG. 7A has an oxide semiconductor film 108_1 on the insulating film 104 and an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1. Further, the channel region 108i, the source region 108s, and the drain region 108d are the oxide semiconductor film 108_1 and the oxide semiconductor film 10, respectively.
It is a two-layer laminated structure of 8_2.

The first oxide semiconductor film 108 included in the transistor 150F shown in FIG. 7B includes an oxide semiconductor film 108_1 on the insulating film 104, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide semiconductor. It has an oxide semiconductor film 108_3 on the film 108_2. Further, the channel region 108i includes an oxide semiconductor film 108_1 and an oxide semiconductor film 108_.
2 and the oxide semiconductor film 108_3 have a three-layer laminated structure, and the source region 108s and the drain region 108d are the oxide semiconductor film 108_1 and the oxide semiconductor film 1, respectively.
It is a two-layer laminated structure of 08_2. In the cross section of the transistor 150F in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side surfaces of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.

The first oxide semiconductor film 108 included in the transistor 150G shown in FIG. 8 is an insulating film 10.
Oxide semiconductor film 108_2 on 4 and oxide semiconductor film 10 on oxide semiconductor film 108_2
8_3 and. Further, the channel region 108i is a laminated structure of two layers of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3, and the source region 108s and the drain region 108d are each having a single layer structure of the oxide semiconductor film 108_2. be. In the cross section of the transistor 150G in the channel width (W) direction, the oxide semiconductor film 108_3 is formed.
It covers the side surface of the oxide semiconductor film 108_2.

On the side surface of the channel region 108i in the channel width (W) direction or its vicinity, defects (for example, oxygen deficiency) are likely to be formed due to damage in processing, or contamination is likely to occur due to adhesion of impurities. Therefore, even if the channel region 108i is substantially true, the channel width of the channel region 108i (
The side surface in the W) direction or its vicinity is activated, and tends to be a low resistance (n-type) region. also,
When the side surface of the channel region 108i in the channel width (W) direction or its vicinity is an n-type region,
Parasitic channels may be formed because the n-type region serves as a carrier path.

Therefore, in the transistor 150F and the transistor 150G, the channel region 108i is formed in a laminated structure, and the side surface of the channel region 108i in the channel width (W) direction is covered with one layer of the laminated structure. With this configuration, it is possible to suppress defects on or near the side surface of the channel region 108i, or reduce the adhesion of impurities to the side surface or its vicinity of the channel region 108i.

<Band structure>
Here, the band structure of the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110, the band structure of the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110, and the insulating film 104, Oxide semiconductor films 108_1, 108_
The band structure of No. 2 will be described with reference to FIGS. 9A to 9C. 9 (A) to 9 (C) are band structures in the channel region 108i.

9 (A) shows the insulating film 104, the oxide semiconductor film 108_1, 108_2, 108_3, and the like.
This is an example of a band structure in the film thickness direction of a laminated structure having an insulating film 110. In addition, FIG. 9 (
B) is an example of a band structure in the film thickness direction of a laminated structure having an insulating film 104, an oxide semiconductor film 108_2, 108_3, and an insulating film 110. Further, FIG. 9C shows the insulating film 104.
This is an example of a band structure in the film thickness direction of a laminated structure having oxide semiconductor films 108_1 and 108_2, and an insulating film 110. The band structure is an insulating film 104 for easy understanding.
, 108_1, 108_2, 108_3 of the oxide semiconductor film, and the energy level (Ec) at the lower end of the conduction band of the insulating film 110.

Further, FIG. 9A shows a metal oxide target in which silicon oxide films are used as the insulating films 104 and 110 and the atomic number ratio of the metal element is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. It is formed by using an oxide semiconductor film formed by using a metal oxide target having an atomic number ratio of a metal element of In: Ga: Zn = 4: 2: 4.1 as an oxide semiconductor film 108_2. An oxide semiconductor film is used, and an oxide semiconductor film formed by using a metal oxide target having an atomic number ratio of metal elements of In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_3 is used. It is a band diagram.

Further, in FIG. 9B, silicon oxide films are used as the insulating films 104 and 110, and the atomic number ratio of the metal element is set to In: Ga: Zn = 4: 2: 4.1 as the oxide semiconductor film 108_2. It is formed by using an oxide semiconductor film formed by using an object target, and by using a metal oxide target having an atomic number ratio of a metal element of In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_3. It is a band diagram of the structure which uses the oxide semiconductor film.

Further, FIG. 9C shows a metal oxide target in which silicon oxide films are used as the insulating films 104 and 110 and the atomic number ratio of the metal element is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. It is formed by using an oxide semiconductor film formed by using a metal oxide target having an atomic number ratio of a metal element of In: Ga: Zn = 4: 2: 4.1 as an oxide semiconductor film 108_2. It is a band diagram of the structure using the oxide semiconductor film formed by using the oxide semiconductor film.

As shown in FIG. 9A, in the oxide semiconductor films 108_1, 108_2, 108_3, the energy level at the lower end of the conduction band changes gently. Further, as shown in FIG. 9B, in the oxide semiconductor films 108_2 and 108_3, the energy level at the lower end of the conduction band changes gently. Further, as shown in FIG. 9C, the oxide semiconductor films 108_1 and 108_
At 2, the energy level at the lower end of the conduction band changes gently. In other words, it can also be said to be continuously changing or continuously joining. In order to have such a band structure, at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3, a trap center or a recombination center is formed. It is assumed that there are no impurities that form such defect levels.

In order to form a continuous bond on the oxide semiconductor films 108_1, 108_2, 108_3,
It is necessary to continuously stack the films without exposing them to the atmosphere by using a multi-chamber type film forming apparatus (sputtering apparatus) equipped with a load lock chamber.

With the configuration shown in FIGS. 9A to 9C, the oxide semiconductor film 108_2 becomes a well, and the channel region is formed in the oxide semiconductor film 108_2 in the transistor using the laminated structure. I understand.

By providing the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor film 1
The trap level that can be formed on 08_2 can be kept away from the oxide semiconductor film 108_2.

In addition, the trap level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 that functions as a channel region, and electrons are likely to accumulate in the trap level. .. The accumulation of electrons at the trap level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the trap level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2. By doing so, it becomes difficult for electrons to accumulate at the trap level, it is possible to increase the on-current of the transistor, and it is possible to increase the field effect mobility.

Further, in the oxide semiconductor films 108_1 and 108_3, the energy level at the lower end of the conduction band is closer to the vacuum level than in the oxide semiconductor film 108_2, and typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2 is closer. And the difference between the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, and 2 eV or less.
Or it is 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, or 0.
5 eV or more and 2 eV or less, or 1 eV or less.

With such a configuration, the oxide semiconductor film 108_2 becomes the main current path. That is, the oxide semiconductor film 108_2 has a function as a channel region, and the oxide semiconductor films 108_1 and 108_3 have a function as an oxide insulating film. Further, as the oxide semiconductor films 108_1 and 108_3, it is preferable to use an oxide semiconductor film composed of one or more of the metal elements constituting the oxide semiconductor film 108_2 on which the channel region is formed. With such a configuration, the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2,
Alternatively, interfacial scattering is unlikely to occur at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. Therefore, since the movement of the carrier is not hindered at the interface, the field effect mobility of the transistor is increased.

Further, in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as a part of the channel region, a material having a sufficiently low conductivity shall be used. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be called oxide insulating films because of their physical characteristics and / or functions. Alternatively, the oxide semiconductor films 108_1 and 108_3 have an electron affinity (difference between the vacuum level and the energy level at the lower end of the conduction band) smaller than that of the oxide semiconductor films 108_2.
It is assumed that a material having an energy level at the lower end of the conduction band having a difference (band offset) from the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2 is used. Further, in order to suppress the difference in the threshold voltage depending on the magnitude of the drain voltage, the oxide semiconductor film 108
A material in which the energy level at the lower end of the conduction band of _1 and 108_3 is closer to the vacuum level than 0.2 eV than the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2, preferably 0.5 eV.
It is preferable to apply a material close to the vacuum level.

Further, in the present embodiment, the oxide semiconductors 108_1 and 108_3 are formed by using a metal oxide target having an atomic number ratio of metal elements of In: Ga: Zn = 1: 3: 2. The configuration using a membrane has been exemplified, but the present invention is not limited to this. For example, as the oxide semiconductor films 108_1 and 108_1, In: Ga: Zn = 1: 1: 1 [atomic number ratio], In: Ga: Zn = 1: 1: 1.2 [atomic number ratio], In: Ga. : Zn = 1: 3: 4 [
Atomic number ratio], In: Ga: Zn = 1: 3: 6 [Atomic number ratio], In: Ga: Zn = 1: 4:
5 [atomic number ratio], In: Ga: Zn = 1: 5: 6 [atomic number ratio], or In: Ga: Zn
An oxide semiconductor film formed by using a metal oxide target having a = 1: 10: 1 [atomic number ratio] may be used. Alternatively, as the oxide semiconductor films 108_1 and 108_3, oxide semiconductor films formed by using a metal oxide target having an atomic number ratio of metal elements of Ga: Zn = 10: 1 may be used. In this case, an oxide semiconductor film formed by using a metal oxide target having an atomic number ratio of metal elements of In: Ga: Zn = 1: 1: 1 is used as the oxide semiconductor film 108_1, and the oxide semiconductor film 108_1 is used. , 108_3 and the atomic number ratio of the metal element is Ga: Z.
When the oxide semiconductor film formed by using the metal oxide target of n = 10: 1 is used, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_1,
It is preferable because the difference from the energy level at the lower end of the conduction band of 108_3 can be 0.6 eV or more.

The oxide semiconductor films 108_1 and 108_1 are used as In: Ga: Zn = 1: 1: 1.
When using a metal oxide target of [atomic number ratio], oxide semiconductor films 108_1, 108
_3 may be In: Ga: Zn = 1: β1 (0 <β1 ≦ 2): β2 (0 <β2 ≦ 2). Further, as the oxide semiconductor films 108_1 and 108_1, In: Ga: Zn = 1.
When using a metal oxide target with a ratio of 3: 4 [atomic number ratio], the oxide semiconductor film 108_1
, 108_3 are In: Ga: Zn = 1: β3 (1 ≦ β3 ≦ 5): β4 (2 ≦ β4 ≦ 6).
May be. Further, as the oxide semiconductor films 108_1 and 108_3, In: Ga:
When using a metal oxide target with Zn = 1: 3: 6 [atomic number ratio], the oxide semiconductor film 1
08_1 and 108_3 are In: Ga: Zn = 1: β5 (1 ≦ β5 ≦ 5): β6 (4 ≦ β).
6 ≦ 8) may occur.

<Method of manufacturing semiconductor devices>
Next, an example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 10 to 13. 10 to 13 are cross-sectional views in the channel length (L) direction and the channel width (W) direction for explaining the method for manufacturing the transistor 150 and the capacitive element 160.

First, the gate electrode 106 is formed on the substrate 102. Next, the insulating film 104 is formed on the substrate 102 and the gate electrode 106, and the oxide semiconductor film is formed on the insulating film 104. Then, the oxide semiconductor film is processed into an island shape to form the oxide semiconductor film 107 (see FIG. 10A).

In this embodiment, a sputtering method is used as the gate electrode 106, and the thickness is 50 nm.
A laminated film of the tantalum nitride film of No. 1 and a copper film having a thickness of 100 nm is formed. The gate electrode 1
As a method for processing the conductive film to be 06, either one or both of the wet etching method and the dry etching method may be used. Here, the copper film is etched by a wet etching method, and then the tantalum nitride film is etched by a dry etching method to process a conductive film to form a gate electrode 106.

The insulating film 104 includes a sputtering method, a CVD method, a vapor deposition method, and pulsed laser deposition (
It can be formed by appropriately using a PLD) method, a printing method, a coating method, or the like. In the present embodiment, a plasma CVD apparatus is used as the insulating film 104 to form a silicon nitride film having a thickness of 400 nm and a silicon oxide film having a thickness of 50 nm.

Further, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. Insulating film 10
Examples of oxygen added to 4 include oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecule ions and the like. Further, as the addition method, there are an ion doping method, an ion implantation method, a plasma treatment method and the like. Further, after forming a film that suppresses the desorption of oxygen on the insulating film, oxygen may be added to the insulating film 104 via the film.

As the above-mentioned film that suppresses the desorption of oxygen, a conductive film or a semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten is used. Can be formed.

Further, when oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with microwaves to generate high-density oxygen plasma.

Examples of the oxide semiconductor film 107 include a sputtering method, a coating method, a pulse laser vapor deposition method, and the like.
It can be formed by a laser ablation method, a thermal CVD method, or the like. The oxide semiconductor film 107 can be processed by forming a mask on the oxide semiconductor film by a lithography process and then etching a part of the oxide semiconductor film using the mask. Further, the oxide semiconductor film 107 in which the elements are separated may be directly formed by using a printing method.

When the oxide semiconductor film is formed by the sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be appropriately used as the power supply device for generating plasma. Further, as the sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), oxygen, a mixed gas of rare gas and oxygen is appropriately used. In the case of a mixed gas of rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

When forming an oxide semiconductor film, for example, when a sputtering method is used, the substrate temperature is set to 150 ° C. or higher and 750 ° C. or lower, or 150 ° C. or higher and 450 ° C. or lower, or 200 ° C. or higher and 350 ° C. or lower. It is preferable to form a film because the crystallinity can be enhanced.

In this embodiment, a sputtering device is used as the oxide semiconductor film 107, and an In—Ga—Zn metal oxide (In: Ga: Zn) is used as the sputtering target.
= 4: 2: 4.1 [atomic number ratio]) to form an oxide semiconductor film having a film thickness of 35 nm.

Further, after forming the oxide semiconductor film 107, heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film 107. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, or 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

The heat treatment can be carried out in a rare gas such as helium, neon, argon, xenon, krypton, or an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. It is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water or the like. The processing time may be 3 minutes or more and 24 hours or less.

For the heat treatment, an electric furnace, an RTA device, or the like can be used. By using the RTA device, the heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

By forming a film while heating the oxide semiconductor film, or by performing heat treatment after forming the oxide semiconductor film, the hydrogen concentration obtained by SIMS in the oxide semiconductor film is 5 × 10.
¹⁹ atoms / cm ³ or less, or 1 x 10 ¹⁹ atoms / cm ³ or less, 5 x 10 ^1
8 atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 1
It can be 0 ¹⁷ atoms / cm ³ or less, or 1 × 10 ¹⁶ atoms / cm ³ or less.

Next, the insulating film 110_0 is formed on the insulating film 104 and the oxide semiconductor film 107 (FIG. 1).
See 0 (B)).

As the insulating film 110_0, a silicon oxide film or a silicon nitride nitride film can be formed by using a plasma chemical vapor deposition apparatus (PECVD apparatus, or simply referred to as a plasma CVD apparatus). In this case, it is preferable to use a sedimentary gas containing silicon and an oxidizing gas as the raw material gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide and the like.

Further, as the insulating film 110_0, the oxidizing gas with respect to the sedimentary gas is made larger than 20 times and 1
A silicon oxide film with a small amount of defects can be formed by using a PECVD apparatus having a pressure of less than 00 times, or 40 times or more and 80 times or less, and a pressure in the processing chamber of less than 100 Pa or 50 Pa or less.

Further, as the insulating film 110_0, the substrate placed in the vacuum-exhausted processing chamber of the PECVD apparatus is held at 280 ° C. or higher and 400 ° C. or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the treatment chamber at 20 Pa or higher and 250 Pa or higher. Hereinafter, it is more preferably 100 Pa or more and 250 Pa or less, and the insulating film 110_
As 0, a dense silicon oxide film or silicon nitride film can be formed.

Further, the insulating film 110_0 may be formed by using a plasma CVD method using microwaves. Microwave refers to the frequency range of 300 MHz to 300 GHz. Microwaves
The electron temperature is low and the electron energy is low. Further, in the supplied electric power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and it is possible to excite a high-density plasma (high-density plasma). .. Therefore, it is possible to form the insulating film 110_0 with less plasma damage to the film-deposited surface and deposits and less defects.

Further, the insulating film 110_0 can be formed by using a CVD method using an organic silane gas. As the organic silane gas, ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ )
), Tetramethylsilane (TMS: Chemical formula Si (CH ₃ ) ₄ ), Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMDS), Triethoxysilane (SiH (OC)). ₂ H ₅ ) ₃ ),
Silicon-containing compounds such as trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) can be used. By using the CVD method using an organic silane gas, an insulating film 110_0 having a high covering property can be formed.

In the present embodiment, a PECVD apparatus is used as the insulating film 110_0 to form a silicon oxide film having a thickness of 100 nm.

Next, after forming a mask by lithography at a desired position on the insulating film 110_0,
By etching a part of the insulating film 110_0 and the insulating film 104, the gate electrode 106
(See FIG. 10 (C)) to form an opening 143 that reaches.

As a method for forming the opening 143, either one or both of the wet etching method and the dry etching method may be used. In the present embodiment, the dry etching method is used to form the opening 143.

Next, the oxide semiconductor film 111_0 is formed on the insulating film 110_0 so as to cover the opening 143. When the oxide semiconductor film 111_0 is formed, the insulating film 1 is formed from the oxide semiconductor film 111_0.
Oxygen is added to 10_0 (see FIG. 10 (D)).

In FIG. 10D, the oxygen added to the insulating film 110_0 is schematically represented by an arrow.

As a method for forming the oxide semiconductor film 111_0, it is preferable to use a sputtering method and to form the oxide semiconductor film 111_0 in an atmosphere containing oxygen gas at the time of formation. By forming the oxide semiconductor film 111_0 in an atmosphere containing oxygen gas at the time of formation, oxygen can be suitably added to the insulating film 110_0. The method for forming the oxide semiconductor film 111_0 is not limited to the sputtering method, and other methods, for example, the ALD method may be used.

In the present embodiment, the oxide semiconductor film 111_0 is an IGZO film (In: Ga: Zn = 4) which is an In—Ga—Zn oxide having a film thickness of 50 nm by using a sputtering method.
: 2: 4.1 (atomic number ratio) is formed. Further, oxygen addition treatment may be performed in the insulating film 110_0 before the formation of the oxide semiconductor film 111_0 or after the formation of the oxide semiconductor film 111_0. The method of the oxygen addition treatment may be the same as the oxygen addition that can be performed after the formation of the insulating film 104.

Next, the mask 1 is placed at a desired position on the oxide semiconductor film 111_0 by a lithography process.
40 is formed (see FIG. 11 (A)).

Next, etching is performed from the mask 140, and the conductive film 112_0 and the insulating film 110_0 are performed.
And process. After that, by removing the mask 140, the island-shaped oxide semiconductor film 111
And the island-shaped insulating film 110 (see FIG. 11B).

In the present embodiment, the conductive film 112_0 and the insulating film 110_0 are processed.
This is done using the dry etching method.

When processing the oxide semiconductor film 111_0 and the insulating film 110, the oxide semiconductor film 1
The film thickness of the oxide semiconductor film 107 in the region where 11 is not superimposed may be reduced. Alternatively, when the oxide semiconductor film 111_0 and the insulating film 110 are processed, the thickness of the insulating film 104 in the region where the oxide semiconductor film 107 does not overlap may be reduced. In addition, the oxide semiconductor film 111_
During the processing of 0 and the insulating film 110_0, an etchant or etching gas (eg, for example)
Chlorine, etc.) is added to the oxide semiconductor film 107, or the oxide semiconductor film 111_0
, Or the constituent elements of the insulating film 110_0 may be added to the oxide semiconductor film 107.

Next, the insulating film 1 is placed on the insulating film 104, the oxide semiconductor film 107, and the oxide semiconductor film 111.
16 is formed. By forming the insulating film 116, the oxide semiconductor film 107 in contact with the insulating film 116 becomes a source region 108s and a drain region 108d. In addition, the insulating film 1
The oxide semiconductor film 107 in contact with 10 becomes a channel region 108i. As a result, the first oxide semiconductor film 108 having the channel region 108i, the source region 108s, and the drain region 108d is formed. Further, by forming the insulating film 116, the oxide semiconductor film 111 in contact with the insulating film becomes the second oxide semiconductor films 111a and 111b (see FIG. 11C).

In FIG. 11C, the film and the region whose resistance is reduced by the formation of the insulating film 116 are shown with different hatching than before the resistance reduction.

The insulating film 116 can be formed by selecting the material described above. In the present embodiment, a PECVD apparatus is used as the insulating film 116 to form a silicon nitride film having a thickness of 100 nm.

By using the silicon nitride film as the insulating film 116, nitrogen or hydrogen in the silicon nitride film can be supplied to the source region 108s and the drain region 108d in contact with the insulating film 116.

Further, before forming the insulating film 116, an impurity element is added to the oxide semiconductor film 107 and / or the oxide semiconductor film 111, or after the insulating film 116 is formed, the insulating film 116 is formed.
An impurity element may be added to the oxide semiconductor film 107 and / or the oxide semiconductor film 111 via the above.

Examples of the treatment for adding the impurity element include an ion doping method, an ion implantation method, and a plasma treatment method. In the case of the plasma treatment method, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. As the device for generating the plasma, a dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, or the like can be used.

As raw material gases for impurity elements, B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , Al.
One or more of H ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, H ₂ and noble gases can be used. Alternatively, B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , Al H diluted with a noble gas.
One or more of ₃ , AlCl ₃ , F ₂ , HF, and H ₂ can be used. Typical examples of rare gas elements include helium, neon, argon, krypton, xenon and the like.

Alternatively, after adding the noble gas, B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , Al H ₃ ,
One or more of AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ are oxide semiconductor film 1
It may be added to 07. Or B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ ,
After adding one or more of AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ , a rare gas may be added to the oxide semiconductor film 107.

Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 12A).

The insulating film 118 can be formed by selecting the material described above. In the present embodiment, a PECVD apparatus is used as the insulating film 118 to form a silicon oxide film having a thickness of 300 nm.

Next, a mask is formed at a desired position of the insulating film 118 by lithography, and then the insulating film 118 and a part of the insulating film 116 are etched to form an opening 141a reaching the source region 108s and a drain region 108d. An opening 141b to reach and an opening 142 to reach the second oxide semiconductor film 111b are formed (see FIG. 12B).

As a method for etching the insulating film 118 and the insulating film 116, either one or both of the wet etching method and the dry etching method may be used. In the present embodiment, the insulating film 118 and the insulating film 116 are processed by using a dry etching method.

Next, a conductive film is formed on the source region 108s, the drain region 108d, the second oxide semiconductor film 111b, and the insulating film 118 so as to cover the openings 141a, 141b, 142, and the conductive film is desired. By processing into a shape, the conductive films 120a and 120b are formed. At this point, the transistor 150 is formed (see FIG. 12C).

The conductive films 120a and 120b can be formed by selecting the materials described above. In the present embodiment, a sputtering device is used as the conductive films 120a and 120b.
A laminated film of a tungsten film having a thickness of 50 nm and a copper film having a thickness of 400 nm is formed.

As a method for processing the conductive film to be the conductive film 120a and 120b, either one or both of the wet etching method and the dry etching method may be used. In the present embodiment, the copper film is etched by the wet etching method, and then the tungsten film is etched by the dry etching method to process the conductive film to form the conductive films 120a and 120b.

Next, the insulating film 122 is formed on the conductive films 120a and 120b and the insulating film 118 (
See FIG. 13 (A)).

The insulating film 122 can be formed by selecting the material described above. In the present embodiment, a plasma CVD apparatus is used as the insulating film 122 to form a silicon nitride film having a thickness of 100 nm.

Next, a conductive film is formed on the insulating film 122, and the conductive film is processed into a desired shape.
Form the conductive film 123. At this point, the capacitive element 160 is formed (FIG. 13B).
reference). When the resistance value of the conductive film 123 is higher than the desired value, a conductive film serving as an auxiliary electrode may be formed on the conductive film 123.

The conductive film 123 can be formed by selecting the material described above. In the present embodiment, a sputtering device is used as the conductive film 123 to form an indium tin oxide having a thickness of 100 nm.

By the above steps, the semiconductor device 100 (transistor 150 and capacitive element 160) shown in FIG. 1 can be manufactured.

As the film (insulating film, metal oxide film, oxide semiconductor film, conductive film, etc.) constituting the transistor 150, in addition to the above-mentioned forming method, a sputtering method, a chemical vapor deposition (CVD) method, etc.
It can be formed by using a vacuum deposition method, a pulsed laser deposition (PLD) method, or an ALD method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may also be used.
Examples of thermal CVD methods include organometallic chemical vapor deposition (MOCVD) methods.

In the thermal CVD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, and the raw material gas and the oxidizing agent are sent into the chamber at the same time, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate to form a film. As described above, since the thermal CVD method is a film forming method that does not generate plasma, it has an advantage that defects are not generated due to plasma damage.

A thermal CVD method such as the MOCVD method can form a film such as the conductive film, an insulating film, an oxide semiconductor film, or a metal oxide film described above, and for example, an In—Ga—Zn—O film is formed. In some cases, trimethylindium (In (CH ₃ ) ₃ ), trimethylgallium (Ga (CH ₃ ))
) ₃ ), and dimethylzinc is used (Zn (CH ₃ ) ₂ ). Not limited to these combinations, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn (C ₂ H ₅ ) ₂ ) can be used instead of dimethylzinc. You can also do it.

When a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH, Hf [N (CH ₃ ) ₂ ] 4] ₄ ) And hafnium amide such as tetrakis (ethylmethylamide) hafnium) and ozone (ozone) as an oxidizing agent.
Two types of gas of O ₃ ) are used.

When an aluminum oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al (CH ₃ ) 3) ₃
), Etc.) are vaporized, and two types of gas, _H2O , are used as the oxidizing agent. Other materials include tris (dimethylamide) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptane dinate) and the like.

When a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the surface to be deposited, and radicals of an oxidizing gas ( _O2 , dinitrogen monoxide) are supplied and adsorbed. React with things.

When a tungsten film is formed by a film forming apparatus using ALD, WF ₆ gas and B ₂ H ₆ gas are sequentially introduced to form an initial tungsten film, and then WF ₆ gas and H are formed.
Tungsten film is formed using ₂ gases. In addition, SiH ₄ gas may be used instead of B ₂ H ₆ gas.

Further, an oxide semiconductor film, for example, In-Ga-Zn-O, is used by a film forming apparatus using ALD.
When forming a film, an In—O layer is formed by using In (CH ₃ ) ₃ gas and O ₃ gas.
After that, a GaO layer is formed by using Ga (CH ₃ ) ₃ gas and O ₃ gas, and then Zn.
(CH ₃ ) A ZnO layer is formed by using ₂ gas and O ₃ gas. The order of these layers is not limited to this example. Further, using these gases, an In—Ga—O layer or an In—Zn—O layer,
A mixed compound layer such as a Ga—Zn—O layer may be formed. The H ₂ O gas obtained by bubbling water with an inert gas such as Ar may be used instead of the O ₃ gas, but it is preferable to use the O ₃ gas containing no H.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 2)
In this embodiment, an example of an oxide semiconductor applicable to a transistor and a capacitive element of the semiconductor device of one aspect of the present invention will be described.

Hereinafter, the structure of the oxide semiconductor will be described.

As used herein, the term "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less.
Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Also, "almost vertical" means
A state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. As a non-single crystal oxide semiconductor, CAAC-OS (c-axis-aligned)
crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor)
octa), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l)
ike oxide semiconductor) and amorphous oxide semiconductors.

From another viewpoint, the oxide semiconductor is divided into an amorphous oxide semiconductor and other crystalline oxide semiconductors. As crystalline oxide semiconductors, single crystal oxide semiconductors, CAAC-
There are OS, polycrystalline oxide semiconductor, nc-OS and the like.

Amorphous structures are generally isotropic and have no anisotropic structure, the arrangement of atoms is not fixed in a metastable state, the bond angle is flexible, and short-range order is present but long-range order is present. It is said that it does not have.

That is, a stable oxide semiconductor is completely amorphous.
) It cannot be called an oxide semiconductor. Further, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-li
ke OS is an unstable structure that is not isotropic but has voids (also referred to as voids).
In terms of instability, the a-like OS is physically close to an amorphous oxide semiconductor.

<CAAC-OS>
First, CAAC-OS will be described.

CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis oriented crystal portions (also referred to as pellets).

A case where CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when structural analysis by the out-of-plane method is performed on CAAC-OS having crystals of InGaZnO ₄ classified in the space group R-3m, the diffraction angle (2θ) is as shown in FIG. 14 (A). A peak appears near 31 °. Since this peak is attributed to the (009) plane of the crystal of InGaZnO ₄ , in CAAC-OS, the crystal has c-axis orientation and the c-axis forms the CAAC-OS film (formed). It can be confirmed that the surface is oriented substantially perpendicular to the surface) or the upper surface. 2θ is 31 °
In addition to the peaks in the vicinity, peaks may appear in the vicinity of 2θ of 36 °. The peak in which 2θ is in the vicinity of 36 ° is due to the crystal structure classified into the space group Fd-3m. Therefore, CAAC
-OS preferably does not show the peak.

On the other hand, in-pla in which X-rays are incident on CAAC-OS from a direction parallel to the surface to be formed.
When the structural analysis by the ne method is performed, a peak appears in the vicinity of 2θ at 56 °. This peak is I
It is attributed to the (110) plane of the crystal of nGaZnO ₄ . Then, even if 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), it is clear as shown in FIG. 14 (B). No peak appears. On the other hand, single crystal InGaZ
When 2θ is fixed in the vicinity of 56 ° and φ-scanned with respect to _no4 , six peaks attributed to the crystal plane equivalent to the (110) plane are observed as shown in FIG. 14 (C). Therefore, X
From the structural analysis using RD, it can be confirmed that the orientation of the a-axis and the b-axis of CAAC-OS is irregular.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, InGaZ
When an electron beam having a probe diameter of 300 nm is incident on CAAC-OS having a crystal of _no4 in parallel with the surface to be formed of CAAC-OS, a diffraction pattern (selected area electron diffraction) as shown in FIG. 14 (D) is applied. Also called a pattern.) May appear. In this diffraction pattern, In
A spot due to the (009) plane of the crystal of GaZnO ₄ is included. Therefore, it can be seen from the electron diffraction that the pellets contained in CAAC-OS have c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. On the other hand, the diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface is shown in FIG. 14 (E).
Shown in. From FIG. 14 (E), a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation even by electron diffraction using an electron beam having a probe diameter of 300 nm. It is considered that the first ring in FIG. 14 (E) is caused by the (010) plane and the (100) plane of the crystal of InGaZnO ₄ . Further, it is considered that the second ring in FIG. 14 (E) is caused by the (110) plane or the like.

In addition, a transmission electron microscope (TEM: Transmission Electron Mi)
By observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image of CAAC-OS and a diffraction pattern by crosscopy), a plurality of pellets can be confirmed. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, the grain boundary (also referred to as grain boundary) may not be clearly confirmed. Therefore, CAAC
-It can be said that the OS is unlikely to cause a decrease in electron mobility due to grain boundaries.

FIG. 15A shows a high resolution T of the cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface.
The EM image is shown. For observation of high-resolution TEM images, spherical aberration correction (Spherical Ab)
The erration (ector) function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image is
For example, it can be observed with an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 15 (A), pellets, which are regions where metal atoms are arranged in layers, can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellets can also be referred to as nanocrystals (nc: nanocrystals). In addition, CAAC-OS can be used as CANC (C-Axis Aligned nan).
It can also be called an oxide semiconductor having ocrystals). The pellet is CAAC
-The film of OS reflects the unevenness of the surface to be formed or the upper surface, and is parallel to the surface to be formed or the upper surface of CAAC-OS.

Further, in FIGS. 15 (B) and 15 (C), CAAC observed from a direction substantially perpendicular to the sample surface.
-A Cs-corrected high-resolution TEM image of the plane of the OS is shown. 15 (D) and 15 (E) are shown in FIGS. 15 (D) and 15 (E).
15 (B) and 15 (C) are image-processed images, respectively. The method of image processing will be described below. First, FIG. 15 (B) is obtained by performing a fast Fourier transform (FFT: Fast).
An FFT image is acquired by performing a Fourier Transform) process. Next, in the acquired FFT image, mask processing is performed to leave a range between 2.8 nm ^-1 and 5.0 nm ^-1 with respect to the origin. Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT:).
An image processed image is acquired by performing an Inverse Fast Fourier Transform) process. The image thus obtained is called an FFT filtering image. The FFT filtering image is an image obtained by extracting a periodic component from a Cs-corrected high-resolution TEM image, and shows a grid array.

In FIG. 15 (D), the disordered portion of the lattice arrangement is shown by a broken line. The area surrounded by the broken line is
It is one pellet. The part indicated by the broken line is the connecting portion between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. The shape of the pellet is not limited to the regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 15 (E), a dotted line indicates a portion where the orientation of the grid arrangement changes between a region where the grid arrangement is aligned and another region where the grid arrangement is aligned, and the change in the orientation of the grid arrangement is shown. It is shown by a broken line. A clear grain boundary cannot be confirmed even in the vicinity of the dotted line. Distorted hexagons, pentagons and / and heptagons can be formed by connecting the surrounding grid points around the grid points near the dotted line. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because CAAC-OS has a non-dense atomic arrangement in the ab plane direction.
It is considered that the strain can be tolerated by changing the bond distance between atoms due to the substitution of the metal element.

As shown above, CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, CA
AC-OS, CAA crystal (c-axis-aligned a-b-pl)
It can also be referred to as an ane-anchored crystal).

CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of oxide semiconductors may be reduced due to the inclusion of impurities or the formation of defects, CAAC-OS has impurities and defects (
It can be said that it is an oxide semiconductor with few oxygen deficiencies.

Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon, which has a stronger bond with oxygen than a metal element constituting an oxide semiconductor, deprives the oxide semiconductor of oxygen, disturbs the atomic arrangement of the oxide semiconductor, and lowers the crystallinity. It becomes a factor. Further, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.

When an oxide semiconductor has impurities or defects, its characteristics may fluctuate due to light, heat, or the like. For example, impurities contained in an oxide semiconductor may be a carrier trap or a carrier generation source. For example, oxygen deficiency in an oxide semiconductor may become a carrier trap or a carrier generation source by capturing hydrogen.

CAAC-OS, which has few impurities and oxygen deficiency, is an oxide semiconductor having a low carrier density. Specifically, it is less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ pieces / cm ³ , and more preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × ^10-9 pieces / cm. It can be an oxide semiconductor having a carrier density of ³ or more. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

<Nc-OS>
Next, the nc-OS will be described.

The case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on nc-OS by the out-of-plane method, a peak indicating orientation does not appear. That is, the crystals of nc-OS have no orientation.

Further, for example, nc-OS having a crystal of InGaZnO ₄ is sliced and the thickness is 34 nm.
When an electron beam having a probe diameter of 50 nm is incident on the region of FIG. 16 in parallel with the surface to be formed, FIG.
A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) is observed. Further, FIG. 16B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 16B, a plurality of spots are observed in the ring-shaped region. Therefore, the order of the nc-OS is not confirmed by incident an electron beam having a probe diameter of 50 nm, but the order is confirmed by incident an electron beam having a probe diameter of 1 nm.

Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm,
As shown in FIG. 16C, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape may be observed. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in the range of the thickness of less than 10 nm. Since the crystals are oriented in various directions, there are some regions where regular electron diffraction patterns are not observed.

FIG. 16D shows a Cs-corrected high-resolution TEM image of the cross section of the nc-OS observed from a direction substantially parallel to the surface to be formed. The nc-OS has a region in which a crystal portion can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal portion contained in nc-OS has a size of 1 nm or more and 10 nm or less, and in particular, it often has a size of 1 nm or more and 3 nm or less. The size of the crystal part is 1.
Oxide semiconductors larger than 0 nm and 100 nm or less are fine crystal oxide semiconductors (fine).
It may be called a crystalline oxide semiconductor). In the nc-OS, for example, the crystal grain boundaries may not be clearly confirmed in a high-resolution TEM image. It should be noted that the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystal portion of nc-OS may be referred to as a pellet.

As described above, the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

Since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS is used.
It can also be referred to as an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide semiconductor having NANC (Non-Aligned nanocrystals).

The nc-OS is an oxide semiconductor having higher regularity than the amorphous oxide semiconductor. for that reason,
The defect level density of nc-OS is lower than that of a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in crystal orientation between different pellets. Therefore, the defect level density of nc-OS is higher than that of CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

FIG. 17 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 17A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 17 (B
) Is a high-resolution cross-sectional TEM image of a-like OS after electron (e- ⁾ irradiation of 4.3 × 10 ⁸ e ⁻ / nm ² . From FIGS. 17 (A) and 17 (B), a-like OS
It can be seen that a striped bright region extending in the vertical direction is observed from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is presumed to be a void or a low density region.

Due to the presence of voids, the a-like OS has an unstable structure. In the following, a-like
To show that the OS has an unstable structure as compared with CAAC-OS and nc-OS, the structural change due to electron irradiation is shown.

Prepare a-like OS, nc-OS and CAAC-OS as samples. Both samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. Due to the high resolution cross-sectional TEM image, each sample has a crystal part.

The unit cell of the crystal of InGaZnO ₄ has three In—O layers, and Ga—Zn—
It is known that a total of 9 layers having 6 layers of O have a structure in which layers are stacked in the c-axis direction. The spacing between these adjacent layers is about the same as the grid plane spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, in the following, InGaZn is defined as a portion where the interval between the plaids is 0.28 nm or more and 0.30 nm or less.
It was regarded as the crystal part of _O4 . The plaids correspond to the ab planes of the InGaZnO ₄ crystal.

FIG. 18 is an example of investigating the average size of the crystal portions (22 to 30 locations) of each sample. The length of the above-mentioned plaid is defined as the size of the crystal portion. From FIG. 18, a-like
It can be seen that in the OS, the crystal portion becomes larger according to the cumulative irradiation amount of electrons related to the acquisition of the TEM image. From FIG. 18, the crystal part (also referred to as the initial nucleus), which had a size of about 1.2 nm at the initial stage of observation by TEM, has a cumulative irradiation amount of electrons (e ⁻ ) of 4.2 × ¹⁰⁸ e ⁻ .
It can be seen that at / ^nm2 , it grows to a size of about 1.9 nm. On the other hand, nc
-OS and CAAC-OS have a cumulative electron irradiation amount of 4.2 x ¹⁰⁸ from the start of electron irradiation.
It can be seen that there is no change in the size of the crystal part in the range of e ⁻ / nm ² . From FIG. 18, the size of the crystal part of nc-OS and CAAC-OS is determined regardless of the cumulative irradiation amount of electrons.
It can be seen that they are about 1.3 nm and about 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × ¹⁰⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

As described above, in the a-like OS, growth of the crystal portion may be observed by electron irradiation. On the other hand, in nc-OS and CAAC-OS, almost no growth of the crystal portion due to electron irradiation is observed. That is, the a-like OS is compared with the nc-OS and the CAAC-OS.
It turns out that the structure is unstable.

Further, since it has a void, the a-like OS has a structure having a lower density than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. Also, the density of nc-OS and CAAC
-The density of OS is 92.3% or more and less than 100% of the density of a single crystal having the same composition. Oxide semiconductors having a density of less than 78% of a single crystal are difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of the single crystal InGaZnO ₄ having a rhombohedral crystal structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ³ . .. Further, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio],
The density of nc-OS and the density of CAAC-OS are 5.9 g / cm ³ or more and 6.3 g / cm ³
Is less than.

When a single crystal having the same composition does not exist, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition is relative to the ratio of combining single crystals having different compositions.
It may be estimated using a weighted average. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures, and each has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, a-like OS, nc-OS, or the like.
A laminated film having two or more of CAAC-OS may be used.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 3)
In the present embodiment, the display device 80, which is one aspect of the present invention, will be described with reference to FIGS. 19 to 31.

In the display device 80 shown in FIG. 19A, the pixel unit 71, the scanning line driving circuit 74, and the signal line driving circuit 76 are arranged in parallel or substantially parallel to each other, and the potential is increased by the scanning line driving circuit 74. It has m scanning lines 77 to which the is controlled, and n signal lines 79 each of which is arranged in parallel or substantially parallel and whose potential is controlled by the signal line driving circuit 76. Further, the pixel portion 7
1 has a plurality of pixels 70 arranged in a matrix. Further, along the signal line 79, each has a common line 75 arranged in parallel or substantially parallel to each other. Further, the scanning line drive circuit 74 and the signal line drive circuit 76 may be collectively referred to as a drive circuit unit.

Each scanning line 77 is electrically connected to n pixels 70 arranged in any of the pixels 70 arranged in m rows and n columns in the pixel unit 71. Further, each signal line 79 is electrically connected to m pixels 70 arranged in any of the pixels 70 arranged in m rows and n columns. Both m and n are integers of 1 or more. Further, each common line 75 is m.
Of the pixels 70 arranged in the row n columns, the pixels 70 are electrically connected to the m pixels 70 arranged in any row.

FIG. 19B shows an example of a circuit configuration that can be used for the pixel 70 of the display device 80 shown in FIG. 19A.

The pixel 70 shown in FIG. 19B includes a liquid crystal element 51, a transistor 52, and a capacitive element 55.
And have.

One of the pair of electrodes of the liquid crystal element 51 is connected to the transistor 52, and the potential is the pixel 70.
It is set appropriately according to the specifications of. The other of the pair of electrodes of the liquid crystal element 51 is connected to the common wire 75, and a common potential (common potential) is given as the potential. The liquid crystal contained in the liquid crystal element 51 is
The orientation state is controlled by the data written in the transistor 52.

The liquid crystal element 51 is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). As the liquid crystal used for the liquid crystal element 51, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like depending on the conditions.

Further, when the transverse electric field method is adopted, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent may be used.
It has a short response speed and is optically isotropic. Further, the liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent does not require an orientation treatment and has a small viewing angle dependence. In addition, since it is not necessary to provide an alignment film, the rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. ..

As a driving method of the display device 80 having the liquid crystal element 51, TN (Twisted Ne) is used.
matic) mode, IPS (In-Plane-Switching) mode, FFS
(Fringe Field Switching) mode, ASM (Axially)
Symmetrically aligned Micro-cell mode, OCB (Opt)
ical Compensated Birefringence mode, FLC (F)
errolectric Liquid Crystal) mode, AFLC (Ant)
The iFerolectric Liquid Crystal) mode and the like can be used.

Further, the display device 80 is a normally black type liquid crystal display device, for example, vertical orientation (VA).
It may be a transmissive liquid crystal display device that employs a mode. The vertical orientation mode is MVA.
(Multi-Domain Vertical Element) mode, PVA
(Patterned Vertical Alignment) mode, ASV mode and the like can be used.

In this embodiment, mainly the lateral electric field method, typically the FFS mode, and the DPS described later will be described.
The mode will be described.

In the configuration of the pixel 70 shown in FIG. 19B, one of the source electrode and the drain electrode of the transistor 52 is electrically connected to the signal line 79, and the other is electrically connected to one of the pair of electrodes of the liquid crystal element 51. Be connected. Further, the first gate electrode of the transistor 52 is a scanning line 77.
Is electrically connected to. The transistor 52 has a function of controlling the writing of data of the data signal. Further, the transistor 52 has a second gate electrode electrically connected to the first gate electrode. That is, in the transistor 52, the first gate electrode and the second gate electrode
The gate electrodes of are at the same potential. The first gate electrode and the second gate electrode may operate independently and can be given different potentials. For example, the second gate electrode may be electrically connected to the wiring 78 having a function of giving a potential different from that of the scanning line 77 (.
See FIG. 19 (C). Further, the transistor 52 may be configured not to have a first gate electrode or a second gate electrode.

In the configuration of the pixel 70 shown in FIG. 19B, one of the pair of electrodes of the capacitive element 55 is connected to the other of the source electrode and the drain electrode of the transistor 52. The other of the pair of electrodes of the capacitive element 55 is electrically connected to the common wire 75. The potential value of the common line 75 is appropriately set according to the specifications of the pixel 70. The capacitance element 55 has a function as a holding capacitance for holding the written data. In the display device 80 driven by the FFS mode, one of the pair of electrodes of the capacitive element 55 is a part or all of one of the pair of electrodes of the liquid crystal element 51, and the other of the pair of electrodes of the capacitive element 55. Is a part or all of the other of the pair of electrodes of the liquid crystal element 51.

<Configuration example of element substrate>
Next, a specific configuration of the element substrate included in the display device 80 will be described. First, FF
FIG. 20 shows a top view of a plurality of pixels 70a, 70b, 70c included in the display device 80 driven by the S mode.

In FIG. 20, the conductive film 13 that functions as a scanning line is provided so as to extend in a direction substantially orthogonal to the signal line (left-right direction in the figure). The conductive film 21a that functions as a signal line is provided so as to extend in a direction substantially orthogonal to the scanning line (vertical direction in the figure). The conductive film 13 (scanning line 77 in FIG. 19A) that functions as a scanning line is electrically connected to the scanning line driving circuit 74, and the conductive film 21a that functions as a signal line (FIG. 19A). ) Signal line 79)
Is electrically connected to the signal line drive circuit 76 (see FIG. 19A).

The transistor 52 is provided in the vicinity of the intersection of the scanning line and the signal line. The transistor 52 is a conductive film 13 that functions as a first gate electrode, a first gate insulating film (not shown in FIG. 20), and a first oxide semiconductor film 18 formed on the first gate insulating film. , The conductive films 21a and 21b that function as either one or the other of the source electrode and the drain electrode, respectively.
, A second gate insulating film formed on the channel region 18i, and a second oxide semiconductor film 19a formed on the second gate insulating film and functioning as a second gate electrode. The first oxide semiconductor film 18 has a channel region 18i that overlaps with the second oxide semiconductor film 19a, a first source / drain region 18_1 that is in contact with the conductive film 21a, and a conductive film 2.
It has a second source / drain region 18_2, which is in contact with 1b. Further, the second oxide semiconductor film 19a is electrically connected to the conductive film 13 via the openings provided in the first gate insulating film and the second gate insulating film.

The conductive film 13 also functions as a scanning line, and the region superimposing on the first oxide semiconductor film 18 functions as a first gate electrode of the transistor 52. The conductive film 21a also functions as a signal line, and the region superimposing on the first source / drain region 18_1 functions as a source electrode or a drain electrode of the transistor 52. Further, in FIG. 20, the end portion of the conductive film 13 is located outside the end portion of the channel region 18i in the upper surface shape. Therefore, the conductive film 13 functions as a light-shielding film that blocks light from a light source such as a backlight. As a result, the channel region 18i included in the transistor is not irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed.

Further, the conductive film 21b is electrically connected to the second oxide semiconductor film 19b having the function of a pixel electrode. Further, an insulating film (not shown in FIG. 20) is provided on the second oxide semiconductor film 19b, and the conductive film 29 is provided on the insulating film.

The conductive film 29 has a striped region extending in a direction intersecting the signal line. Further, the striped region is connected to a region extending in a direction parallel to or substantially parallel to the signal line. Therefore, in the plurality of pixels of the display device 80, the conductive film 29 having the striped regions has the same potential in each region.

The capacitive element 55 is formed in a region where the second oxide semiconductor film 19b and the conductive film 29 are superimposed. The second oxide semiconductor film 19b and the conductive film 29 have translucency. That is, the capacitive element 55 has translucency.

Since the capacitive element 55 has translucency, the capacitive element 55 can be formed large (in a large area) in the pixel 70. Therefore, it is possible to obtain a display device having an aperture ratio of 50% or more, preferably 60% or more, and an increased capacity value while increasing the aperture ratio. For example, in a high-resolution display device, for example, a liquid crystal display device, the area of pixels is small and the area of capacitive elements is also small. Therefore, in a high-resolution display device,
The capacitance value stored in the capacitive element becomes smaller. However, since the capacitive element 55 shown in the present embodiment has translucency, by providing the capacitive element in a pixel, it is possible to increase the aperture ratio while obtaining a sufficient capacitance value in each pixel. Typically, it can be suitably used for a high-resolution display device having a pixel density of 200 ppi or more, further 300 ppi or more, and further 500 ppi or more.

Further, in the liquid crystal display device, the larger the capacitance value of the capacitive element, the longer the period during which the orientation of the liquid crystal molecules of the liquid crystal element can be kept constant in the situation where an electric field is applied. When displaying a still image, the period can be lengthened, so that the number of times the image data is rewritten can be reduced, and power consumption can be reduced. Further, since the structure shown in the present embodiment can increase the aperture ratio even in a high-resolution display device, it is possible to increase the aperture ratio.
The light from a light source such as a backlight can be efficiently used, and the power consumption of the display device can be reduced.

Next, a cross-sectional view of the alternate long and short dash line Q1-R1 and the alternate long and short dash line S1-T1 in FIG. 20 is shown in FIG.
Shown in 1. The transistor 52 shown in FIG. 21 is a top gate type transistor. The alternate long and short dash line Q1-R1 is a cross-sectional view of the transistor 52 in the channel length direction and the capacitive element 55, and the cross-sectional view of S1-T1 is a cross-sectional view of the transistor 52 in the channel width direction.

The transistor 52 shown in FIG. 21 has a conductive film 13 that functions as a first gate electrode provided on the substrate 11. Further, the first having a region overlapping the insulating film 12 formed on the substrate 11 and the conductive film 13 and the conductive film 13 functioning as a gate electrode via the insulating film 12.
The oxide semiconductor film 18 of the above, the insulating film 14 superimposed on the channel region 18i included in the first oxide semiconductor film 18 on the first oxide semiconductor film 18, and the insulating film 14 superimposed on the insulating film 14. It has a second oxide semiconductor film 19a, which functions as a second gate electrode. Further, on the insulating film 12, the first oxide semiconductor film 18 and the second oxide semiconductor film 19a, the insulating film 1 is placed.
5. The insulating film 16 is provided in this order. The conductive film 21a is electrically connected to the first source / drain region 18_1 included in the first oxide semiconductor film 18 through the openings provided in the insulating film 15 and the insulating film 16. The conductive film 21b has a second source / drain region 1 contained in the first oxide semiconductor film 18 through the insulating film and the openings provided in the insulating film 16.
It is electrically connected to 8_2. Further, the insulating film 17 is provided on the insulating film 16, the conductive film 21a and the conductive film 21b, and the conductive film 29 is provided on the insulating film 17.

The transistor 52 is a transistor having a dual gate structure in which the channel region 18i is sandwiched between two upper and lower gate electrodes, with the conductive film 13 as the first gate electrode and the second oxide semiconductor film 19a as the second gate electrode.

Further, the capacitive element 55 has a second oxide semiconductor film 19b that functions as one of a pair of electrodes having 14 insulating films, and an insulating film that functions as a dielectric film on the second oxide semiconductor film 19b. 15. It has an insulating film 16 and an insulating film 17, and a conductive film 29 having a function as the other of a pair of electrodes on the insulating film 17.

The cross-sectional view of one aspect of the embodiment of the present invention is not limited thereto. It can be configured in various ways. For example, the second oxide semiconductor film 19b may have a slit. Alternatively, the second oxide semiconductor film 19b may have a comb tooth shape.

As for the configuration of the display device 80 according to one aspect of the present invention, the configuration of the semiconductor device described in the first embodiment can be referred to. That is, for the material and manufacturing method of the substrate 11, the substrate 102 can be referred to. For the material and manufacturing method of the conductive film 13, the gate electrode 106 can be referred to. For the material and manufacturing method of the insulating film 12, the insulating film 104 can be referred to. For the material and manufacturing method of the first oxide semiconductor film 18, reference can be made to the first oxide semiconductor film 108. The materials and manufacturing methods of the second oxide semiconductor films 19a and 19b can refer to the second oxide semiconductor films 111a and 111b, respectively.
For the materials and manufacturing methods of the conductive film 21a and the conductive film 21b, reference to the conductive film 120a and the conductive film 120b, respectively. For the materials and manufacturing methods of the insulating film 15, the insulating film 16 and the insulating film 17, the insulating film 116, the insulating film 118, and the insulating film 122 can be referred to, respectively. For the material and manufacturing method of the conductive film 29, the conductive film 123 can be referred to.

<Structure example of element substrate (modification example 1)>
Next, a plurality of pixels 70d having a configuration different from the pixels shown in FIG. 20 of the display device 80,
The top view of 70e and 70f is shown in FIG. 22.

In FIG. 22, the conductive film 13 that functions as a scanning line is provided so as to extend in the left-right direction in the figure. The conductive film 21a that functions as a signal line is provided so as to extend in a direction substantially orthogonal to the scanning line (vertical direction in the figure) so as to have a partially bent dogleg (V-shaped) shape. The conductive film 13 that functions as a scanning line is electrically connected to the scanning line driving circuit 74, and the conductive film 21a that functions as a signal line is electrically connected to the signal line driving circuit 76 (). See FIG. 19 (A)).

The transistor 52 is provided in the vicinity of the intersection of the scanning line and the signal line. The transistor 52 is a conductive film 13 that functions as a first gate electrode, a first gate insulating film (not shown in FIG. 22), and a first oxide semiconductor film 18 formed on the first gate insulating film. , The conductive films 21a and 21b that function as either one or the other of the source electrode and the drain electrode, respectively.
, A second gate insulating film formed on the channel region 18i, and a second oxide semiconductor film 19a formed on the second gate insulating film and functioning as a second gate electrode. The first oxide semiconductor film 18 has a channel region 18i that overlaps with the second oxide semiconductor film 19a, a first source / drain region 18_1 that is in contact with the conductive film 21a, and a conductive film 2.
It has a second source / drain region 18_2, which is in contact with 1b. Further, the second oxide semiconductor film 19a is electrically connected to the conductive film 13 via the openings provided in the first gate insulating film and the second gate insulating film.

The conductive film 13 also functions as a scanning line, and the region superimposing on the first oxide semiconductor film 18 functions as a first gate electrode of the transistor 52. The conductive film 21a also functions as a signal line, and the region superimposing on the first source / drain region 18_1 functions as a source electrode or a drain electrode of the transistor 52. Further, in FIG. 22, the end portion of the conductive film 13 is located outside the end portion of the channel region 18i in the upper surface shape. Therefore, the conductive film 13 functions as a light-shielding film that blocks light from a light source such as a backlight. As a result, the channel region 18i included in the transistor is not irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed.

Further, the conductive film 21b is electrically connected to the second oxide semiconductor film 19b having the function of a pixel electrode. The second oxide semiconductor film 19b is formed in a comb-teeth shape. Further, an insulating film (not shown in FIG. 22) is provided on the second oxide semiconductor film 19b, and the conductive film 2 is provided on the insulating film.
9 is provided.

The conductive film 29 is formed in a comb-teeth shape so as to partially overlap with the second oxide semiconductor film 19b and to mesh with the second oxide semiconductor film 19b in the top view. Further, the conductive film 29 is connected to a region extending in a direction parallel to or substantially parallel to the scanning line. Therefore, the display device 8
In the plurality of pixels of 0, the conductive film 29 has the same potential in each region. The second oxide semiconductor film 19b and the conductive film 29 have a dogleg (V-shaped) shape that is bent along the signal line (conductive film 21a).

The capacitive element 55 is formed in a region where the oxide semiconductor film 19b and the conductive film 29 overlap.
The oxide semiconductor film 19b and the conductive film 29 have translucency. That is, the capacitive element 55 has translucency.

Next, a cross-sectional view of the alternate long and short dash line Q2-R2 and the alternate long and short dash line S2-T2 in FIG. 22 is shown in FIG.
Shown in 3. The transistor 52 shown in FIG. 23 is a top gate type transistor. The alternate long and short dash line Q2-R2 is a cross-sectional view of the transistor 52 in the channel length direction and the capacitive element 55, and the cross-sectional view of S2-T2 is a cross-sectional view of the transistor 52 in the channel width direction.

The transistor 52 shown in FIG. 23 has a conductive film 13 that functions as a first gate electrode provided on the substrate 11. Further, the first having a region overlapping the insulating film 12 formed on the substrate 11 and the conductive film 13 and the conductive film 13 functioning as a gate electrode via the insulating film 12.
The oxide semiconductor film 18 of the above, the insulating film 14 superimposed on the channel region 18i included in the first oxide semiconductor film 18 on the first oxide semiconductor film 18, and the insulating film 14 superimposed on the insulating film 14. It has a second oxide semiconductor film 19a, which functions as a second gate electrode. Further, on the insulating film 12, the first oxide semiconductor film 18 and the second oxide semiconductor film 19a, the insulating film 1 is placed.
5. The insulating film 16 is provided in this order. The conductive film 21a is electrically connected to the first source / drain region 18_1 included in the first oxide semiconductor film 18 through the openings provided in the insulating film 15 and the insulating film 16. The conductive film 21b has a second source / drain region 1 contained in the first oxide semiconductor film 18 through the insulating film and the openings provided in the insulating film 16.
It is electrically connected to 8_2. Further, the insulating film 17 is provided on the insulating film 16, the conductive film 21a and the conductive film 21b, and the conductive film 29 is provided on the insulating film 17.

The transistor 52 is a transistor having a dual gate structure in which the channel region 18i is sandwiched between two upper and lower gate electrodes, with the conductive film 13 as a first gate electrode and the second oxide semiconductor film 19a as a second gate electrode.

In the pixel shown in FIG. 23, the second oxide semiconductor film 19b having the function of a pixel electrode is provided on the insulating film 14 in the region where the orientation of the liquid crystal displayed on the insulating film 27 and the conductive film 29 is controlled. The conductive film 29 having the function of a common electrode is provided on the insulating film 17. As described above, a method for driving a display device that controls the orientation of a liquid crystal display by generating an electric field between a pair of electrodes arranged on different planes is described as DPS (Differential-Plane-Sw).
It can be called an itching) mode.

Further, the second oxide semiconductor film 19b, the insulating film 15, the insulating film 16 and the insulating film 17 are
The region where the conductive film 29 overlaps functions as the capacitive element 55.

The liquid crystal display device shown in FIGS. 22 and 23 has a second oxide semiconductor film 19b and a conductive film 29.
The capacitive element of the pixel is formed by the configuration in which the vicinity of each end of the pixel is superimposed. With such a configuration, in a large-sized liquid crystal display device, the capacitive element can be formed into an appropriate size without being too large.

As shown in FIGS. 24 and 25, the second oxide semiconductor film 19b may have a function of a common electrode, and the conductive film 29 may have a function of a pixel electrode. Further, the insulating film 14 may not be provided at a position where it overlaps with the second oxide semiconductor film 19b (see FIG. 25).

Further, as shown in FIGS. 26 and 27, the second oxide semiconductor film 19b and the conductive film 29 may not be superimposed. The positional relationship between the oxide semiconductor film 19b and the conductive film 29 can be appropriately determined depending on the resolution of the display device and the size of the capacitive element according to the driving method.

In the pixel configuration shown in FIG. 26, one of the pair of electrodes of the capacitive element 55 is the conductive film 21c, and the conductive film 21c is the other of the source electrode and the drain electrode of the transistor 52 via the second oxide semiconductor film 19b. It is electrically connected to the conductive film 21b. The other of the pair of electrodes of the capacitive element 55 is electrically connected to the conductive film 29.

Further, in the liquid crystal display device shown in FIGS. 22 and 23, the width (d1) of the region extending in a direction parallel to or substantially parallel to the signal line (conductive film 21a) of the oxide semiconductor film 19b is the signal of the conductive film 29. The configuration is smaller than the width (d2) of the region extending in a direction parallel to or substantially parallel to the line (see FIG. 23), but the configuration is not limited to this. As shown in FIGS. 28 and 29, the width d1 may be larger than the width d2. Further, the width d1 and the width d2 may be equal. Further, in one pixel (for example, pixel 70d), the widths of a plurality of regions of the oxide semiconductor film 19b and / or the conductive film 29 extending in a direction parallel to or substantially parallel to the signal line may be different. ..

Further, as shown in FIGS. 30 and 31, the common electrode may be provided on the same layer as the oxide semiconductor film 19b, that is, on the insulating film 14. The common electrode 19c shown in FIGS. 30 and 31 can be simultaneously formed of the same material as the oxide semiconductor film 19b.

In the pixel configuration shown in FIG. 30, one of the pair of electrodes of the capacitive element 55 is a second oxide semiconductor film 19b. The other of the pair of electrodes of the capacitive element 55 is a conductive film 21c that is electrically connected to the conductive film 29.

As for the configuration of the display device 80 according to one aspect of the present invention, the configuration of the semiconductor device described in the first embodiment can be referred to. That is, for the material and manufacturing method of the substrate 11, the substrate 102 can be referred to. For the material and manufacturing method of the conductive film 13, the gate electrode 106 can be referred to. For the material and manufacturing method of the insulating film 12, the insulating film 104 can be referred to. For the material and manufacturing method of the first oxide semiconductor film 18, reference can be made to the first oxide semiconductor film 108. The materials and manufacturing methods of the second oxide semiconductor films 19a and 19b can refer to the second oxide semiconductor films 111a and 111b, respectively.
For the materials and manufacturing methods of the conductive film 21a and the conductive film 21b, reference to the conductive film 120a and the conductive film 120b, respectively. For the materials and manufacturing methods of the insulating film 15, the insulating film 16 and the insulating film 17, the insulating film 116, the insulating film 118, and the insulating film 122 can be referred to, respectively. For the material and manufacturing method of the conductive film 29, the conductive film 123 can be referred to.

The display device according to one aspect of the present invention may have the function of a touch sensor. Specifically, the common electrode of the display device, for example, the conductive film 29 may have the function of at least one of the pair of electrodes constituting the touch sensor. At this time, the display device according to one aspect of the present invention can also be referred to as a touch panel.

Hereinafter, a method, a mode, a configuration example of a touch sensor or a touch panel according to an aspect of the present invention, and a configuration example of a semiconductor device according to the present invention will be described with reference to the drawings.

[Example of sensor detection method]
FIG. 32A is a block diagram showing a configuration of a mutual capacitance type touch sensor. FIG. 32
In (A), the pulse voltage output circuit 401 and the current detection circuit 402 are shown. Note that FIG. 32
In (A), as an example, the electrode 421 to which the pulse voltage is applied is shown as 6 wires of X1-X6, and the electrode 422 which detects the change in current is shown as 6 wires of Y1-Y6. note that,
The number of electrodes is not limited to this. Further, FIG. 32 (A) illustrates a capacitance 403 formed by overlapping the electrodes 421 and 422 or by arranging the electrodes 421 and 422 in close proximity to each other. The functions of the electrode 421 and the electrode 422 may be interchanged with each other. Alternatively, the pulse voltage output circuit 401 and the current detection circuit 402 may be replaced with each other.

As an example, the pulse voltage output circuit 401 is a circuit for sequentially applying a pulse to the wiring of X1-X6. By applying a pulse voltage to the wiring of X1-X6, a change occurs in the electric field between the electrodes 421 and the electrodes 422 forming the capacitance 403. Then, a current flows through the capacity 403 due to the pulse voltage. At this time, the electric field generated between the electrodes changes depending on whether or not a finger, a pen, or the like is present in the vicinity, due to shielding by touching the finger, the pen, or the like. That is, the capacity value of the capacity 403 changes by touching with a finger or a pen. As a result, the magnitude of the current flowing through the capacitance 403 changes depending on the pulse voltage. In this way, it is possible to detect the proximity or contact of the object to be detected by utilizing the fact that the capacitance value is changed by the touch of a finger or a pen.

The current detection circuit 402 is a circuit for detecting a change in the current in the wiring of Y1-Y6 due to a change in the capacity value in the capacity 403. In the wiring of Y1-Y6, there is no change in the current value detected when there is no proximity or contact with the detected object, but the current value when the capacitance value decreases due to the proximity or contact of the detected object to be detected. Detects a decreasing change. The current may be detected by detecting the total amount of current. In that case, the detection may be performed using an integrator circuit or the like. Alternatively, the peak value of the current may be detected. In that case, the current may be converted into a voltage to detect the peak value of the voltage value.

Next, FIG. 32 (B) shows a timing chart of input / output waveforms in the mutual capacitance type touch sensor shown in FIG. 32 (A). In FIG. 32 (B), it is assumed that the detected object is detected in each matrix in one frame period. Further, in FIG. 32 (B), when the detected object is not detected (
Two cases are shown: non-touch) and detection of the object to be detected (touch). The wiring of Y1 to Y6 shows a waveform having a voltage value corresponding to the detected current value. The display operation is also performed on the display panel. It is desirable that the timing of this display operation and the timing of the touch sensor operate in synchronization with each other. In addition, FIG.
2 (B) shows an example in the case where the display operation is not synchronized with the display operation.

Pulse voltage is applied to the wiring of X1-X6 in order, and Y1- according to the pulse voltage.
The waveform in the Y6 wiring changes. X1-X6 when there is no proximity or contact with the object to be detected
The waveform of Y1-Y6 changes uniformly according to the change of the voltage of the wiring of. On the other hand, since the current value decreases at the location where the object to be detected is close to or in contact with the object to be detected, the corresponding voltage value waveform also changes.

By detecting the change in the capacitance value in this way, it is possible to detect the proximity or contact of the object to be detected. It should be noted that the detected object such as a finger or a pen may not come into contact with the touch sensor or the touch panel, and the signal may be detected even when the object is close to the touch sensor or the touch panel.

In FIG. 32B, an example is shown in which pulse voltages are sequentially applied to the wirings of X1-X6, but one aspect of the present invention is not limited to this. For example, a pulse voltage may be applied to a plurality of wires at the same time. For example, first, a pulse voltage is applied to the wirings of X1 to X3. Next, a pulse voltage is applied to the wiring of X2 to X4. Next, a pulse voltage is applied to the wiring of X3 to X5. In this way, pulse voltages may be applied to a plurality of wires at the same time. Then, the sensitivity of the sensor can be increased by performing arithmetic processing on the read signal.

Further, the pulse voltage output circuit 401 and the current detection circuit 402 are, for example, one IC.
It is preferably formed in. The IC is preferably mounted on a touch panel, for example, or on a substrate in a housing of an electronic device. In addition, in the case of a flexible touch panel, the parasitic capacitance may increase at the bent part and the influence of noise may increase. Therefore, an IC to which a driving method less susceptible to noise is applied is used. It is preferable to use it. For example, it is preferable to use an IC to which a driving method for increasing the signal-noise ratio (S / N ratio) is applied.

In the case of the in-cell type touch sensor, a circuit for driving the display unit is provided. For example, the circuit is a gate line drive circuit, a source line drive circuit, or the like. These circuits may also be formed in the IC. Therefore, at least one of the pulse voltage output circuit 401 or the current detection circuit 402 and at least one of the gate line drive circuit or the source line drive circuit may be formed in one IC. For example, a source line drive circuit is often formed in an IC because of its high drive frequency. Further, the current detection circuit 4
Since 02 may require an operational amplifier or the like, it is often formed in an IC. Therefore, the source line drive circuit and the current detection circuit 402 may be formed in one IC. In this case, the gate line drive circuit and the pulse voltage output circuit 401 may be formed together with the pixels on the substrate on which the pixels are formed. Alternatively, the source line drive circuit, the current detection circuit 402, and the pulse voltage output circuit 401 may be formed in one IC.

Further, although FIG. 32 (A) shows the configuration of a passive matrix type touch sensor in which only the capacitance 403 is provided at the intersection of the wirings as the touch sensor, an active matrix type touch sensor having a transistor and a capacitance may be used. ..

Although the driving method in the case of the mutual capacitance method has been described in FIG. 32, one aspect of the present invention is not limited to this. For example, the self-capacity method may be used. In that case,
The pulse voltage output circuit 401 also has a function of detecting a current. Similarly, the current detection circuit 402 also has a function of outputting a pulse voltage. Alternatively, the mutual capacity method and the self-capacity method may be switched and operated depending on the situation.

[Example of in-cell touch panel configuration]
Here, an example in which at least one of the pair of electrodes constituting the touch sensor is arranged on a substrate on which a display element, a transistor, or the like is provided (hereinafter, also referred to as an element substrate) will be described.

Hereinafter, a configuration example of a touch panel (so-called in-cell type) in which a touch sensor is incorporated in a display unit having a plurality of pixels will be described. Here, an example in which a liquid crystal element is applied as a display element provided in a pixel is shown. However, one aspect of the present invention is not limited to this, and various display elements can be applied.

FIG. 33 is an equivalent circuit diagram of a part of the pixel circuit provided in the display unit of the touch panel illustrated in this configuration example.

One pixel has at least a transistor 463 and a liquid crystal element 464. In addition to this, the pixel may have a holding capacity. Wiring 46 to the gate of transistor 463
1 and the wiring 62 are electrically connected to one of the source and the drain.

The common electrodes of the liquid crystal element 464 having a plurality of pixels adjacent to each other in the Y direction are electrically connected to form one block. The electrodes 471_1 and 471_2 shown in FIG. 33 are provided extending in the Y direction and serve as common electrodes in a region in which the liquid crystal element 464 is configured (a region in which the electric field generated by the pixel electrode and the common electrode controls the orientation of the liquid crystal). Function. Electrode 471_
Blocks containing a plurality of pixels sharing a common electrode by 1,471_2 are designated as blocks 465_1 and 465_2, respectively.

Further, the common electrodes of the liquid crystal element 464 having the plurality of pixels adjacent to each other in the X direction across the blocks 465_1 and 465_2 are electrically connected to form one block. FIG. 33
The electrodes 472_1 to 472_4 shown in the above are provided extending in the X direction and function as common electrodes in the region where the liquid crystal element 464 is formed. Blocks containing a plurality of pixels sharing a common electrode by electrodes 472_1 to 472_4 are designated as blocks 467_1 to 467_4, respectively. Although only a part of the pixel circuit is shown in FIG. 33, in reality, these blocks are repeatedly arranged in the X direction and the Y direction.

With such a configuration, the pair of electrodes constituting the touch sensor and the common electrode of the liquid crystal element included in the pixel circuit can be combined. That is, in FIG. 33, the electrode 471_1
, 471_2 also serve as a common electrode of the liquid crystal element 464 and one electrode of the touch sensor. Further, the electrodes 472_1 to 472_4 also serve as a common electrode of the liquid crystal element 464 and the other electrode of the touch sensor. Therefore, the configuration of the touch panel can be simplified.

The common electrode of the liquid crystal element 464 included in one pixel can serve as either one electrode or the other electrode constituting the touch sensor. In other words, the pixels of the display unit are a pixel in which the common electrode doubles as one electrode of the touch sensor (also referred to as a first pixel) and a pixel in which the common electrode doubles as the other electrode of the touch sensor (also referred to as a second pixel). ) And include. Therefore, in the display unit of the touch panel shown in this configuration example, the first pixel and the second pixel
Depending on the arrangement of the pixels of the touch sensor, the top surface shape of one electrode and the other electrode constituting the touch sensor can be any shape.

FIG. 34 (A) is an equivalent circuit diagram showing a connection configuration of a plurality of electrodes 472 extending in the X direction and a plurality of electrodes 471 extending in the Y direction. As an example, the case where the touch sensor is a projection type and a mutual capacitance type is shown. An input voltage (or selection voltage) or a common potential (or a ground potential or a reference potential) can be input to each of the electrodes 471 extending in the Y direction. Further, a ground potential (or a reference potential) can be input to each of the electrodes 472 extending in the X direction, or the electrode 472 can be electrically connected to the detection circuit. The electrodes 471 and 472 can be interchanged. That is, the electrode 471 and the detection circuit may be connected.

Hereinafter, the operation of the touch panel described above will be described with reference to FIGS. 34 (B) and 34 (C).

Here, as an example, one frame period is divided into a writing period and a detection period. The writing period is a period for writing image data to the pixels, and wiring 461 (also referred to as a gate line or a scanning line) is sequentially selected. On the other hand, the detection period is a period during which sensing is performed by the touch sensor, and electrodes 471 extending in the Y direction are sequentially selected, and an input voltage is input.

FIG. 34 (B) is an equivalent circuit diagram during the writing period. During the writing period, a common potential is input to both the electrode 472 extending in the X direction and the electrode 471 extending in the Y direction.

FIG. 34 (C) is an equivalent circuit diagram at a certain point in the detection period. During the detection period, each of the electrodes 472 extending in the X direction conducts with the detection circuit. Further, the electrode 4 extending in the Y direction
Of the 71, the input voltage is input to the selected one, and the common potential is input to the other ones.

As described above, it is preferable to independently provide the image writing period and the sensing period by the touch sensor. For example, it is preferable to perform sensing during the return period of the display. This makes it possible to suppress a decrease in the sensitivity of the touch sensor due to noise during writing of the pixels.

In addition, although an example of the case where one frame period is divided into a writing period and a detection period is shown here, one aspect of the present invention is not limited to this. For example, one horizontal period (also referred to as one gate selection period) may be divided into a writing period and a detection period for operation.

In addition, although the example in the case where the pulse voltage is sequentially applied to the electrode 471 is shown, one aspect of the present invention is not limited to this. For example, a pulse voltage may be applied to a plurality of electrodes 471 at the same time. For example, first, a pulse voltage is applied to the first to third electrodes 471. Next, a pulse voltage is applied to the second to fourth electrodes 471. Next, the 3rd to 5th electrodes 4
A pulse voltage is applied to 71. In this way, pulse voltages may be applied to the plurality of electrodes 471 at the same time. Then, the sensitivity of the sensor can be increased by performing arithmetic processing on the read signal.

Although the driving method in the case of the mutual capacitance method is described in FIG. 34, one aspect of the present invention is not limited to this. For example, the self-capacity method may be used. In that case,
The circuit that outputs the pulse voltage also has a function of detecting the current. Similarly, the detection circuit will also have a function of outputting a pulse voltage. Alternatively, the mutual capacity method and the self-capacity method may be switched and operated depending on the situation.

[About the touch panel method]
Hereinafter, some methods applicable to the touch panel of one aspect of the present invention will be described.

In the present specification and the like, the touch panel has a function of displaying (outputting) an image or the like on the display surface and a function as a touch sensor for detecting that a detected object such as a finger or a stylus touches or approaches the display surface. And have. Therefore, the touch panel is one aspect of the input / output device. Therefore, it can be said that the touch panel is a display device with a built-in touch sensor.

Further, in the present specification and the like, on the substrate of the touch panel, for example, FPC (Flexible P) is used.
lint Circuit) or TCP (Tape Carrier Packag)
A connector such as e) is attached, or COG (Chip On G) is attached to the board.
A touch panel module with an IC (integrated circuit) mounted by the lass) method.
Sometimes referred to as a display module, or simply a touch panel.

The capacitive touch sensor applicable to one aspect of the present invention includes a pair of conductive films.
A capacitance is formed between the pair of conductive films. Detection can be performed by utilizing the fact that the magnitude of the capacitance between the pair of conductive films changes when the object to be detected touches or is close to the pair of conductive films.

As the capacitance method, there are a surface type capacitance method, a projection type capacitance method and the like. As the projection type capacitance method, there are a self-capacitance method, a mutual capacitance method, and the like mainly due to the difference in the drive method. It is preferable to use the mutual capacitance method because simultaneous multipoint detection is possible. However, one aspect of the present invention is not limited to this.

Further, as the display element of the touch panel of one aspect of the present invention, a liquid crystal element (longitudinal electric field method or horizontal electric field method), MEMS (Micro Electro Mechanical)
Optical element using al System), organic EL (Electro Lumines)
Cense) element, inorganic EL element and light emitting diode (LED: Light Emitti)
Various display elements such as a light emitting element such as ng Diode) and an electrophoresis element can be used.

Here, it is preferable to use a liquid crystal element to which the transverse electric field method is applied as the display element in the display device. When a transparent conductive film is used in the pixel electrode and the common electrode, it can be used as a transmissive display device. On the other hand, when a reflective electrode is used in the pixel electrode or the common electrode, it can be used as a reflective display device.
Both the pixel electrode and the common electrode may be used as the reflective electrode. Alternatively, a reflection type display device may be provided by providing a reflection electrode separately from the pixel electrode and the common electrode. In the reflection type display device, a semi-transmissive type display device may be provided by providing a region through which the light of the backlight can be transmitted. For example, a part of the pixel electrode or the common electrode may be used as a transmission electrode, and another part may be used as a reflection electrode. Even when a reflective electrode is used as a pixel electrode or a common electrode, it may be used as a transmissive display device depending on the operation mode of the liquid crystal display.

In the display device of one aspect of the present invention, the display panel and the touch sensor are integrated by having at least one of a pair of electrodes (also referred to as a conductive film or wiring) constituting the touch sensor on one of the pair of substrates. It has a structure that has become. Therefore, the thickness of the display device is reduced, and a lightweight display device can be realized.

35 (A) to 35 (C) are schematic cross-sectional views illustrating the mode of the touch panel 410 according to one aspect of the present invention.

The touch panel 410 includes a substrate 411, a substrate 412, an FPC 413, a conductive film 414, a pixel 400a, a pixel 400b, a liquid crystal element 420a, 420b, a colored film 431, and the like.

The pixel 400a includes a liquid crystal element 420a, and the pixel 400b includes a liquid crystal element 420b.
The liquid crystal element 420a is composed of a conductive film 419a, a conductive film 429a, and a liquid crystal 423. Further, the liquid crystal element 420b is composed of a conductive film 419b, a conductive film 429b and a liquid crystal 423. In FIGS. 35 (A) and 35 (B), the conductive film 419a and the conductive film 41
9b has a function as a pixel electrode. The conductive film 429a and the conductive film 429b have a function as a common electrode. Further, in FIG. 35 (A), the liquid crystal elements 420a and 420b are referred to as FF.
An example is shown in the case of using a liquid crystal element to which the S (Fringe Field Switching) mode is applied.

The conductive film 419a and the conductive film 419b are provided on the same surface. Alternatively, the conductive film 4
The 19a and the conductive film 419b are formed of the same conductive film. An insulating film 424 is provided on the conductive film 419a and the conductive film 419b. The conductive film 429a and the conductive film 429b are provided on the same surface, specifically, on the insulating film 424. Or the conductive film 42
9a and the conductive film 429b are formed of the same conductive film. As an example, the conductive film 429a and the conductive film 429b have a comb-shaped upper surface shape or a top surface shape (also referred to as a planar shape) having one or more slit-shaped openings.

The touch sensor can detect using the capacitance formed between the conductive film 429a of the pixel 400a and the conductive film 429b of the pixel 400b. With such a configuration, the common electrodes (429a, 429b) included in the liquid crystal element can also serve as a pair of electrodes functioning as a touch sensor. Therefore, since the process can be simplified, the yield can be improved and the manufacturing cost can be reduced. The conductive film 429a,
The conductive film 429b is electrically connected to the FPC 413 attached to the substrate 411 side via the conductive film 414. Alternatively, at least one of the conductive film 429a or the conductive film 429b is connected to a circuit having a function capable of outputting a pulse voltage. also,
The conductive films 419a and 419b are electrically connected to a transistor (not shown). The transistor is a drive circuit (gate line drive circuit or source line drive circuit).
Alternatively, it is electrically connected to the FPC 413.

For example, the conductive film 429a and the conductive film 429b in FIG. 35 (A) correspond to the conductive film 29 in FIG. Further, the conductive film 419a and the conductive film 419b in FIG. 35 (A) correspond to the second oxide semiconductor film 19b in FIG. 21.

In addition, in FIG. 35A, the conductive film 419a and the conductive film 429a (or the conductive film 419b) are shown.
And the conductive film 429b) have regions that overlap each other. This region can function as a capacitive element. That is, this region can function as a holding capacity for holding the potential of the pixel electrode. However, one aspect of the present invention is not limited to this. For example, the conductive film 419a and the conductive film 429a (or the conductive film 419b and the conductive film 429b) are
In areas that contribute to the display (in so-called openings), they may not overlap each other. That is, in the region contributing to the display (in the so-called opening), the positions of the end portions of the electrodes may be aligned vertically.

As shown in FIG. 35 (B), the touch panel 410 has a conductive film 429a and a conductive film 429.
In addition to b, the conductive film 419a and the conductive film 419b may also have a comb-shaped upper surface shape or an upper surface shape provided with one or more slit-shaped openings. The drive method of the liquid crystal elements 420a and 420b in FIG. 35B is IPS (In-Plane-Switchchi).
ng) mode. With such a configuration, the size of the holding capacity can be reduced.

For example, the conductive film 429a and the conductive film 429b in FIG. 35 (B) correspond to the conductive film 29 in FIG. 27. Further, the conductive film 419a and the conductive film 419b in FIG. 35B correspond to the second oxide semiconductor film 19b in FIG. 27.

Further, as shown in FIG. 35 (C), the conductive film 419a and the conductive film 419b may have a function as a common electrode, and the conductive film 429a and the conductive film 429b may have a function as a pixel electrode. In FIG. 35 (C), the touch sensor is a conductive film 4 included in the pixel 400a.
The capacitance formed between the 19a and the conductive film 419b of the pixel 400b can be used for detection. The conductive film 419a and the conductive film 419b are electrically connected to the FPC 413 attached to the substrate 411 side via the conductive film 414. Or, conductive film 419
At least one of a or the conductive film 419b is connected to a circuit having a function capable of outputting a pulse voltage. Further, the conductive films 429a and 429b are electrically connected to a transistor (not shown).

In FIG. 35B, for example, a non-transparent electrode may be used as the common electrode and the pixel electrode. For example, a material similar to the conductive material used in the gate electrode, the source electrode, the drain electrode, or the like may be used. This is because, in the IPS mode, it is difficult for an electric field to be applied to the liquid crystal 423 above the electrodes. Therefore, it is difficult to control the orientation of the liquid crystal 423. Therefore, it is unlikely to be an area that contributes to display. Therefore, it is not necessary to transmit the light from the backlight. Therefore, even in a transmissive display device, the common electrode and the pixel electrode may be configured by using aluminum, molybdenum, titanium, tungsten, copper, silver, or the like. These electrodes may be formed in the shape of a mesh or in the shape of nanowires. The common electrode also functions as an electrode for a touch sensor. Therefore, it is desirable that the resistance value is as low as possible. Therefore, a non-transparent electrode is desirable because it has a lower resistance value than a transparent electrode such as indium tin oxide (also referred to as ITO).

In FIGS. 35 (A) to 35 (C), the common electrode and the pixel electrode are used as the common electrode and the pixel electrode.
A transparent conductive film such as ITO may be used. Further, a conductive film having a lower resistance value may be provided as an auxiliary wiring on the transparent conductive film or under the transparent conductive film. As the auxiliary wiring, for example, a material similar to the conductive material used in the gate electrode, the source electrode, the drain electrode, or the like may be used. Specifically, it may be configured by using aluminum, molybdenum, titanium, tungsten, copper, silver or the like.

When the auxiliary wiring is provided on the transparent conductive film, a halftone mask (also referred to as a gray tone mask or a phase difference mask) is used, and the transparent conductive film and the auxiliary wiring are connected by using one mask. , May be formed. In that case, the transparent conductive film is always provided under the auxiliary wiring. However, one aspect of the present invention is not limited to this. The transparent conductive film and the auxiliary wiring may be formed in different steps by using different masks.

In FIGS. 35 (A) to 35 (C), the common electrode may be connected to an auxiliary wiring having a low resistance value. For example, the common electrode and the auxiliary wiring are connected via an opening of an insulating film provided between them. For example, the auxiliary wiring and the gate electrode (or gate signal line) may be formed of the same conductive film. Alternatively, the auxiliary wiring and the source / drain electrode (or source signal line) may be formed of the same conductive film.

In addition, for example, the conductive film in a floating state may be arranged on the upper side of the substrate 412.
Examples of such cases are shown in FIGS. 36 (A), 36 (B), and 36 (C). In this way, the conductive film 428a is provided so as to overlap with the common electrode of the pixel 400a. Similarly, conductive film 428
b is provided so as to overlap with the common electrode of the pixel 400b. As a result, the capacitive elements are provided in series. Further, since the electric field distribution is in an appropriate state, the sensitivity of the touch sensor can be improved. Further, when the detected body is in close proximity to or in contact with the substrate 412, the detected body may be charged with static electricity. In such a case, the influence of static electricity can be reduced by providing the conductive film 428a, the conductive film 428b, and the like on the upper side of the substrate 412.

37 (A) corresponds to FIGS. 35 (A) and 35 (B). In the configuration shown in FIG. 37 (A), the touch sensor has a sensor electrode 459a and a sensor electrode 459b. The sensor electrode 459a has the function of a common electrode in the pixel 400a, and is formed of the same conductive film as the conductive film 429a of the pixel 400a. Further, the sensor electrode 459b is the pixel 4.
At 00b, it has the function of a common electrode and is formed of the same conductive film as the conductive film 429b of the pixel 400b. The sensor electrode 459a has one or more slit-shaped openings 426 in the pixel 400a. Further, the sensor electrode 459b has one or more slit-shaped openings 426 in the pixel 400b.

The sensor electrode 459a is provided in an island shape in a size that functions as a common electrode of the pixel 400a, and is electrically connected to a wiring 453 extending in one direction (for example, the X direction).
Further, the sensor electrode 459b is provided so as to extend in a direction intersecting with the one direction (for example, the Y direction). The wiring 453 can be formed at the same time as the source electrode and the drain electrode of the transistor included in the pixels 400a and 400b, for example.

Further, as shown in FIG. 37 (B), the sensor electrode 459a is electrically connected to the wiring 453 extending in one direction (for example, the X direction), and the sensor electrode 459b intersects the one direction. It may be electrically connected to the wiring 454 extending in the direction (for example, the Y direction). At this time, the sensor electrode 459a and the sensor electrode 459b are each pixel 40.
It is provided in an island shape in a size that functions as a common electrode of 0a and 400b. Wiring 454
For example, it can be formed at the same time as the first gate electrode of the transistor included in the pixels 400a and 400b. It should be noted that one sensor electrode provided in an island shape is not a common electrode of one pixel, but
It may be provided so as to function as a common electrode of a plurality of pixels.

It should be noted that this embodiment can be appropriately combined with other embodiments shown in the present specification.

(Embodiment 4)
In the present embodiment, vertical orientation (VA: Ve) applicable to the liquid crystal display device according to one aspect of the present invention.
The configuration of the pixel including the liquid crystal element operating in the vertical alignment mode will be described with reference to FIGS. 38 and 39. FIG. 38 is a top view of the pixels included in the liquid crystal display device, and FIG. 39 is a side view including a cross section of the cutting lines A1-B1 of FIG. 38. Further, FIG. 40A is an equivalent circuit diagram of pixels included in the liquid crystal display device.

The VA type is a kind of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is a system in which liquid crystal molecules face in the direction perpendicular to the panel surface when no voltage is applied.

In this embodiment, pixels are particularly divided into several areas (subpixels).
It is devised to defeat the molecules in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering a multi-domain design will be described.

Z1 in FIG. 38 is a top view of the substrate 602 on which the pixel electrode 611b is formed, Z3 is a top view of the substrate 601 on which the common electrode 671 is formed, and Z2 is common with the substrate 602 on which the pixel electrode 611b is formed. It is a top view of the state in which the substrate 601 on which the electrode 671 is formed is overlapped.

A transistor 650, a pixel electrode 611b connected to the transistor 650, and a capacitive element 661 are formed on the substrate 602. The drain electrode 620b of the transistor 650 has an insulating film 616.
And is electrically connected to the pixel electrode 611b via the opening 641b provided in the insulating film 618. An insulating film 616, an insulating film 618, and an insulating film 622 are provided on the pixel electrode 611b in this order.

The transistor 650 is a transistor (transistor 1) described in the first embodiment.
50, Transistor 150A to Transistor 150G) can be applied.

The capacitive element 630 is composed of a capacitive wiring 607 which is a first capacitive wiring, an insulating film 604, and a pixel electrode 611b. The capacitive wiring 607 can be formed of the same material as the gate wiring 606 of the transistor 650 at the same time.

As the pixel electrode 611b, the oxide semiconductor film having a low resistivity described in the first embodiment can be applied. That is, the material and manufacturing method of the pixel electrode 611b are the first embodiment.
The second oxide semiconductor film 111b shown by the above can be referred to.

The pixel electrode 611b is provided with a slit 674. The slit 674 is for controlling the orientation of the liquid crystal display.

The transistor 651, the pixel electrode 612b connected to the transistor 651, and the capacitive element 662 can be formed in the same manner as the transistor 650, the pixel electrode 611b, and the capacitive element 661, respectively. Both the transistor 650 and the transistor 651 are connected to the wiring 620a. The wiring 620a has a function as a source electrode in the transistor 650 and the transistor 651. The pixel of the liquid crystal display panel shown in the present embodiment is composed of a pixel electrode 611b and a pixel electrode 612b. The pixel electrode 611b and the pixel electrode 612b are sub-pixels.

A colored film 673 and a common electrode 671 are formed on the substrate 601, and a protrusion 675 is formed in contact with the common electrode 671. Further, the common electrode 671 is provided with a slit 672. An alignment film 677 is formed on the insulating film 622 on the pixel electrode 611b side, and an alignment film 678 is formed on the common electrode 671 and the protrusion 675 side. Board 602 and board 601
A liquid crystal layer 680 is formed between the two.

The common electrode 671 is preferably formed by using the same material as the conductive film 123 described in the first embodiment. The slit 672 formed in the common electrode 671 and the protrusion 675 have a function of controlling the orientation of the liquid crystal display.

When a voltage is applied to the pixel electrode 611b provided with the slit 674, electric field distortion (oblique electric field) is generated in the vicinity of the slit 674. The slit 674 and the protrusion 6 on the substrate 601 side.
By arranging the 75 and the slit 672 alternately so as to mesh with each other and effectively generating an oblique electric field to control the orientation of the liquid crystal, the direction in which the liquid crystal is oriented is changed depending on the location. That is, the viewing angle of the liquid crystal display panel is widened by making it multi-domain. The substrate 601
Either one of the protrusion 675 and the slit 672 may be provided on the side.

FIG. 39 shows a state in which the substrate 602 and the substrate 601 are superposed and the liquid crystal is injected. A liquid crystal element is formed by overlapping the pixel electrode 611b, the liquid crystal layer 680, and the common electrode 671.

The equivalent circuit of this pixel structure is shown in FIG. 40 (A). Transistor 650 and transistor 6
29 is both connected to the gate wiring 606 and the wiring 620a. In this case, the capacitance wiring 60
By making the potentials of 7 and the capacitive wiring 609 different, the operations of the liquid crystal element 681 and the liquid crystal element 682 can be made different. That is, by individually controlling the potentials of the capacitive wiring 607 and the capacitive wiring 609, the orientation of the liquid crystal is precisely controlled to widen the viewing angle.

In the transistors 650 and 651 of FIG. 40 (A), the second gate electrode is electrically connected to the first gate electrode, but the present invention is not limited to this. For example, the second gate electrode may be electrically connected to the wiring 4616 having a function of giving a potential different from that of the gate wiring 606 (see FIG. 40B).

It should be noted that this embodiment can be appropriately combined with other embodiments shown in the present specification.

(Embodiment 5)
In the present embodiment, an example of the display device having the transistor exemplified in the previous embodiment will be described below with reference to FIGS. 41 to 44.

FIG. 41 is a top view showing an example of a display device. The display device shown in FIG. 41 includes a pixel unit 702 provided on the first substrate 701, a source driver circuit unit 704 and a gate driver circuit unit 706 provided on the first substrate 701, a pixel unit 702, and a source. Driver circuit unit 7
04, a sealing material 712 arranged so as to surround the gate driver circuit portion 706, and a first
It has a second substrate 705 provided so as to face the substrate 701 of the above. The first substrate 701 and the second substrate 705 are sealed with a sealing material 712. That is,
The pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 are the first.
It is sealed by the substrate 701, the sealing material 712, and the second substrate 705. In addition, FIG. 4
Although not shown in 1, a display element is provided between the first substrate 701 and the second substrate 705.

Further, the display device is electrically connected to the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 in a region different from the region surrounded by the sealing material 712 on the first substrate 701. FPC terminal part 708 (FPC: Flexible)
Printed Circuit) is provided. Further, the FPC terminal portion 708 has an F.
The PC716 is connected, and the pixel section 702 and the source driver circuit section 70 are connected by the FPC716.
Various signals and the like are supplied to 4 and the gate driver circuit unit 706. In addition, the pixel unit 702,
Wiring 710 is connected to the source driver circuit unit 704, the gate driver circuit unit 706, and the FPC terminal unit 708, respectively. Various signals and the like supplied by the FPC 716 are given to the pixel unit 702, the source driver circuit unit 704, the gate driver circuit unit 706, and the FPC terminal unit 708 via the wiring 710.

Further, a plurality of gate driver circuit units 706 may be provided in the display device. Further, as the display device, the source driver circuit unit 704 and the gate driver circuit unit 706 are included in the pixel unit 702.
Although an example of forming on the same first substrate 701 as the above is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit unit 706 may be formed on the first substrate 701, or only the source driver circuit unit 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a single crystal semiconductor film, etc.)
A drive circuit board formed of a polycrystalline semiconductor film) may be mounted on the first board 701. The method of connecting the separately formed drive circuit board is not particularly limited.
A COG (Chip On Glass) method, a wire bonding method, or the like can be used.

The pixel unit 702 included in the display device has a plurality of transistors and capacitive elements, and the semiconductor device described in the first embodiment can be applied. Further, the source driver circuit unit 7
The 04 and the gate driver circuit unit 706 have a plurality of transistors and wiring contact units, and the semiconductor device described in the second embodiment can be applied.

Further, the display device can use various forms or have various display elements. The display element is, for example, a liquid crystal element, an LED (white LED, red LED, green LED, etc.).
EL (electroluminescence) elements including (blue LEDs, etc.) (EL elements containing organic and inorganic substances, organic EL elements, inorganic EL elements), transistors (transistors that emit light according to current), electron emitting elements, electrophoresis elements, etc. Glazing light valve (GLV)
MEMS (Micro Electro Mechanical Systems) such as Digital Micromirror Device (DMD), DMS (Digital Micro Shutter) Element, MIRASOL (Registered Trademark) Display, IMOD (Interference Modulation) Element, piezoelectric Ceramic Display, etc. ), Such as a display element and an electrowetting element. In addition to these, a display medium whose contrast, brightness, reflectance, transmittance and the like are changed by an electric or magnetic action may be provided. Further, quantum dots may be used as the display element. An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection type liquid crystal display). An EL display or the like is an example of a display device using an EL element. As an example of a display device using an electron emitting element, a field emission display (FED) or an SED type planar display (SED: Surface-conduction Electron-emitt)
er Display) and so on. An example of a display device using quantum dots is a quantum dot display. An example of a display device using electronic ink or an electrophoresis element is electronic paper. In the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

As the display method in the display device, a progressive method, an interlaced method, or the like can be used. In addition, as a color element controlled by pixels when displaying in color, RGB (
R is red, G is green, and B is blue). For example, it may be composed of four pixels of R pixel, G pixel, B pixel, and W (white) pixel. Alternatively, as in the pentile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to the display device for color display, and can be applied to the display device for monochrome display.

In addition, white light (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is used for the backlight.
A colored film (also referred to as a color filter) may be used in order to display the display device in full color using W). The colored film is, for example, red (R), green (G), blue (B).
, Yellow (Y) and the like can be used in appropriate combinations. By using a colored film,
Color reproducibility can be improved as compared with the case where a coloring film is not used. At this time, by arranging the region having the colored film and the region not having the colored film, the white light in the region without the colored film may be directly used for display. By arranging a region that does not have a colored film in a part thereof, it is possible to reduce the decrease in brightness due to the colored film and reduce the power consumption by about 20% to 30% in a bright display. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from an element having each emission color. .. By using the self-luminous element, the power consumption may be further reduced as compared with the case of using the colored film.

In the present embodiment, the configuration of the display device using the liquid crystal element as the display element is described.
This will be described with reference to FIG. 42. Further, the configuration of the display device using the EL element as the display element will be described with reference to FIG. 43.

FIG. 42 is a cross-sectional view taken along the alternate long and short dash line UV shown in FIG. 41. The display device 700A shown in FIG. 42 includes a routing wiring unit 711, a pixel unit 702, a source driver circuit unit 704, and an FPC terminal unit 708. Further, the routing wiring unit 711 has a wiring 710. Further, the pixel unit 702 has a transistor 750 and a capacitive element 790. Further, the source driver circuit unit 704 has a transistor 752.

For example, as the transistor 750 and the transistor 752, the transistor (transistor 150, transistor 150A to transistor 150G) described in the first embodiment can be applied.

The transistor used in this embodiment has an oxide semiconductor film that has been purified to a high degree and suppresses the formation of oxygen deficiency. The transistor can lower the current value (off current value) in the off state. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long when the power is on. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, since the transistor used in this embodiment can obtain a relatively high field effect mobility, it can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driving circuit portion can be formed on the same substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, even in the pixel portion, by using a transistor capable of high-speed driving, it is possible to provide a high-quality image.

As the capacitive element 790, the capacitive element 160 shown in the first embodiment can be used.
Since the capacitive element 790 has translucency, the capacitive element 790 can be formed large (in a large area) in one pixel of the pixel unit 702. Therefore, it is possible to obtain a display device having an increased capacity value while increasing the aperture ratio.

Further, in FIG. 42, insulating films 764, 766, and 768 are provided on the transistor 750.

The insulating films 764, 766, and 768 are the insulating films 116 and 768 shown in the first embodiment, respectively.
It can be formed by the same material and manufacturing method as 118 and 122. Further, a flattening film may be provided on the insulating film 122.

Further, the wiring 710 is formed in the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. The wiring 710 is a transistor 750.
It may be a conductive film formed in a process different from that of the source electrode and the drain electrode of 752, for example, a conductive film that functions as a gate electrode. When a material containing a copper element is used as the wiring 710, for example, signal delay due to wiring resistance is small, and display on a large screen is possible.

Further, the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 791, and an FPC 71.
Has 6. The connection electrode 760 is formed in the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is F.
It is electrically connected to the terminal of the PC 716 via the anisotropic conductive film 791.

Further, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Further, as the first substrate 701 and the second substrate 705, the same materials as the substrate 102 shown in the first embodiment can be used.

On the second substrate 705 side, a light-shielding film 738 that functions as a black matrix, a colored film 736 that functions as a color filter, and an insulating film 734 that is in contact with the light-shielding film 738 and the colored film 736 are provided.

Further, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching the insulating film.
It is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. A spherical spacer may be used as the structure 778.

Further, in the present embodiment, the configuration in which the structure 778 is provided on the first substrate 701 side has been exemplified, but the present invention is not limited thereto. For example, the structure 778 may be provided on the second substrate 705 side, or the structure 778 may be provided on both the first substrate 701 and the second substrate 705.

The display device 700A has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and has a function as a counter electrode. The display device 700A has a conductive film 772 and a conductive film 774.
By changing the orientation state of the liquid crystal layer 776 depending on the voltage applied to the light crystal layer 776, the transmission and non-transmission of light are controlled and an image can be displayed. The alignment film 746 is provided on the conductive film 772 and the insulating film 768, and the alignment film 748 is provided in contact with the conductive film 774.

Further, the conductive film 772 is connected to a conductive film that functions as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed on the insulating film 768 and functions as a pixel electrode, that is, one electrode of the display element. The display device 700A is a so-called transmissive color liquid crystal display device in which a backlight, a side light, or the like is provided on the substrate 701 side and is displayed via a liquid crystal element 775 and a colored film 736.

As the conductive film 772 and the conductive film 774, a conductive film having a translucent light in visible light or a conductive film having a reflective property in visible light can be used. As the conductive film having translucency in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. Further, as the conductive film 772 and the conductive film 774, the same materials as the conductive film 123 shown in the first embodiment can be used.

The display device 700A shown in FIGS. 41 and 42 exemplifies a transmissive color liquid crystal display device, but the present invention is not limited thereto. For example, the conductive film 772 may be used as a reflective color liquid crystal display device by using a conductive film having a reflective film in visible light.

Although not shown in FIG. 42, optical members (optical substrates) such as a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used.

In the sealing material 712, substances (water, etc.) that become impurities for display elements and transistors are used.
It has at least a function of preventing or suppressing invasion from the outside. In addition, 7 for the sealing material
12 Another function may be added. For example, the function to strengthen the structure, the function to strengthen the adhesiveness,
The sealing material 712 may have a function of enhancing impact resistance and the like.

As the sealing material 712, it is preferable to use a material that does not dissolve in the liquid crystal layer even when it comes into contact with the liquid crystal layer before curing. As the sealing material 712, for example, an epoxy resin, an acrylic resin, or the like can be applied. The resin material may be either a thermosetting type or a photocuring type. Further, as the sealing material 712, a resin obtained by mixing an acrylic resin and an epoxy resin may be used. At this time, a UV initiator, a thermosetting agent, a coupling agent, or the like may be mixed. It may also contain a filler.

Further, as the sealing material, the same material as the adhesive layer 781 described later may be used.

As the liquid crystal used for the liquid crystal layer 776, the liquid crystal used for the liquid crystal element 51 shown in the third embodiment can be referred to.

Further, as a driving method of the display device having a liquid crystal element, various driving methods shown in the third embodiment can be applied.

Subsequently, when the display device shown in FIG. 41 includes an EL element instead of the liquid crystal element, the alternate long and short dash line U
Sectional views at −V are shown in FIGS. 43 and 44. Since the description of FIG. 42 can be referred to for the same configuration as that of FIG. 42, a configuration different from that of FIG. 42 will be described below.

The display device 700B shown in FIG. 43 has an EL element 785. The EL element 785 has a conductive film 782, a conductive film 784, and an EL layer 786. The EL layer 786 contains a luminescent organic compound or a luminescent inorganic compound. The conductive film 782 is provided on the insulating film 783 and has a function as a reflective electrode. The insulating film 783 has a function as a flattening film. Further, the EL layer 786 and the conductive film 784 are provided on the conductive film 782 in this order. As the conductive film 784,
A conductive film having a translucent property in visible light can be used. The display device 700B can display an image by putting the EL layer 786 into a light emitting state or a non-light emitting state by the voltage applied to the conductive film 782 and the conductive film 784.

The substrate 701 and the substrate 705 are bonded by an adhesive layer 781. Adhesive layer 78
As 1, various curable resins such as a photocurable resin such as an ultraviolet curable resin, a reaction curable resin, a heat curable resin, and an anaerobic resin can be used. Examples of these resins include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin and the like. In particular, a material having low moisture permeability such as an epoxy resin is preferable. Further, a two-component mixed type resin may be used. Further, an adhesive sheet or the like may be used.

In FIG. 43, the connecting electrode 760 is formed in the same process as the conductive film functioning as the first gate electrode of the transistors 750 and 752, the conductive film formed in the same process as the source electrode and the drain electrode, and the conductive film formed in the same process. An example of being composed of a laminated film of a conductive film 782 is shown. In the FPC terminal portion 708, various insulating films have openings so that the conductive films constituting the connection electrode 760 are electrically connected to each other.

Further, in FIG. 43, the pair of electrodes constituting the capacitive element 790 are transistors 750 and 75.
A conductive film formed in the same process as the conductive film that functions as the first gate electrode of 2, and a second.
An example is shown in which the film is formed in the same process as the oxide semiconductor film that functions as the gate electrode of the above.

Further, the transistor 750 has a gate electrode above the channel region. Therefore,
Since the conductive film 782 is provided at a position where it overlaps with the transistor 750, the aperture ratio of the pixels of the pixel unit 702 can be improved.

Although FIG. 43 is a top-emission type display device in which the light emitted by the EL layer 786 is emitted to the substrate 705 side, the display device according to one aspect of the present invention may be a bottom-emission type display device. In the display device 700C shown in FIG. 44, the light emitted by the EL layer 786 is emitted toward the substrate 701. In the case of the bottom emission type, the colored film 736 and the light-shielding film 738 are provided below the EL layer 786, for example, on the insulating film 768.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 6)
In the present embodiment, the touch panel that can be used in the display device of one aspect of the present invention will be described with reference to FIGS. 45 to 50. In this embodiment, a light emitting device, specifically EL.
An example is a touch panel using an element.

[Touch panel configuration example]
45 (A) and 45 (B) are perspective views of the touch panel 505. For clarification, typical components are shown. FIG. 46 (A) is a cross-sectional view between the alternate long and short dash line MN shown in FIG. 45 (A).

As shown in FIGS. 45A and 45B, the touch panel 505 includes a display unit 501, a scanning line drive circuit 303g (1), a touch sensor 595, and the like. In addition, touch panel 505
Has a substrate 510, a substrate 511, and a substrate 590.

The touch panel 505 has a plurality of pixels and a plurality of wirings 311. Multiple wiring 311
Can supply a signal to the pixels. The plurality of wirings 311 are routed to the outer peripheral portion of the substrate 510, and a part thereof constitutes the terminal 319. Terminal 319 is FPC509 (1)
Electrically connect with.

The touch panel 505 has a touch sensor 595 and a plurality of wirings 598. The plurality of wires 598 are electrically connected to the touch sensor 595. Multiple wirings 598 are boards 590
It is routed around the outer circumference of the terminal, and a part of it constitutes a terminal. And the terminal is FPC509 (
It is electrically connected to 2). In FIG. 45B, for the sake of clarity, the electrodes, wiring, and the like of the touch sensor 595 provided on the back surface side (the surface side facing the substrate 510) of the substrate 590 are shown by solid lines.

For example, a capacitive touch sensor can be applied to the touch sensor 595. As the capacitance method, there are a surface type capacitance method, a projection type capacitance method and the like. Here, a case where a projection type capacitance type touch sensor is applied is shown.

The projection type capacitance method includes a self-capacitance method and a mutual capacitance method mainly due to the difference in the drive method. It is preferable to use the mutual capacitance method because simultaneous multipoint detection is possible.

In addition, various sensors capable of detecting the proximity or contact of a detection target such as a finger can be applied to the touch sensor 595.

The projection type capacitance type touch sensor 595 has an electrode 591 and an electrode 592. The electrode 591 is electrically connected to any one of the plurality of wires 598, and the electrode 592 is connected to the plurality of wires 598.
Electrically connect to any of the others.

As shown in FIGS. 45A and 45B, the electrode 592 has a shape in which a plurality of quadrilaterals repeatedly arranged in one direction are connected at a corner.

The electrode 591 is a quadrilateral and is repeatedly arranged in a direction intersecting the extending direction of the electrode 592. The plurality of electrodes 591 do not necessarily have to be arranged in a direction orthogonal to one electrode 592, and may be arranged so as to form an angle of less than 90 degrees.

The wiring 594 is provided so as to intersect with the electrode 592. The wiring 594 electrically connects two electrodes 591 sandwiching the electrode 592. At this time, a shape in which the area of the intersection between the electrode 592 and the wiring 594 is as small as possible is preferable. As a result, the area of the region where the electrodes are not provided can be reduced, and the unevenness of the transmittance can be reduced. As a result, it is possible to reduce the uneven brightness of the light transmitted through the touch sensor 595.

The shapes of the electrodes 591 and 592 are not limited to this, and various shapes can be taken. For example, a plurality of electrodes 591 are arranged so as not to form a gap as much as possible, and the electrodes 5 are interposed via an insulating film.
A plurality of 92 may be provided at intervals so as to form a region that does not overlap with the electrode 591. At this time, it is preferable to provide a dummy electrode electrically isolated from the two adjacent electrodes 592 because the area of the region having different transmittance can be reduced.

A more specific configuration example of the touch sensor 595 will be described later.

As shown in FIG. 46 (A), the touch panel 505 has a substrate 510, an adhesive layer 503, an insulating film 504, a substrate 511, an adhesive layer 513, and an insulating film 515. Further, the substrate 510 and the substrate 511 are bonded by an adhesive layer 360.

In the adhesive layer 597, the substrate 590 is attached to the substrate 511 so that the touch sensor 595 overlaps the display unit 501. The adhesive layer 597 has translucency.

The electrodes 591 and 592 are formed by using a conductive material having translucency. As the translucent conductive material, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide to which gallium is added can be used. A membrane containing graphene can also be used. The graphene-containing film can be formed, for example, by reducing a film containing graphene oxide formed in the form of a film. Examples of the method of reduction include a method of applying heat.

Further, it is desirable that the resistance value of the conductive film such as the electrode 591, the electrode 592, and the wiring 594, that is, the material used for the wiring and the electrode constituting the touch panel is low. As an example, ITO, indium zinc oxide, ZnO, silver, copper, aluminum, carbon nanotubes, graphene and the like may be used. In addition, metal nanowires constructed with a large number of conductors that are very thin (eg, a few nanometers in diameter) may be used. Since the transmittance is high, metal nanowires, carbon nanotubes, graphene, or the like may be used for the electrodes used for the display element, for example, the pixel electrodes and the common electrodes.

After forming a film of a translucent conductive material on the substrate 590 by a sputtering method, unnecessary parts are removed by various patterning techniques such as a photolithography method, and the electrode 59
1 and the electrode 592 can be formed.

The electrodes 591 and 592 are covered with an insulating film 593. Further, an opening reaching the electrode 591 is provided in the insulating film 593, and the wiring 594 electrically connects the adjacent electrodes 591.
Since the translucent conductive material can increase the aperture ratio of the touch panel, it can be suitably used for the wiring 594. Further, the material having higher conductivity than the electrode 591 and the electrode 592 is
Since the electric resistance can be reduced, it can be suitably used for the wiring 594.

The touch sensor 595 can be protected by providing an insulating film 593 and an insulating film covering the wiring 594.

Further, the connection layer 599 electrically connects the wiring 598 and the FPC 509 (2).

The display unit 501 has a plurality of pixels 302 arranged in a matrix.

The pixel 302 has a plurality of sub-pixels. Each sub-pixel has a light emitting element and a pixel circuit.

The pixel circuit can supply electric power to drive the light emitting element. The pixel circuit is electrically connected to a wiring capable of supplying a selection signal. Further, the pixel circuit is electrically connected to a wiring capable of supplying an image signal.

The scanning line drive circuit 303g (1) can supply the selection signal to the pixel 302.

The image signal line drive circuit 303s (1) can supply an image signal to the pixel 302.

As shown in FIG. 46 (A), the touch panel 505 has a substrate 510, an adhesive layer 503, an insulating film 504, a substrate 511, an adhesive layer 513, and an insulating film 515. Further, the substrate 510 and the substrate 511 are bonded by an adhesive layer 360.

The substrate 510 and the insulating film 504 are bonded to each other by an adhesive layer 503. Further, the substrate 511 and the insulating film 515 are bonded to each other by the adhesive layer 513.

The substrate 510 and the substrate 511 are preferably flexible.

The first embodiment can be referred to for the materials that can be used for the substrate and the insulating film. Further, for the material that can be used for the adhesive layer, the fifth embodiment can be referred to.

Further, the adhesive layer includes a photocurable resin such as an ultraviolet curable resin, a reaction curable resin, and a thermosetting resin.
Various curable resins such as anaerobic resins can be used. Examples of these resins include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, and imide resin.
Examples thereof include PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin and the like. In particular, a material having low moisture permeability such as an epoxy resin is preferable. Further, a two-component mixed type resin may be used. Further, an adhesive sheet or the like may be used.

The pixel 302 has a sub-pixel 302R, a sub-pixel 302G, and a sub-pixel 302B (FIG. 4).
In 6, only the sub-pixel 302R is shown). Further, the sub-pixel 302R is a light emitting module 38.
It has 0R, the sub-pixel 302G has a light emitting module 380G, and the sub pixel 302B has a light emitting module 380B.

For example, the sub-pixel 302R has a light emitting element 350R and a pixel circuit. The pixel circuit includes a transistor 302t capable of supplying power to the light emitting element 350R. Further, the light emitting module 380R has a light emitting element 350R and an optical element (for example, a colored film 367R that transmits red light).

The light emitting element 350R has a lower electrode 351R, a semi-transmissive electrode 351Ra, an EL layer 353, and an upper electrode 352 laminated in this order (see FIG. 46 (B)). Note that FIG. 46 (B) is an enlarged view of the region 555 in FIG. 46 (A).

The EL layer 353 has a first EL layer 353a, an intermediate layer 354, and a second EL layer 353b laminated in this order.

A microcavity structure can be arranged in the light emitting element 350R. Specifically, a film that reflects visible light (for example, FIG. 4) is arranged so that specific light can be efficiently extracted.
6 (B) lower electrode 351R) and semi-reflective / semi-transmissive film (for example, FIG. 46 (B)).
The EL layer may be arranged between the upper electrodes 352) in the above. The semi-transmissive electrode 351Ra has a function of an optical adjustment layer, and by making the optical adjustment layer a different film thickness in each sub-pixel of the sub-pixels 302R, 302G, and 302B, light of a specific wavelength is efficiently produced for each sub-pixel. It can be taken out well. The light emitting element 350R may be configured not to be provided with the semitransmissive electrode 351Ra.

For example, the light emitting module 380R has an adhesive layer 360 in contact with the light emitting element 350R and the colored film 367R (see FIG. 46 (A)).

The colored film 367R is located at a position overlapping with the light emitting element 350R. As a result, the light emitting element 350
A part of the light emitted by R passes through the adhesive layer 360 and the colored film 367R and is emitted to the outside of the light emitting module 380R as shown by the arrow in the figure.

The touch panel 505 has a light-shielding film 367BM. The light-shielding film 367BM is provided so as to surround the colored film (for example, the colored film 367R).

The touch panel 505 has an antireflection layer 367p at a position overlapping the display unit 301. As the antireflection layer 367p, for example, a circular polarizing plate can be used.

The touch panel 505 has an insulating film 321. The insulating film 321 is a transistor 302t.
Etc. are covered. The insulating film 321 can be used as a layer for flattening the unevenness caused by the pixel circuit or the image pickup pixel circuit. Further, an insulating film having a layer capable of suppressing diffusion of impurities to the transistor 302t or the like can be applied to the insulating film 321. In the present embodiment, the insulating film 321 is an example of laminating two layers, but the insulating film 321 may be a single layer or a laminated three or more layers.

The touch panel 505 has a partition wall 328 that overlaps the end of the lower electrode 351R. note that,
A spacer for controlling the distance between the substrate 510 and the substrate 511 may be provided on the partition wall 328.

The scanning line drive circuit 303g (1) includes a transistor 303t and a capacitance 303c. The drive circuit can be formed on the same substrate in the same process as the pixel circuit.

The transistor (for example, transistor 302t, transistor 303t) included in the touch panel 505 is the transistor (transistor 1) described in the first embodiment.
50, Transistor 150A to Transistor 150G) can be applied.

[Touch sensor configuration example]
Hereinafter, a more specific configuration example of the touch sensor 595 will be described with reference to the drawings.

FIG. 47 (A) shows a schematic top view of the touch sensor 595. The touch sensor 595 has a plurality of electrodes 531 and a plurality of electrodes 532, a plurality of wirings 541, and a plurality of wirings 54 on the substrate 590.
Has 2. Further, the substrate 590 is provided with an FPC 550 that is electrically connected to each of the plurality of wirings 541 and the plurality of wirings 542.

FIG. 47 (B) shows an enlarged view of the region surrounded by the alternate long and short dash line in FIG. 47 (A). Electrode 531
Has a shape in which a plurality of diamond-shaped electrode patterns are continuous in the lateral direction of the paper surface. The diamond-shaped electrode patterns arranged in a row are electrically connected to each other. Similarly, the electrode 532 is also the same.
A plurality of rhombic electrode patterns have a shape in which they are connected in the vertical direction of the paper surface, and the rhombic electrode patterns arranged in a row are electrically connected to each other. Further, a part of the electrode 531 and the electrode 532 overlap each other and intersect with each other. At this intersection, an insulator is sandwiched so that the electrode 531 and the electrode 532 are not electrically short-circuited.

Further, as shown in FIG. 47 (C), the electrode 532 may be composed of a plurality of electrodes 533 having a rhombic shape and a bridge electrode 534. The island-shaped electrodes 533 are arranged side by side in the vertical direction of the paper surface, and two adjacent electrodes 533 are electrically connected by a bridge electrode 534. With such a configuration, the electrode 533 and the electrode 531 can be formed at the same time by processing the same conductive film. Therefore, it is possible to suppress the variation in these film thicknesses, and it is possible to suppress the variation in the resistance value and the light transmittance of each electrode depending on the location. Although the electrode 532 has a bridge electrode 534 here, the electrode 53
1 may have such a configuration.

Further, as shown in FIG. 47 (D), the inside of the diamond-shaped electrode patterns of the electrodes 531 and 532 shown in FIG. 47 (B) may be hollowed out so that only the contour portion is left. At this time, if the widths of the electrodes 531 and 532 are so narrow that they cannot be visually recognized by the user,
As will be described later, a light-shielding material such as a metal or an alloy may be used for the electrode 531 and the electrode 532. Further, the electrode 531 or the electrode 532 shown in FIG. 47 (D) is the bridge electrode 534.
It may be configured to have.

One electrode 531 is electrically connected to one wiring 541. Also one electrode 53
2 is electrically connected to one wiring 542.

Here, when the touch sensor 595 is superposed on the display surface of the display panel to form a touch panel, it is preferable to use a translucent conductive material for the electrodes 531 and 532. Further, when a translucent conductive material is used for the electrode 531 and the electrode 532, and the light from the display panel is taken out through the electrode 531 or the electrode 532, the same conductivity is used between the electrode 531 and the electrode 532. It is preferable to arrange the conductive film containing the sex material as a dummy pattern.
As described above, by filling a part of the gap between the electrode 531 and the electrode 532 with a dummy pattern, the variation in the light transmittance can be reduced. As a result, it is possible to reduce the uneven brightness of the light transmitted through the touch sensor 595.

As the translucent conductive material, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide to which gallium is added can be used. A membrane containing graphene can also be used. The graphene-containing film can be formed, for example, by reducing a film containing graphene oxide formed in the form of a film. Examples of the method of reduction include a method of applying heat.

Alternatively, a metal or alloy thin enough to have translucency can be used. For example, metals such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, and alloys containing the metals can be used. Alternatively, a nitride of the metal or alloy (for example, titanium nitride) may be used. Further, among the conductive films containing the above-mentioned materials, a laminated film in which two or more are laminated may be used.

Further, as the electrode 531 and the electrode 532, a conductive film processed to be thin so as not to be visually recognized by the user may be used. For example, by processing such a conductive film into a lattice shape (mesh shape), high conductivity and high visibility of the display device can be obtained. At this time, the conductive film is 30
nm or more and 100 μm or less, preferably 50 nm or more and 50 μm or less, more preferably 50 n
It is preferable to have a portion having a width of m or more and 20 μm or less. In particular, a conductive film having a pattern width of 10 μm or less is preferable because it is extremely difficult for the user to visually recognize it.

As an example, FIGS. 48 (A) to 48 (D) show a part of the electrode 531 or the electrode 532 (FIG. 47).
(B) shows an enlarged schematic diagram of the part surrounded by the alternate long and short dash line circle). FIG. 48 (A
) Shows an example in the case where the lattice-shaped conductive film 561 is used. At this time, by arranging the conductive film 561 so as not to overlap with the display element of the display device, it is preferable because the light from the display device is not blocked. In that case, the orientation of the grid should be the same as the arrangement of the display elements.
Further, it is preferable that the period of the grid is an integral multiple of the period of the arrangement of the display elements.

Further, FIG. 48B shows an example of a lattice-shaped conductive film 562 processed so as to form a triangular opening. With such a configuration, it is possible to lower the resistance as compared with the case shown in FIG. 48 (A).

Further, as shown in FIG. 48 (C), the conductive film 56 having a pattern shape having no periodicity.
It may be 3. With such a configuration, it is possible to suppress the occurrence of moire when it is overlapped with the display unit of the display device. Here, moire refers to an interference pattern caused by diffraction or interference when external light or the like is transmitted or reflected by a conductive film or the like provided at equal intervals with a fine width. say.

Further, conductive nanowires may be used for the electrode 531 and the electrode 532. FIG. 48 (D
) Shows an example when nanowire 564 is used. By dispersing the adjacent nanowires 564 so as to be in contact with each other at an appropriate density, a two-dimensional network is formed, and the film can function as a conductive film having extremely high translucency. For example, the average diameter is 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 5 n.
Nanowires of m or more and 25 nm or less can be used. As nanowire 564, A
Metal nanowires such as g nanowires, Cu nanowires and Al nanowires, carbon nanotubes and the like can be used. For example, in the case of Ag nanowires, the light transmittance is 8.
It is possible to realize 9% or more and a sheet resistance value of 40 or more and 100 or less Ω / □.

FIG. 47 (A) and the like show an example in which a plurality of rhombuses are connected in one direction as the upper surface shape of the electrode 531 and the electrode 532, but the shape of the electrode 531 and the electrode 532 is not limited to this. It can have various upper surface shapes such as a band shape (rectangular shape), a band shape having a curve, and a zigzag shape. Further, although it is shown above that the electrodes 531 and 532 are arranged so as to be orthogonal to each other, they do not necessarily have to be arranged so as to be orthogonal to each other, and the angle formed by the two electrodes is less than 90 degrees. There may be.

49 (A) to 49 (C) show an example in which an electrode 536 and an electrode 537 having a fine linear upper surface shape are used instead of the electrodes 531 and 532. FIG. 49A shows an example in which the linear electrodes 536 and 537 are arranged in a grid pattern, respectively.

Further, FIG. 49B shows an example in which the electrode 536 and the electrode 537 have a zigzag-shaped upper surface shape. At this time, as shown in FIG. 49 (B), the electrodes 536 and 537 are arranged so as to be relatively offset from each other instead of overlapping the center positions of the linear portions.
It is preferable because the length of the portion facing in parallel with the electrode can be increased, the mutual capacitance between the electrodes is increased, and the detection sensitivity is improved. Alternatively, as shown in FIG. 49 (C), if the upper surface shape of the electrode 536 and the electrode 537 is such that a part of the zigzag straight line portion protrudes, even if the center positions of the straight line portions are overlapped and arranged. Since the length of the facing portions can be increased, the mutual capacitance between the electrodes can be increased.

Enlarged views of the area surrounded by the alternate long and short dash line in FIG. 49 (B) are shown in FIGS. 50 (A), (B) and (C), and FIG.
Enlarged views of the region surrounded by the alternate long and short dash line in 9 (C) are shown in FIGS. 50 (D), (E), and (F), respectively. Further, each figure shows an electrode 536, an electrode 537, and an intersection 538 at which they intersect. As shown in FIGS. 50 (B) and 50 (E), the linear portions of the electrodes 536 and 537 in FIGS. 50 (A) and 50 (D) may have a meandering shape so as to have corners. FIG. 50
As shown in (C) and (F), the shape may meander so that the curve is continuous.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 7)
In this embodiment, a configuration example of a light emitting element that can be used for the EL element 785 shown in the fifth embodiment and the light emitting element 350R shown in the sixth embodiment will be described. The EL layer 220 shown in this embodiment is the EL layer 786 and the EL layer 3 shown in other embodiments.
Corresponds to 53.

<Structure of light emitting element>
The light emitting element 230 shown in FIG. 51 (A) has an E between a pair of electrodes (electrode 218, electrode 222).
It has a structure in which the L layer 220 is sandwiched. In the following description of the present embodiment, as an example, the electrode 218 is used as an anode and the electrode 222 is used as a cathode.

Further, the EL layer 220 may be formed to include at least a light emitting layer, and may have a laminated structure including a functional layer other than the light emitting layer. Functional layers other than the light emitting layer include substances with high hole injectability, substances with high hole transport, substances with high electron transport, substances with high electron inject, and bipolar (electron and hole transport). A layer containing a substance (high substance) or the like can be used. Specifically, functional layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be appropriately combined and used.

In the light emitting element 230 shown in FIG. 51 (A), a current flows due to a potential difference applied between the electrode 218 and the electrode 222, and holes and electrons are recombined in the EL layer 220 to emit light. That is, the structure is such that a light emitting region is formed on the EL layer 220.

In the present invention, the light emitted from the light emitting element 230 is taken out from the electrode 218 or the electrode 222 side. Therefore, either the electrode 218 or the electrode 222 is made of a translucent substance.

A plurality of EL layers 220 may be laminated between the electrodes 218 and the electrodes 222 as in the light emitting element 231 shown in FIG. 51 (B). When it has an n-layer (n is a natural number of 2 or more) laminated structure, the m-th (m is a natural number of 1 or more and smaller than n) EL layer 220 and (m).
+1) It is preferable to provide a charge generation layer 220a between the EL layer 220 and the second EL layer 220. The configuration excluding the electrode 218 and the electrode 222 corresponds to the EL layer 117 of the above embodiment.

The charge generation layer 220a can be formed by using a composite material of an organic compound and a metal oxide. Examples of the metal oxide include vanadium oxide, molybdenum oxide, tungsten oxide and the like. As the organic compound, various compounds such as an aromatic amine compound, a carbazole derivative, an aromatic hydrocarbon, an oligomer having them as a basic skeleton, a dendrimer, a polymer and the like can be used. As the organic compound, it is preferable to use a hole-transporting organic compound having a hole mobility of 10 to ⁶ cm ² / Vs or more. However, any substance other than these may be used as long as it is a substance having a higher hole transport property than electrons. Since these materials used for the charge generation layer 220a are excellent in carrier injection property and carrier transport property, it is possible to realize low current drive and low voltage drive of the light emitting element 230. In addition to the composite material, the metal oxide, the organic compound and the alkali metal, the alkaline earth metal, the alkali metal compound, the alkaline earth metal compound and the like can be used for the charge generation layer 220a.

The charge generation layer 220a may be formed by combining a composite material of an organic compound and a metal oxide and another material. For example, a layer containing a composite material of an organic compound and a metal oxide may be formed in combination with a layer containing one compound selected from electron-donating substances and a compound having high electron transport property. Further, a layer containing a composite material of an organic compound and a metal oxide may be formed in combination with a transparent conductive film.

The light emitting element 231 having such a configuration is unlikely to cause energy transfer between adjacent EL layers 220, and can easily be a light emitting element having both high luminous efficiency and long life. It is also easy to obtain phosphorescence emission from one light emitting layer and fluorescence emission from the other.

The charge generation layer 220a has a function of injecting holes into one of the EL layers 220 formed in contact with the charge generation layer 220a when a voltage is applied to the electrodes 218 and 222. It has a function of injecting electrons into the other EL layer 220.

The light emitting element 231 shown in FIG. 51 (B) can obtain various light emitting colors by changing the type of the light emitting material used for the EL layer 220. Further, by using a plurality of light emitting materials having different light emitting colors as the light emitting material, it is possible to obtain light emission having a broad spectrum or white light emission.

When white light emission is obtained by using the light emitting element 231 shown in FIG. 51 (B), the combination of the plurality of EL layers may be a configuration that includes red, blue, and green light and emits white light, for example. , An EL layer containing a blue fluorescent material as a light emitting material and an EL layer containing a green and red phosphorescent material as a light emitting material can be mentioned. Further, the configuration may include an EL layer exhibiting red emission, an EL layer exhibiting green emission, and an EL layer exhibiting blue emission. Alternatively, white light emission can be obtained even with a configuration having an EL layer that emits light having a complementary color relationship. EL
In a laminated element in which two layers are laminated, when the emission colors from these EL layers have a complementary color relationship, the complementary color relationship includes a combination of blue and yellow, or a combination of blue-green and red.

In the above-mentioned configuration of the laminated element, by arranging the charge generating layer between the laminated light emitting layers, high-luminance light emission can be obtained while keeping the current density low, and a long-life element can be realized. can.

Quantum dots can also be used as the light emitting material. Quantum dots are semiconductor nanocrystals with a size of several nm and are composed of about 1 × 10 ³ to 1 × 10 ⁶ atoms. Since quantum dots shift energy depending on their size, even quantum dots composed of the same substance have different emission wavelengths depending on their size, and the emission wavelength can be easily adjusted by changing the size of the quantum dots used. be able to.

Further, since the peak width of the emission spectrum of the quantum dot is narrow, it is possible to obtain emission with good color purity. Further, it is said that the theoretical internal quantum efficiency of quantum dots is almost 100%, which is much higher than 25% of organic compounds exhibiting fluorescence emission, and is equivalent to that of organic compounds exhibiting phosphorescence emission. From this, it is possible to obtain a light emitting device having high luminous efficiency by using quantum dots as a light emitting material. Moreover, since the quantum dots, which are inorganic compounds, are excellent in their intrinsic stability, it is possible to obtain a light emitting device that is preferable from the viewpoint of life.

Materials that make up the quantum dots include elements of Group 14 of the Periodic Table, elements of Group 15 of the Periodic Table, elements of Group 16 of the Periodic Table, compounds consisting of multiple Group 14 elements of the Periodic Table, and Group 4 to Periodic Table of the Periodic Table. 1st
Compounds of elements belonging to Group 4 and elements of Group 16 of the Periodic Table, compounds of Group 2 of the Periodic Table and elements of Group 16 of the Periodic Table, compounds of Group 13 of the Periodic Table and elements of Group 15 of the Periodic Table, A compound of the 13th group element of the periodic table and the 17th group element of the periodic table, a compound of the 14th group element of the periodic table and the 15th group element of the periodic table, and a compound of the 11th group element of the periodic table and the 17th group element of the periodic table. , Iron oxides, titanium oxides,
Calcogenide spinels, various semiconductor clusters, etc. can be mentioned.

Specifically, cadmium selenium, cadmium sulfide, cadmium tellurate, zinc selenium, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenate, mercury tellurate, indium arsenide, indium phosphate, gallium arsenide. , Gallium phosphate, indium nitride, gallium nitride, antimonized indium, antimonized gallium, aluminum phosphate, aluminum arsenide, antimonized aluminum, lead selenium, lead tellurate, lead sulfide, indium selenate, indium tellurate, sulfide Indium, gallium selenium, arsenic sulfide, arsenide selenium, arsenic tellurium, antimony sulfide, antimony selenium, antimony telluride, bismuth sulfide, bismuth serene, bismus tellurium, silicon, silicon carbide, germanium, tin, selenium, Tellurium, boron, carbon, phosphorus, boron nitride, boron phosphate, boron arsenide,
Aluminum nitride, aluminum sulfide, barium sulfide, barium selenium, barium selenium, calcium sulfide, calcium selenium, calcium telluride, berylium sulfide, beryllium selenium, beryllium telluride, magnesium sulfide, magnesium selenium, germanium selenium, selenium Germanium calcium, germanium telluride, tin sulfide, tin selenate,
Tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenium, nickel oxide, cobalt oxide, cobalt sulfide, triiron tetroxide, iron sulfide, manganese oxide, sulfide Molybdenum, vanadium oxide, tungsten oxide, tantalum oxide, titanium oxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, selenium, zinc and cadmium compounds, indium, arsenic and phosphorus compounds, cadmium and selenium Sulfur compounds, cadmium, selenium and tellurium compounds, indium, gallium and arsenic compounds, indium, gallium and selenium compounds, indium, selenium and sulfur compounds, copper, indium and sulfur compounds and combinations thereof. It can, but is not limited to these. Further, so-called alloy-type quantum dots whose composition is represented by an arbitrary ratio may be used. For example, alloy-type quantum dots of cadmium, selenium, and sulfur can change the emission wavelength by changing the content ratio of the elements, and are therefore one of the effective means for obtaining blue emission.

The structure of the quantum dots includes a core type, a core-shell type, a core-multishell type, etc., and any of them may be used, but the shell is made of another inorganic material that covers the core and has a wider bandgap. By forming it, the influence of defects and dangling bonds existing on the surface of the nanocrystal can be reduced. As a result, it is preferable to use core-shell type or core-multi-shell type quantum dots because the quantum efficiency of light emission is greatly improved. Examples of shell materials include zinc sulfide and zinc oxide.

In addition, since quantum dots have a high proportion of surface atoms, they are highly reactive and are prone to aggregation. Therefore, it is preferable that a protective agent is attached or a protecting group is provided on the surface of the quantum dot. Due to the attachment of the protective agent or the provision of a protecting group,
It can prevent aggregation and increase the solubility in a solvent. It is also possible to reduce reactivity and improve electrical stability. Examples of the protective agent (or protective group) include polyoxyethylene alkyl ethers such as polyoxyethylene lauryl ether, polyoxyethylene stearyl ether, and polyoxyethylene oleyl ether, tripropylphosphine, tributylphosphine, trihexylphosphine, and tri. Trialkylphosphins such as octylphosphine, polyoxyethylene alkylphenyl ethers such as polyoxyethylene n-octylphenyl ether, polyoxyethylene n-nonylphenyl ether, tri (n-hexyl) amine, tri (n-octyl) Amine, tri (n-decyl)
Tertiary amines such as amines, organic phosphorus compounds such as tripropylphosphine oxide, tributylphosphine oxide, trihexylphosphine oxide, trioctylphosphine oxide, tridecylphosphine oxide, polyethylene such as polyethylene glycol dilaurate and polyethylene glycol distearate. Glycoldiesters, and organic nitrogen compounds such as nitrogen-containing aromatic compounds such as pyridine, lutidine, colidin, and quinoline.
Includes aminoalkanes such as hexylamine, octylamine, decylamine, dodecylamine, tetradecylamine, hexadecylamine, octadecylamine, dialkyl sulfides such as dibutyl sulfide, dialkyl sulfoxides such as dimethyl sulfoxide and dibutyl sulfoxide, and thiophene. Examples thereof include organic sulfur compounds such as sulfur aromatic compounds, higher fatty acids such as palmitic acid, stearic acid and oleic acid, alcohols, sorbitan fatty acid esters, fatty acid-modified polyesters, tertiary amine-modified polyurethanes and polyethyleneimines. ..

Since the band gap of quantum dots increases as the size decreases, the size of the quantum dots is appropriately adjusted so that light having a desired wavelength can be obtained. As the crystal size becomes smaller, the emission of quantum dots shifts to the blue side, that is, to the high energy side. Therefore, by changing the size of the quantum dots, the wavelengths of the spectra in the ultraviolet region, visible region, and infrared region are used. Its emission wavelength can be adjusted over the region. The size (diameter) of the quantum dots is 0.
Those in the range of 5 nm to 20 nm, preferably 1 nm to 10 nm are usually often used. The narrower the size distribution of the quantum dots, the narrower the emission spectrum of the quantum dots, and the better the color purity of the quantum dots can be obtained. In addition, the shape of the quantum dot is not particularly limited, and it is spherical.
It may be rod-shaped, disk-shaped, or any other shape. Since the quantum rod, which is a rod-shaped quantum dot, exhibits light having directivity polarized in the c-axis direction, it is possible to obtain a light emitting element having better external quantum efficiency by using the quantum rod as a light emitting material. ..

By the way, in the EL element, in many cases, the luminous efficiency is improved by dispersing the light emitting material in the host material, but the host material needs to be a substance having singlet excitation energy or triplet excitation energy equal to or higher than that of the light emitting material. be. In particular, when a blue phosphorescent material is used, it is extremely difficult to develop a host material that has more triplet excitation energy and is excellent in terms of lifetime. Here, since the quantum dots can maintain the luminous efficiency even if the light emitting layer is formed only by the quantum dots without using the host material, a preferable light emitting element can be obtained from the viewpoint of the life in this respect as well. When the light emitting layer is formed only by quantum dots, it is preferable that the quantum dots have a core-shell structure (including a core-multishell structure).

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 8)
In the present embodiment, the display module and the electronic device having the semiconductor device of one aspect of the present invention will be described with reference to FIGS. 52 and 53.

The display module 8000 shown in FIG. 52 has a touch panel 8004 connected to the FPC8003, a display panel 8006 connected to the FPC8005, a backlight 8007, a frame 8009, and a printed circuit board 801 between the upper cover 8001 and the lower cover 8002.
0, has battery 8011.

The display device of one aspect of the present invention can be used, for example, in the display panel 8006.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006.

The touch panel 8004 can be used by superimposing a resistance film type or capacitance type touch panel on the display panel 8006. It is also possible to equip the facing substrate (sealing substrate) of the display panel 8006 with a touch panel function. In addition, the display panel 8
It is also possible to provide an optical sensor in each pixel of 006 to form an optical touch panel.

The backlight 8007 has a light source 8008. Note that FIG. 52 illustrates the configuration in which the light source 8008 is arranged on the backlight 8007, but the present invention is not limited to this. For example, a light source 8008 may be arranged at the end of the backlight 8007, and a light diffusing plate may be used. When a self-luminous light emitting element such as an organic EL element is used, or when a reflective panel or the like is used, the backlight 8007 may not be provided.

In addition to the protective function of the display panel 8006, the frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. Further, the frame 8009 may have a function as a heat sink.

The printed circuit board 8010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying electric power to the power supply circuit may be an external commercial power source or a power source provided by a separately provided battery 8011. The battery 8011 can be omitted when a commercial power source is used.

Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.

53 (A) to 53 (G) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, and an operation key 50.
05 (including power switch or operation switch), connection terminal 5006, sensor 5007 (including power switch)
Force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, (Including the function of measuring vibration, odor or infrared rays), microphone 5008, etc. can be provided.

FIG. 53 (A) is a mobile computer, and in addition to the above-mentioned one, switch 5009.
, Infrared port 5010, etc. can be provided. FIG. 53B is a portable image reproduction device (for example, a DVD reproduction device) provided with a recording medium, and may have a second display unit 5002, a recording medium reading unit 5011, and the like in addition to those described above. can. FIG. 53 (C) is a goggle type display, in addition to the above-mentioned one, the second display unit 5002 and the support unit 5012.
, Earphones 5013, etc. can be provided. FIG. 53 (D) is a portable gaming machine, which may have a recording medium reading unit 5011 and the like in addition to those described above. FIG. 53 (E) is a digital camera with a television image receiving function, which may have an antenna 5014, a shutter button 5015, an image receiving unit 5016, and the like, in addition to those described above. FIG. 53 (F) is a portable gaming machine, and in addition to those described above, the second display unit 5002 and the recording medium reading unit 5011.
, Etc. can be possessed. FIG. 53 (G) is a portable television receiver, and in addition to the above-mentioned one, a charger 5017 capable of transmitting and receiving signals and the like can be provided.

The electronic devices shown in FIGS. 53 (A) to 53 (G) can have various functions.
For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing by various software (programs), Wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, program or data recorded on recording medium to be read and displayed It can have a function of displaying on a unit, and the like. Further, in an electronic device having a plurality of display units, a function of mainly displaying image information on one display unit and mainly displaying character information on another display unit, or consideration of parallax on a plurality of display units. It is possible to have a function of displaying a three-dimensional image by displaying the image. Further, in an electronic device having an image receiving unit, a function of shooting a still image, a function of shooting a moving image, a function of automatically or manually correcting the shot image, and a function of recording the shot image as a recording medium (external or built in the camera). It can have a function of saving, a function of displaying a captured image on a display unit, and the like. It should be noted that FIGS. 53 (A) to 5
The functions that the electronic device shown in 3 (G) can have are not limited to these, and can have various functions.

FIG. 53 (H) is a smart watch, which has a housing 7302, a display panel 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like.

The display panel 7304 mounted on the housing 7302 that also serves as the bezel portion has a non-rectangular display area. The display panel 7304 may be a rectangular display area. The display panel 7304 can display an icon 7305 representing a time, another icon 7306, and the like.

The smart watch shown in FIG. 53 (H) can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing by various software (programs), Wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, program or data recorded on recording medium to be read and displayed It can have a function of displaying on a unit, and the like.

Further, inside the housing 7302, a speaker, a sensor (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current) ,
It can have a function of measuring voltage, electric power, radiation, flow rate, humidity, inclination, vibration, odor or infrared rays), a microphone and the like. The smart watch can be manufactured by using a light emitting element for the display panel 7304.

The electronic device described in the present embodiment is characterized by having a display unit for displaying some information. The display device shown in any one of the third to fifth embodiments can be applied to the display unit.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

11 Substrate 12 Insulation film 13 Conductive film 14 Insulation film 15 Insulation film 16 Insulation film 17 Insulation film 18 Oxide semiconductor film 18_1 Source / drain region 18_1 Source / drain region 18i Channel region 19a Oxide semiconductor film 19b Oxide semiconductor film 19c Common electrode 21a Conductive plate 21b Conductive plate 21c Conductive plate 27 Insulation film 29 Conductive plate 51 Liquid crystal element 52 Transistor 55 Capacitive element 62 Wiring 70 Pixel 70a Pixel 70b Pixel 70c Pixel 70d Pixel 70e Pixel 70f Pixel 71 Pixel part 74 Scanning line drive circuit 75 Common line 76 Signal line drive circuit 77 Scan line 78 Wiring 79 Signal line 80 Display device 100 Semiconductor device 100A Semiconductor device 100B Semiconductor device 100C Semiconductor device 100D Semiconductor device 100E Semiconductor device 100F Semiconductor device 100G Semiconductor device 102 Substrate 104 Insulation film 106 Gate electrode 107 Oxide Semiconductor film 108 Oxide semiconductor film 108_1 Oxide semiconductor film 108_1 Oxide semiconductor film 108_3 Oxide semiconductor film 108b Oxide semiconductor film 108d Drain region 108f region 108i Channel region 108s Source region 110 Insulation film 110_0 Insulation film 111 Oxide semiconductor film 111_0 Oxide semiconductor film 111a Oxide semiconductor film 111b Oxide semiconductor film 112 Conductive 112_0 Conductive 116 Insulation film 117 EL layer 118 Insulation film 120a Conductive 120b Conductive 120c Conductive 122 Insulation film 123 Conductive 124 Conductive 140 Mask 141a Opening 141b Opening 142 Opening 143 Opening 144 Opening 145 Opening 150 Transistor 150A Transistor 150B Transistor 150C Transistor 150D Transistor 150E Transistor 150F Transistor 150G Transceiver 160 Capacitive element 218 Electrode 220 EL layer 220a Charge generation layer 222 Electrode 230 Emitting element 231 Light emitting element 301 Display unit 302 pixel 302B Sub pixel 302G Sub pixel 302R Sub pixel 302t Transistor 303c Capacity 303g Scanning line drive circuit 303s Image signal line drive circuit 303t Transistor 311 Wiring 319 Terminal 321 Insulation film 328 Partition 350R Light emitting element 351R Lower electrode 351Ra Semi-transmissive electrode 352 Upper electrode 353 EL layer 353a EL layer 35 3b EL layer 354 Intermediate layer 360 Adhesive layer 367BM Light-shielding film 367p Anti-reflection layer 367R Colored film 380B Light emitting module 380G Light emitting module 380R Light emitting module 400a Pixel 400b Pixel 401 Pulse voltage output circuit 402 Current detection circuit 403 Capacity 410 Touch panel 411 Board 412 Board 413 FPC
414 Conductive 419a Conductive 419b Conductive 420a Liquid crystal element 420b Liquid crystal element 421 Electrode 422 Electrode 423 Liquid crystal 424 Insulating film 426 Opening 428a Conductive 428b Conductive 429a Conductive 429b Conductive 431 Colored film 453 Wire 454 Wire 459a Sensor electrode 459b Sensor electrode 461 Wiring 463 Transistor 464 Liquid crystal element 465_1 Block 465_2 Block 467_1 Block 467_1 Block 471 Electrode 471_1 Electrode 471_2 Electrode 472 Electrode 472_1 Electrode 472_4 Electrode 501 Display unit 503 Adhesive layer 504 Insulation film 505 Touch panel 509 FPC
510 Substrate 511 Substrate 513 Adhesive layer 515 Insulation film 531 Electrode 532 Electrode 533 Electrode 534 Bridge electrode 536 Electrode 537 Electrode 538 Crossing 541 Wiring 542 Wiring 550 FPC
555 Area 561 Conductive 562 Conductive 563 Conductive 564 Nanowire 590 Substrate 591 Electrode 592 Electrode 593 Insulation film 594 Wiring 595 Touch sensor 597 Adhesive layer 598 Wiring 599 Connection layer 601 Board 602 Board 604 Insulation film 606 Gate wiring 607 Capacitance wiring 609 Wiring 611b Pixel electrode 612b Pixel electrode 616 Insulation film 618 Insulation film 620a Wiring 620b Drain electrode 622 Insulation film 629 Transistor 630 Capacitive element 641b Opening 650 Transistor 651 Transistor 661 Capacitive element 662 Capacitive element 671 Common electrode 672 Slit 673 Colored film 674 Slit 675 Protrusion 677 Alignment film 678 Alignment film 680 Liquid crystal layer 681 Liquid crystal element 682 Liquid crystal element 700A Display device 700B Display device 700C Display device 701 Board 702 Pixel part 704 Source driver circuit part 705 Board 706 Gate driver circuit part 708 FPC terminal part 710 Wiring 711 Wiring Part 712 Sealing material 716 FPC
734 Insulation film 736 Colored film 738 Light-shielding film 746 Alignment film 748 Alignment film 750 Transistor 752 Transistor 760 Connection electrode 764 Insulation film 766 Insulation film 768 Insulation film 772 Conductive 774 Conductive 775 Liquid crystal element 77 Liquid crystal layer 778 Structure 781 Adhesive layer 782 Conductive 783 Insulation film 784 Conductive 785 EL element 786 EL layer 790 Capacitive element 791 Anisotropic conductive film 4616 Wiring 5000 Housing 5001 Display 5002 Display 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading part 5012 Support part 5013 Earphone 5014 Antenna 5015 Shutter button 5016 Image receiving part 5017 Charger 7302 Housing 7304 Display panel 7305 Icon 7306 Icon 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Clasp 8000 Display module 8001 Top cover 8002 Bottom cover 8003 FPC
8004 touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery

Claims (3)

A semiconductor device having a transistor and a capacitive element,
The transistor is provided with an oxide semiconductor film, a first insulating film above the oxide semiconductor film, and a first insulating film provided above the first insulating film and having a region overlapping with the oxide semiconductor film. It has a metal oxide film and a conductive layer that functions as a source electrode or a drain electrode.
The conductive layer is provided on a second insulating film provided above the first metal oxide film, and the oxide semiconductor film is provided through an opening provided in the second insulating film. Electrically connected to
The second insulating film includes a region in contact with the upper surface and the side surface of the first metal oxide film, a region in contact with the side surface of the first insulating film, and a region in contact with the upper surface of the oxide semiconductor film. Have,
The capacitive element has a second metal oxide film, a first conductive film, and a third insulating film between the second metal oxide film and the first conductive film. ,
The second metal oxide film is a semiconductor device having the same material as the first metal oxide film and having a function as an electrode of a display element . A semiconductor device having a transistor and a capacitive element,
The transistor is provided with an oxide semiconductor film, a first insulating film above the oxide semiconductor film, and a first insulating film provided above the first insulating film and having a region overlapping with the oxide semiconductor film. It has a metal oxide film and a conductive layer that functions as a source electrode or a drain electrode.
The conductive layer is provided on a second insulating film provided above the first metal oxide film, and the oxide semiconductor film is provided through an opening provided in the second insulating film. Electrically connected to
The second insulating film includes a region in contact with the upper surface and the side surface of the first metal oxide film, a region in contact with the side surface of the first insulating film, and a region in contact with the upper surface of the oxide semiconductor film. Have,
The capacitive element has a second metal oxide film, a first conductive film, and a third insulating film between the second metal oxide film and the first conductive film. ,
The second metal oxide film has the same material as the first metal oxide film and is electrically connected to the transistor .
Each of the first metal oxide film and the second metal oxide film has In, Ga, and Zn, and has In, Ga, and Zn.
The second metal oxide film is a semiconductor device having a function as an electrode of a display element . A semiconductor device having a transistor and a capacitive element,
The transistor is provided with an oxide semiconductor film, a first insulating film above the oxide semiconductor film, and a first insulating film provided above the first insulating film and having a region overlapping with the oxide semiconductor film. It has a metal oxide film and a conductive layer that functions as a source electrode or a drain electrode.
The conductive layer is provided on a second insulating film provided above the first metal oxide film, and the oxide semiconductor film is provided through an opening provided in the second insulating film. Electrically connected to
The second insulating film includes a region in contact with the upper surface and the side surface of the first metal oxide film, a region in contact with the side surface of the first insulating film, and a region in contact with the upper surface of the oxide semiconductor film. Have,
The capacitive element has a second metal oxide film, a first conductive film, and a third insulating film between the second metal oxide film and the first conductive film. ,
The second metal oxide film has the same material as the first metal oxide film and has the same material.
The second metal oxide film is a semiconductor device that is electrically connected to the transistor and has a function as an electrode of a display element.

Images