JP6970519B2 - Transmitter and receiver - Google Patents

Description

The present invention relates to the technical fields of satellite broadcasting and terrestrial broadcasting, as well as fixed communication and mobile communication, and particularly to a transmitting device and a receiving device for digital data.

As a technique for improving transmission performance under white noise, a coded modulation technique that enables improvement in transmission performance by appropriately combining the strength of the error correction code and the bits of the modulation mapping in digital modulation has been proposed. (See, for example, Non-Patent Document 1).

The coded modulation technology described in Non-Patent Document 1 and the like is also adopted in the Japanese satellite digital broadcasting standard ISDB-S (see, for example, Non-Patent Document 2), and has a proven track record as a technique that contributes to improvement of transmission performance. There is.

The basic principle of the technique described in Non-Patent Document 1 is among the bits constituting the symbol (hereinafter referred to as symbol constituent bits) in consideration of the Euclidean distance between the signal points after mapping the bits to the symbol. , Strong error correction is applied to bits in which 1/0 is inverted between signal points with short Euclidean distances, and conversely weak for bits in which 1/0 is inverted between signal points with long Euclidean distances. By performing error correction or not performing coding processing, noise immunity is improved while maintaining overall information efficiency.

Further, Non-Patent Document 1 proposes a symbol assignment method to a signal point called a set partitioning method using 8PSK (phase-shift keying) as an example. In the set partitioning method, a plurality of code sequences that can be divided for each bit are used as an input symbol sequence, and the symbol constituent bits of the input symbol sequence are uniformly divided so that the minimum Euclidean distance between signal points is expanded. This is a transmission method that assigns symbols to signal points used for modulation. As an example, an example of a symbol assignment method to 8PSK signal points by the partitioning method will be described with reference to FIG.

FIG. 11 already shows a symbol (000, 001, ..., 111) composed of 3 bits to be assigned to each signal point of 8PSK, which is a signal point using the following division procedure. It is obtained as a result of assigning a symbol to, and has not yet been determined at the time of partitioning the set.

In the first division, the eight signal points are divided into two signal point groups consisting of four signal points so that the Euclidean distance (minimum Euclidean distance) between adjacent signal points is maximized. Here, of the two signal point groups, a1 = 0 is assigned to the first bit (most significant bit) of the symbol constituent bit, and a1 = 1 is assigned to the other signal point group.

Next, the two signal point groups composed of the four signal points obtained in the first division are each divided into four signal point groups consisting of two signal points so as to maximize the minimum Euclidean distance. .. Here, when a signal point group composed of four signal points is divided into two signal point groups, a2 = 0 is assigned to the second bit of the symbol constituent bit in one signal point group, and a2 = 0 is assigned to the other. Allocates a2 = 1.

Further, although omitted in FIG. 11, the four signal point groups composed of the two signal points obtained in the second division are each divided into eight signal point groups consisting of one signal point. Here, when the signal point group composed of two signal points is divided into one signal point, a3 = 0 is set in the third bit (least significant bit) of the symbol constituent bit in one signal point group. Allocate, and a3 = 1 is assigned to the other.

As a result of performing the above three-step partitioning, a 3-bit unique symbol is assigned to each of the eight signal points.

By assigning symbols to these signal points, in the case of 8PSK, the first bit (corresponding to a1 in FIG. 11) is the minimum Euclidean distance at 8PSK, and the second bit (corresponding to a2 in FIG. 11) is QPSK. It is possible to decode each bit under the condition of the minimum Euclidean distance of (Quadrature Phase Shift Keying) and the minimum Euclidean distance of BPSK (Binary Phase-Shift Keying) for the third bit (corresponding to a3 in FIG. 11). Will be.

Further, FIGS. 12 and 13 show examples of the symbol allocation method when the set partitioning method is applied to 16QAM (Quadrature Amplitude Modulation) and 32QAM. It can be confirmed that the minimum Euclidean distance is widened by advancing the division as in the case of 8PSK. In FIGS. 12 and 13, an example of division into the first bit (a1: most significant bit) and the second bit (a2) is shown, but the minimum Euclidean distance is also the same for the third bit (a3) and thereafter. It can be divided to expand.

According to such a transmission method of the set division method, the assignment of the symbol to the signal point obtained by the set division method is shared in advance between transmission and reception, and the transmitting side receives data to be transmitted by each bit constituting the symbol. , Modulation is performed by encoding with an error correction code of correction capability suitable for the minimum Euclidean distance between the corresponding signal points, and on the receiving side, decoding corresponding to the coding on the transmitting side is performed after demodulation, resulting in high noise immunity. A transmission system can be realized.

On the other hand, when the set division method is applied to multi-valued modulation, the minimum Euclidean distance increases for each bit to be divided and the error correction capability also differs for each bit, so that the transmission performance is improved at a predetermined coding rate. It is necessary to optimize the error correction code according to the error correction capability for each bit.

By the way, the transmission method of the advanced wideband satellite digital broadcasting described in DVB-S2 (see Non-Patent Document 3), DVB-S2X (see Non-Patent Document 4), which is a European satellite digital broadcasting system, and ARIB STD-B44 (hereinafter, It is called an advanced satellite broadcasting system. For example, in Non-Patent Document 5), a gray code is adopted as a technique for assigning a symbol to a signal point.

The Gray code has a uniform correction capability for each bit in BPSK and QPSK, but in multi-value modulation of 8 PSK or more, the error correction capability between bits included in the symbol becomes non-uniform. It is an obstacle in improving the transmission performance in the coding rate.

Therefore, in order to improve the above-mentioned problem due to the Gray code, a technique for further improving the transmission method by the partitioning method and improving the transmission performance when the correction ability of each bit is different is disclosed (for example, a patent). See Document 1).

Japanese Unexamined Patent Publication No. 2014-155195

G. Ungerboeck, “Channel coding with multilevel / phase signals”, IEEE Transaction Information Theory, Vol.IT-28, No.1, January 1982, p.55-67 "Satellite digital broadcasting transmission method standard ARIB STD-B20 3.0 version", [online], revised on May 31, 2001, ARIB, [search on February 15, 2016], Internet <URL: http: / /www.arib.or.jp/english/html/overview/doc/2-STD-B20v3_0.pdf> Digital Video Broadcasting (DVB), “Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2)”, [online], Final draft ETSI EN 302 307 V1. 2.1 (2009-04), [Search on February 15, 2016], Internet <URL: http://www.etsi.org/deliver/etsi_en/302300_302399/302307/01.02.01_40/en_302307v010201o.pdf> Digital Video Broadcasting (DVB), “Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; Part2: DVB-S2 Extensions (DVB-S2X)”, [online], Draft ETSI EN 302 307-2 V1.1.1 (2014-10), [Search on February 15, 2016], Internet <URL: http://www.etsi.org/deliver/etsi_en/302300_302399/30230702/01.01. 01_20 / en_30230702v010101a.pdf> "Transmission method standard for advanced broadband satellite digital broadcasting ARIB STD-B44 2.0 version", [online], revised on July 31, 2014, ARIB, [search on February 15, 2016], Internet <URL: http //arib.or.jp/english/html/overview/doc/2-STD-B44v2_0.pdf>

As described above, in the partitioning method, the correction capability differs for each bit. Therefore, in order to improve the transmission performance at a predetermined coding rate, the error correction code is optimized according to the error correction capability for each bit. Is required.

Therefore, Patent Document 1 discloses a technique for improving the transmission performance when the correction capability of each bit differs depending on the transmission method by the partition of a set method, but a specific example thereof is disclosed only for 8PSK. .. On the other hand, it is not disclosed what values should be adopted for the LDPC (Low Density Parity Check) coding rate and the inspection matrix of the LDPC code in 64QAM to improve the frequency utilization efficiency and the transmission performance. Therefore, in adopting the transmission method based on the partition of a set method, there is a possibility that the broadcaster may use the LDPC coding rate (or the inspection matrix of the LDPC code) in which the transmission performance is not improved in some cases.

Therefore, a plurality of code sequences that can be divided for each bit are used as an input symbol sequence, and the symbol constituent bits of the input symbol sequence are uniformly divided by a set division method so that the minimum Euclidean distance between signal points is expanded. In the method, a specific LDPC coding rate in 64QAM and a specific numerical value regarding the value related to the inspection matrix of the LDPC code have been desired.

Furthermore, it is necessary to improve the information bit rate in order to meet the need for higher image quality for ultra-high-definition video such as 4K and 8K. For that purpose, the number of modulation multi-values is increased and the parity of the error correction code is increased. It is necessary to reduce the bits and increase the average coding rate, and at the same time, increase the C / N in which the error correction code satisfies the pseudo error free. ^{Usually, a bit error rate of 1.0 × 10-11} is often used as a pseudo-error-free evaluation point at the required C / N.

FIG. 14 shows an example of bit allocation to a symbol when the set partitioning method is applied to 64QAM, which is a conventional technique. Further, FIGS. 15 and 16 show the process of partitioning a set of 64QAM when the partitioning method by mapping shown in FIG. 14 is applied. As shown in FIGS. 15 and 16, the minimum Euclidean distance increases as the division progresses, and decoding with less error can be expected as the bits in the latter stage.

FIG. 17 shows the C / N vs. bit error rate characteristics for each bit of 64QAM when FIG. 14 is applied. From FIG. 17, as described above, it can be seen that the later bits have a smaller bit error rate under a constant C / N condition.

However, when the partition of a set method is applied to 64QAM, a new problem arises regarding LDPC code design. In FIG. 17, attention is paid to the point of C / N = 16.0 dB as a target value satisfying pseudo-error free. The bit error rate (0 dotted line in the figure) that intersects with the characteristics of the first bit is 2.51 × 10 ^-1 . Assuming that the first bit is BPSK, ^{the C / N corresponding to P = 2.51 × 10 -1} in BPSK can be calculated from the equation (1). Note that erfc () indicates a complementary error function.

From the formula (1), the C / N corresponding to ^{P = 2.51 × 10 -1 corresponds to −6.47 dB.} Since this condition requires a very low coding rate in order to satisfy the pseudo-error free in the error correction code of the first bit, it becomes difficult to design the LDPC code applied to the first bit. The simulated value of the required C / N at the LDPC coding rate of 41/120 (approximate value 1/3) in the advanced satellite broadcasting system-4.0 dB is a guideline for the lower limit of the C / N that satisfies the pseudo error-free (pseudo-error free). See Non-Patent Document 5).

Further, attention is paid to the characteristics of the 5th and 6th bits in FIG. When viewed from C / N = 16.0 dB, the bit error rate of both the 5th bit and the 6th bit is ^{less than 1 × 10-6} , and a simple error correction code such as a BCH code provides sufficient pseudo-error free. Can be expected. However, focusing on the performance of the BCH (65535, 65167) abbreviated code, the bit error rate before error correction that satisfies the pseudo error-free with only the BCH (65535, 65167) abbreviated code is 1.2 × 10 ^-4. It can be seen that the bit error rate characteristics of the 5th bit and the 6th bit are excessive performance in the vicinity of C / N = 16.0 dB. That is, since the 5th bit and the 6th bit have an excessive minimum Euclidean distance in the C / N of interest, the minimum Euclidean distance of the 5th and 6th bits is the other bit when considering the overall performance. It is desirable to allocate to.

The present invention has been made in view of the above problems, and provides a digital data transmitting device and a receiving device that apply the partitioning method to 64QAM and improve the average coding rate and frequency utilization efficiency. The purpose.

In order to solve the above-mentioned problems, in the present invention, as a means for achieving pseudo-error-free in the vicinity of required C / N = 16.0 dB, the LDPC coding rate of each bit of the symbol constituent bits of 64QAM by the set division method is used. LDPC average coding rate 96/120 (that is, 4/5) is applied. Then, when the set division method is applied, an LDPC code having a predetermined LDPC coding rate for each bit is internally coded and has a predetermined correction capability according to the error correction capability for each bit constituting the symbol. By applying a concatenated code having a BCH code as an external code, a digital data transmitting device and a receiving device with improved frequency utilization efficiency are configured. That is, the concatenated code applied to each bit constituting the symbol has a BCH (65535, 65343) abbreviated code or a BCH (65535, 65167) abbreviated code as an external code, and further has a code length 44880 as an internal code. Has an LDPC code. Further, the LDPC code has a predetermined coding rate in each bit of the symbol constituent bits of 64QAM, and the LDPC average coding rate from the highest 1st bit to the lowest 6th bit is 96 /. It is configured to be 120 (that is, 4/5). Further, in order to solve the problems caused by the conventional set partitioning method, the bit error rates of the first bit and the second bit before error correction are made to be almost the same, and the fourth bit, the fifth bit, and the fourth bit are the same. Partitioning method modified so that the bit error rates before error correction of 6 bits are almost the same (in the specification of the present application, the "variation partitioning method" is used to clearly distinguish from the partitioning method of the conventional technique. Also referred to as). More specifically, the features of the present invention will be described below.

The first feature is
In the transmission device that transmits digital data, 64QAM is applied as the modulation method and 96/120 (that is, 4/5) is applied as the LDPC average coding rate, and the concatenated code composed of the LDPC code and the BCH code is used. Symbols are assigned to the signal points used for modulation, and two types are assigned according to the bit value of the first bit so that the minimum Euclidean distance between the symbols of the first bit is equal in the division from the first bit to the second bit. It is divided into two types according to the bit value of the second bit so that the minimum Euclidean distance between the symbols of the second bit is equal in the division from the second bit to the third bit, and the third bit to the third bit. Divide into two types according to the bit value of the 3rd bit so that the minimum Euclidean distance between the symbols of the 3rd bit is equal in the division up to 4 bits, and the 4th bit in the division from the 4th bit to the 5th bit. Divide into two types according to the bit value of the 4th bit so that the minimum Euclidean distance between the symbols of the 5th bit is equal, and the minimum Euclidean distance between the symbols of the 5th bit is equal in the division from the 5th bit to the 6th bit. When combined with the set division method that divides into two types according to the bit value of the 5th bit and equalizes the minimum Euclidean distance between the symbols of the 6th bit , the concatenation code is used for each of the symbols. It has a predetermined number of coding ratios determined according to the required correction capability of the bits, and when coding the LDPC code for each bit of the symbol constituent bits in the set division method, the first bit (highest order). In the division from the bit) to the sixth bit (lowest bit), the minimum euclidean distance between the symbols in the first bit and the minimum euclidean distance between the symbols in the second bit are equal in the division from the first bit to the second bit. Therefore, it is encoded by an LDPC code having an equal coding ratio, and is divided from the second bit to the third bit, the third bit to the fourth bit, the fourth bit to the fifth bit, and the fifth bit to the sixth bit. In, the minimum euclidean distance between the symbols of the 4th bit and the minimum euclidean distance between the symbols of the 5th bit are equal, and the minimum euclidean distance between the symbols of the 5th bit and the minimum euclidean distance between the symbols of the 6th bit are equal. Since they are equal to each other, they are configured to be encoded by a predetermined BCH code having the same coding rate. This makes it possible to improve the frequency utilization efficiency in the partitioning method.

The second feature is
In the LDPC code, the code length of the LDPC code is 44,880 bits. This enables highly consistent transmission with MPEG-2 TS (Motion Pictures Expert Group 2 Transport Stream).

The third feature is
In the concatenated code of the LDPC code and the BCH code, the BCH code is a BCH (65535, 65343) abbreviated code or a BCH (65535, 65167) abbreviated code. This makes it possible to obtain sufficient error tolerance even when the internal code parity is not added in order to improve the frequency utilization efficiency.

The fourth feature is
When the BCH code is a BCH (65535, 65343) abbreviated code, all the information bits constituting the code sequence are configured in byte units. As a result, it is possible to divide a variable length packet composed of bytes such as TLV into bytes even in the information bit region of the code sequence.

The fifth feature is
The LDPC code has 52/120 for the first bit, 52/120 for the second bit, and a third bit for 6 bits constituting a 64QAM modulation symbol having an average coding rate of 96/120 (that is, 4/5). 112/120 for the 4th bit, 120/120 for the 4th bit (without LDPC parity), 120/120 for the 5th bit (without LDPC parity), and 120/120 for the 6th bit (without LDPC parity). It is in. By having the coding rate determined according to the required correction capability for each bit in this way, it is possible to improve the frequency utilization efficiency in the partitioning method.

The sixth feature is
In a transmission device composed of the features of the first to fifth points, information regarding a coding rate of one or more of the LDPC code and the BCH code used on the transmission device side is transmitted by a transmission multiplex control signal. Thereby, it is possible to provide a transmission / reception device in which coding and decoding are matched according to the coding rate used.

The seventh feature is
In the receiving device that receives the signal transmitted by the transmitting device configured by the features of the first to sixth points, the minimum Euclidean distance is the same in the division from the first bit to the second bit, and the third bit to the third bit. The symbol is based on the correspondence between the signal point and the symbol obtained by the set division in which the minimum Euclidean distance is equal in the division from the 4th bit, the 4th bit to the 5th bit, and the 5th bit to the 6th bit. In LDPC decoding of each bit constituting the above, the first bit, the second bit, the third bit, the fourth bit, the fifth bit, and the sixth bit were used for the LDPC code according to the correction ability of each bit in this order. The LDPC decoding process is performed by the inspection matrix.

The eighth feature is
In the receiving device that receives the signal transmitted by the transmitting device configured by the features of the first to sixth points, the decoding corresponding to the LDPC code and the BCH code of the coding rate used for the coding on the transmitting side is performed. It is in. This enables efficient error correction and decoding.

The ninth feature is
In the receiving device that receives the signal transmitted by the transmitting device configured by the sixth feature, the coding rate information of one or more of the LDPC code and the BCH code is determined based on the transmission multiplex control signal. be. Thereby, it is possible to provide a transmission / reception device in which coding and decoding are matched according to the coding rate used.

By constructing the transmitting device and the receiving device by incorporating the above techniques, it is possible to improve the transmission performance when combining the partitioning method and the error correction code.

That is, the transmission device of the present invention is a transmission device that transmits digital data, and is a division from the first bit to the second bit as an allocation of a signal point used for the orthogonal modulation means by 64QAM and the modulation of the 64QAM. In, the minimum Euclidean distance between the symbols of the first bit is equalized into two types according to the bit value of the first bit, and the minimum between the symbols of the second bit in the division from the second bit to the third bit. It is divided into two types according to the bit value of the second bit so that the Euclidean distances are equal, and the third is such that the minimum Euclidean distance between the symbols of the third bit is equal in the division from the third bit to the fourth bit. It is divided into two types according to the bit value of the bit, and two types are divided according to the bit value of the fourth bit so that the minimum Euclidean distance between the symbols of the fourth bit is equal in the division from the fourth bit to the fifth bit. is divided into is divided into two types according to the bit value of the fifth bit as the minimum Euclidean distance between symbols of the fifth bit in the split extending from the fifth bit to the sixth bit equals sixth bit symbol The minimum euclidean distance between symbols is equal, the minimum euclidean distance between symbols in the first bit is equal to the minimum euclidean distance between symbols in the second bit, and the minimum euclidean distance between symbols in the fourth bit is equal to that of the fifth bit. A signal point used for 64QAM modulation by a set split method that divides so that the minimum Euclidean distance between symbols is equal and the minimum Euclidean distance between 5th bit symbols and the minimum Euclidean distance between 6th bit symbols are equal. The symbol to be assigned to is provided with an error correction coding means for forming a symbol composition bit composed of a plurality of code sequences that can be divided into 6 bits by using a concatenated code composed of an LDPC code and a BCH code. The coding rate of the LDPC code is determined for each bit of the symbol constituent bits of the symbol divided by the set division method in the bit order from the most significant bit to the least significant bit of the symbol constituent bits according to the required correction capability. The error-correcting coding means uses the coding rate of the LDPC code determined for each bit to form the symbol constituent bit of the 64QAM so that the LDPC average coding rate is 96/120. It is characterized by that. This makes it possible to improve the frequency utilization efficiency in the partitioning method. Further, in order to make this feature effective, it is preferable that the code length of the LDPC code is 44,880 bits in the transmission device of the present invention so as to enable highly consistent transmission with the MPEG-2 TS. ..

Further, in the transmission device of the present invention, the BCH code is a BCH (65535, 65343) abbreviated code or a BCH (65535, 65167) abbreviated code. This makes it possible to obtain sufficient error tolerance even when the internal code parity is not added in order to improve the frequency utilization efficiency.

Further, in the transmission device of the present invention, the LDPC code is 52/120, second to the first bit, which is the most significant bit, with respect to 6 bits of the symbol constituent bits for 64QAM having the LDPC average coding rate of 96/120. 52/120 for bits, 112/120 for the 3rd bit, 120/120 for the 4th bit (without LDPC parity), 120/120 for the 5th bit (without LDPC parity), 120 for the 6th bit, which is the least significant bit. It is characterized by having a coding rate of / 120 (without LDPC parity). By having the coding rate determined according to the required correction capability for each bit in this way, it is possible to improve the frequency utilization efficiency in the partitioning method.

Further, in the transmission device of the present invention, the orthogonal modulation means transmits information regarding a coding rate of one or more of the LDPC code and the BCH code by a transmission multiplex control signal (that is, a TMCC signal). It is characterized by being provided with signal multiplexing means. Thereby, it is possible to provide a transmission / reception device in which coding and decoding are matched according to the coding rate used.

Further, in the transmission device of the present invention, the error correction coding means includes a encoder that LDPC-encodes the digital data using a check matrix unique to each coding rate, and the encoder is 44880. Using the check matrix initial value table, which is a code length consisting of bits and is predetermined for each code rate, as the initial value, one element of the submatrix corresponding to the information length corresponding to the code rate 52/120 is 374 in the column direction. The inspection matrix initial value table (Table 1) having a coding rate of 52/120 has a means for performing LDPC coding using an inspection matrix arranged and configured in a cycle for each column, and is composed of the following table. It is characterized by.

In particular, the inspection matrix initial value table (Table 1) having a coding rate of 52/120 is configured to be commonly used for the first bit and the second bit in the partitioning method (variation partitioning method) according to the present invention. Therefore, there is an advantage that the amount of data to be retained, that is, the number of check matrix initial value tables can be reduced as compared with different ones, and the practicality is improved.

Further, in the transmission device of the present invention, the error correction coding means includes a encoder that LDPC-encodes the digital data using a check matrix unique to each coding rate, and the encoder is 44880. Using the check matrix initial value table, which is a code length consisting of bits and is predetermined for each code rate, as the initial value, one element of the submatrix corresponding to the information length corresponding to the code rate 112/120 is 374 in the column direction. The inspection matrix initial value table (Table 2) having a coding rate of 112/120 has a means for performing LDPC coding using an inspection matrix arranged and configured in a cycle for each column, and is composed of the following table. It is characterized by.

The receiving apparatus of the present invention receives a modulated wave signal of 64QAM transmitted from the transmitting apparatus of the present invention performs demodulation and decoding processing, a receiving apparatus of digital data, LDPC codes by the set partitioning method And, it is possible to divide by 6 bits from the orthogonal demodulation means that orthogonally demolishes the 64QAM modulated wave signal composed of the BCH code and outputs the received signal point sequence, and the received signal point sequence of 64QAM. Each bit is provided with a decoding means that acquires a symbol constituent bit composed of a plurality of code sequences, performs LDPC decoding processing using the coding rate of the LDPC code determined for each bit, and also performs BCH decoding processing. coding rate a defined LDPC code, the symbol bits constituting the symbols are divided by the set partitioning method, is determined for each said bit in response to the required correction capability, and the LDPC code is determined for each said bit It is characterized in that the LDPC average coding rate of the coding rate is configured to be 96/120.

Further, in the receiving device of the present invention, the decoding means is characterized in that decoding corresponding to the LDPC code and the BCH code of the coding rate used for the coding on the transmitting side. As a result, optimum BER characteristics can be obtained for the symbol constituent bits corresponding to each division step, and transmission with excellent noise immunity becomes possible.

Further, in the receiving device of the present invention, the decoding means includes a coding rate determining means for discriminating one or more coding rate information among the LDPC code and the BCH code based on the transmission multiplex control signal. And. Thereby, it is possible to provide a transmission / reception device in which coding and decoding are matched according to the coding rate used.

Further, the receiving device of the present invention receives the modulated wave signal transmitted by the transmitting device of the present invention, and encodes the LDPC code individually set for each bit of the symbol constituent bits in the partitioning method. It is characterized by decoding based on the rate.

Further, the receiving device of the present invention receives the modulated wave signal transmitted by the transmitting device of the present invention, and encodes the LDPC code individually set for each bit of the symbol constituent bits in the partitioning method. It is characterized by decoding based on the rate and the inspection matrix.

According to the present invention, it is possible to improve the performance of coded modulation in a combination of an error correction code and multi-level modulation (64QAM), and to improve the transmission performance under white noise.

It is a figure which shows the structural example of the transmitting device and the receiving device of one Embodiment in this invention. As Example 1 according to the present invention, the first bit LDPC coding rate 52/120, the second bit LDPC coding rate 52/120, the third bit LDPC coding rate 112/120, the fourth bit LDPC coding rate 120. / 120 (without LDPC parity), 5th bit LDPC coding rate 120/120 (without LDPC parity), 6th bit LDPC coding rate 120/120 (without LDPC parity), and BCH (65535, 65343) abbreviated codes. It is a figure which shows the slot configuration example of the case. It is a figure which shows the bit assignment to the symbol of the transformation set partitioning method in 64QAM which concerns on this invention. It is a figure which shows the example of the division from the 1st bit to the 2nd bit, and from the 2nd bit to the 3rd bit of the modification set partitioning method in 64QAM which concerns on this invention. It is a figure which shows the example of the division from the 3rd bit to the 4th bit, and from the 4th bit to the 5th bit of the modification set partitioning method in 64QAM which concerns on this invention. It is a figure which shows the C / N vs. bit error rate characteristic before error correction for each bit in 64QAM which concerns on this invention. As the second embodiment of the present invention, the information bits are configured in byte units in all the code sequences, the first bit LDPC coding rate 52/120, the second bit LDPC coding rate 52/120, and the third bit LDPC code. Conversion rate 112/120, 4th bit LDPC coding rate 120/120 (without LDPC parity), 5th bit LDPC coding rate 120/120 (without LDPC parity), 6th bit LDPC coding rate 120/120 (LDPC) It is a figure which shows the slot configuration example in the case of (no parity) and BCH (65535, 65343) abbreviated code. As Example 3 according to the present invention, the first bit LDPC coding rate 52/120, the second bit LDPC coding rate 52/120, the third bit LDPC coding rate 112/120, the fourth bit LDPC coding rate 120 / 120 (without LDPC parity), 5th bit LDPC coding rate 120/120 (without LDPC parity), 6th bit LDPC coding rate 120/120 (without LDPC parity), and BCH (65535, 65167) abbreviated codes. It is a figure which shows the slot configuration example of the case. It is a figure which shows the C / N vs. bit error rate characteristic which contrasts this invention with the conventional technique. It is a figure which shows the required C / N comparison result which compared the present invention with the conventional technique. It is a figure which shows the division example of the set partitioning method in 8PSK conventionally. It is a figure which shows the division example of the set partitioning method in the conventional 16QAM. It is a figure which shows the division example of the set partitioning method in 32QAM conventionally. It is a figure which shows the bit allocation to the symbol of the set partitioning method in the conventional 64QAM. It is a figure which shows the example of the division from the 1st bit to the 2nd bit, and from the 2nd bit to the 3rd bit of the conventional set division method in 64QAM. It is a figure which shows the example of the division from the 3rd bit to the 4th bit, and from the 4th bit to the 5th bit of the conventional set division method in 64QAM. It is a figure which shows the C / N vs. bit error rate characteristic before the error correction for each bit in the conventional 64QAM.

Hereinafter, a transmitting device and a receiving device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a transmitting device 10 and a receiving device 20 according to an embodiment of the present invention. In the actual transmission device 10, the receiver receives information such as a function of multiplexing a synchronous signal with a modulated wave signal in order to identify the head of an error correction code, and a setting of a transmission method adopted in ISDB-S or the like. It has a function of multiplexing a transmission multiplex control signal (also referred to as a TMCC signal) for advance notice with a modulated wave signal. Further, the actual receiving device 20 has a synchronization detection function that detects a synchronization signal multiplexed with the modulated wave signal and detects the beginning of an error correction code, and detects information such as a transmission method setting from a transmission multiplex control signal. It has a control function for setting the modulation method, coding rate, etc., but its detailed illustration is omitted.

(Device configuration)
[Transmitter]
Referring to FIG. 1, the transmission device 10 of the present embodiment is a forward error correction type transmission device, and includes a serial / parallel conversion unit 11, an error correction coding unit 12, and a coding rate setting unit 13. A mapping unit 14, an orthogonal modulation unit 15, and a coding rate discrimination signal multiplexing unit 16 are provided. That is, the functional block configuration of the transmission device 10 is the same as that of the coding modulation transmission device by the partition of a set method, but the processing of the error correction coding unit 12, the coding rate setting unit 13, and the accompanying mapping unit 14 are conventional techniques. Is different.

The serial / parallel conversion unit 11 has a 1-bit transmission data series, where M = log ₂ L-bit data series (in the case of 64-value modulation, M = log ₂ 64 =), where L is the multi-valued number of the modulation method to be used. It is converted into a 6-bit series) and sent to the error correction coding unit 12.

The error correction coding unit 12 is composed of a first error correction coding unit 12-1 to a sixth error correction coding unit 12-6, and is encoded by a predetermined error correction code (for example, a BCH code and an LDPC code). The 6 code sequences are generated.

In each of the first error correction coding unit 12-1 to the sixth error correction coding unit 12-6, the external code is used as the BCH (65535, 65343) shortened code as the first embodiment, and the internal code is the LDPC having a code length of 44880. Let it be a code. When the coding rate applied to the LDPC code described later is 120/120, LDPC parity is not added, and as Example 1, error correction coding is performed using only the BCH (65535, 65343) shortened code. As will be described later, in the slot of the third embodiment, a BCH (65535, 65167) abbreviated code can be used.

The coding rate setting unit 13 individually sets the coding rate of the LDPC code for each bit of the symbol constituent bits in the set partitioning method. In particular, as the LDPC code according to the present invention, the LDPC code has an average coding rate of 96/120 (that is, 4/5), and the minimum euclide between the symbols in the first bit in the division from the first bit to the second bit described later. The distance and the minimum Euclidean distance between the symbols in the second bit are equal, and the second bit to the third bit, the third bit to the fourth bit, the fourth bit to the fifth bit, and the fifth bit to the sixth bit. In the division, the minimum Euclidean distance between the 4th bit symbols and the minimum Euclidean distance between the 5th bit symbols are equal, and the minimum Euclidean distance between the 5th bit symbols and the minimum Euclidean distance between the 6th bit symbols. In each bit of 64QAM modulation based on the modified set division method, the first bit has a coding rate of 52/120, the second bit has a coding rate of 52/120, and the third bit has 112 /. 120, the 4th bit has a coding rate of 120/120 (without LDPC parity), the 5th bit has a coding rate of 120/120 (without LDPC parity), and the 6th bit has a coding rate of 120/120 (without LDPC parity). None) Set the coding rate. Thereby, error correction coding unit 12, the minimum Euclidean distance is equal to between symbols at the minimum Euclidean distance and the second bit between symbols in the first bit in the split extending from first bit to the second bit, and the second In the division from bit to 3rd bit, 3rd bit to 4th bit, 4th bit to 5th bit, and 5th bit to 6th bit, the minimum Euclidean distance between the symbols of the 4th bit and the 5th bit. Considering the ability to correct the symbol constituent bits by the modified set division method that divides so that the minimum Euclidean distance between the symbols is equal and the minimum Euclidean distance between the 5th bit symbols and the minimum Euclidean distance between the 6th bit symbols are equal. The coding ratio is set, and LDPC coding having sufficient correction capability can be performed. This makes it possible to improve the frequency utilization efficiency in the partitioning method.

FIG. 2 shows the slot configuration of the first embodiment when the code group obtained from the error correction coding unit 12 is slotted based on the above settings. In the present invention, the LDPC code length is 44880, which is the same code length as that of the advanced satellite broadcasting system (see Non-Patent Document 5). It is possible, and in FIG. 2, it is possible to apply the same allocation including the slot header. Further, also in the mapping unit 14 described later, mapping that does not cause excess or deficiency of bit allocation when 64QAM is applied is possible.

The mapping unit 14 uses the code sequence of the six systems as an input symbol sequence, and outputs the amplitude values of the I-axis and the Q-axis of the signal points corresponding to the symbols as a modulation signal point sequence. FIG. 3 shows an example of bit allocation to a symbol when the modified set partitioning method in 64QAM according to the present invention is applied. Further, FIGS. 4 and 5 show the process of partitioning a set of 64QAM when the modified partitioning method by mapping shown in FIG. 3 is applied. That is, the correspondence between the symbol and the signal point used in the mapping according to the present invention is the minimum Euclidean distance between the symbols in the first bit and the second in the division from the first bit to the second bit shown in FIGS. 4 and 5. The minimum Euclidean distance between the symbols in the bits is equal, and in the division from the 2nd bit to the 3rd bit, the 3rd bit to the 4th bit, the 4th bit to the 5th bit, and the 5th bit to the 6th bit . The minimum euclidean distance between the symbols of the 4th bit is equal to the minimum euclidean distance between the symbols of the 5th bit, and the minimum euclidean distance between the symbols of the 5th bit is equal to the minimum euclidean distance between the symbols of the 6th bit. The set division obtained by the constructed modified set division method is used. That is, in the modified set division method of the present invention, the minimum Euclidean distance is the same in the division from the first bit to the second bit, and the third bit to the fourth bit, the fourth bit to the fifth bit, and the fifth bit to the same. By dividing the signal points so that the minimum Euclidean distances are equal in the division up to the sixth bit, the correspondence between the symbols and the signal points is acquired. Comparing FIGS. 15 and 16 which are the set division methods of the conventional technique with FIGS. 4 and 5 which are the modified set division methods of the present invention, in the conventional technique, the minimum Euclidean is gradually reduced in the first bit to the sixth bit. In contrast to the increase in distance, in the present invention, the minimum euclidean distance between symbols in the first bit and the minimum euclidean distance between symbols in the second bit are equal before and after the division from the first bit to the second bit. the third bit from the second bit, the fourth bit from the third bit, the fifth bit from the fourth bit, in the dividing, from the fifth bit to the sixth bit (FIG. 4 and partly omitted in FIG. 5), the The minimum euclidean distance between the 4-bit symbols and the minimum euclidean distance between the 5th bit symbols are equal, and the minimum euclidean distance between the 5th bit symbols and the minimum euclidean distance between the 6th bit symbols are equal. Recognize.

FIG. 6 shows the C / N vs. bit error rate characteristics when this division is applied. From FIG. 6, it can be seen that the characteristics of the first bit and the second bit before error correction are almost completely the same, and the characteristics of the fourth bit, the fifth bit, and the sixth bit before the error correction are almost the same. Recognize. Further, it can be seen that the bit error rate of the first and second bits intersecting with C / N = 16.0 dB is 1.47 × 10 ^-1 (dotted line in FIG. 6). This is −2.59 dB when the first bit and the second bit are each assumed to be BPSK and converted into C / N by the equation (1). As described above, -4.0 dB is a guideline for the lower limit of C / N that satisfies the pseudo error free, so the value of C / N that is −2.59 dB is a value that can be sufficiently expected to be pseudo error free. .. Therefore, the LDPC code design of the first bit, which was difficult with the conventional technique, can be realized by the technique of the present invention. Based on this characteristic, the same coding rate of 52/120 is applied to the LDPC code applied to the first bit and the second bit.

Therefore, the mapping unit 14 functions as a symbol / signal point conversion means for converting an input symbol sequence composed of a plurality of code sequences into a signal point sequence based on the above correspondence.

The orthogonal modulation unit 15 executes a roll-off filter process on the modulation signal sequence generated by the mapping unit 14, and then transmits the modulated wave signal subjected to orthogonal modulation to an external transmission line.

The coding rate discrimination signal multiplexing unit 16 receives the coding rate information for each bit of the symbol constituent bits set for the error correction coding unit 12 by the coding rate setting unit 13 from the coding rate setting unit 13. It has a function of multiplexing with a modulated wave signal in the orthogonal modulation unit 15 so as to be transmitted by a transmission multiplex control signal (that is, a TMCC signal).

[Receiver]
The receiving device 20 of the present embodiment is a forward error correction type receiving device, and includes the orthogonal demodulation unit 21, the 1st to 6th bit logarithmic likelihood ratio calculation units 22-1 to 22-6, and the 1st to 1st. A sixth bit error correction decoding unit 23-1 to 23-6, a parallel / serial conversion unit 24, and a coding rate determination unit 25 are provided. That is, the functional block configuration of the receiving device 20 is the same as that of the coded modulation receiving device by the partition of a set method, but the processing of the orthogonal demodulation unit 21 and the first to sixth bit error correction decoding units 23-1 to 23-6. Is different from the conventional technique.

The orthogonal demodulation unit 21 transmits a 64QAM modulated wave signal obtained by modulating the modulated signal sequence based on the correspondence between the symbol and the signal point obtained by the modified set division method according to the present invention described above via a transmission line. It is received from 10 and demodulated orthogonally, and the received signal point sequence corresponding to the symbol of the main signal is output. Therefore, the orthogonal demodulation unit 21 serves as an orthogonal demodulation means that restores and outputs a modulated signal point series modulated based on the correspondence between the symbol and the signal point obtained by the partitioning method according to the present invention by performing orthogonal demodulation. Function.

The first bit log-likelihood ratio calculation unit 22-1 has 1 and 0 bits for the first bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set division method according to the present invention. The probability (likelihood) P11 and P10 are calculated, and the natural logarithm (LLR: log-likelihood ratio) of their ratio P11 / P10 is calculated and sent to the first bit error correction decoding unit 23-1.

The first bit error correction decoding unit 23-1 encodes the first bit constituting the symbol by using the log likelihood ratio of the first bit by the first bit log-like likelihood ratio calculation unit 22-1. Internal code error correction is performed according to the LDPC code inspection matrix corresponding to the coding rate 52/120, which is the coding rate information for the first bit obtained from the rate discrimination unit 25, and further, the LDPC decoding result is input as an embodiment. In No. 1, external code error correction is executed according to the BCH (65535, 65343) abbreviated code generation polymorphism, and the decoding result of the first bit is sent to the second bit logarithmity ratio calculation unit 22-2 and the parallel / serial conversion unit 24. do.

The second bit log-likelihood ratio calculation unit 22-2 is based on the correspondence between the symbol and the signal point obtained by the set partitioning method according to the present invention, and the second bit constituting the symbol has the same log-likelihood as the first bit. The degree ratio is calculated and sent to the second bit error correction decoding unit 23-2.

The second bit error correction decoding unit 23-2 encodes the second bit constituting the symbol by using the logarithmic likelihood ratio of the second bit by the second bit logarithmic probability ratio calculation unit 22-2. Internal code error correction is performed according to the LDPC code inspection matrix corresponding to the coding rate 52/120, which is the coding rate information for the second bit obtained from the rate determination unit 25, and further, the LDPC decoding result is input as an embodiment. In No. 1, external code error correction is executed according to the BCH (65535, 65343) abbreviated code generation polymorphism, and the decoding result of the second bit is sent to the third bit logarithmity ratio calculation unit 22-3 and the parallel / serial conversion unit 24. do.

The third bit log-likelihood ratio calculation unit 22-3 is the same as the first and second bits for the third bit constituting the symbol based on the correspondence between the symbol and the signal point obtained by the set partitioning method according to the present invention. The log-likelihood ratio is calculated and sent to the third bit error correction decoding unit 23-3.

The third bit error correction decoding unit 23-3 encodes the third bit constituting the symbol by using the log likelihood ratio of the third bit by the third bit log likelihood ratio calculation unit 22-3. Internal code error correction is performed according to the LDPC code inspection matrix corresponding to the coding rate 112/120, which is the coding rate information for the third bit obtained from the rate discrimination unit 25, and further, the LDPC decoding result is input as an embodiment. In No. 1, external code error correction is executed according to the BCH (65535, 65343) abbreviated code generation polymorphism, and the decoding result of the third bit is sent to the fourth bit logarithmity ratio calculation unit 22-4 and the parallel / serial conversion unit 24. do.

The fourth bit logarithmic likelihood ratio calculation unit 22-4 describes the first, second, and first bits constituting the symbol based on the correspondence between the symbol and the signal point obtained by the partitioning method according to the present invention. The logarithmic likelihood ratio is calculated in the same manner as for the 3 bits and sent to the 4th bit error correction decoding unit 23-4.

The 4th bit error correction decoding unit 23-4 encodes the 4th bit constituting the symbol by using the log likelihood ratio of the 4th bit by the 4th bit log likelihood ratio calculation unit 22-4. External code error correction is executed according to the BCH (65535, 65343) shortened code generation polypoly of Example 1, which corresponds to the coding rate 120/120, which is the coding rate information for the 4th bit obtained from the rate discrimination unit 25. , The decoding result of the 4th bit is sent to the parallel / serial conversion unit 24.

The fifth bit log-likelihood ratio calculation unit 22-5 describes the first, second, and first bits constituting the symbol based on the correspondence between the symbol and the signal point obtained by the partitioning method according to the present invention. 3. Similarly to the 4th bit, the log-likelihood ratio is calculated and sent to the 5th bit error correction decoding unit 23-5.

The fifth bit error correction decoding unit 23-5 encodes the fifth bit constituting the symbol by using the log likelihood ratio of the fifth bit by the fifth bit logarithmic probability ratio calculation unit 22-5. External code error correction is executed according to the BCH (65535, 65343) shortened code generation polypoly of Example 1, which corresponds to the coding rate 120/120, which is the coding rate information for the fifth bit obtained from the rate determining unit 25. , The decoding result of the 5th bit is sent to the parallel / serial conversion unit 24.

The sixth bit log-likelihood ratio calculation unit 22-6 describes the first, second, and first bits constituting the symbol based on the correspondence between the symbol and the signal point obtained by the partitioning method according to the present invention. The log-likelihood ratio is calculated in the same manner as in the third, fourth, and fifth bits, and sent to the sixth bit error correction decoding unit 23-6.

The sixth bit error correction decoding unit 23-6 encodes the sixth bit constituting the symbol by using the log likelihood ratio of the sixth bit by the sixth bit logarithmic probability ratio calculation unit 22-6. External code error correction is executed according to the BCH (65535, 65343) shortened code generation polypoly of Example 1, which corresponds to the coding rate 120/120, which is the coding rate information for the sixth bit obtained from the rate determining unit 25. , The decoding result of the 6th bit is sent to the parallel / serial conversion unit 24.

In this way, the 1st to 6th bit log-like likelihood ratio calculation units 22-1 to 22-6 and the 1st to 6th bit error correction decoding units 23-1 to 23-6 are the first to second bits. A variant that divides so that the minimum Euclidean distance is equal in the division to the bit, and the minimum Euclidean distance is equal in the division from the 3rd bit to the 4th bit, the 4th bit to the 5th bit, and the 5th bit to the 6th bit. Sequential decoding is performed using the decoding result obtained for each bit and the logarithmic likelihood ratio based on the correspondence between the symbol and the signal point obtained by the set division method. Therefore, the 1st to 6th bit log-likelihood ratio calculation units 22-1 to 22-6 and the 1st to 6th bit error correction decoding units 23-1 to 23-6 perform the above-mentioned partitioning to the signal point. It functions as a decoding means for decoding each symbol constituent bit based on the correspondence between the signal point to which the symbol is assigned and the symbol.

The parallel / serial conversion unit 24 performs parallel / serial conversion of the decoding result of the data series corresponding to the bits constituting the symbols obtained from the first to sixth bit error correction decoding units 23-1 to 23-6, and 1 bit. The received data series of is sent to the outside.

The coding rate determination unit 25 notifies the receiving device 20 of information such as a function of multiplexing a synchronization signal with a modulated wave signal and a transmission method setting in order to identify the head of an error correction code obtained from the orthogonal demodulation unit 21. The transmission multiplex control signal is input, and the coding rate information for the 1st to 6th bits used by the 1st to 6th bit error correction decoding units 23-1 to 23-6 is discriminated from the transmission multiplex control signal. The first to sixth bits are sent to the error correction and decoding units 23-1 to 23-6, respectively.

In the first embodiment shown in FIG. 2, it is assumed that the slot header area is utilized to accommodate a variable length packet configured in byte units such as a TLV packet, but in the slot configuration of the first embodiment. When viewed for each code sequence that constitutes a slot, it is expected that the information bits are not configured in byte units, and it will be difficult to write byte information indicating a break in a variable-length packet to the slot header area. NS.

Therefore, by using a slot configuration in which the information bits are configured in byte units for each code sequence of the second embodiment shown in FIG. 7, information indicating a break of the variable length packet composed in byte units is written in the slot header area. It is possible to secure the function and accommodate it.

Further, in order to apply a BCH code having a higher correction capability as an external code, a slot having a code length of 44880 bits is replaced with a slot of Example 3 as shown in FIG. 8 using a BCH (65535, 65167) shortened code. It can be configured.

That is, in the slot configuration of the first embodiment shown in FIG. 2, a 176-bit slot header and a 6-bit stuff bit are provided as in the conventional slot configuration of the advanced satellite broadcasting system, and the target required C is provided. In / N, the bit error of the 4th bit (a4), the 5th bit (a5), and the least significant bit (a6) in which the minimum Euclidean distance is large among the bits of the symbol constituent bits is shortened by BCH (65535, 65343). When the code is too large to be corrected by the code alone, it is desirable to enhance the correction capability without changing the code length consisting of 44880 bits. Further, by applying the BCH (65535, 65167) shortening code to each of the first bit to the third bit, it is possible to reduce the influence of error propagation when decoding in order from the first bit.

Therefore, as shown in FIG. 8, in the slot configuration of the third embodiment, the slot header area is deleted, the deleted 176 bits are allocated to the parity of the BCH code, and the BCH (65535, 65343) shortening of the correction capability of 12 bits is performed. The code is strengthened to a BCH (65535, 65167) shortened code with a correction capacity of 23 bits. Even if the slot header is deleted in this way, there is no problem in signal identification by providing information that can distinguish both of them in the transmission multiplex control signal.

As a result, in the slot configuration according to the present invention, when the target required C / N is sufficiently high (that is, when the target value is higher than the required C / N determined by the BCH (65535, 65343) abbreviation code). , The slot configuration of the third embodiment (FIG. 8) is adopted, and the slot configuration of the first embodiment or the second embodiment (FIG. 2, 7) and the slot configuration of the third embodiment are adopted according to the target required C / N. (Fig. 8) is switched and adopted.

The BCH (65535, 65167) abbreviated code generation polynomial is as disclosed in Patent Document 1. Further, the generation polynomial of the BCH (65535, 65343) abbreviated code is as disclosed in Non-Patent Document 5.

As an effect of the present invention, the transmission performance (simulation result) when the transmission device 10 and the reception device 20 of FIG. 1 and the slot configuration of FIG. 8 are used will be described. Assuming white noise in the transmission model, the maximum number of LDPC code decoding iterations was set to 50 per stage.

In FIG. 9, as an example having the same coding rate, when the LDPC code (coding rate 4/5) of the advanced BS method is applied to the 64APSK coding rate 4/5 and the Gray coded 64QAM of DVB-S2. The characteristics of are also described. The result of FIG. 9 was linearly extrapolated, and the C / N of BER = 1 × 10-11 was defined as the required C / N. The comparison result of the required C / N is shown in FIG. From FIG. 10, it can be seen that the present invention has an improvement of 0.01 dB over DVB-S2X and 0.67 dB over Gray coded 64QAM.

Although the above-described embodiment has been described based on a specific example, the present invention does not specify a transmission method, and is applicable to other transmission methods such as satellite broadcasting, terrestrial broadcasting, mobile communication, and fixed communication. .. Further, the signal point arrangement shown in FIG. 3 by the modified partition of a set method according to the present invention is only an example, and for example, the phase relationship in FIG. 3 is inverted by 180 degrees from the purpose of the present invention. Other signal point arrangements can be used as long as they do not deviate.

According to the present invention, it is possible to improve the performance of coded modulation in the combination of the error correction code and multi-level modulation (64QAM) and improve the transmission performance under white noise. Therefore, the error-correcting code and multi-level modulation can be improved. It is useful for any application that utilizes modulation (64QAM).

10 Transmitter 11 Serial / parallel conversion unit 12 Error correction coding unit 12-1 First error correction coding unit 12-2 Second error correction coding unit 12-3 Third error correction coding unit 12-4 4th Error correction coding unit 12-5 5th error correction coding unit 12-6 6th error correction coding unit 13 Coding rate setting unit 14 Mapping unit 15 Orthogonal modulation unit 16 Coding rate discrimination signal multiplexing unit 20 Receiver 21 Orthogonal demodulation unit 22-1 1st bit log-like likelihood ratio calculation unit 22-2 2nd bit log-like likelihood ratio calculation unit 22-3 3rd bit log-like likelihood ratio calculation unit 22-4 4th bit log-like likelihood ratio calculation Part 22-5 5th bit log-like likelihood ratio calculation part 22-6 6th bit log-like likelihood ratio calculation part 23-1 1st bit error correction decoding part 23-2 2nd bit error correction decoding part 23-3 3rd Bit error correction decoding unit 23-4 4th bit error correction decoding unit 23-5 5th bit error correction decoding unit 23-6 6th bit error correction decoding unit 24 Parallel / serial conversion unit 25 Coding rate discrimination unit

Claims (13)

A transmitter that transmits digital data
Quadrature modulation means by 64QAM and
As the assignment of signal points used for the modulation of 64QAM, there are two types according to the bit value of the first bit so that the minimum Euclidean distance between the symbols of the first bit is equal in the division from the first bit to the second bit. It is divided into two types according to the bit value of the second bit so that the minimum Euclidean distance between the symbols of the second bit is equal in the division from the second bit to the third bit, and the third bit to the fourth bit are divided. It is divided into two types according to the bit value of the 3rd bit so that the minimum Euclidean distance between the symbols of the 3rd bit is equal in the division to the bit, and the 4th bit is divided in the division from the 4th bit to the 5th bit. It is divided into two types according to the bit value of the 4th bit so that the minimum Euclidean distance between the symbols is equal, and the minimum Euclidean distance between the symbols of the 5th bit becomes equal in the division from the 5th bit to the 6th bit. As described above, the minimum Euclidean distance between the symbols of the 6th bit is equalized by dividing into two types according to the bit value of the 5th bit, and the minimum Euclidean distance between the symbols in the 1st bit and the symbol in the 2nd bit are equalized. The minimum Euclidean distance is equal, the minimum Euclidean distance between the 4th bit symbols and the minimum Euclidean distance between the 5th bit symbols are equal, and the minimum Euclidean distance between the 5th bit symbols and the 6th bit symbol. Symbols that are assigned to signal points used for 64QAM modulation by the set division method that divides so that they are equal to the minimum Euclidean distance can be divided into 6 bits using a concatenated code consisting of an LDPC code and a BCH code. It is provided with an error correction coding means for forming a symbol constituent bit consisting of a plurality of code sequences.
The coding rate of the LDPC code is set for each bit of the symbol constituent bits of the symbol divided by the set division method in the bit order from the most significant bit to the least significant bit of the symbol constituent bits according to the required correction capability. It has been set and
The error correction coding means is characterized in that the 64QAM symbol constituent bits are formed so that the LDPC average coding rate is 96/120 by using the coding rate of the LDPC code determined for each bit. Transmitter. The transmission device according to claim 1, wherein the LDPC code has a code length of 44,880 bits. The transmission device according to claim 1 or 2, wherein the BCH code is a BCH (65535, 65343) abbreviated code or a BCH (65535, 65167) abbreviated code. The invention according to any one of claims 1 to 3, wherein when the BCH code is a BCH (65535, 65343) abbreviated code, all the information bits constituting the code sequence are configured in byte units. Transmitter. The LDPC code is 52/120 for the first bit, which is the most significant bit, 52/120 for the second bit, and a third bit for 6 bits of the symbol constituent bits for 64QAM having an LDPC average coding rate of 96/120. 112/120 for the 4th bit, 120/120 for the 4th bit (without LDPC parity), 120/120 for the 5th bit (without LDPC parity), and 120/120 for the 6th bit, which is the least significant bit (without LDPC parity). The transmission device according to any one of claims 1 to 4, wherein the transmission device has a conversion rate. The orthogonal modulation means according to claim 1, further comprising a coding rate discrimination signal multiplexing means for transmitting information regarding a coding rate of one or more of the LDPC code and the BCH code by a transmission multiplex control signal. 5. The transmission device according to any one of 5. The error correction coding means includes a encoder that LDPC-encodes the digital data using a check matrix unique to each code rate, and the coder has a code rate of 44,880 bits. Using a predetermined check matrix initial value table as the initial value, one element of the submatrix corresponding to the information length corresponding to the coding rate 52/120 is arranged in the column direction at a cycle of every 374 columns. The inspection matrix initial value table having a coding rate of 52/120 has a means for performing LDPC coding using the inspection matrix.

The transmitting device according to any one of claims 1 to 6, wherein the transmission device comprises. The error correction coding means includes a encoder that LDPC-encodes the digital data using a check matrix unique to each code rate, and the coder has a code rate of 44,880 bits. Using a predetermined check matrix initial value table as the initial value, one element of the submatrix corresponding to the information length corresponding to the coding rate 112/120 is arranged in the column direction at a cycle of every 374 columns. The inspection matrix initial value table having a coding rate of 112/120 has a means for performing LDPC coding using the inspection matrix.

The transmitting device according to any one of claims 1 to 6, wherein the transmission device comprises. A digital data receiving device that receives a 64QAM modulated wave signal transmitted from the transmitting device according to any one of claims 1 to 8 and performs demodulation and decoding processing.
And quadrature demodulating means for quadrature demodulating the modulated wave signal of 64QAM subjected to constituted concatenated coding from the LDPC code and BCH code, and outputs the received signal point sequence by the set partitioning method,
From the received signal point sequence of 64QAM, a symbol constituent bit consisting of a plurality of code sequences that can be divided by 6 bits is acquired, and LDPC decoding processing is performed using the coding rate of the LDPC code determined for each bit, and the operation is performed. It is equipped with a decoding means that performs BCH decoding processing.
Coding rate of the LDPC code defined for each of the bits, the symbol bits constituting the symbols are divided by the set partitioning method, is determined for each said bit in response to the required correction capability, and is determined for each said bit A receiving device characterized in that the LDPC average coding rate of the coding rate of the LDPC code is 96/120. The receiving device according to claim 9, wherein the decoding means performs decoding corresponding to the LDPC code and the BCH code of the coding rate used for the coding on the transmitting side. 9. The receiver described. The code of the LDPC code set individually for each bit of the symbol constituent bits in the partitioning method by receiving the modulated wave signal transmitted by the transmitting device according to any one of claims 1 to 6. A receiving device characterized by decoding based on the conversion rate. The code of the LDPC code set individually for each bit of the symbol constituent bits in the partitioning method by receiving the modulated wave signal transmitted by the transmitting device according to any one of claims 7 or 8. A receiving device characterized by decoding based on the conversion rate and the inspection matrix.

Images