JP6903328B2 - Amplifier circuit - Google Patents

Description

The present invention relates to an amplifier circuit.

In an image acquisition device such as a scanner, a facsimile transmitter / receiver, and a copier, a two-dimensional image is acquired by moving a linear sensor in which light receiving elements are arranged in one direction in a direction perpendicular to the arrangement direction. Further, in the image acquisition device, the output signal from the linear sensor is subjected to predetermined processing by an amplifier circuit or the like. The amplifier circuit used here is required to have a wide input range, low noise, high input impedance, and the like.

The amplifier circuit has various configurations. The most basic of these is the inverting amplifier circuit. The inverting amplifier circuit is formed between an operational amplifier, a first resistor provided between an input terminal into which a voltage signal is input and an inverting input terminal of the operational amplifier, and an inverting input terminal and an output terminal of the operational amplifier. It is provided with a second resistor provided. The inverting amplifier circuit is preferable because it has a wide input range. However, the input impedance of the inverting amplifier becomes the resistance value of the first resistor, and if this resistance value exceeds 100 kΩ, there is a problem in terms of the band of the inverting amplifier circuit, so there is a limit to increasing the input impedance. .. The inverting amplifier circuit is also limited in terms of noise reduction. An amplifier circuit using a rail-to-rail input (see, for example, Fig. 4.4.2 of Non-Patent Document 1) is also preferable in that it has a wide input range, but has a limitation in noise reduction. Other amplifier circuits having various configurations are known (see, for example, Fig. 1 of Non-Patent Document 2 and Fig. 4 of Non-Patent Document 3).

Further, although the performance requirements of the amplifier circuit differ depending on the application, the amplifier circuit is required to have excellent linearity over the entire input range in many applications. Non-Patent Documents 4 and 5 describe the configuration of an amplifier circuit intended to improve linearity. In the amplifier circuit described in Non-Patent Document 4, the non-linearity of the transistors constituting the input differential pair is canceled by giving the resistor that determines the gain non-linearity, and the linearity is improved. In the amplifier circuit described in Non-Patent Document 5, by providing a plurality of input differential pairs each having non-linearity, the non-linearity of the plurality of input differential pairs as a whole is reduced and the linearity is improved. Try. However, although the amplifier circuits described in Non-Patent Documents 4 and 5 improve the linearity over the entire input range, the wide input range may not be sufficient depending on the application.

Johan Huijsing, “OperationalAmplifiers, Theory and Design, Second Edition,” ISBN978-94-007-0595-1, Springer 2011. Phanumas Khumsat, PiamsukAnantaseth, Pasin Isarasena, “A Low-Voltage Class-AB CMOS Variable Gain Amplifier,” 200750th Midwest Symposium on Circuits and Systems, pp.253-256, 2007. Adrian Leuciuc, “Awide linear range low-voltage transconductor,” Proceedings of the 2003 International Symposium on Circuits and Systems, pp. I-161 -I-164, vol.1, DOI: 10.1109 / ISCAS.2003.1205, May 2003. F. Krummenacher and N. Joehl, “A4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning,” IEEEJournal of Solid State Circuits, Vol.23, No.3, pp.750-758, June 1998. M. B. Elamien and S. A. Mahmoud, “Alinear CMOS balanced output Transconductor Using Double Differential Pair with SourceDegeneration and Adaptive Biasing,” 2016 IEEE 59th InternationalMidwest Symposium on Circuits and Systems, October 2016.

Conventional amplifier circuits cannot harmoniously satisfy the specifications required for processing output signals from linear sensors in image acquisition devices such as scanners, facsimile transceivers and copiers.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an amplifier circuit capable of harmoniously satisfying the requirements of wide input range, high linearity, low noise and high input impedance. And.

The amplifier circuit of the first aspect of the present invention includes a VI converter, a first IV converter, and a second IV converter. The VI converter includes (1) a first resistance circuit provided between node N1 and node N2, (2) a gate, a source connected to node N1, a drain connected to node N3, and the like. The first conductive MOS transistor M1 having the (3) gate, the source connected to the node N2, and the drain connected to the node N4, and the first conductive MOS transistor M2 having (4). ) A second conductive MOS transistor M3 having a gate connected to node N7, a source, and a drain connected to node N3, and (5) a gate connected to node N8, a source, and a node. A second conductive MOS transistor M4 having a drain connected to N4, (6) a first conductive MOS transistor M5 having a gate, a source, and a drain connected to node N1. (7) A first conductive MOS transistor M6 having a gate, a source, and a drain connected to node N2, and (8) a gate, a source connected to node N5, and connected to node N7. First conductive MOS transistor M7 having a drain, (9) gate, source connected to node N6, and drain connected to node N8. A second conductive MOS transistor M9 having (10) a gate connected to the node N7, a source, and a drain connected to the node N7, and (11) a gate connected to the node N8. A second conductive MOS transistor M10 having a source and a drain connected to the node N8, and (12) a first conductive MOS having a gate, a source, and a drain connected to the node N5. It includes a first conductive MOS transistor M12 having a transistor M11, a (13) gate, a source, and a drain connected to a node N6. Of the first conductive type and the second conductive type, one is P type and the other is N type.

In the amplifier circuit of the first aspect of the present invention, the gates of the MOS transistors M1 and M7 are connected to the first input terminal. The gates of the MOS transistors M2 and M8 are connected to the second input terminal. The sources of the MOS transistors M5, M6, M11, and M12 are connected to the first reference potential input terminal. The sources of the MOS transistors M3, M4, M9, and M10 are connected to the second reference potential input terminal. Each of the MOS transistors M5, M6, M11, and M12 is a constant current source.

In the amplifier circuit of the first aspect of the present invention, the MOS transistors M7 and M11 are replicas of the MOS transistors M1 and M5, and carry a current amount p times the current amount flowd by the MOS transistor M5. The MOS transistors M3 and M9 form a current mirror circuit having a mirror ratio of 1: p. The MOS transistors M8 and M12 are replicas of the MOS transistors M2 and M6, and carry a current amount q times the amount of the current flowed by the MOS transistor M6. The MOS transistors M4 and M10 form a current mirror circuit having a mirror ratio of 1: q.

In the amplifier circuit of the first aspect of the present invention, the first IV converter is connected to the node N3, converts the input first current signal into a first voltage signal, and outputs the first voltage signal. The second IV converter is connected to the node N4, converts the input second current signal into a second voltage signal, and outputs the second voltage signal.

The amplifier circuit of the second aspect of the present invention includes a VI converter, a first IV converter, and a second IV converter. The VI converter includes (1) a first resistance circuit provided between node N1 and node N2, (2) a gate, a source connected to node N1, a drain connected to node N3, and the like. The first conductive MOS transistor M1 having the (3) gate, the source connected to the node N2, and the drain connected to the node N4, and the first conductive MOS transistor M2 having (4). ) A second conductive MOS transistor M3 having a gate connected to node N7, a source, and a drain connected to node N3, and (5) a gate, a source, and a drain connected to node N4. A second conductive MOS transistor M4 having the above, a (6) gate, a source, and a first conductive MOS transistor M5 having a drain connected to the node N1, and (7) a gate. It has a first conductive MOS transistor M6 having a source and a drain connected to the node N2, (8) a gate, a source connected to the node N5, and a drain connected to the node N7. A second conductive MOS transistor M9 having a first conductive MOS transistor M7, (9) a gate connected to the node N7, a source, and a drain connected to the node N7, and (10) a gate. A first conductive MOS transistor M11 having a source and a drain connected to the node N5.

In the amplifier circuit of the second aspect of the present invention, the gates of the MOS transistors M1 and M7 are connected to the first input terminal. The gate of the MOS transistor M2 is connected to the second input end. The sources of the MOS transistors M5, M6, and M11 are connected to the first reference potential input terminal. The sources of the MOS transistors M3, M4, and M9 are connected to the second reference potential input end. Each of the MOS transistors M5, M6, M11, and M4 is a constant current source. The MOS transistors M7 and M11 are replicas of the MOS transistors M1 and M5, and carry a current amount p times the amount of the current flowed by the MOS transistor M5. The MOS transistors M3 and M9 form a current mirror circuit having a mirror ratio of 1: p.

In the amplifier circuit of the second aspect of the present invention, the first IV converter is connected to the node N3, converts the input first current signal into a first voltage signal, and outputs the first voltage signal. The second IV converter is connected to the node N4, converts the input second current signal into a second voltage signal, and outputs the second voltage signal.

In the present invention, it is preferable that the VI converter further includes a second resistance circuit provided between the node N3 and the node N4.

_{The amplification circuit of the present invention adds the current amount ΔI 1} to the current amount of the current signal output from the node N3 to the first IV converter to obtain the current amount of the first current signal input to the first IV converter. A current that adjusts and adjusts the current amount of the second current signal input to the second IV converter by adding the _{current amount ΔI 2} to the current amount of the current signal output from the node N4 to the second IV converter. It is preferable to further include an adjusting unit. It is preferable that the _{current amounts ΔI 1} and ΔI ₂ applied by the current adjusting unit are variable. ΔI ₁ and ΔI ₂ may be positive, zero, or negative.

In the present invention, the first resistance circuit is preferably a combined resistance circuit having a variable resistance value. The combined resistance circuit is preferably provided with a first network provided between the first and second ends, the first network being provided between the nodes N11 and N12. A resistor R1, a resistor R2 provided between the node N12 and the node N13, a resistor R3 provided between the node N13 and the node N14, and a resistor R3 provided between the node N14 and the node N11. The resistor R4 provided, the resistor R5 provided between the node N11 and the node N13, the switch SW0 provided in series with the resistor R4 between the node N14 and the node N11, and the node N12. Includes a switch SW1 provided in series with the resistor R2 between and the node N13. Node N12 is connected to the first end and node N14 is connected to the second end.

The amplifier circuit of the present invention can harmoniously meet the requirements of wide input range, high linearity, low noise and high input impedance.

FIG. 1 is a diagram showing a configuration of an amplifier circuit 1A of a first configuration example. FIG. 2 is a diagram showing the relationship between the input voltage value difference (Vinp-Vinn) and the drain currents I _d1 and I _d2. FIG. 3 is a diagram showing the configuration of the amplifier circuit 1A of the first configuration example. FIG. 4 is a graph showing an example of the relationship between the _{drain voltage V d} and the drain current I _d of the MOS transistor as a constant current source. FIG. 5 is a diagram showing the configuration of the amplifier circuit 1B of the second configuration example. FIG. 6 is a diagram showing the relationship between the input voltage value Vinp and the output current difference in each of the amplifier circuit 1A (FIG. 3) of the first configuration example and the amplifier circuit 1B (FIG. 5) of the second configuration example. FIG. 7 is a diagram showing time waveforms of output voltage values (Voutp, Voutn) in each of the amplifier circuit 1A (FIG. 3) of the first configuration example and the amplifier circuit 1B (FIG. 5) of the second configuration example. FIG. 8 shows the common voltage ((Voutp + Voutn) / 2) and voltage difference (Voutp−) of the differential output in the amplifier circuit 1A (FIG. 3) of the first configuration example and the amplifier circuit 1B (FIG. 5) of the second configuration example, respectively. Voutn) It is a figure which shows each time waveform. FIG. 9 is a diagram showing the configuration of the amplifier circuit 1C of the third configuration example. FIG. 10 is a diagram showing the configuration of the amplifier circuit 1D of the fourth configuration example. FIG. 11 is a circuit diagram of the combined resistance circuit 2A of the first configuration example. FIG. 12 is a table summarizing the combined resistance values for each value of the control signal in the combined resistance circuit 2A of the first configuration example. FIG. 13 is a circuit diagram of the combined resistance circuit 2B of the second configuration example. FIG. 14 is a table summarizing the combined resistance values for each value of the control signal in the combined resistance circuit 2B of the second configuration example. FIG. 15 is a circuit diagram of the combined resistance circuit 2C of the third configuration example. FIG. 16 is a circuit diagram of the combined resistance circuit 2D of the fourth configuration example. FIG. 17 is a table summarizing the combined resistance values for each value of the control signal in the combined resistance circuit 2D of the fourth configuration example.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicate description will be omitted. The present invention is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

(Example of first configuration of amplifier circuit)
FIG. 1 is a diagram showing a configuration of an amplifier circuit 1A of a first configuration example. The amplifier circuit 1A inputs a voltage signal to the first input terminal 1a and the second input terminal 1b, and outputs a voltage signal having a value corresponding to the value of the input voltage signal and the resistance value of the first resistance circuit 2 to the first output terminal. Output is performed from 1c and the second output terminal 1d. The amplifier circuit 1A includes a VI converter 10A, a first IV converter 11, and a second IV converter 12. It is preferable that the amplifier circuit 1A further includes a current adjusting unit 13.

The VI converter 10A includes a first resistance circuit 2, a first MOS transistor 31, a second MOS transistor 32, a first constant current source 41, a second constant current source 42, a third constant current source 43, and a fourth constant current source 44. Including. The first resistance circuit 2 is provided between the node N1 and the node N2. The resistance value of the first resistance circuit 2 may be fixed. The first resistance circuit 2 may be a single resistor. The first resistance circuit 2 may be a combined resistance circuit having a variable resistance value.

The gate of the first MOS transistor 31 is connected to the first input terminal 1a. The source of the first MOS transistor 31 is connected to the node N1. The drain of the first MOS transistor 31 is connected to the node N3. The gate of the second MOS transistor 32 is connected to the second input terminal 1b. The source of the second MOS transistor 32 is connected to the node N2. The drain of the second MOS transistor 32 is connected to the node N4. The first MOS transistor 31 and the second MOS transistor 32 have the same characteristics as each other.

The first constant current source 41 is provided between the first reference potential input end and the node N1. The first constant current source 41 causes a constant amount of current to flow from the first reference potential input end to the node N1. The second constant current source 42 is provided between the first reference potential input end and the node N2. The second constant current source 42 causes a constant amount of current to flow from the first reference potential input end to the node N2. The third constant current source 43 is provided between the node N3 and the second reference potential input end. The third constant current source 43 causes a constant amount of current to flow from the node N3 to the second reference potential input end. The fourth constant current source 44 is provided between the node N4 and the second reference potential input end. The fourth constant current source 44 causes a constant amount of current to flow from the node N4 to the second reference potential input end. The amount of current I flowing through each of the first constant current source 41, the second constant current source 42, the third constant current source 43, and the fourth constant current source 44 is the same as each other.

For example, when the first reference potential is higher than the second reference potential, the first MOS transistor 31 and the second MOS transistor 32 are PIXTA transistors. Alternatively, when the first reference potential is lower than the second reference potential, the first MOS transistor 31 and the second MOS transistor 32 are NMOS transistors.

In the VI converter 10A, the voltage value Vinp is input to the first input terminal 1a, and the voltage value Vinn is input to the second input terminal 1b. When Vinp and Vinn are different from each other, a potential difference is generated between the node N1 and the node N2, and a current flows through the first resistance circuit 2. If the amount of current I _r flowing in the first resistor circuit 2 is smaller than the current amount I, each of the gate first 1MOS transistor 31 and the 2MOS transistor 32 - the potential difference Vgs between the source are substantially equal to each other.

Therefore, the difference in source potential between the first MOS transistor 31 and the second MOS transistor 32 (that is, the potential difference between the node N1 and the node N2) is substantially equal to the difference between Vinp and Vinn. When the resistance value of the first resistor circuit 2 and r _r, the amount of current I _r flowing from the node N1 to the node N2 via the first resistor circuit 2 is approximately expressed by the following equation (1). The amount of current I _r, depending on the magnitude relationship between the Vinp and Vinn, positive, and either zero or negative.

_{The amount of current I d1} (drain current of the first MOS transistor 31) flowing from the node N1 to the node N3 via the first MOS transistor 31 flows in the first resistance circuit 2 with respect to the amount of current I flowing through the first constant current source 41. becomes a value obtained by subtracting the amount of current I _r, is expressed by the following equation (2). Of the amount of current I _d1, the amount of current flowing from the node N3 to the third constant current source 43 is because it is I, the current amount of the current signal outputted from the node N3 to the first 1IV converter 11 is -I _r ..

_{The amount of current I d2} (drain current of the second MOS transistor 32) flowing from the node N2 to the node N4 via the second MOS transistor 32 flows in the first resistance circuit 2 with respect to the amount of current I flowing by the second constant current source 42. becomes a value obtained by adding the amount of current I _r, is expressed by the following equation (3). Of the amount of current I _d2, the amount of current flowing from the node N4 to the fourth constant current source 44 because it is I, the current amount of the current signal outputted from the node N4 to the second 2IV converter 12 becomes + I _r.

The first IV converter 11 includes an operational amplifier 51 and a resistor 52. The resistor 52 is provided between the inverting input terminal and the output terminal of the operational amplifier 51. The inverting input terminal of the operational amplifier 51 is connected to the node N3 of the VI converter 10A. A reference potential Vcm is input to the non-inverting input terminal of the operational amplifier 51. The first IV converter 11 converts the first current signal input to the inverting input terminal of the operational amplifier 51 into a first voltage signal, and outputs the first voltage signal from the output terminal of the operational amplifier 51. The output terminal of the operational amplifier 51 is connected to the first output terminal 1c.

The second IV transducer 12 includes an operational amplifier 61 and a resistor 62. The resistor 62 is provided between the inverting input terminal and the output terminal of the operational amplifier 61. The inverting input terminal of the operational amplifier 61 is connected to the node N4 of the VI converter 10A. A reference potential Vcm is input to the non-inverting input terminal of the operational amplifier 61. The second IV converter 12 converts the second current signal input to the inverting input terminal of the operational amplifier 61 into a second voltage signal, and outputs the second voltage signal from the output terminal of the operational amplifier 61. The output terminal of the operational amplifier 61 is connected to the second output terminal 1d.

The first IV converter 11 and the second IV converter 12 have the same IV conversion characteristics as each other. The resistance value of each of the resistor 52 and the resistor 62 may be fixed. The resistor 52 and the resistor 62 may be a combined resistance circuit having a variable resistance value.

Current adjusting unit 13 adds the current amount [Delta] I ₁ with respect to the current amount of the current signal outputted from the node N3 to the first 1IV converter 11 (-I _r), the input to the 1IV converter 11 1 Adjust the current amount I ₁ of the current signal. The current amount I ₁ of this first current signal is expressed by the following equation (4). The current adjusting unit 13, the current amount of the current signal outputted from the node N4 to the second 2IV converter 12 (+ _{I r)} by adding the amount of current [Delta] I ₂ relative to, the input to the 2IV transducer 12 adjusting the current amount I ₂ of second current signal. The current amount I ₂ of this second current signal is expressed by the following equation (5).

_{The current amounts ΔI 1} and ΔI ₂ applied by the current adjusting unit 13 may be positive, zero, or negative. For example, _{if ΔI 1} is negative, the current amount I ₁ of the first current signal is reduced by the absolute value of ΔI _1. It _{is preferable that the absolute values of ΔI 1} and ΔI ₂ are equal to each other, one is positive and the other is negative. It is preferable that _{ΔI 1} and ΔI _{2 are variable.}

Assuming that the resistance values of the resistor 52 and the resistor 62 are r _f , the voltage value Voutp of the first voltage signal output from the first output terminal 1c is represented by the following equation (6). The voltage value Voutn of the second voltage signal output from the second output terminal 1d is represented by the following equation (7).

When a differential signal (Vinp, Vinn) is input to the first input terminal 1a and the second input terminal 1b, the differential signal (Voutp, Voutn) is output from the first output terminal 1c and the second output terminal 1d. .. The voltage value Vinn input to the second input terminal 1b may be fixed, and a single-ended signal (Vinp) may be input to the first input terminal 1a. In this case as well, the first output terminal 1c and the second A differential signal (Voutp, Voutn) is output from the output terminal 1d.

The difference (Voutp-Voutn) of the voltage values output from each of the first output terminal 1c and the second output end 1d is expressed by the following equation (8). In the first term on the right side of the equation (8), 2 r _f / r _r is a coefficient multiplied by the difference (Vinp-Vinn) of the voltage values input to each of the first input terminal 1a and the second input end 1b. It corresponds to the gain of the amplifier circuit 1A. The gain is inversely proportional to _{the resistance value r r} of the first resistance circuit 2. _{If the resistance value r r} of the first resistance circuit 2 is variable, the gain is also variable. Further, the second term on the right side of the equation (8) corresponds to an offset added to the output differential signal. _{If the current amounts ΔI 1} and ΔI ₂ applied by the current adjusting unit 13 are variable, the offset is also variable.

The relationship between the input voltage value difference (Vinp-Vinn) in the amplifier circuit 1A and the drain currents I _d1 and I _d2 is shown in FIG. As shown in this figure, _{by increasing the resistance value r r of the first resistance circuit 2, the drain currents I d1} and I _d2 are linear with respect to the input voltage value difference in a wide range of the input voltage value difference. Increase or decrease. _{Further, increasing the resistance value r r} of the first resistance circuit 2 reduces the gain. That is, when the difference between the input voltage values extends over a relatively wide range, the resistance value r _r of the first resistance circuit 2 may be made relatively large, whereby the gain can be made relatively small. .. On the contrary, when the difference between the input voltage values remains in a relatively narrow range, the resistance value r _r of the first resistance circuit 2 may be made relatively small, thereby increasing the gain relatively. it can. _{Further, even if the gain is changed by adjusting the resistance value r r} of the first resistance circuit 2, the change in noise of the output voltage signal is small. Further, since the input voltage signal is applied to the gates of the first MOS transistor 31 and the second MOS transistor 32, the input impedance is high. In this way, the amplifier circuit 1A can harmoniously satisfy the requirements of a wide input range, low noise, and high input impedance, and the output signal from the linear sensor in an image acquisition device such as a scanner, a facsimile transmitter / receiver, and a copier. Can be suitably used when processing.

Considering the VI converter 10A alone, the nodes N3 and N4, which are the output ends of the VI converter 10A, have high impedance. However, since the first IV converter 11 and the second IV converter 12 are provided after the VI converter 10A, the nodes N3 and N4 of the VI converter 10A in the first stage to the first IV converter 11 and the second IV in the latter stage. Even if a current flows through the converter 12, the potentials of the nodes N3 and N4 are maintained at V cm, so that the nodes N3 and N4 have low impedance.

When the drive voltage of the load circuit provided after the amplifier circuit 1A is lower than the drive voltage of the amplifier circuit 1A, the reference potential Vcm given to the first IV converter 11 and the second IV converter 12 may be set to an appropriate value. .. That is, the first IV converter 11 and the second IV converter 12 can also serve as a level conversion stage.

In the amplifier circuit 1A, the VI converter 10A in the front stage and the first IV converter 11 and the second IV converter 12 in the rear stage are connected by a current interface. _{From this, the current amounts I 1} and I ₂ input to the first IV converter 11 and the second IV converter 12 in the subsequent stage can be adjusted by the current adjusting unit 13, and the offset of the output signal can be adjusted. it can. Further, since the input impedances of the first IV converter 11 and the second IV converter 12 are low, even if the parasitic capacitance is large, the influence is small.

Since the first IV converter 11 and the second IV converter 12 in the subsequent stage can be designed independently of the VI converter 10A in the previous stage, they can be configured to have a drive capability according to the load.

FIG. 3 is a diagram showing the configuration of the amplifier circuit 1A of the first configuration example. In this figure, in particular, each constant current source in the VI converter 10A in FIG. 1 is represented by a MOS transistor. The MOS transistor M1 in FIG. 3 corresponds to the first MOS transistor 31 in FIG. The MOS transistor M2 corresponds to the second MOS transistor 32. The MOS transistor M3 corresponds to the third constant current source 43, and a reference potential Vbbn is given to the gate. The MOS transistor M4 corresponds to the fourth constant current source 44, and a reference potential Vbbn is given to the gate. The MOS transistor M5 corresponds to the first constant current source 41, and a reference potential Vbbp is given to the gate. The MOS transistor M6 corresponds to the second constant current source 42, and a reference potential Vbbp is given to the gate.

The first constant current source 41 (MOS transistor M5), the second constant current source 42 (MOS transistor M6), the third constant current source 43 (MOS transistor M3), and the fourth constant current source 44 (MOS transistor M4) each flow. The change in the amount of current affects the amount of current output from the VI converter 10A to the first IV converter 11 and the second IV converter 12, and the voltage value output from the first output terminal 1c and the second output end 1d. Affects (Voutp, Voutn). Therefore, it is required that the change in the amount of current flowing through each of the first constant current source 41, the second constant current source 42, the third constant current source 43, and the fourth constant current source 44 is sufficiently small.

For example, when the voltage value Vinn input to the second input terminal 1b is fixed and a single-ended signal (Vinp) is input to the first input terminal 1a, the voltage value is used to secure the input range as wide as possible. It is preferable to set Vinn close to the upper or lower limit of the input range so that the single-ended signal (Vinp) can vary over a wide range. Not limited to this case, when the voltage value input to the first input terminal 1a or the second input end 1b changes in a wide range, the potential of the node N1 or the node N2 changes significantly, and the first constant current source 41 The amount of current flowing through the (MOS transistor M5) or the second constant current source 42 (MOS transistor M6) may change. As a result, the voltage values (Voutp, Voutn) output from the first output terminal 1c and the second output end 1d may change. That is, the linearity of the output voltage value (Voutp, Voutn) with respect to the input voltage value (Vinp, Vinn) may be low.

The cascode configuration is known as a technique for suppressing a change in the amount of current of a constant current source in order to improve linearity. However, since the cascode configuration narrows the input range, it is difficult to adopt it in an amplifier circuit aiming at a wide input range. Therefore, it is not preferable that the constant current source has a cascode configuration, and it is inevitable that the amount of current changes according to the input voltage value.

When the potential of the node N1 changes due to the change of the voltage value Vinp of the first input terminal 1a, and the current amount of the first constant current source 41 (MOS transistor M5) changes by δI, the node N3 is converted to the first IV. The amount of current output to the device 11 also changes by δI. As a result, the difference (Voutp-Voutn) of the voltage values output from each of the first output terminal 1c and the second output end 1d changes by _{r f δ I.}

FIG. 4 is a graph showing an example of the relationship between the _{drain voltage V d} and the drain current I _d of the MOS transistor as a constant current source. Here, the source voltage of the MOS transistor is 3.3 V, and the gate voltage is set so that the amount of current flowing through the MOS transistor is around 50 μA. The drain voltage V _d was changed in the range of 1.3 _{V to 2.8 V, and the drain current I d} was obtained by simulation calculation. In addition to showing the simulation results, this figure shows _{a straight line when the relationship between the drain voltage V d} and the drain current I _d is approximated by a linear function expression, and this relationship is approximated by a quadratic function expression. The curve is also shown.

When the relationship between the drain voltage V _d [unit V] and the drain current I _d [unit μA] is approximated by a linear function expression, the relationship between the two is an approximate expression of _{I d} ≈ -1.12019V _{d + 52.52034.} It is represented by. This indicates that the drain current I _d is also changed 2% by a change in 1V input voltage difference. However, if the relationship between the two can be approximated sufficiently accurately by a linear function expression, the gain of the amplifier circuit will change only slightly, and the problem of non-linearity of the input / output characteristics of the amplifier circuit will be a problem. small.

On the other hand, _{the relationship between the drain voltage V d} and the drain current I _d cannot be approximated sufficiently accurately by the linear function formula, and this relationship can be approximated by a higher-order functional formula of quadratic or higher. If there is no choice but to do so, higher-order terms cannot be ignored. When approximated by a quadratic function formula, the relationship between the ^two is expressed by the approximate formula _{I d} ≈ -0.4281V _d 2 + 0.6349V _{d + 50.803.} If the quadratic term of this approximate expression cannot be ignored, the problem of non-linearity of the input / output characteristics of the amplifier circuit becomes large. The configuration example of the amplifier circuit described below is intended to solve such a problem.

(Example of second configuration of amplifier circuit)
FIG. 5 is a diagram showing the configuration of the amplifier circuit 1B of the second configuration example. The amplifier circuit 1B includes a VI converter 10B, a first IV converter 11, and a second IV converter 12. It is preferable that the amplifier circuit 1B further includes a current adjusting unit 13. Compared with the configuration of the amplifier circuit 1A of the first configuration example shown in FIG. 3, the amplifier circuit 1B of the second configuration example shown in FIG. 5 includes a VI converter 10B instead of the VI converter 10A. It's different.

The VI converter 10B includes a first resistance circuit 2 and MOS transistors M1 to M12. The first resistance circuit 2 is provided between the node N1 and the node N2. The resistance value of the first resistance circuit 2 may be fixed. The first resistance circuit 2 may be a single resistor. The first resistance circuit 2 may be a combined resistance circuit having a variable resistance value. Each of the MOS transistors M1 to M12 has a gate, a source and a drain.

The source of the MOS transistor M1 is connected to the node N1. The drain of the MOS transistor M1 is connected to the node N3. The source of the MOS transistor M2 is connected to the node N2. The drain of the MOS transistor M2 is connected to the node N4. The gate of the MOS transistor M3 is connected to the node N7. The drain of the MOS transistor M3 is connected to the node N3. The gate of the MOS transistor M4 is connected to the node N8. The drain of the MOS transistor M4 is connected to the node N4. The drain of the MOS transistor M5 is connected to the node N1. The drain of the MOS transistor M6 is connected to the node N2.

The source of the MOS transistor M7 is connected to the node N5. The drain of the MOS transistor M7 is connected to the node N7. The source of the MOS transistor M8 is connected to the node N6. The drain of the MOS transistor M8 is connected to the node N8. The gate and drain of the MOS transistor M9 are connected to the node N7. The gate and drain of the MOS transistor M10 are connected to the node N8. The drain of the MOS transistor M11 is connected to the node N5. The drain of the MOS transistor M12 is connected to the node N6.

The gates of the MOS transistors M1 and M7 are connected to the first input terminal 1a. The gates of the MOS transistors M2 and M8 are connected to the second input terminal 1b. The sources of the MOS transistors M5, M6, M11, and M12 are connected to the first reference potential input terminal. The sources of the MOS transistors M3, M4, M9, and M10 are connected to the second reference potential input terminal. Each of the MOS transistors M5, M6, M11, and M12 is a constant current source, and a reference potential Vbbp is given to the gate.

For example, when the first reference potential is higher than the second reference potential, the MOS transistors M1, M2, M5 to M8, M11, and M12 are MOSFET transistors, and the MOS transistors M3, M4, M9, and M10 are NMOS transistors. is there. Alternatively, when the first reference potential is lower than the second reference potential, the MOS transistors M1, M2, M5 to M8, M11, and M12 are NMOS transistors, and the MOS transistors M3, M4, M9, and M10 are MOSFET transistors. is there.

The MOS transistors M7 and M11 are replicas of the MOS transistors M1 and M5, and carry a current amount p times the amount of the current flowed by the MOS transistor M5. The MOS transistors M3 and M9 form a current mirror circuit having a mirror ratio of 1: p. As a result, the drain current of the MOS transistor M3 becomes the same as the drain current of the MOS transistor M5. Therefore, even if the potential of the node N1 changes due to the change of the voltage value Vinp of the first input terminal 1a and the current amount of the MOS transistor M5 changes, the amount of current output from the node N3 to the first IV converter 11 remains. It does not change.

The MOS transistors M8 and M12 are replicas of the MOS transistors M2 and M6, and carry a current amount q times the amount of the current flowed by the MOS transistor M6. The MOS transistors M4 and M10 form a current mirror circuit having a mirror ratio of 1: q. As a result, the drain current of the MOS transistor M4 becomes the same as the drain current of the MOS transistor M6. Therefore, even if the potential of the node N2 changes due to the change of the voltage value Vinn of the second input terminal 1b and the current amount of the MOS transistor M6 changes, the amount of current output from the node N4 to the second IV converter 12 remains. It does not change.

Each value of p and q is arbitrary and may be 1 or less than 1. The smaller each value of p and q is, the smaller the amount of current flowing through the replica is, which is preferable in terms of reducing power consumption. However, if the amount of current flowing through the replica is too small, the operating speed of the replica tends to be slow and noise tends to be large. Therefore, each value of p and q is preferably less than 1 and preferably 0.1 or more, and more preferably 0.2 or more.

The current amount _{I r} flowing in the first resistor circuit 2 is flowing through the MOS transistors M1, it does not flow through the MOS transistor M7. Therefore, since the potentials of the nodes N1 and N5 are slightly different from each other, strictly speaking, the current amount of the MOS transistor M11 is slightly different from p times the current amount of the MOS transistor M5. However, since this difference in the amount of current is significantly compressed with respect to the change in the input voltage value Vinp, it is relatively small as a non-linear factor and can be ignored. The same applies to the MOS transistors M6 and M12.

Next, the results of a simulation performed to compare the linearity of the input / output characteristics of the amplifier circuit 1A (FIG. 3) of the first configuration example and the amplifier circuit 1B (FIG. 5) of the second configuration example will be described.

FIG. 6 is a diagram showing the relationship between the input voltage value Vinp and the output current difference in each of the amplifier circuit 1A (FIG. 3) of the first configuration example and the amplifier circuit 1B (FIG. 5) of the second configuration example. Here, Vinn was fixed at 1.8V and Vinp was changed. The amount of current output from the node N3 to the first IV converter 11 in the amplifier circuit 1B of the second configuration example showed good linearity in a certain range of the input voltage value Vinp, and therefore, in that range, between the two. The relationship was approximated by a linear function equation. The output current difference on the vertical axis shows the difference with respect to the amount of current obtained from this linear function equation. As shown in this figure, in the first configuration example, distortion is observed over the entire input range, whereas in the second configuration example, good linearity can be obtained over a wide input range.

FIG. 7 is a diagram showing time waveforms of output voltage values (Voutp, Voutn) in each of the amplifier circuit 1A (FIG. 3) of the first configuration example and the amplifier circuit 1B (FIG. 5) of the second configuration example. In each configuration example, the input voltage value Vinp was a square wave. As shown in this figure, the high / low levels are aligned in the second configuration example as compared with the first configuration example.

FIG. 8 shows the common voltage ((Voutp + Voutn) / 2) and voltage difference (Voutp−) of the differential output in the amplifier circuit 1A (FIG. 3) of the first configuration example and the amplifier circuit 1B (FIG. 5) of the second configuration example, respectively. Voutn) It is a figure which shows each time waveform. This figure is obtained from the time waveform of the output voltage value of FIG. As shown in this figure, in the second configuration example, the fluctuation of the common voltage at the transition of the input voltage value is small as compared with the first configuration example, and the common voltage is constant during the period other than the transition of the input voltage value. Is. Further, the amplitude of the voltage difference is smaller in the second configuration example than in the first configuration example.

In the first configuration example, when the input voltage value Vinp decreases, the current of the MOS transistor M5 increases, and the current flowing out from the node N3 increases, so that the amplitude of the voltage difference increases. In the first configuration example, when the input voltage value Vinp is high level, the voltage is the same as Vinn, so the output level is also the same. In the first configuration example, the common voltage fluctuates according to the input voltage value due to the asymmetry of the output level with respect to the input level. On the other hand, in the second configuration example, there is almost no dependence on the input level of the common voltage.

(Third configuration example of an amplifier circuit)
FIG. 9 is a diagram showing the configuration of the amplifier circuit 1C of the third configuration example. The amplifier circuit 1C includes a VI converter 10C, a first IV converter 11, and a second IV converter 12. It is preferable that the amplifier circuit 1C further includes a current adjusting unit 13.

Compared with the configuration of the amplifier circuit 1B of the second configuration example shown in FIG. 5, the amplifier circuit 1C of the third configuration example shown in FIG. 9 is provided with the VI converter 10C instead of the VI converter 10B. It's different. Compared with the VI converter 10B in the second configuration example, the VI converter 10C in the third configuration example is different in that the second resistance circuit 3 is further included. The second resistance circuit 3 is provided between the node N3 and the node N4. The resistance value of the second resistance circuit 3 may be fixed or variable.

The potentials of the nodes N3 and N4, which are the output ends of the VI converter 10B in the second configuration example, are theoretically fixed at the reference potential Vcm and do not fluctuate. However, in reality, when the input voltage signal contains a high frequency component, the fluctuation of the potential of the nodes N3 and N4 may not be negligible. The fluctuation of the potential of the nodes N3 and N4 appears as a settling delay of the output voltage value difference (Voutp-Voutn).

On the other hand, in the VI converter 10C in the third configuration example, the fluctuation of the potential of the nodes N3 and N4 is suppressed by providing the second resistance circuit 3 between the node N3 and the node N4. This makes it possible to accelerate the setting of the output voltage value difference (Voutp-Voutn).

Since the second resistance circuit 3 is theoretically provided between the nodes N3 and N4 where there is no potential difference, when the input voltage signal does not contain a high frequency component, the contribution to the amplification operation or the performance is small. When the input voltage signal contains a high frequency component, the second resistance circuit 3 can alleviate the potential difference between the nodes N3 and N4 caused by the delay of the circuit operation and approach the ideal amplification operation.

(Fourth configuration example of an amplifier circuit)
FIG. 10 is a diagram showing the configuration of the amplifier circuit 1D of the fourth configuration example. The amplifier circuit 1D includes a VI converter 10D, a first IV converter 11, and a second IV converter 12. It is preferable that the amplifier circuit 1D further includes a current adjusting unit 13.

Compared with the configuration of the amplifier circuit 1B of the second configuration example shown in FIG. 5, the amplifier circuit 1D of the fourth configuration example shown in FIG. 10 is provided with the VI converter 10D instead of the VI converter 10B. It's different. Compared with the VI converter 10B in the second configuration example, the VI converter 10D in the fourth configuration example is different in that the MOS transistors M8, M10, and M12 are not provided, and the MOS transistor M4 is a constant current source. The difference is that the reference potential Vbbn is given to the gate.

When the voltage value Vinn input to the second input terminal 1b is fixed and a single-ended signal (Vinp) is input to the first input terminal 1a, the first input terminal 1a is as in this configuration example. A replica (MOS transistors M7, M11) and a current mirror circuit (MOS transistors M3, M9) may be provided only on the side of.

(Modification example of amplifier circuit)
The amplifier circuit of the present invention is not limited to the above configuration example, and various modifications can be made. For example, the first IV converter 11 and the second IV converter 12 can have any configuration. The second resistance circuit 3 in the amplifier circuit 1C of the third configuration example may also be provided in the amplifier circuit 1D of the fourth configuration example. Conventional linearization techniques may be combined to further improve linearity.

The first resistance circuit 2 may be a combined resistance circuit having a variable resistance value as described above. In that case, the first resistance circuit 2 may have a configuration in which a resistor and a switch are connected in series as a constituent unit, and a plurality of constituent units are connected in parallel. The first resistance circuit 2 may have a configuration in which a resistor and a switch are connected in parallel as a constituent unit, and a plurality of constituent units are connected in series. The first resistance circuit 2 is preferably a combined resistance circuit 2A to 2D described below.

(First configuration example of combined resistance circuit)
FIG. 11 is a circuit diagram of the combined resistance circuit 2A of the first configuration example. The combined resistance circuit 2A includes a first network 20A between the first end 2a and the second end 2b. The first network 20A includes resistors R1 to R5 and switches SW0 and SW1.

The resistor R1 is provided between the node N11 and the node N12. The resistor R2 and the switch SW1 are connected in series with each other and are provided between the node N12 and the node N13. The resistor R3 is provided between the node N13 and the node N14. The resistor R4 and the switch SW0 are connected in series with each other and are provided between the node N14 and the node N11. The resistor R5 is provided between the node N11 and the node N13. The node N12 is connected to the first end 2a. Node N14 is connected to the second end 2b. The combined resistance circuit 2A can have a combined resistance value between the first end 2a and the second end 2b according to the on / off state of each of the two switches SW0 and SW1.

The control signal for controlling the on / off of each of the two switches SW0 and SW1 can be represented by a 2-bit binary number (b1, b0). The switch SW0 is in the off state when b0 = 0, and is in the on state when b0 = 1. The switch SW1 is in the off state when b1 = 0, and is in the on state when b1 = 1. In this example, no circuit is needed to decode the control signal.

The resistance value of the resistor R1 and _{r 1.} Let the resistance value of the resistor R2 be r ₂ . The resistance value of the resistor R3 and _{r 3.} The resistance value of the resistor R4 and _{r 4.} The resistance value of the resistor R5 and _{r 5.} When the control signal has a value of 00b, both the switch SW1 and the switch SW0 are turned off, and the combined resistance value r _00b of the combined resistance circuit 2A is represented by the following equation (9). When the control signal has a value of 01b, the switch SW1 is turned off, the switch SW0 is turned on, and the combined resistance value r _01b of the combined resistance circuit 2A is represented by the following equation (10). When the control signal has a value of 10b, the switch SW1 is turned on, the switch SW0 is turned off, and the combined resistance value r _10b of the combined resistance circuit 2A is represented by the following equation (11). When the control signal has a value of 11b, both the switch SW1 and the switch SW0 are turned on, and the combined resistance value r _11b of the combined resistance circuit 2A is represented by the following equation (12). In Eqs. (10) and (11), in the operator //, the resistor having the resistance value x and the resistor having the resistance value y are connected in parallel by the equation x // y = xy / (x + y). Represents the operation of finding the combined resistance value of the resistance circuit.

These combined resistance value r _00b, r _01b, so r _10b, r _11b becomes a desired value, the resistance value _r 1 ~r ₅ resistors R1~R5 may be set. For example, the following (13) the combined resistance value as represented by the formula r _00b, r _01b, as r _10b, r _11b is geometric series of common ratio m, resistor the resistance of R1 to R5 _{r 1} ~ R ₅ can be set.

Whereas unknown (resistance value _r 1 ~r ₅₎ is five, since equation (Equation (9) to (12) below) is four, uniquely determines the resistance value _r 1 ~r ₅ You may not be able to. Therefore, it is preferable to set a constraint that the resistivity ratio (r ₃ / r ₁ ) and the resistivity ratio (r ₄ / r ₂ ) are equal to each other, that is, a constraint that the relationship represented by the following equation (14) is satisfied. .. By providing such a constraint, the number of unknowns can be increased to four. Incidentally, it is possible to use a formula processing software in determining the resistance value r ₁ ~r _5.

An example of the resistance value _r 1 ~r ₅ resistors R1~R5 is as follows.
r ₁ = 3842.04Ω
r ₂ = 7670.18Ω
r ₃ = 1200.54Ω
r ₄ = 2399.02Ω
r ₅ = 906.028Ω

FIG. 12 is a table summarizing the combined resistance values for each value of the control signal when the resistors R1 to R5 having these resistance values are used. This figure also shows the ON / OFF state of switches SW0 and SW1 for each value of the control signal. The combined resistance value shown in this figure is slightly different from the geometric progression, but this is so that the gain will be exactly the geometric progression when the combined resistance circuit is applied to the actual variable gain amplifier circuit. This is due to the fact that each resistance value is corrected. Such correction is preferably performed for each circuit.

If a resistor and a switch are provided in series between the two nodes and the on-resistance value of the switch cannot be ignored, the sum of the resistance value of the resistor and the on-resistance value of the switch is the above value. It is preferable to set the resistance value of the resistor as described above.

The combined resistance circuit 2A of this configuration example can have four desired combined resistance values by using two switches. Since the number of switches is small, the influence of parasitic capacitance can be reduced. Since the decoding circuit is unnecessary and the resistance matrix is small, the layout area can be reduced when the combined resistance circuit 2A is formed on the semiconductor substrate.

(Second configuration example of combined resistance circuit)
FIG. 13 is a circuit diagram of the combined resistance circuit 2B of the second configuration example. The combined resistance circuit 2B includes a first network 20A and a second network 20B between the first end 2a and the second end 2b. Compared with the configuration of the combined resistance circuit 2A of the first configuration example shown in FIG. 11, the combined resistance circuit 2B of the second configuration example shown in FIG. 13 is located between the first end 2a and the second end 2b. The difference is that a second network 20B is further provided. The second network 20B is provided in parallel with the first network 20A. The second network 20B includes resistors R6 to R10 and switches SW2 to SW4.

The resistor R6 and the switch SW2 are connected in series with each other and are provided between the node N21 and the node N22. The resistor R7 and the switch SW4 are connected in series with each other and are provided between the node N22 and the node N23. The resistor R8 is provided between the node N23 and the node N24. The resistor R9 and the switch SW3 are connected in series with each other and are provided between the node N24 and the node N21. The resistor R10 is provided between the node N21 and the node N23. The node N22 is connected to the first end 2a. The node N24 is connected to the second end 2b. The combined resistance circuit 2B can have a combined resistance value between the first end 2a and the second end 2b according to the on / off state of each of the five switches SW0 to SW4.

As an example, the control signal for controlling the on / off of each of the five switches SW0 to SW4 can be represented by a 3-bit binary number (b2, b1, b0). The switch SW0 is in the off state when b0 = 0, and is in the on state when b0 = 1. The switch SW1 is in the off state when b1 = 0, and is in the on state when b1 = 1. The switch SW2 is in the off state when b2 = 0, and is in the on state when b2 = 1. The switch SW3 is in the off state when b0 & b2 = 0, and is in the on state when b0 & b2 = 1. The switch SW4 is in the off state when b1 & b2 = 0, and is in the on state when b1 & b2 = 1. The operator & represents an operation to obtain a logical product.

A decoding circuit is used in this example. The decoding circuit inputs a control signal represented by a 3-bit binary number (b2, b1, b0). Then, this decoding circuit outputs the value of the logical product of the bit b0 and the bit b2 and gives it to the switch SW3, and also outputs the value of the logical product of the bit b1 and the bit b2 and gives it to the switch SW4.

When b2 = 0, all of the three switches SW2 to SW4 in the second network 20B are turned off, so that the combined resistance value of the combined resistance circuit 2B is the same as in the case of the first configuration example. It becomes the combined resistance value of the first network 20A corresponding to each value of bits b1 and b0. When b2 = 1, the combined resistance value of the combined resistance circuit 2B is the combined resistance value of the first network 20A and the second network 20B connected in parallel. The combined resistance value of the second network 20B when b2 = 1 is a value corresponding to each value of the bits b1 and b0. Resistance _r 6 _{~r 10} of resistor _R 6 _{to R 10} of the second network 20B is set in the same manner as the method of setting the resistance value _r 1 ~r ₅ of the first network 20A in the first configuration example be able to.

An example of the resistance value _r 1 _{~r 10} resistor R1~R10 is as follows.
r ₁ = 3842.04Ω
r ₂ = 7670.18Ω
r ₃ = 1200.54Ω
r ₄ = 2399.02Ω
r ₅ = 906.028Ω
r ₆ = 3497.20Ω
r ₇ = 5948.26Ω
r ₈ = 1172.25Ω
r ₉ = 1993.024Ω
r ₁₀ = 797.874Ω

FIG. 14 is a table summarizing the combined resistance values for each value of the control signal when the resistors R1 to R10 having these resistance values are used. This figure also shows the on / off state of switches SW0 to SW4 for each value of the control signal.

If a resistor and a switch are provided in series between the two nodes and the on-resistance value of the switch cannot be ignored, the sum of the resistance value of the resistor and the on-resistance value of the switch is the above value. It is preferable to set the resistance value of the resistor as described above.

The combined resistance circuit 2B of this configuration example can have at least eight desired combined resistance values using five switches. Since the number of switches is small, the influence of parasitic capacitance can be reduced. Since the configuration of the decoding circuit is simple and the resistance matrix is small, the layout area can be reduced when the combined resistance circuit 2B is formed on the semiconductor substrate.

(Third configuration example of combined resistance circuit)
FIG. 15 is a circuit diagram of the combined resistance circuit 2C of the third configuration example. The combined resistance circuit 2C includes a first network 20A and a third network 20C between the first end 2a and the second end 2b. Compared with the configuration of the combined resistance circuit 2B of the second configuration example shown in FIG. 13, the combined resistance circuit 2C of the third configuration example shown in FIG. 15 replaces the second network 20B with the third network 20C. It differs in that it has. The third network 20C is provided in parallel with the first network 20A. The third network 20C includes resistors R6 to R10 and switches SW2 to SW4.

In the second network 20B in the second configuration example, the switch SW2 is connected in series with the resistor R6 and is provided between the node N21 and the node N22. On the other hand, in the third network 20C in the third configuration example, the switch SW2 is connected in series with the resistor R10 and is provided between the node N21 and the node N23. The combined resistance circuit 2C can have a combined resistance value between the first end 2a and the second end 2b according to the on / off state of each of the five switches SW0 to SW4.

Similar to the combined resistance circuit 2B of the second configuration example, the combined resistance circuit 2C of the third configuration example controls on / off of each of the five switches SW0 to SW4 as an example, as shown in FIG. The control signal can be represented by a 3-bit binary number (b2, b1, b0), and the combined resistance value for each value of the control signal can be set by setting each resistance value of the resistors R1 to R10. ..

The combined resistance circuit 2C of this configuration example can also have at least eight desired combined resistance values using five switches. Since the number of switches is small, the influence of parasitic capacitance can be reduced. Since the configuration of the decoding circuit is simple and the resistance matrix is small, the layout area can be reduced when the combined resistance circuit 2C is formed on the semiconductor substrate.

(Fourth configuration example of combined resistance circuit)
FIG. 16 is a circuit diagram of the combined resistance circuit 2D of the fourth configuration example. The combined resistance circuit 2D includes a first network 20A and a fourth network 20D between the first end 2a and the second end 2b. Compared with the configuration of the combined resistance circuit 2B of the second configuration example shown in FIG. 13, the combined resistance circuit 2D of the fourth configuration example shown in FIG. 16 replaces the second network 20B with the fourth network 20D. It differs in that it has. The fourth network 20D is provided in parallel with the first network 20A. The fourth network 20D includes resistors R6 to R10 and switches SW2 to SW4.

In the second network 20B in the second configuration example, the switch SW2 is connected in series with the resistor R6 and is provided between the node N21 and the node N22. On the other hand, in the fourth network 20D in the fourth configuration example, the switch SW2 is provided between the node N24 and the second end 2b. The combined resistance circuit 2D can have a combined resistance value between the first end 2a and the second end 2b according to the on / off state of each of the five switches SW0 to SW4.

As an example, the control signal for controlling the on / off of each of the five switches SW0 to SW4 can be represented by a 3-bit binary number (b2, b1, b0). The switch SW0 and the switch SW3 are in the off state when b0 = 0, and are in the on state when b0 = 1. The switch SW1 and the switch SW4 are in the off state when b1 = 0, and are in the on state when b1 = 1. The switch SW2 is in the off state when b2 = 0, and is in the on state when b2 = 1. In this example, no circuit is needed to decode the control signal.

When b2 = 0, the switch SW2 in the fourth network 20D is turned off, so that the combined resistance value of the combined resistance circuit 2D is the value of each of the bits b1 and b0, as in the case of the first configuration example. It becomes the combined resistance value of the first network 20A according to. When b2 = 1, the combined resistance value of the combined resistance circuit 2D is the combined resistance value of the first network 20A and the fourth network 20D connected in parallel. The combined resistance value of the fourth network 20D when b2 = 1 is a value corresponding to each value of the bits b1 and b0.

In the combined resistance circuit 2D of the fourth configuration example, similarly to the combined resistance circuit 2B of the second configuration example, the control signal for controlling the on / off of each of the five switches SW0 to SW4 is a 3-bit binary number (b2, b2). It can be represented by b1 and b0), and the combined resistance value for each value of the control signal can be set by setting each resistance value of the resistors R1 to R10. FIG. 17 is a table summarizing the combined resistance values for each value of the control signal when the resistors R1 to R10 having these resistance values are used. This figure also shows the on / off state of switches SW0 to SW4 for each value of the control signal.

If a resistor and a switch are provided in series between the two nodes and the on-resistance value of the switch cannot be ignored, the sum of the resistance value of the resistor and the on-resistance value of the switch is the above value. It is preferable to set the resistance value of the resistor as described above. If the on-resistance of the switch SW2 is not negligible, the node N22, the resistance value of the resistor R6~R10 so that the sum becomes a desired value of the on resistance value of the combined resistance value and the switch SW2 between N24 _r 6 ~ it is preferable to set the r _10.

The combined resistance circuit 2D of this configuration example can have at least eight desired combined resistance values using five switches. Since the number of switches is small, the influence of parasitic capacitance can be reduced. Since the decoding circuit is unnecessary and the resistance matrix is small, the layout area can be reduced when the combined resistance circuit 2D is formed on the semiconductor substrate.

(Modification example of combined resistance circuit)
The combined resistance circuit is not limited to the combined resistance circuits 2A to 2D of the first to fourth configuration examples, and various modifications can be made. For example, in the second configuration example, the switch SW2 may be provided between the node N23 and the node N24 instead of the configuration in which the switch SW2 is provided between the node N21 and the node N22. Equivalent. Further, in the fourth configuration example, instead of the configuration in which the switch SW2 is provided between the node N24 and the second end 2b, the switch SW2 may be provided between the node N22 and the first end 2a. It is also equivalent as a simple configuration.

The combined resistance circuit has a configuration in which two or more networks of the same type or different types of any one of the second network 20B, the third network 20C, and the fourth network 20D are provided in parallel with the first network 20A. May be. The combined resistance circuit may be configured such that resistors are provided in series or in parallel with respect to the first network 20A. Further, the combined resistance circuit may be configured to provide resistors and switches connected in series or in parallel to the first network 20A in parallel.

The resistors R1 to R10 may be a single resistor, or may have a configuration in which a plurality of resistors are connected in series or in parallel. When forming a resistor on a semiconductor substrate, there is a range of resistance values that can be easily realized. Therefore, in order to realize a resistance value that deviates from that range, a plurality of resistors having resistance values within that range are connected in series or in parallel. It is preferable that the configuration is connected to.

1A to 1D ... Amplification circuit, 1a ... 1st input end, 1b ... 2nd input end, 1c ... 1st output end, 1d ... 2nd output end, 2 ... 1st resistance circuit, 2A to 2D ... Combined resistance circuit, 2a ... 1st end, 2b ... 2nd end, 10A, 10B ... VI converter, 11 ... 1st IV converter, 12 ... 2nd IV converter, 13 ... Current regulator, 20A ... 1st network, 20B ... 1st 2 network, 20C ... 3rd network, 20D ... 4th network, 31 ... 1st MOS transistor, 32 ... 2nd MOS transistor, 41 ... 1st constant current source, 42 ... 2nd constant current source, 43 ... 3rd Constant current source, 44 ... 4th constant current source, 51 ... Computational amplifier, 52 ... Resistor, 61 ... Computational amplifier, 62 ... Resistor, M1 to M12 ... MOS transistor, N1 to N4, N11 to N14, N21 to N24 ... Node, R1 to R10 ... Resistor, SW0 to SW4 ... Switch.

Claims (6)

It is equipped with a VI converter, a 1st IV converter and a 2nd IV converter.
The VI converter
The first resistance circuit provided between the node N1 and the node N2,
A first conductive MOS transistor M1 having a gate, a source connected to the node N1, and a drain connected to the node N3.
A first conductive MOS transistor M2 having a gate, a source connected to the node N2, and a drain connected to the node N4.
A second conductive MOS transistor M3 having a gate connected to the node N7, a source, and a drain connected to the node N3.
A second conductive MOS transistor M4 having a gate connected to the node N8, a source, and a drain connected to the node N4.
A first conductive MOS transistor M5 having a gate, a source, and a drain connected to the node N1.
A first conductive MOS transistor M6 having a gate, a source, and a drain connected to the node N2.
A first conductive MOS transistor M7 having a gate, a source connected to a node N5, and a drain connected to the node N7.
A first conductive MOS transistor M8 having a gate, a source connected to a node N6, and a drain connected to the node N8.
A second conductive MOS transistor M9 having a gate connected to the node N7, a source, and a drain connected to the node N7.
A second conductive MOS transistor M10 having a gate connected to the node N8, a source, and a drain connected to the node N8.
A first conductive MOS transistor M11 having a gate, a source, and a drain connected to the node N5.
A first conductive MOS transistor M12 having a gate, a source, and a drain connected to the node N6.
Including
The gates of the MOS transistors M1 and M7 are connected to the first input terminal, and the gates are connected to the first input terminal.
The gates of the MOS transistors M2 and M8 are connected to the second input end, and the gates are connected.
The sources of the MOS transistors M5, M6, M11, and M12 are connected to the first reference potential input terminal.
The sources of the MOS transistors M3, M4, M9, and M10 are connected to the second reference potential input end.
Each of the MOS transistors M5, M6, M11, and M12 is a constant current source.
The MOS transistors M7 and M11 are replicas of the MOS transistors M1 and M5, and a current amount p times the amount of the current flowed by the MOS transistor M5 is passed.
The MOS transistors M3 and M9 form a current mirror circuit having a mirror ratio of 1: p.
The MOS transistors M8 and M12 are replicas of the MOS transistors M2 and M6, and carry a current amount q times the current amount flowd by the MOS transistor M6.
The MOS transistors M4 and M10 form a current mirror circuit having a mirror ratio of 1: q.
The first IV converter is connected to the node N3, converts an input first current signal into a first voltage signal, and outputs the first voltage signal.
The second IV converter is connected to the node N4, converts an input second current signal into a second voltage signal, and outputs the second voltage signal.
Amplifier circuit. It is equipped with a VI converter, a 1st IV converter and a 2nd IV converter.
The VI converter
The first resistance circuit provided between the node N1 and the node N2,
A first conductive MOS transistor M1 having a gate, a source connected to the node N1, and a drain connected to the node N3.
A first conductive MOS transistor M2 having a gate, a source connected to the node N2, and a drain connected to the node N4.
A second conductive MOS transistor M3 having a gate connected to the node N7, a source, and a drain connected to the node N3.
A second conductive MOS transistor M4 having a gate, a source, and a drain connected to the node N4.
A first conductive MOS transistor M5 having a gate, a source, and a drain connected to the node N1.
A first conductive MOS transistor M6 having a gate, a source, and a drain connected to the node N2.
A first conductive MOS transistor M7 having a gate, a source connected to a node N5, and a drain connected to the node N7.
A second conductive MOS transistor M9 having a gate connected to the node N7, a source, and a drain connected to the node N7.
A first conductive MOS transistor M11 having a gate, a source, and a drain connected to the node N5.
Including
The gates of the MOS transistors M1 and M7 are connected to the first input terminal, and the gates are connected to the first input terminal.
The gate of the MOS transistor M2 is connected to the second input end,
The sources of the MOS transistors M5, M6, and M11 are connected to the first reference potential input end.
The sources of the MOS transistors M3, M4, and M9 are connected to the second reference potential input end.
Each of the MOS transistors M5, M6, M11, and M4 is a constant current source.
The MOS transistors M7 and M11 are replicas of the MOS transistors M1 and M5, and a current amount p times the amount of the current flowed by the MOS transistor M5 is passed.
The MOS transistors M3 and M9 form a current mirror circuit having a mirror ratio of 1: p.
The first IV converter is connected to the node N3, converts an input first current signal into a first voltage signal, and outputs the first voltage signal.
The second IV converter is connected to the node N4, converts an input second current signal into a second voltage signal, and outputs the second voltage signal.
Amplifier circuit. The VI converter further includes a second resistance circuit provided between the node N3 and the node N4.
The amplifier circuit according to claim 1 or 2. _{The current amount ΔI 1} is added to the current amount of the current signal output from the node N3 to the first IV converter to adjust the current amount of the first current signal input to the first IV converter. _{, The current amount ΔI 2} is added to the current amount of the current signal output from the node N4 to the second IV converter to adjust the current amount of the second current signal input to the second IV converter. Further equipped with a current adjusting unit,
The amplifier circuit according to any one of claims 1 to 3. The first resistance circuit is a combined resistance circuit having a variable resistance value.
The amplifier circuit according to claim 4. The combined resistance circuit includes a first network provided between the first end and the second end.
The first network is
A resistor R1 provided between the node N11 and the node N12,
A resistor R2 provided between the node N12 and the node N13,
A resistor R3 provided between the node N13 and the node N14,
A resistor R4 provided between the node N14 and the node N11,
A resistor R5 provided between the node N11 and the node N13,
A switch SW0 provided in series with the resistor R4 between the node N14 and the node N11,
A switch SW1 provided in series with the resistor R2 between the node N12 and the node N13,
Including
The node N12 is connected to the first end and
The node N14 is connected to the second end,
The amplifier circuit according to claim 5.

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