JP6900661B2 - Verification equipment, methods and programs - Google Patents

Description

The present invention relates to a technique for testing a system including a processor.

A random test is known in which a system including a processor is made to execute a randomly generated test instruction sequence to detect a malfunction. The detection of fraudulent behavior in the random test is determined by the result of executing the test command sequence to the end. However, in the random test, since the sequence of test instructions is randomly determined, the execution result of the preceding test instruction may be overwritten by the subsequent test instruction without being referred to. In such a case, even if the preceding test instruction causes an illegal operation, the illegal operation is hidden by the subsequent test instruction. As described above, in a general random test, there is a problem that an illegal operation caused by a preceding test instruction may not be detected.

An example of a technique related to such a problem is described in Patent Document 1. This related technique uses a flag indicating whether each register can be changed when generating a test instruction sequence. Specifically, this related technique updates the flag of the register to be written by the generated test instruction every time one test instruction is generated so as to indicate that it cannot be changed. In addition, this related technology updates the flag of the register to be read by the generated test instruction so as to indicate that it can be changed. Then, this related technology does not adopt the test instruction when there is a register to be written in the randomly generated test instruction as the next test instruction and the flag that cannot be changed is set. Random generation is redone. As a result, the related art does not generate a sequence of test instructions in which subsequent test instructions overwrite the execution results of the preceding test instructions without reference.

Further, an example of another technique related to such a problem is described in Patent Document 2. This related technique uses a change register table when generating the test instruction sequence. Specifically, this related technique registers the register changed by the generated test instruction in the change register table each time one test instruction is generated. This related technique also deletes the registers referenced in the generated test instructions from the change register table. However, the register changed by the generated test instruction may already be registered in the change register table. In this case, the related technique incorporates a test instruction that references the register prior to the test instruction. As a result, the related art does not generate a sequence of test instructions in which subsequent test instructions overwrite the execution results of the preceding test instructions without reference.

Japanese Patent No. 2903721 Japanese Unexamined Patent Publication No. 09-330242

However, the related techniques described in Patent Document 1 and Patent Document 2 have the following problems.

These related techniques rewrite the test instruction sequence to make it possible to detect the illegal operation of the preceding test instruction. However, rewriting the test command sequence impairs the randomness of the test. Also, rewriting the test instruction sequence may make it difficult to test register and memory dependencies. Therefore, there is a problem that the random test using these related techniques has a biased test content.

The present invention has been made to solve the above-mentioned problems. That is, an object of the present invention is to provide a technique for easily detecting an illegal operation of a preceding test instruction in a random test of a system including a processor without impairing the randomness of the test.

In the verification device of the present invention, a test instruction sequence acquisition unit that acquires a test instruction sequence that is a sequence of test instructions to be executed by a system including a processor, and a storage area updated by a preceding test instruction in the test instruction sequence are provided. A checkpoint detector that detects subsequent test instructions that are updated without reference as checkpoints, from the beginning of the test instruction sequence to just before each checkpoint, and from the beginning to the end of the test instruction sequence. It includes a test instruction sequence execution unit that causes the system to execute sequentially, and an execution result verification unit that verifies each execution result by the system.

Further, in the method of the present invention, a computer device acquires a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor, and in the test instruction sequence, a storage area updated by a preceding test instruction is referred to. Subsequent test instructions that are updated without being executed are detected as checkpoints, and the system is sequentially executed from the beginning of the test instruction sequence to immediately before each checkpoint and from the beginning to the end of the test instruction sequence. , A method of verifying each execution result by the system.

Further, the program of the present invention includes a test instruction sequence acquisition step for acquiring a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor, and a storage area updated by a preceding test instruction in the test instruction sequence. A checkpoint detection step that detects subsequent test instructions that are updated without reference to as checkpoints, from the beginning of the test instruction sequence to just before each checkpoint, and from the beginning to the end of the test instruction sequence. , The computer device is made to execute the test instruction sequence execution step to be sequentially executed by the system and the execution result verification step to verify each execution result by the system.

INDUSTRIAL APPLICABILITY The present invention can provide a technique for easily detecting an illegal operation of a preceding test instruction in a random test of a system including a processor without impairing the randomness of the test.

It is a block diagram which shows the structure of the verification apparatus as embodiment of this invention. It is a figure which shows an example of the hardware composition of the verification apparatus as embodiment of this invention. It is a flowchart explaining the operation of the verification apparatus as embodiment of this invention. It is a flowchart explaining the operation which the verification apparatus as embodiment of this invention detects a checkpoint. It is a flowchart explaining the operation which the verification apparatus as embodiment of this invention executes the test instruction sequence up to just before a checkpoint. It is a figure explaining the specific example of the test order sequence acquired in embodiment of this invention. It is a figure explaining the specific example of the update list generated in embodiment of this invention. It is a figure explaining the specific example of the checkpoint list generated in embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a functional block configuration of the verification device 1 as an embodiment of the present invention. In FIG. 1, the verification device 1 includes a test command sequence acquisition unit 11, a checkpoint detection unit 12, a test command sequence execution unit 13, and an execution result verification unit 14.

Here, the verification device 1 can be configured by the hardware elements as shown in FIG. In FIG. 2, the verification device 1 includes a processor 1001, a register 1002, and a memory 1003. In this case, each functional block of the verification device 1 is composed of a processor 1001 that reads and executes a computer program stored in the memory 1003 and controls each unit. In this example, the processor 1001, the register 1002, and the memory 1003 constitute the system 100 to be verified. That is, in this example, the verification device 1 is realized on the system 100 to be verified. However, the hardware configuration of the verification device 1 is not limited to the above configuration. Further, the verification device 1 may be configured by using a processor different from the processor 1001 included in the system 100 to be verified.

Next, each functional block will be described.

The test command sequence acquisition unit 11 acquires the test command sequence. Here, the test instruction sequence is a sequence of test instructions to be executed by the system 100. Further, it is desirable that the test command sequence is randomly generated. Specifically, in the test instruction sequence, test instructions in which the types of instructions and the allocation of the storage area accessed by the instructions are randomly selected are arranged in a randomly determined order. For example, the storage area accessed in the test instruction shall be selected and allocated from register 1002 and / or memory 1003.

Further, it is assumed that the acquired test instruction sequence is stored in the memory 1003. For example, the test command sequence acquisition unit 11 may acquire the test command sequence by generating the test command sequence and store it in the memory 1003. Alternatively, the test instruction sequence acquisition unit 11 may acquire information indicating the position where the test instruction sequence generated by an external test instruction sequence generation program or the like is stored in the memory 1003.

The checkpoint detection unit 12 detects a checkpoint in the test command sequence. Here, the checkpoint means a subsequent test instruction in which the storage area updated by the preceding test instruction is updated without being referred to.

The test command sequence execution unit 13 causes the system 100 to execute the test command sequence from the beginning to immediately before the checkpoint for each checkpoint detected by the checkpoint detection unit 12. Further, the test command sequence execution unit 13 causes the system 100 to execute the test command sequence from the beginning to the end.

Specifically, the test instruction sequence execution unit 13 temporarily sets the test instruction sequence so that the execution of instructions is stopped immediately before the checkpoint. Such a setting may be realized by, for example, interrupt processing. Specifically, the test instruction sequence execution unit 13 may temporarily replace the checkpoint instruction with an interrupt instruction that generates a software-like interrupt. In this case, the test instruction sequence execution unit 13 saves the instruction to be replaced in the save area on the memory 1003 before the replacement, and after the execution of the test instruction sequence up to the checkpoint is completed, the save area Write the instruction back to its position in the original test instruction sequence. Alternatively, the test instruction sequence execution unit 13 may be set to generate a hardware interrupt instead of executing the instruction when the instruction address being executed matches the instruction address of the checkpoint.

When the execution of the test instruction sequence up to immediately before the checkpoint is realized by interrupt processing, the interrupt processing is, for example, to output the execution result of the test instruction sequence up to that point to an output device (not shown). Processing may be set.

The execution result verification unit 14 verifies the execution result by the system 100. Specifically, the execution result verification unit 14 compares the execution result of the test command sequence up to immediately before each checkpoint and the execution result of the test command sequence from the beginning to the end with their respective expected values.

The execution result of the test instruction sequence up to immediately before a certain checkpoint may be a value stored in a storage area to be accessed by the test instruction of the checkpoint. Here, the checkpoint test instruction is a subsequent test instruction in which the storage area updated by the preceding test instruction is updated without reference. Therefore, in the execution result of the test instruction sequence up to immediately before the checkpoint, the value stored in the storage area to be accessed by the checkpoint test instruction is expected to be the value updated by the preceding test instruction. Will be done. In other words, in the execution result of the test instruction sequence up to just before the checkpoint, if the value stored in the storage area to be accessed by the checkpoint test instruction is not as expected, the preceding test instruction causes an illegal operation. The possibility that it has happened will be detected.

Further, the execution result of the test command sequence from the beginning to the end may be the value of all the storage areas updated by the test command sequence.

The expected values for the execution result of the test command sequence from the beginning to immediately before each checkpoint and the execution result of the test instruction sequence from the beginning to the end are obtained in advance based on the test instruction sequence. It is assumed that

Further, the execution result verification unit 14 outputs an error when the execution result is not as expected. Further, the execution result verification unit 14 first executes the test command sequence from the beginning to immediately before the checkpoint closest to the beginning, and then sequentially executes the test instruction sequence from the beginning to immediately before the next checkpoint. You may let it run. Further, the execution result verification unit 14 may end the operation when an error is output regarding the execution result of the test instruction sequence up to immediately before any checkpoint.

The operation of the verification device 1 configured as described above will be described with reference to FIG.

First, the test command sequence acquisition unit 11 acquires the test command sequence (step S11).

Next, the checkpoint detection unit 12 detects one or more checkpoints in the test command sequence (step S12). The details of the operation of step S12 will be described later.

Next, the test command sequence execution unit 13 selects one of the detected checkpoints (step S13).

For example, in the case of the first execution of step S13, the test command sequence execution unit 13 selects the checkpoint closest to the beginning of the test command sequence. Further, if it is not the first execution of step S13, the test command sequence execution unit 13 selects a checkpoint closest to the beginning next to the checkpoint selected in the previous step S13.

Next, the test command sequence execution unit 13 causes the system 100 to execute the test command sequence from the beginning of the test command sequence to immediately before the selected checkpoint (step S14). The details of the operation of step S14 will be described later.

Next, the execution result verification unit 14 reads the execution result of the test instruction sequence by the system 100 (step S15).

Specifically, as described above, the execution result verification unit 14 may read the value of the storage area scheduled to be updated by the test instruction of the corresponding checkpoint.

Then, the execution result verification unit 14 determines whether or not the verification result of the execution result is normal (step S16). Specifically, the execution result verification unit 14 may determine whether or not the execution result is as expected.

Here, if the verification result is not normal (No in step S16), the execution result verification unit 14 outputs an error as the verification result (step S20). Then, the verification device 1 ends the operation.

On the other hand, when the verification result is normal (Yes in step S16), the verification device 1 determines whether or not there is the next checkpoint (step S17).

Here, if there is a next checkpoint (Yes in step S17), the verification device 1 repeats the operation from step S13 for the next checkpoint.

On the other hand, when there is no next checkpoint (No in step S17), the test command sequence execution unit 13 causes the system 100 to execute the test command sequence from the beginning to the end (step S18).

Next, the execution result verification unit 14 reads the execution result of the test instruction sequence by the system 100 (step S19).

Specifically, the execution result verification unit 14 may read the values of all the storage areas updated by the execution of the test command sequence by the system 100.

Next, the execution result verification unit 14 verifies whether or not the verification result of the execution result is normal, and outputs the verification result (step S20). Specifically, the execution result verification unit 14 may output whether or not the execution result is as expected.

Next, the details of the checkpoint detection operation in step S12 will be described with reference to FIG. In this detection operation, the checkpoint detection unit 12 generates a checkpoint list. The checkpoint list consists of information that associates the identification information of the test instruction that becomes the checkpoint with the identification information of the storage area that is updated by the test instruction. As the identification information of the test instruction, the address on the memory 1003 in which the test instruction is stored can be applied. Further, as the identification information of the storage area, the number of the register 1002 or the address on the memory 1003 can be applied. Further, in this detection operation, the checkpoint detection unit 12 uses the update list as the information used in the process of generating the checkpoint list. The update list holds a list of storage identification information that has been updated but not referenced by the execution of a test instruction. At the beginning of this operation, no information is stored in the checkpoint list and update list.

In FIG. 4, first, the checkpoint detection unit 12 reads one test instruction in order from the beginning of the test instruction sequence (step S31).

Next, the checkpoint detection unit 12 determines whether or not the identification information of the storage area referred to by this test instruction is already stored in the update list (step S32).

Here, if the corresponding identification information is not stored (No in step S32), the operation of the checkpoint detection unit 12 proceeds to step S34.

On the other hand, when the corresponding identification information is already stored (Yes in step S32), the checkpoint detection unit 12 deletes the identification information of the corresponding storage area from the update list (step S33).

Next, the checkpoint detection unit 12 determines whether or not the identification information of the storage area updated by this test instruction is already stored in the update list (step S34).

Here, when the corresponding identification information is not stored (No in step S34), the checkpoint detection unit 12 adds the corresponding identification information to the update list (step S35).

On the other hand, when the corresponding identification information is already stored (Yes in step S34), the checkpoint detection unit 12 displays the identification information of this test instruction and the storage area updated by this test instruction in the checkpoint list. It is registered in association with the identification information (step S36).

Then, the checkpoint detection unit 12 repeats the operation from step S31 for the next test command unless this test command is at the end of the test command sequence (No in step S37).

On the other hand, if this test instruction is at the end of the test instruction sequence (Yes in step S37), the checkpoint detection unit 12 ends the checkpoint detection operation.

Next, the details of the execution operation of the test instruction sequence up to immediately before a certain checkpoint in step S14 will be described with reference to FIG.

First, the test command sequence execution unit 13 saves the test command of the checkpoint selected in the test command sequence to the save area (step S41).

Next, the test instruction sequence execution unit 13 rewrites the test instruction of the selected checkpoint in the test instruction sequence into an interrupt instruction that generates an interrupt process (step S42).

As described above, as the interrupt process, a process of outputting the execution result up to that point to the output device may be set.

Next, the test command sequence execution unit 13 causes the system 100 to execute the test command sequence up to immediately before the selected checkpoint (step S43). Specifically, the system 100 executes the test instructions in order from the beginning, and outputs the execution result of the test instruction sequence up to immediately before the checkpoint interrupt process to the output device.

Next, the test command sequence execution unit 13 writes back the test command of the checkpoint saved in step S41 to the position of the checkpoint (step S44). Then, the test command sequence execution unit 13 ends the execution operation of the test command sequence up to immediately before this checkpoint.

This completes the description of the operation of the verification device 1.

Next, the operation of the verification device 1 will be described with a specific example.

In this example, it is assumed that the test command sequence shown in FIG. 6 has been acquired (step S11). This test command sequence consists of 10 test commands. Identification information of instructions 1 to 10 is assigned to each test instruction in order from the beginning. The instruction address described in the line of each test instruction represents the address on the memory 1003 in which the test instruction is stored. Each test instruction is an instruction to write the value read from the allocated storage area or the result of performing four arithmetic operations on the read value to the allocated storage area. Here, there are eight registers 1002 to be allocated, and REG # n (n is an integer from 0 to 7) represents the value of the nth register 1002. Further, MEM (x) represents the value of the address x in the memory 1003. Here, it is assumed that the size of the value stored in each register 1002 and the size of the value accessed by MEM (x) are equal to each other, for example, 8 bytes. Further, "<-" represents an instruction to update the storage area on the left side with the value on the right side. Further, "+", "-", "*", and "÷" represent addition, subtraction, multiplication, and division, respectively.

First, the checkpoint detection operation in step S12 will be described.

First, the checkpoint detection unit 12 reads the instruction 1 "REG # 0 <-MEM (0x20000)" (step S31). The storage area referenced by instruction 1 is MEM (0x20000), and the storage area to be updated is REG # 0.

Here, since the instruction 1 is the first instruction, the update list does not store the identification information of the storage area referenced or updated by the instruction 1 (No in step S32, No in S34). Therefore, the checkpoint detection unit 12 adds REG # 0, which is the identification information of the storage area updated by the instruction 1, to the update list (step S35). The update list is as shown in the column of instruction 1 in FIG.

Then, since the instruction 1 is not the last instruction (No in step S37), the checkpoint detection unit 12 repeats the operation from step S31.

The processing from step S31 for the next instruction 2 “REG # 3 <−REG # 1 + REG # 2” is substantially the same as the processing for instruction 1. That is, since the identification information of the storage area referenced or updated by the instruction 2 is not stored in the update list, the checkpoint detection unit 12 adds the updated storage area REG # 3 to the update list. The update list is as shown in the column of instruction 2 in FIG.

The processing from step S31 for the next instruction 3 “MEM (0x20100) <−REG # 4 * REG # 5” is substantially the same as the processing for instructions 1 and 2. That is, since the identification information of the storage area referenced or updated by the instruction 3 is not stored in the update list, the checkpoint detection unit 12 adds the updated storage area MEM (0x20100) to the update list. The update list is as shown in the column of instruction 3 in FIG.

Next, the checkpoint detection unit 12 reads the instruction 4 “REG # 4 <−REG # 3-REG # 0” (step S31). The storage areas referenced by instruction 4 are REG # 3 and REG # 0, and the storage areas to be updated are REG # 4.

Here, REG # 3 and REG # 0 referred to by the instruction 4 are stored in the update list (Yes in step S32). Therefore, the checkpoint detection unit 12 deletes REG # 3 and REG # 0 from the update list (step S33).

Further, REG # 4 updated by the instruction 4 is not stored in the update list (No in step S34). Therefore, the checkpoint detection unit 12 adds REG # 4, which is the identification information of the storage area updated by the instruction 4, to the update list. The update list is as shown in the column of instruction 4 in FIG.

The processing from step S31 for the next instruction 5 “REG # 3 <−REG # 2 ÷ REG # 6” is substantially the same as the processing for instructions 1 to 3. That is, the checkpoint detection unit 12 adds the updated storage area REG # 3 to the update list because the identification information of the storage area referenced or updated by the instruction 5 is not stored in the update list. The update list is as shown in the column of instruction 5 in FIG.

The processing from step S31 for the next instruction 6 “MEM (0x20018) <−REG # 0” is substantially the same as the processing for instructions 1 to 5. That is, since the identification information of the storage area referenced or updated by the instruction 6 is not stored in the update list, the checkpoint detection unit 12 adds the updated storage area MEM (0x20018) to the update list. The update list is as shown in the column of instruction 6 in FIG.

Next, the checkpoint detection unit 12 reads the instruction 7 “MEM (0x20100) <−REG # 5” (step S31). The storage area referenced by instruction 7 is REG # 5, and the storage area to be updated is MEM (0x20100).

Here, the update list does not store the identification information of the storage area referred to by the instruction 7 (No in step S32), but stores the MEM (0x20100) to be updated (Yes in step S34). ..

Therefore, the checkpoint detection unit 12 associates the instruction address 0x1030 of the instruction 7 with the identification information MEM (0x20100) of the storage area to be updated, and adds it to the checkpoint list.

As a result, the information shown in the first line of FIG. 8 has been added to the checkpoint list. The update list has not been updated since the time when the instruction 6 was analyzed, and is as shown in the column of the instruction 7.

The processing from step S31 for the next instruction 8 “REG # 7 <−REG # 2 + REG # 0” is substantially the same as the processing for instructions 1 to 3 and 5 to 6. That is, since the identification information of the storage area referenced or updated by the instruction 8 is not stored in the update list, the checkpoint detection unit 12 adds the updated storage area REG # 7 to the update list. The update list is as shown in the column of instruction 8 in FIG.

The processing from step S31 for the next instruction 9 “REG # 4 <−MEM (0x20020)” is substantially the same as the processing for instruction 7. That is, the checkpoint detection unit 12 does not update the update list because the identification information of the storage area referred to by the instruction 9 is not stored in the update list. Further, since the checkpoint detection unit 12 stores the storage area identification information REG # 4 updated by the instruction 9 in the update list, the instruction address 0x1040 of the instruction 9 and the update storage area identification information REG # 4 are stored in the update list. Associate with # 4 and add to the checkpoint list. As a result, the information shown in the second line of FIG. 8 has been added to the checkpoint list. The update list has not been updated since the time when the instruction 8 was analyzed, and is as shown in the column of the instruction 9.

Next, the checkpoint detection unit 12 reads the instruction 10 “MEM (0x2050) <−REG # 7” (step S31). The storage area referenced by instruction 10 is REG # 7, and the storage area to be updated is MEM (0x2050).

Here, REG # 7 referred to by instruction 10 is stored in the update list (Yes in step S32). Therefore, the checkpoint detection unit 12 deletes REG # 7 from the update list (step S33).

Further, the MEM (0x2050) updated by the instruction 10 is not stored in the update list (No in step S34). Therefore, the checkpoint detection unit 12 adds MEM (0x20050), which is the identification information of the storage area updated by the instruction 10, to the update list. The update list is as shown in the column of instruction 10 in FIG.

Then, since the instruction 10 is the last instruction (Yes in step S37), the checkpoint detection unit 12 ends the checkpoint detection operation in step S12.

As a result, the checkpoint list shown in FIG. 8 was generated.

Next, the test command sequence execution unit 13 causes the system 100 to sequentially execute the test command sequence based on the generated checkpoint list.

Specifically, first, the test instruction sequence execution unit 13 selects the instruction 7 of 0x1030, which is the instruction address of the first checkpoint (step S13).

Next, the test instruction sequence execution unit 13 backs up the instruction 7 to the save area (steps S14 and S41).

Next, the test instruction sequence execution unit 13 overwrites the interrupt instruction at the instruction address 0x1030 (step S42).

Next, the test instruction sequence execution unit 13 causes the system 100 to sequentially execute the first instruction 1 of the test instruction sequence (step S43). At this time, the execution of the instruction is stopped at the instruction address 0x1030 by the interrupt instruction replaced by the instruction 7. That is, the system 100 executes instructions 1 to 6 to stop the process. Therefore, the execution result verification unit 14 outputs the execution results up to that point to the output device.

Next, the execution result verification unit 14 writes back the instruction 7 backed up in the save area to the instruction address 0x1030 rewritten as an interrupt instruction (step S44).

Next, the execution result verification unit 14 refers to the checkpoint list and acquires the value of MEM (0x20100), which is the identification information of the storage area associated with the stopped instruction address 0x1030 (step S15).

Then, the execution result verification unit 14 compares the value of MEM (0x20100) with the expected value (step S16).

Here, it is assumed that the value of MEM (0x20100) is as expected (Yes in step S16).

Then, since there is the next checkpoint (Yes in step S17), the test instruction sequence execution unit 13 selects the instruction 9 of 0x1040, which is the instruction address of the next checkpoint (step S13).

Next, the test instruction sequence execution unit 13 backs up the instruction 9 in the save area (steps S14 and S41).

Next, the test instruction sequence execution unit 13 overwrites the interrupt instruction at the instruction address 0x1040 (step S42).

Next, the test instruction sequence execution unit 13 causes the system 100 to sequentially execute the first instruction 1 of the test instruction sequence (step S43). At this time, the execution of the instruction is stopped at the instruction address 0x1040 by the interrupt instruction replaced by the instruction 9. That is, the system 100 executes instructions 1 to 8 to stop the process. Therefore, the execution result verification unit 14 outputs the execution results up to that point to the output device.

Next, the execution result verification unit 14 writes back the instruction 9 backed up in the save area to the instruction address 0x1040 rewritten as an interrupt instruction (step S44).

Next, the execution result verification unit 14 refers to the checkpoint list and acquires the value of REG # 4, which is the identification information of the storage area associated with the stopped instruction address 0x1040 (step S15).

Then, the execution result verification unit 14 compares the value of REG # 4 with the expected value (step S16).

Here, it is assumed that the value of REG # 4 is as expected (Yes in step S16).

Then, the execution result verification unit 14 proceeds to the next step S18 because the current checkpoint is the last checkpoint and there is no next checkpoint (No in step S17).

That is, the execution result verification unit 14 causes the system 100 to execute the first instruction 1 to the last instruction 10 of the test instruction sequence (step S18).

Then, the execution result verification unit 14 reads the values of all the storage areas updated in the instructions of the test instruction sequence (step S19).

Then, the execution result verification unit 14 compares each value of the read storage area with the expected value, and outputs the result (step S20).

This is the end of the explanation of the specific example.

Next, the effect of the embodiment of the present invention will be described.

The verification device as an embodiment of the present invention can easily detect an illegal operation of a preceding test instruction in a random test of a system including a processor without impairing the randomness of the test.

The reason will be explained. In the present embodiment, the test instruction sequence acquisition unit acquires a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor. Then, the checkpoint detection unit detects as a checkpoint a subsequent test instruction that is updated without reference to the storage area updated by the preceding test instruction in the test instruction sequence. Then, the test command sequence execution unit causes the system to sequentially execute from the beginning of the test instruction sequence to immediately before each checkpoint and from the beginning to the end. Then, the execution result verification unit verifies each execution result by the system.

As described above, in the present embodiment, even if an illegal operation occurs in the middle of the test instruction sequence, the execution result before the subsequent instruction overwrites the execution result is checked, so that the illegal operation can be performed more reliably. You will be able to detect it.

Further, in the present embodiment, in the execution of the test instruction sequence until immediately before the checkpoint, not all the storage areas are subject to verification, but the storage area to be referred to at the checkpoint is subject to verification. As described above, in the present embodiment, since the verification process is performed on the execution result of the test instruction sequence up to immediately before each checkpoint, the number of verification processes themselves is increased, but the storage area to be verified in each verification process is used. Suppress the increase in numbers. As a result, the present embodiment can reduce the increase in processing time.

In the embodiment of the present invention, an example in which each functional block of the verification device is realized by a CPU that executes a computer program stored in a memory has been mainly described. Not limited to this, a part, all, or a combination thereof of each functional block may be realized by dedicated hardware.

Further, in the above-described embodiment of the present invention, the functional blocks of the verification device may be distributed and realized in a plurality of devices.

Further, in the above-described embodiment of the present invention, the operation of the verification device described with reference to each flowchart is stored in the storage device (storage medium) of the computer device as the computer program of the present invention. Then, the CPU may read and execute the computer program. Then, in such a case, the present invention is composed of the code or storage medium of the computer program.

Further, the present invention is not limited to the above-described embodiment of the present invention, and can be implemented in various modes.

1 Verification device 11 Test instruction sequence acquisition unit 12 Checkpoint detection unit 13 Test instruction sequence execution unit 14 Execution result verification unit 100 System 1001 Processor 1002 Register 1003 Memory

Claims (5)

A test instruction sequence acquisition unit that acquires a test instruction sequence that is a sequence of test instructions to be executed by a system including a processor, and a test instruction sequence acquisition unit.
In the test instruction sequence, a checkpoint detection unit that detects as a checkpoint a subsequent test instruction that is updated without reference to the storage area updated by the preceding test instruction.
A test command sequence execution unit that causes the system to sequentially execute the test command sequence from the beginning to immediately before each checkpoint and from the beginning to the end of the test instruction sequence.
An execution result verification unit that verifies the storage area that will be accessed by the checkpoint test instruction when each execution result by the system is executed until just before the checkpoint.
Verification device equipped with. For each checkpoint, the test instruction sequence execution unit temporarily replaces the test instruction of the checkpoint with an interrupt instruction that temporarily stops the execution of the instruction immediately before the checkpoint , whereby the test instruction sequence is described from the beginning of the test instruction sequence. The verification device according to claim 1, wherein the system is executed until immediately before the checkpoint. The execution result verification unit verifies the storage area to be updated by the instruction of the checkpoint for the execution result from the beginning of the test instruction sequence to immediately before each checkpoint, and verifies the storage area of the test instruction sequence. The verification device according to claim 1 or 2, wherein the execution result from the beginning to the end is verified for the storage area updated in each test instruction. The computer device
Obtain a test instruction sequence, which is a sequence of test instructions to be executed by the system including the processor,
In the test instruction sequence, the subsequent test instruction updated without reference to the storage area updated by the preceding test instruction is detected as a checkpoint.
The system is sequentially executed from the beginning of the test instruction sequence to immediately before each checkpoint and from the beginning to the end of the test instruction sequence.
A method of verifying the storage area to be accessed by a checkpoint test instruction when each execution result by the system is executed until just before the checkpoint. A test instruction sequence acquisition step for acquiring a test instruction sequence, which is a sequence of test instructions to be executed by a system including a processor, and a test instruction sequence acquisition step.
In the test instruction sequence, a checkpoint detection step of detecting a subsequent test instruction updated as a checkpoint without referring to the storage area updated by the preceding test instruction, and a checkpoint detection step.
A test command sequence execution step that causes the system to sequentially execute the test command sequence from the beginning to immediately before each checkpoint and from the beginning to the end of the test instruction sequence.
When each execution result by the system is executed until just before the checkpoint, the execution result verification step for verifying the storage area to be accessed by the checkpoint test instruction, and the execution result verification step.
A program that causes a computer device to execute.

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