JP6851716B2 - Game machine - Google Patents

Description

The present invention relates to a game machine that performs a lottery process caused by a game operation and executes an image effect corresponding to the lottery result, and more particularly to a game machine that can stably execute a powerful image effect.

A ball game machine such as a pachinko machine is equipped with a symbol start port provided on the game board, a symbol display unit for displaying a series of symbol variation modes by a plurality of display symbols, and a large winning opening for opening and closing the opening / closing plate. It is composed of. Then, when the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is set, and after the game ball is paid out as the prize ball, the displayed symbol is changed for a predetermined time on the symbol display unit. After that, when the symbol is stopped in a predetermined mode such as 7, 7, 7, a big hit state is reached, and the big winning opening is repeatedly opened to generate a game state advantageous to the player.

Whether or not to generate such a game state is determined by a big hit lottery executed on the condition that the game ball wins at the symbol start opening, and the above symbol variation operation is based on the lottery result. It has become a thing. For example, when the lottery result is in the winning state, an effect operation called a reach action or the like is executed for about 20 seconds, and then special symbols are arranged. On the other hand, even in the case of a lost state, the same reach action may be executed. In this case, the player pays close attention to the transition of the production operation while strongly paying attention to the big hit state. Then, if the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

In this type of gaming machine, there is a high demand for complicated and abundant productions, especially for image productions. Therefore, the display device is getting bigger and bigger, and we want to raise the resolution as much as possible, including moving images that change at high speed.

However, since the amount of data in a high-resolution moving image increases by the amount of the resolution, there is a problem in securing a large amount of various types of moving images and still images in a memory (CGROM). That is, as the size of the CGROM increases, the manufacturing cost increases and there is a problem in terms of the arrangement space.

The present invention has been made in view of the above problems, and is a gaming machine capable of securing a large amount of moving images and still images without enlarging the memory and realizing a wide variety of image production. The purpose is to provide.

In order to achieve the above object, the present invention is a sub that executes an image effect corresponding to a lottery result of a lottery process executed due to a predetermined switch signal based on a control command received from another control means. A gaming machine provided with control means, the sub-control means is an image effect control means that centrally controls an image effect, and compressed data that is a component of a still image and / or a moving image that constitutes the image effect. It has a data storage means for storing the data, and an image generation means for realizing the image effect by outputting the image data generated from the compressed data based on the instruction of the image effect control means to one or a plurality of display devices. configured Te, the image presentation control means, while the list generating means for generating a drawing list specifying the image display of one frame of the display device is provided, the said image generating means, generates said list generation means a drawing circuit for generating image data of the one frame corresponding to the drawing list and the receiving image data generated by the rendering circuit, a display circuit configured to the required processing, the display circuit output An output circuit that receives the image data to be output and outputs the data to the display device in a predetermined signal format is provided, and the drawing circuit corresponds to the drawing list and, when necessary, the first display device for the first display device. The display circuit is a first display circuit that reads out and processes the image data of the first frame buffer in response to generating image data in the 1-frame buffer and the second frame buffer for the second display device, respectively. And a second display circuit that reads and processes the image data of the second frame buffer, and the functions of the first frame buffer and the second frame buffer are interchangeably switched. In the double buffer structure, when the drawing circuit generates image data in one of the double buffers, the image effect control means instructs the display circuit to read the stored contents of the other double buffer. The reduced data stored in the data storage means after being reduced to W (W <1) times in the horizontal direction and H (H ≦ 1) times in the vertical direction is the second frame. via a buffer, the second display circuit 1 / W times is a lateral, the predetermined effect condition for outputting the vertical direction as an enlarged image data is enlarged to 1 / H times, the relative said second frame buffer The switching instruction is configured to be output to the first frame buffer at a cycle twice as long as the switching instruction .

The reduced data is preferably stored in the data storage means as moving image compressed data constituting the moving image. Further, it is preferable that the reduction process of the reduced data is executed for the rectangular image and W <H ≦ 1 is set.

Further, the present invention is a game provided with a sub-control means for executing an image effect corresponding to a lottery result of a lottery process executed due to a predetermined switch signal based on a control command received from another control means. The sub-control means is an image effect control means that centrally controls the image effect, and a data storage unit that stores compressed data that is a component of a still image and / or a moving image that constitutes the image effect. And an image generation means that realizes an image effect by outputting image data generated from compressed data based on an instruction of the image effect control means to one or a plurality of display devices. The effect control means is provided with a list generation means for generating a drawing list that specifies an image display for one frame of the display device, while the image generation means corresponds to the drawing list generated by the list generation means. A drawing circuit that generates image data for one frame, a display circuit that receives the image data generated by the drawing circuit, performs necessary processing, and outputs the image data, and receives image data output by the display circuit. An output circuit that outputs data to the display device in a predetermined signal format is provided, and the list generation means and the drawing circuit are intermittently operated with a predetermined operation cycle. The drawing list generated by the list generation means is interpreted by the drawing circuit at a timing delayed by an integral N times (N> 0) of the predetermined operation cycle, so that the image data specified by the drawing list is generated. The drawing circuit generates image data in the first frame buffer for the first display device and the second frame buffer for the second display device, respectively, when necessary. Correspondingly, the display circuit includes a first display circuit that reads and processes the image data of the first frame buffer and a second display circuit that reads and processes the image data of the second frame buffer. Both the first frame buffer and the second frame buffer have a double buffer structure in which the functions are interchangeably switched, and the drawing circuit generates image data in one of the double buffers. At the timing of the operation, the display circuit has a configuration in which the image effect control means outputs a switching instruction so as to read the other stored content of the double buffer, and a predetermined effect state in which the auxiliary moving image is reproduced at 1/2 times speed. Then, the auxiliary image data for playing the auxiliary moving image, together with other normal image data, is described as described above. While the auxiliary image data is generated in the first frame buffer, the drawing list is configured so that the update cycle of the auxiliary image data is twice the update cycle of the normal image data.

According to the game machine of the present invention described above, it is possible to secure a large amount of moving images and still images without increasing the size of the memory, and it is possible to realize a wide variety of image effects.

It is a perspective view of the pachinko machine shown in an Example. It is a front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of an Example. It is a block diagram which illustrates the circuit structure of an effect control part and an image control part. It is a drawing explaining the structure of a clock IC. It is a block diagram which shows the internal structure of the composite chip which is in charge of image production. It is a drawing explaining operation of a display circuit. It is a drawing explaining the structure of a memory, and the operation procedure which realizes an image effect. It is a flowchart explaining the operation content of 1st Example which does not use a preloader. It is a drawing explaining the operation in the case of low-speed playback of an auxiliary moving image in a sub-display device. It is a drawing explaining the operation in the case of normal reproduction of a normal moving image and low-speed reproduction of an auxiliary moving image in a main display device. It is a flowchart explaining the operation content of the 2nd Example which uses a preloader. It is a drawing explaining operation of 2nd Example.

Hereinafter, the present invention will be described in detail based on Examples. FIG. 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM consists of a rectangular frame-shaped wooden outer frame 1 that is detachably attached to the island structure and a front frame 3 that is pivotally attached to the island structure via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotally attached to the front side thereof so as to be openable and closable.

Illumination lamps such as LED lamps are arranged in a substantially C shape on the outer periphery of the glass door 6. On the other hand, a total of three speakers are arranged at the upper left and right positions and the lower side of the glass door 6. The two speakers arranged at the upper part are configured to output the sound of the left and right channels R and L, respectively, and the lower speaker is configured to output the deep bass.

An upper plate 8 for storing a game ball for launch is mounted on the front plate 7, and a lower plate 9 for storing a game ball overflowing or extracted from the upper plate 8 and a launch handle are below the front frame 3. 10 is provided. The launch handle 10 is interlocked with the launch motor, and the game ball is launched by a striking mallet that operates according to the rotation angle of the launch handle 10.

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not normally function, but when the game state changes to the button chance state, the built-in lamp is lit and the game can be operated. The button chance state is a game state provided as needed.

On the right side of the upper plate 8, an operation panel 12 for ball lending operation for a card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a game ball for a predetermined amount. A ball lending switch for instructing lending and a return switch for instructing the return of cards at the end of the game are provided.

As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 composed of an outer rail and an inner rail made of metal is provided in an annular shape, and a central opening HO is provided substantially in the center thereof. A movable effect body (not shown) is concealed below the central opening HO, and the movable effect body is raised to be exposed at the time of the movable notice effect, so that the predetermined reliability is achieved. The notice production is realized. Here, the advance notice effect is an effect of uncertainly notifying the player that a big hit state that is advantageous to the player will be invited, and the reliability of the advance notice effect means the probability that the big hit state will be invited.

A main display device DS1 composed of a large liquid crystal color display (LCD) is arranged in the central opening HO, and a movable sub display device composed of a small liquid crystal color display is arranged on the right side of the main display device DS1. DS2 is arranged. The main display device DS1 is a device that displays a specific symbol related to a jackpot state in a variable manner and displays a background image, various characters, and the like in an animated manner. The display device DS1 has special symbol display units Da to Dc in the central portion and a normal symbol display unit 19 in the upper right portion. Then, in the special symbol display units Da to Dc, a reach effect that is expected to invite a big hit state may be executed, and in the special symbol display units Da to Dc and its surroundings, a notice effect by an appropriate moving image or the like is executed. To.

Normally, the sub-display device DS2 displays image information in a stationary state in which the display screen is tilted at an angle that is easy for the player to see. However, at the time of the predetermined advance notice effect, the predetermined advance notice moving image (auxiliary moving image) is displayed while moving to the left side of the drawing while changing the inclination angle to an angle that is easy for the player to see. That is, the sub-display device DS2 of the embodiment is not only a display device but also functions as a movable effect body that executes a notice effect. Here, the notice effect by the sub-display device DS2 is set with high reliability, and the player pays attention to the moving operation of the sub-display device DS2 with great expectation.

In this embodiment, the moving image effect is executed not only by the main display device DS1 but also by the sub display device DS2, but the sub display device DS2 and / or so that various kinds of moving images can be played back without increasing the size of the CGROM. The main display device DS1 reproduces an auxiliary moving image whose production value is not high at a low speed. The details of this point will be described later, but the normal moving image mainly reproduced by the main display device DS1 is about 30 fps (frame per second), whereas the auxiliary moving image mainly reproduced by the sub display device DS2 is 15 fps. It is about the same, and while suppressing the total amount of video data, it realizes a wide variety of video production.

By the way, in the game area where the game ball falls and moves, the first symbol start opening 15a, the second symbol start opening 15b, the first big winning opening 16a, the second big winning opening 16b, the normal winning opening 17, and the gate 18 Are arranged. Each of these winning openings 15 to 18 has a detection switch inside, so that the passage of a game ball can be detected.

At the upper part of the first symbol start port 15a, an effect stage 14 configured to be able to win a prize in the first symbol start port 15 is arranged after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. There is. Then, when the game ball wins a prize in the first symbol start opening 15, the special symbol display units Da to Dc are configured to start the variable operation.

The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening / closing claws, and when the stop symbol after the change of the normal symbol display unit 19 displays a hit symbol, it is predetermined. The opening / closing claws are opened only for a period of time or until a predetermined number of game balls are detected.

The normal symbol display unit 19 displays a normal symbol, and when a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates by a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the lottery random value is displayed and stopped.

The first big winning opening 16a is configured to have a slide board that moves forward and backward, and the second big winning opening 16b is configured to have an opening / closing plate whose lower end is pivotally supported and opens forward. .. The operation of the first large winning opening 16a and the second large winning opening 16b is not particularly limited, but in this embodiment, the first large winning opening 16a corresponds to the first symbol starting opening 15a and is the second large winning opening. 16b is configured to correspond to the first symbol start port 15b.

That is, when the game ball wins the first symbol start port 15a, the fluctuation operation of the special symbol display units Da to Dc is started, and then when the predetermined jackpot symbols are aligned with the special symbol display portions Da to Dc, the first jackpot The barrel special game is started, and the slide board of the first large winning opening 16a is opened forward to facilitate the winning of the game ball.

On the other hand, as a result of the fluctuating operation started by winning the game ball to the second symbol start port 15b, when the predetermined jackpot symbols are aligned with the special symbol display units Da to Dc, the second jackpot special game is started and the second jackpot is started. The opening / closing plate of the two major winning openings 16b is opened to facilitate the winning of the game ball. The game value of the special game (big hit state) varies depending on the jackpot symbols that are lined up, but which game value is given is determined in advance based on the lottery result according to the winning timing of the game ball. It is determined.

In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls win a prize. Such an operation is continued up to, for example, 15 times, and is controlled in a state advantageous to the player. If the stop symbol after the change of the special symbol display units Da to Dc is a specific symbol among the special symbols, the privilege that the game after the end of the special game is in a high probability state (probability change state) is provided. Granted.

FIG. 3 is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the above operations, and FIG. 4 is a detailed diagram of a part thereof. As shown in FIG. 3, this pachinko machine GM has a power supply board 20 that receives AC24V and outputs various DC voltages, power supply abnormality signals ABN1 and ABN2, a system reset signal (power supply reset signal) SYS, and a game control operation. The main control board 21 that is centrally responsible for the above, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD received from the effect control board 22. The payout control board 23 that drives the two display devices DS1 and DS2 based on', and the payout control board 24 that controls the payout motor M based on the control command CMD received from the main control board 21 to pay out the game ball. And a launch control board 25 that launches a game ball in response to a player's operation.

As shown in the figure, the control command CMD output from the main control board 21 is transmitted to the effect control board 22. Further, the control command CMD "output by the main control board 21 is transmitted to the payout control board 24 via the main board relay board 32.

The control commands CMD, CMD', CMD "are all 16 bits long, but the control commands related to the main control board 21 and the payout control board 24 are transmitted in parallel twice every 8 bit length. On the other hand, the control command CMD'transmitted from the effect control board 22 to the image control board 23 is collectively transmitted in parallel with a 16-bit length. Therefore, the advance notice effects including the movable notice effect are diversified and many. Even when the control command of is continuously transmitted and received, the process can be completed quickly and does not interfere with other control operations.

As shown in the figure, in this embodiment, the liquid crystal interface board 28 accessible from the image control board 23 and the effect control board 22 is provided. The liquid crystal interface board 28 is equipped with a clock circuit (real-time clock) RTC capable of measuring the current time and a memory element (Static Random Access Memory) SRAM for storing game performance information.

Further, in this embodiment, the image control board 23 drives the main display device DS1 and the sub display device DS2 via the liquid crystal interface board 28 on which the LVDS receiving circuit or the like is mounted. Here, the liquid crystal interface board 28 and the image control board 23 are directly connected to the male connector and the female connector without going through a wiring cable. Similarly, with respect to the effect control board 23 and the liquid crystal interface board 28, the male connector and the female connector are directly connected without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire substrate can be minimized, and the noise resistance can be improved by minimizing the connection line.

Computer circuits such as a one-chip microcomputer are mounted on the main control board 21, the effect control board 22, the image control board 23, and the payout control board 24, respectively. Therefore, in this specification, the main control unit 21 and the effect control unit are functionally generically referred to as the circuits mounted on the control boards 21 to 24 and the liquid crystal interface board 28, and the operations realized by the circuits. It may be referred to as 22, the image control unit 23, and the payout control unit 24. With respect to the main control unit 21, all or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 serve as sub control units.

The pachinko machine GM is roughly divided into a frame-side member GM1 surrounded by a broken line in FIG. 3 and a board-side member GM2 fixed to the back surface of the game board 5. The frame-side member GM 1 includes a front frame 3 to which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. It is fixedly installed in. On the other hand, the board-side member GM2 is replaced in response to the model change, and a new board-side member GM2 is attached to the frame-side member GM1 instead of the original board-side member. All except the frame-side member 1 are board-side members GM2.

As shown in the broken line frame of FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 35. They are fixed in place in the front frame 3. On the other hand, on the back surface of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with display devices DS1 and DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by connection connectors C1 to C4 which are centrally arranged at one location.

The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors the on / off of the AC power supply. When the power supply monitoring unit MNT detects that the AC power is turned on, it maintains the system reset signal SYSTEM at the L level for a predetermined time, and then shifts the system reset signal to the H level.

Further, when the power supply monitoring unit MNT detects that the AC power supply is cut off, the power supply abnormality signals ABN1 and ABN2 are immediately changed to the L level. The power supply abnormality signals ABN1 and ABN2 immediately reach the H level after the power is turned on.

By the way, the system reset signal of this embodiment is generated by a DC power source based on an AC power source. Therefore, after the AC power supply is detected (usually the power switch is turned on) and increased to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in a momentary power failure state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are output even in the momentary power failure state of the AC power supply.

The main board relay board 32 outputs the power supply abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power supply board 20 to the main control unit 21 as they are. On the other hand, the power supply relay board 33 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages as they are to the effect control unit 22. Then, the effect control unit 22 outputs the received system reset signal SYS to the image control unit 23 as it is.

On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through a relay board, and directly receives the same power supply abnormality signal ABN2 and backup power supply BAK as received by the main control unit 21 together with other power supply voltages. I have received it.

The system reset signal SYS output by the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputer 40 and the image control unit of the effect control unit 22 are generated by this power supply reset signal. The built-in CPU circuit of 23 is reset in power together with other circuit elements and an internal circuit including VDP.

However, this system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power supply reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 rattles or noise is superimposed on the wiring cable, there is no possibility that the CPUs of the main control unit 21 and the payout control unit 24 are abnormally reset. Since the effect control unit 22 and the image control unit 23 subordinately execute the effect operation based on the control command from the main control unit 21, the effect control unit 22 and the image control unit 23 output from the power supply board 20 in order to avoid complication of the circuit configuration. The system reset signal SYS is used.

The reset circuit RST provided in the main control unit 21 and the payout control unit 24 has a built-in watchdog timer, and each CPU does not receive a regular clear pulse from the CPUs of the control units 21 and 24. Is forcibly reset.

Further, in this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for determining whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputers of the control units 21 and 24, and the initialization switch SW operated by the staff is turned on. It has a value corresponding to the / OFF state.

By receiving the power supply abnormality signals ABN1 and ABN2 from the power supply board 20, the main control unit 21 and the payout control unit 24 start necessary termination processing prior to a power failure or business termination. Further, the backup power supply BAK is a DC 5V DC power supply that retains the data of the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is cut off due to the closing of business or a power failure. Therefore, the main control unit 21 and the payout control unit 24 can restart the game operation before the power is cut off after the power is turned on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

As shown in FIG. 3, the main control unit 21 transmits a control command CMD ”to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 shows a game ball payout operation. The prize ball counting signal, the status signal CON related to the abnormality of the payout operation, and the operation start signal BGN are received. The status signal CON includes, for example, a supply shortage signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 is completed after the power is turned on.

Further, the main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. Then, while receiving the switch signal of the detection switch built in each of the winning openings 16 to 18 on the game board, the solenoids such as the electric tulip are driven. The solenoids and the detection switch are configured to operate at the power supply voltage VB (12V) distributed from the main control unit 21. Further, each switch signal indicating the winning state of the symbol start port 15 is converted into a TTL level or CMOS level switch signal by an interface IC operating at a power supply voltage VB (12V) and a power supply voltage Vcc (5V). After that, it is transmitted to the main control unit 21.

As described above, the effect control board 22, the image control board 23, and the liquid crystal interface board 28 are integrated by connecting the connectors, and the effect control unit 22 passes through the power supply relay board 33 to the power supply board 20. The DC voltage (5V, 12V, 32V) of each level and the system reset signal SYS are received from the above (see FIGS. 3 and 4A).

Further, the effect control unit 22 receives the control command CMD and the strobe signal STB from the main control unit 21. Then, the effect control unit 22 serially transmits the lamp drive signal SDATA to the lamp drive board 36, the lamp drive board 29, and the driver IC mounted on the motor lamp drive board 30 in synchronization with the clock signal CK. By driving a group of lamps composed of a large number of LED lamps and illuminated lamps, a lamp effect based on the control command CMD is realized.

In the case of this embodiment, the lamp effect is executed by the three lamp groups CH0 to CH2, and the lamp drive board 36 clocks the lamp drive signal SDATA0 of CH0 via the frame relay boards 34 and 35. Received in synchronization with signal CK0 (clock synchronous serial communication). The lamp drive signal SDATA0 transmitted as a serial signal is output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, so that the lighting state is updated all at once.

The above points are the same for the lamp drive board 29. The driver IC of the lamp drive board 29 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. At the timing of the change to, the lighting state of the lamp group CH1 is updated all at once.

On the other hand, the driver IC mounted on the motor lamp drive board 30 receives the lamp drive signal transmitted in the clock synchronous manner to drive the lamp group CH2, and also receives the motor drive signal transmitted in the clock synchronous manner to drive the lamp group CH2. It drives the effect motor groups M1 to Mn composed of a plurality of stepping motors. The lamp drive signal and the motor drive signal are a series of serial signals SDATA2, which are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives the serial signal is the timing at which the operation control signal ENABLE2 changes to the active level. Then, the drive states of the lamp group CH2 and the motor groups M1 to Mn are updated.

Further, the effect control unit 22 sends the image control unit 23 a control command CMD'and a strobe signal STB', a system reset signal SYS received from the power supply board 20, and two types of DC voltages (12V, 5V). Is being output. Then, the image control unit 23 drives the display devices DS1 and DS2 based on the control command CMD'to execute various image effects. As shown in FIGS. 3 and 4A, the image control unit 23 includes a built-in CPU circuit (image effect control device) 51 having an internal configuration equivalent to that of a general-purpose one-chip microcomputer, a VDP (Video Display Processor) 52, and the like. It is mainly composed of a composite chip 50 having a built-in structure. Further, a control memory (PROM) 53 for storing the control program of the built-in CPU, a DRAM (Dynamic Random Access Memory) 54 capable of accessing a large amount of data at high speed, and a CGROM 55 for storing a large amount of CG data required for image control. And are installed.

Then, the image data generated by the VDP 52 based on the CG data read from the CGROM 55 is used as a first and second LVDS (Low voltage differential signaling) signal via the liquid crystal interface substrate 28. It is transmitted to the main display device DS1 and the sub display device DS2. The display device DS1 has a built-in LVDS receiver that converts the LVDS signal into an RGB signal, and the display device DS1 has five pairs of LVDS signals from the liquid crystal interface board 28 and a DC including an LED backlight power supply. It is driven by receiving the power supply voltage. On the other hand, the sub-display device DS1 is driven by receiving the digital RGB signal converted by the LVDS receiving unit of the liquid crystal interface board 28 and the DC power supply voltage including the LED backlight power supply.

Subsequently, the configuration of the effect control unit 22 will be described in more detail based on FIG. 4A. As shown in FIG. 4A, the effect control unit 22 includes a one-chip microcomputer 40 (effect control CPU 40) that executes processing such as voice effect, lamp effect, advance notice effect by the effect movable body, and data transfer, and an effect control CPU 40. A control memory (flash memory) 41 for storing the control program and various effect data ENs, and an audio processor 42 for reproducing and outputting an audio signal based on an instruction from the effect control CPU 40 set in the built-in registers RG0 to RGn. The audio memory 43 for storing compressed audio data, which is the original data of the audio signal to be reproduced, and the digital amplifier 46 for receiving the audio signal output from the audio processor 42 are provided.

In the case of this embodiment, the effect data EN stored in the control memory 41 includes scenario data for managing the effect progress of the lamp effect and the sound effect, lamp drive data for determining the blinking mode of the LED, and rotation of the motor. Includes motor drive data, which determines the aspect. The lamp drive data and the motor drive data are output bit by bit in time sequence to become a lamp drive serial signal and a motor drive serial signal.

The one-chip microcomputer 40 has a plurality of serial input / output port SIOs and a plurality of parallel input / output port PIOs. Here, the serial input / output port SIO has a serial output port Soi that outputs a CHi lamp drive signal or a motor drive signal SDATAi in synchronization with the clock signal CKi, and an origin sensor signal (serial signal) of the motor groups M1 to Mn. Is included with the serial port Si that receives the clock signal CK3 in synchronization with the clock signal CK3. It should be noted that i = 0 to 2, which corresponds to the three lamp groups CH0 to CH2 and the motor groups M1 to Mn driven together with the lamp group of CH2.

On the other hand, the parallel input / output port PIO is divided into an output port Po, Po'and an input port Pi, and a control command CMD and a strobe signal STB from the main control unit 21 are input to the input port Pi. On the other hand, the operation control signals ENABLE0 to ENABLE2 are output from the output port Po', and the control command CMD'and the strobe signal STB' are output from the output port Po'. Specifically, after the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are stepped down in the buffer 44 to a logic level corresponding to the power supply voltage of 3.3 V of the one-chip microcomputer 40, It is supplied to the input port Pi in 8-bit units in two batches. Further, the interrupt signal STB is supplied to the interrupt terminal of the effect control CPU 40, and the effect control unit 22 is configured to acquire the control command CMD by the receive interrupt process.

The control command CMD acquired by the effect control unit 22 includes (1) abnormality notification and other notification control commands, as well as (2) a control command for specifying the outline of various effect operations caused by winning a prize at the symbol start port. (Variation pattern command) and control command (symbol specification command) to specify the symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the total production time from the start of the production to the end of the production, and the winning / failing result in the jackpot lottery.

In addition, the symbol designation command includes information for specifying the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, it contains information that identifies the loss. The outline of the effect operation specified by the variation pattern command includes the total time of the effect from the start of the effect to the end of the effect, and the winning / failing result in the big hit lottery. In addition to these, the variable pattern command may be used to specify the presence or absence of the reach effect and the advance notice effect, but even in this case, the specific content of the effect content is not specified.

Therefore, when the effect control unit 22 acquires the variation pattern command, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further embodied. For example, the specific contents of the reach production and the advance notice production are determined. Then, according to the determined specific game content, the lamp effect by blinking the LED group and the preparation operation of the sound effect by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. Outputs the control command CMD'related to the image effect.

In order to realize an image effect synchronized with such an effect operation, the effect control unit 22 issues a 16-bit length control command CMD'to the image control unit 23 together with the strobe signal (interrupt signal) STB'through the output port Po. It is outputting. When the effect control unit 22 receives a symbol designation command, an abnormality notification control command, or other control command, the effect control unit 22 collects the 8-bit unit control commands into a 16-bit length and interrupt signals. It is output to the image control unit 23 together with STB'.

As described above, the voice processor 42 of the present embodiment accesses the voice memory 43 based on the instruction (set value by the voice command SND) received from the effect control CPU 40 to the built-in registers (voice control registers) RG0 to RGn. Then, the necessary audio signal is reproduced and output. As shown in the figure, the voice processor 42 and the voice memory 43 are connected by a voice address bus having a length of 26 bits and a voice data bus having a length of 16 bits. Therefore, 1 Gbit (= 226 * 16) data can be stored in the voice memory 43. In the case of this embodiment, the compressed audio data stored in the audio memory 43 is phrase compressed data specified by a 13-bit long phrase number (000H to 1FFFH), which is equivalent to one song of a series of background music. (BGM) and, such as the production sound of the unity people (notice sound), the highest 8192 type ^{(= 2 13),} respectively, are stored in response to the phrase number. Then, this phrase number is specified by the set value of the voice command SND transmitted from the effect control CPU 40 to the voice control registers RG0 to RGn of the voice processor 42.

The voice command SND has a plurality of (2 or 3) byte lengths, and is used for writing purposes in which a predetermined set value is transmitted to any RGi of a large number of voice control registers RG0 to RGn built in the voice processor 42. To. However, the voice command SND of this embodiment is used not only for writing a set value such as a phrase number, but also for reading status information (error information) STS from a predetermined voice control register RGi. The predetermined voice control register RGi to be accessed is specified by a register address having a length of 1 byte.

The setting value setting (Write) in the voice control register RGi does not necessarily have to be executed individually for each voice control register, and a group of voice control can be performed by designating the SAC data stored in the voice memory 43. It is also possible to complete a series of setting operations for the registers RGi to RGj. Here, the SAC data is an aggregate of a maximum of 512 (maximum 1024 bytes) in which the register address (1 byte) of the voice control register RGi and the set value (plural bytes) of the voice control register RGi correspond to each other. Means. In this embodiment, only the necessary set of such SAC data is stored in the voice memory 43 in advance, and one set of SAC data is specified by a SAC number of about 13 bits, which is a single ID information. It has become like.

Therefore, in the case of this embodiment, the voice command SND for Write uses the SAC number to specify a set of SAC data, or the set value and the register address are individually specified.

As shown in FIG. 4B, the effect control CPU 40 and the voice processor 42 transmit parallel signal lines (data buses) CD0 to CD7 capable of transmitting and receiving 1-byte data, and operation management data. 2-bit length operation management data lines (address bus) A0 to A1 that can be transmitted, 2-bit length control signal lines WR and RD that can control read / write operations, and a chip that selects the voice processor 42. It is connected to the select signal line CS.

The parallel signal lines CD0 to CD7 are realized by the data bus of the effect control CPU 40, and the operation management data lines A0 to A1 are realized by the address bus of the effect control CPU 40, and each is connected to the effect control CPU 40. There is. Then, when the effect control CPU 40 executes, for example, an IOREAD operation or an IOWRITE operation by program processing, the control signals WR, RD and the chip select signal CS are appropriately changed, and the audio specified by the parallel signal lines CD0 to CD7. Read / write (R / W) operation with the control register RGi is realized.

Specifically, as shown in the time chart of FIG. 4B', the register address of the voice control register RGi and the data written to the voice control register RGi are transmitted in parallel through the parallel signal lines CD0 to CD7, respectively. Will be done. Then, whether the 1 byte transmitted in parallel is a register address or write data (write data) is specified by the operation management data A0 to A1.

Therefore, as shown in FIG. 4B, the operation management data (address data A0 to A1) is changed from [00] to [01], while the 1-byte data of the data bus is changed to [voice control register RGi. By changing from [register address] to [data written to the voice control register RGi], a predetermined voice command SND is transmitted. When the write data has a plurality of bytes, as in the case of transmitting the SAC number (13 bits), the operation management data A0 to A1 of [01] can be changed from [00] to [01] to [01]. → While repeating [01], multiple bytes of write data are transmitted.

The voice command transmitted in this way is then activated as long as there is no communication abnormality. However, if a communication abnormality is found, such as data having a plurality of bytes inconsistent with each other, the voice command SND will not be effective. Then, the error flag of the voice control register RGn is set, and this error flag (status information STS) is produced by changing the operation management data A0 to A1 of the address bus from [01] to [10]. The control CPU 40 can receive the data by the Read operation.

As described above, in this embodiment, in the final cycle in which the operation management data A0 to A1 are changed in the order of [00] → [01] → ... [01] → [10], error information (abnormality) having a plurality of bit lengths is used. Time can get FFH). Then, by resending the voice command SND that could not be legitimately transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of the present embodiment, it is possible to surely eliminate the unnaturalness in which the sound production is suddenly interrupted.

In the configuration of FIG. 4B, the effect control CPU 40 receives the status information STS including the error information in parallel from the voice processor 42, but the configuration is not limited to this. That is, it is also preferable to adopt a configuration in which an interrupt signal is output to the effect control CPU 40 when the voice processor 42 recognizes the communication error. In this case, the voice in which the communication error occurs in the interrupt processing program of the effect control CPU 40. All you have to do is resend the command. If such a configuration is adopted, it is possible to omit the error flag (status information STS) acquisition process, that is, the process of transitioning the operation management data A0 to A1 to [10], which is useless in most cases. it can.

As shown in FIGS. 3 and 4A, in this embodiment, the left and right speakers on the upper part of the game machine and the speakers on the lower part of the game machine are driven by the output of the digital amplifier 46. Therefore, the voice processor 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice processor 42 and the digital amplifier 46 becomes complicated.

Therefore, in this embodiment, in order to prevent deterioration of sound quality and avoid complication of wiring, the audio processor 42 and the digital amplifier 46 are connected by four signal lines, and specifically. Is suppressed by a signal line of a total of 4 bits, which is a transfer clock signal SCLK, a channel control signal LRCLK, and 2-bit length serial signals SD1 and SD2.

Here, SD1 is a serial signal for PCM data that identifies the stereo signals R and L of the left and right speakers arranged in the upper part of the game machine, and SD2 is a monaural signal of the deep bass speaker arranged in the lower part of the game machine. It is a serial signal about the PCM data to be specified. Then, the audio processor 42 transmits the audio signal L of the left channel while maintaining the channel control signal LRCLK at the L level, and transmits the audio signal R of the right channel while maintaining the channel control signal LRCLK at the H level. Transmit (see FIG. 4 (c)). Since there is only one deep bass speaker in this embodiment, a monaural audio signal is transmitted, but of course it can be transmitted as a stereo audio signal.

In any case, in this embodiment, since four types of audio signals can be transmitted by four cables, signal transmission without audio deterioration due to noise is possible with the minimum number of cables. That is, since it is serial transmission, the number of cables is overwhelmingly smaller than that of parallel transmission.

Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. Then, inside the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after DA conversion, class D amplification is performed and supplied to each speaker.

Continuing the description of FIG. 4A, the effect control board 22 is a buffer circuit 47 that transfers serial data SDATAi output from the serial output port Soi of the serial input / output port SIO of the one-chip microcomputer 40 and the clock signal CKi. ~ 49 is provided (i = 0 to 2).

Here, the output buffer 47 transfers the lamp drive signal SDATA0 and the clock signal CK0 output by the serial output port So0 to the shift register circuit (driver IC) of the lamp drive board 36. Further, the output buffer 48 transfers the lamp drive signal SDATA1 and the clock signal CK1 output by the serial output port So1 to the driver IC of the lamp drive board 29. As described above, the driver ICs mounted on the lamp drive boards 29 and 36 light and drive the lamp groups of CH0 and CH1.

On the other hand, the buffer circuit 49 functions as an input / output buffer, and transfers the serial signal SDATA2 output by the serial output port So2 to the motor lamp drive board 30 together with the clock signal CK2. Further, the origin sensor signals (serial signals) indicating the origin positions of the group of effect motors M1 to Mn are transferred to the serial input port Si of the one-chip microcomputer 40 in synchronization with the clock signal CK3.

In the case of this embodiment, the serial signal SDATA2 transferred by the buffer circuit 49 is a lamp drive signal (serial signal) for lighting the lamp group CH2 and a motor drive signal (serial signal) for rotating the effect motors M1 to Mn. ) And are continuous. Then, the motor lamp drive board 30 divides these series of serial signals into 16-bit lengths and converts each 16-bit length into a parallel signal to execute a lamp effect and a movable notice effect. Specifically, as an effect operation determined by lottery in response to the control command CMD, a series of lamp effects are executed, and when a motor drive signal is received, the effect motors M1 to Mn are rotated as appropriate. Movable notice production is being executed.

Next, as shown on the left side of FIG. 4A, in this embodiment, the data bus and the address bus of the effect control CPU 40 extend to the liquid crystal interface board 28. For convenience of explanation, this relationship is shown on the left side of FIG. 4A, but the clock circuit RTC is connected to the CPU by the lower 4 bits of the address bus of the effect control CPU 40 and the lower 4 bits of the data bus. It is configured to be freely accessible. Further, the memory element SRAM that stores the game performance information enables random access of the effect control CPU 40 by 16 bits of the address bus of the effect control CPU 40 and the lower 16 bits of the data bus.

The clock circuit RTC is a clock IC (real-time clock) that measures the current date and time, and operates permanently with a secondary battery BT charged by the power supply voltage received from the effect control board 22 together with the memory element SRAM. are doing. That is, while the secondary battery BT (FIG. 5) is charged while the game machine is powered on, after the power of the game machine is cut off, the secondary battery BT in the charged state is used as the basis for charging the secondary battery BT (FIG. 5). The timekeeping operation of the clock circuit RTC is continued, and the effect data is also permanently stored and retained (backup operation).

As shown in FIG. 5, the clock circuit RTC of the embodiment is connected to the effect control CPU 40 through a 4-bit data bus, a 4-bit data bus, and a control bus RD + WR for Read / Write operation. Then, the effect control CPU 40 adds important game information and abnormality information related to the game operation to the date information, daytime information, and time information acquired from the clock circuit RTC, and stores them in the memory element SRAM. ..

This clock circuit RTC has two types of chip select terminals, CS1 and CS0 bars, and allows access from the effect control CPU 40 on condition that the input voltage to each terminal is at a normal level. It has become. Here, the CS0 bar terminal is a normal chip select terminal that receives the output of the address decoder. On the other hand, the CS1 terminal receives the output (voltage drop signal) Vo of the power supply abnormality detection unit ER, and when the CS1 terminal receives an abnormal level output Vo, the abnormality detection flag Fos of the clock circuit RTC is automatically set. It is designed to be set to.

In the case of this embodiment, this abnormality detection flag Fos is determined by the effect control CPU 40 when the power is turned on together with the other abnormality detection flags TEMP. If the abnormality detection flag Fos is in the set state, the date and date at that time and The time is notified. Therefore, if an abnormality in the clock function is found, it can be dealt with quickly.

Even if the voltage of the secondary battery BT drops when the power is cut off, the voltage level of the secondary battery BT quickly recovers when the power is restored and the CS1 terminal returns to the normal level, so access from the effect control CPU 40 is permitted. Will be done. Therefore, if the configuration of this embodiment in which the abnormality detection flag Fos determination process is provided is not adopted, there is a possibility that the abnormality of the clock circuit RTC cannot be permanently detected.

Further, the clock circuit RTC of the embodiment is configured to output an interrupt signal IRQ once a week, for example, at 21:50 every Friday, and the effect control CPU 40 receiving the interrupt signal IRQ is configured to output the interrupt signal IRQ. The game information and abnormality information accumulated in the memory element SRAM up to that point are appropriately aggregated.

The game information to be aggregated is a collection of historical information related to the jackpot state, for example, (1) the number of winnings to the symbol start port required to reach the jackpot state, (2) the symbol in the jackpot state, and so on. Aggregate value and statistical value of big hit state whether it is probable or not, (3) type of notice effect and reach effect that reached big hit state, (4) number of consecutive chans, (5) time of number of balls paid out by consecutive chans Increasing trends, etc. are included. Then, these aggregated information and statistical information are appropriately notified at the request of the player. The player's instruction is specified, for example, by pressing the chance button 11 during the demonstration effect, and the notification content is displayed on the display device DS1.

On the other hand, the abnormal information to be aggregated includes, for example, (1) the number of times the door is opened, (2) the detection type, the number of times of detection, and the detection time of the detection sensor that detects an illegal act, and (3) the symbol start port 15 in the blocked state and the large size. The number of detections, the detection frequency, the detection time, and the like of the act of forcibly opening the winning opening 16 with a wire or the like are included. Then, these aggregated information are displayed on the display device DS1 in response to a special operation by the staff.

As shown in FIG. 5A, the clock circuit RTC of the embodiment is configured to incorporate three internal register tables of Bank0 to Bank2. However, since the Bank 2 register table relates to the time setting and the date setting, only the Bank 0 and Bank 1 register tables are shown in FIGS. 5 (b) and 5 (c). In any case, each register table is composed of 4 bytes × 16 registers, and the current date and time measured by the internal circuit are written in the Bank0 register table (Fig. 5 (b)). It is configured to be.

As shown in FIG. 5B, in the Bank 0 register table, bit 3 of the first register is the abnormality detection flag Fos, and bit 2 of the 14th register indicates that the built-in temperature sensor has detected the abnormal temperature. The temperature anomaly flag TEMP shown. Then, in this embodiment, when the CPU of the effect control unit 22 is reset, the value of the abnormality detection flag Fos is determined to prevent the continuation of the abnormal timing operation. Further, the temperature abnormality of the effect control CPU 40 is quickly detected by arranging the clock circuit RTC close to the effect control CPU 40 and repeatedly determining the value of the temperature abnormality flag TEMP at appropriate time intervals.

Further, in the Bank0 register table, bit 0 of the 15th register is a Busy flag indicating that the register table is being updated. Then, in this embodiment, the current date and the current time are acquired from the Bank0 register table on condition that the Busy flag is in the non-Busy state (update completed). Therefore, in this embodiment, there is no possibility of acquiring the clock information halfway during the update operation or irrational clock information, and the validity of the clock information stored in the memory element SRAM is guaranteed. For example, if the clock information being updated from 1:59:59 to 2:00:00 is acquired, there is a possibility that the clock information at 1:00:00 may be acquired.

Further, the register table of Bank1 is configured so that the generation time of the interrupt signal IRQ can be set. Therefore, in this embodiment, interrupt generation is instructed by setting bit 0 of the 1st register of Bank1 to 1 (Interrupt Enable), and the day of the week of Friday is specified in the 0th to 8th registers of Bank1 and 21. The time information of hours 30:00 is set.

Subsequently, the image control unit 23 will be described in detail with reference to FIGS. 6 to 8. First, FIG. 6A is a circuit block diagram showing the composite chip 50 constituting the image control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a built-in CPU circuit 51 and a VDP circuit 52. Then, the built-in CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays transmission / reception data to each other, and a V blank interrupt signal (VBLANK) is supplied from the VDP circuit 52 to the built-in CPU circuit 51. It is supposed to be done.

Here, the V blank interrupt signal corresponds to the vertical synchronization signal of the display device DS1, and defines the timing at which the output of the image data for one frame of the display device DS1 is completed every 1/60 second. In this embodiment, of the two display circuits 74A / 74B, the display circuit 74A is configured to function steadily, while the display circuit 74B functions when necessary and operates in synchronization with the display circuit 74A. Therefore, in the end, the vertical synchronization signal (V blank interrupt signal) means that the output operation of the display circuit 74A has ended.

The sequence operation based on the V blank interrupt will be described later, but as shown in FIG. 6, the CPUIF circuit 56 includes a control program (PROGRAM_ROM) 53 that non-volatilely stores a control program and necessary control data, and about 2 Mbytes. A work memory (RAM) 57 having a storage capacity of the above is connected, and each is configured to be accessible from the built-in CPU circuit 51.

The built-in CPU circuit 51 is a circuit having the same performance as a general-purpose one-chip microcomputer, and has an image control CPU 63 that comprehensively controls image production based on a control program of a control memory 53, and a CPU when the program goes into a runaway state. A watchdog timer (WDT) 58 that forcibly resets, a RAM 59 that has a storage capacity of about 16 kbytes and is used as a work area of the CPU, and a DMAC (Direct Memory Access Controller) that realizes data transfer without going through the CPU. 60, a serial input / output port (SIO) 61 having a plurality of input ports Si and an output port So, and a parallel input / output port (PIO) 62 having a plurality of input ports Pi and an output port Po. Has been done.

Although the expression "input / output port" is used for convenience, in the image control unit 23, the input / output port includes an input port and an output port that operate independently. This point is the same for the input / output circuit 64p and the input / output circuit 64s described below.

The parallel input / output port 62 is connected to an external device (effect control board 22) through the input / output circuit 64p, and the image control CPU 63 outputs the effect control unit 22 via the input circuit 64p and the parallel input port Pi. The control command CMD'and the interrupt signal STB' are received. On the other hand, in this embodiment, the serial input / output port 61 and the DMAC60 are not used.

Next, the VDP circuit 52 will be described. The VDP circuit 52 includes a CGROM 55 that stores compressed data that is a component of a still image or a moving image that constitutes an image effect, and an external DRAM (Dynamic) having a storage capacity of about 4 Gbit. The Random Access Memory) 54, the main display device DS1, and the sub display device DS2 are connected.

Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory having a storage capacity of about 62 Gbit, and is compressed required by serial transmission. It is configured to retrieve data. Therefore, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is solved, and extremely high-speed transmission operation becomes possible.

The NAND flash memory is mechanically more stable than the hard disk and can be accessed at high speed. On the other hand, since it is a sequential access memory, the access speed is higher than that of the DRAM or SRAM (Static Random Access Memory). Inferior, the access speed becomes slower in the order of built-in VRAM71> external DRAM54> CGROM55. However, by executing a preload operation in which a group of compressed data (CG data) is read out to the DRAM 54 prior to the drawing operation, smooth random access of the CG data during the drawing operation can be realized.

In detail, the VDP circuit 52 has a register group 70 in which various operation parameters defining the operation of the VDP are set, and about 48 Mbytes used when generating image data to be displayed on the display devices DS1 and DS2. The VRAM (video RAM) 71, the data transfer circuit 72 that controls data transmission / reception between each part inside the chip and data transmission / reception to / from the outside of the chip, the preloader 73 that executes the preload operation, and the image data of the VRAM 71 are read out as appropriate. A display circuit 74 of three systems (A / B / C) that executes various image processing in parallel, a graphics decoder 75 that decodes compressed data read from CGROM 55, and still image data and moving image data after decoding as appropriate. A drawing circuit 76 that generates image data for one frame of each display device DS1 and DS2 in combination with, a geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion as part of the operation of the drawing circuit 76, and serial. The SMC unit 78 that can send and receive data, the output selection unit 79 that appropriately selects and outputs the output of the display circuit 74 of the three systems (A / B / C), and the image data output by the output selection unit 79 are converted into LVDS signals. LVDS unit 80, CPUIF unit 81 that relays data transmission / reception with the CPUIF circuit 56, CG bus IF unit 82 that relays data reception from CGROM55, and DRAMIF unit 83 that relays data transmission / reception with the external DRAM 54. , And a VRAMIF unit 84 that relays data transmission / reception with the VRAM 71.

FIG. 6B illustrates the relationship between the CPU IF unit 81, the CG bus IF unit 82, the DRAM IF unit 83, and the VRAM IF unit 84, and the register group 70, the CGROM 55, the DRAM 54, and the VRAM 71, and in particular, the register group. A part of 70 is specifically described. As shown in the figure, the CGROM 55 and the CG bus IF unit 82 are connected by a serial line, the CGROM 55 is sequentially accessed in response to the transmission of the address information Tx, and a group of CG data (compressed data) Rx is sequentially read out. It is designed to be used.

In the first embodiment, the CG data read from the CGROM 55 is stored in the VRAM 71 via the CG bus IF unit 82 → VRAM IF unit 84, and the arrow at the timing T1 + δ in FIG. 8 indicates this reading operation. Shown. As shown in FIG. 8, the VRAM 71 secures a still image decoding area and a moving image decoding area as working areas of the graphics decoder 75, and the CG data is in a compressed state at a position corresponding to the type of CG data. It is stored as it is. Further, as shown in FIGS. 7 and 8, the VRAM 71 also secures a frame buffer FB area for arranging image data for one frame after decoding.

On the other hand, in the second embodiment in which the preloader 73 is made to function, the CG data is stored in the preload area of the DRAM 54 via the CG bus IF unit 82 → the DRAM IF unit 83 prior to the timing required for the decoding process. After that, it is randomly accessed at the required timing and transferred to the VRAM 71. However, in any of the embodiments, the CG data stored in the still image decoding area or the moving image decoding area of the VRAM 71 is decoded by the graphics decoder 75 and then placed in an appropriate position in the frame buffer FB area of the VRAM 71 by the drawing circuit 76. Be expanded. The arrow at the timing T1 + δ'in FIG. 8 indicates this operation.

Returning to FIG. 6A and continuing the description, the data transfer circuit 72 uses a resource (storage medium) inside the VDP circuit and an external storage medium as a transfer source port or a transfer destination port, and performs a data transfer operation between them. Is a circuit that executes. In addition to the VRAM 71, the transfer source port includes a storage medium (resource) connected to a CPU bus, a CG bus, and an external DRAM bus. Similarly, the transfer destination port includes a storage medium connected to a CPU bus, a CG bus, and an external DRAM bus in addition to the VRAM 71. The data transfer circuit 72 is also in charge of transmitting a display list DL that specifies a display image for one frame by a group of drawing commands to the drawing circuit 76 (preloader 73 when necessary).

The preloader 73 is a circuit that interprets the display list DL transmitted by the data transfer circuit 72 and transfers the CG data on the CGROM 55 referred to therein to the preload area of the DRAM 54 designated in advance. At this time, the preloader 73 outputs a display list DL in which the reference destination of the CG data is rewritten to the address after transfer. Then, the rewritten display list DL is transmitted to the drawing circuit 76 by the data transfer circuit 72.

However, in the first embodiment, the preloader 73 is not used. On the other hand, in the second embodiment, a sufficient preload area of the storage area is set in the external DRAM 54 based on the set value in the preloader register (see FIG. 6B). Then, in this second embodiment, the preloaded compressed data is maintained without being overwritten and erased by the subsequent compressed data unless the storage area set as the preload area is used up. Therefore, in the second embodiment using the preload process, the CGROM 55 is accessed only when the required compressed data does not exist in the preload area. Since a sufficient storage area is secured in the preload area, no problem occurs even if CG data for a plurality of frames is preloaded at once.

The drawing circuit 76 sequentially analyzes the drawing commands of the display list DL transmitted by the data transfer circuit 72, and cooperates with the graphics decoder 75, the geometry engine 77, and the like to form a frame buffer FB formed in the VRAM 71. In addition, it is a circuit that draws an image for one frame of the display device DS1 and the display device DS2.

Here, the display list DL is composed of a group of drawing commands described in the order of drawing. The drawing command also includes a command that defines what kind of image is drawn at which position in one frame, and a storage position (source address) such as a CGROM of the image to be drawn is also specified. Then, the drawing circuit 76 interprets such a display list DL and generates image data for each frame of the display devices DS1 and DS2 in the frame buffer FB secured in the built-in VRAM 71 (FIG. 7). reference).

As shown in FIG. 7, the frame buffer FB of this embodiment is divided into three categories (FBa, FBb, FBc) corresponding to the display circuits 74A / 74B / 74C, and each frame buffer FB (FBa, FBb, The drawing position of FBc) is specified by a predetermined drawing command described in the display list DL.

The three-divided frame buffers FB (FBa, FBb, FBc) are double buffers functionally divided into a drawing area and a display area, and two areas (area 0 and area 1) are alternately divided. It is used by switching the usage. That is, when the drawing circuit 76 writes the image data in one of the two areas, the display circuit 74 reads the image data in the other area and outputs the image data to the display devices DS1 and DS2. ing. However, in this embodiment, since the display circuit 74C is not used, the frame buffer FBc is not used.

Although not particularly limited, in the present embodiment, one frame of the display devices DS1 and DS2 is composed of three or more types of images (moving images and still images) in the maximum state. That is, in the display devices DS1 and DS2, in the maximum state, one or a plurality of moving images are reproduced, while a still image that changes with time is superimposed on the background image. .. Therefore, there is a possibility that the amount of CG data will be enormous, especially for moving image production, but the amount of CG data is suppressed by adopting the data reduction method and the low-speed playback method described later.

The basic shape of the still image is stored in the CGROM 55 in advance as a sprite image, and the basic shape is appropriately enlarged / reduced / rotated / deformed and the arrangement position is changed to realize a temporal change. ing. On the other hand, the moving image is a so-called movie that changes smoothly for a predetermined time, and M frames are compressed by a moving image compression method such as an MPEG coding method and stored in the CGROM 55.

In this embodiment, the compressed data of the moving image is divided into normal data compressed while maintaining the original resolution (number of pixels) and reduced data compressed after the resolution is deteriorated. The reduced data is reduced to W times (W <1) in the horizontal direction and H times (H <1) in the vertical direction when viewed from the player, but is greatly reduced in the horizontal direction (W <H <1). ), It is deformed vertically and then compressed. Therefore, in this embodiment, the total amount of CG data can be significantly suppressed, and a large amount of moving image data is stored to increase the variation of image production without increasing the size of the CGROM.

For example, a moving image composed of N frames is as shown in the lower part of FIG. 10, and all pixel data is vertically reduced in units of rectangular image frames and then compressed. Then, after the moving image is decoded, such reduced data is enlarged in the scalers (see FIG. 7) of the display circuits 74A and 74B to the original vertical and horizontal dimensions in frame units. That is, it is enlarged 1 / W times in the horizontal direction and 1 / H times in the vertical direction to restore the original vertical and horizontal dimensions.

This portrait reduction method was experimentally detected by the present inventor, and according to many experimental results, the image quality of the restored image in moving image reproduction is better when the portrait reduction is performed than when the image is reduced to the same size. Is confirmed. The reduction ratio is appropriately selected in the range of 0.5 ≦ H ≦ 1 according to the effect value of the moving image, but in each case, the H / W is about 1.1 to 1.8. I think that is appropriate. In this case, since W = H / 1.1~H / 1.8, the amount of data ^{is H * W = H 2 /1.1~H 2} /1.8, H = 0.9 of In this case, there is a reduction effect of at least 0.74 times. Although the moving image has been described above, the sprite image constituting the still image may be reduced to an appropriate vertical length (H / W> 1) according to the effect value. However, the data reduction effect is more remarkable in the moving image data.

Regardless of whether or not a vertical reduction method that exerts such an effect is adopted, the moving image of this embodiment is a normal moving image in which all frames are reproduced at a reproduction speed of about 30 fps (frame per second), and an effect value. Is not so high, so it is roughly classified into auxiliary moving images that are played at a low speed of about 15 fps. This point is as explained at the beginning, and by playing the auxiliary video at 1/2x speed, that is, by playing the N-second video with the playback time of 2 x N seconds, CG data (video data). We are trying to suppress.

Although not particularly limited, the normal moving image of this embodiment is an IP stream moving image composed of an I frame and a P frame. On the other hand, the auxiliary moving image includes not only the same IP stream moving image as the normal moving image but also an I-stream moving image composed of only I frames. Here, the P frame means a frame composed of a P picture (Predictive Picture) that encodes a difference from the data predicted from the past frame, and although the compression rate is high, sequential reproduction is indispensable.

On the other hand, the I frame means a frame composed of an I picture (Intra Picture) that can be encoded independently without depending on other frames. Therefore, although the compression rate of the I-stream moving image is inferior to that of the IP-stream moving image, reverse playback in which the time is reversed and seek playback in which the I-stream movie is played from an arbitrary position are also possible. Therefore, in the sub-display device DS2, the effect of the effect is enhanced by irregularly reproducing such an I-stream moving image (auxiliary moving image) as needed.

Further, in this embodiment, the amount of CG data is suppressed by reproducing the I-stream moving image, which has a compression rate inferior to that of the IP-stream moving image, at low speed in the main display device DS1 and the sub-display device DS2. Although I-picture and P-picture are terms of the MPEG coding method, the compression method of this embodiment is not necessarily limited to the MPEG method, and the IP stream moving image and the I-stream moving image are compressed by other methods. It can also be configured by method.

Corresponding to such a configuration, the graphics decoder 75 is divided into a still image decoder and a moving image decoder, and decodes the still image and the moving image encoded (compressed) by a predetermined compression algorithm by a decompression algorithm corresponding to each. (Stretched). For example, a still image is compressed by a predetermined algorithm for each image data constituting one still image, and in a P frame of an IP stream moving image, a plurality of still image data for realizing a series of moving images are inserted between frames. It is compressed based on the data difference value.

Next, the display circuit 74 is a circuit that reads out the image data of the frame buffer FB, performs final image processing, and outputs the data (see FIG. 7). As shown in FIG. 7, the image processing in the display circuit 74 includes a scaling process in which the scaler functions to enlarge / reduce the frame image, a delicate color correction process, and a dither that minimizes the quantization error of the entire image. Ring processing and is included. The scaling process includes enlargement processing (horizontal 1 / W times, vertical 1 / H times) of the frame data after video decoding for the vertically elongated reduced moving image data (vertically reduced data).

Then, after undergoing these image processing, digital RGB signals (24 bits in total) are output to the display devices DS1 and DS2 together with the horizontal synchronization signal and the vertical synchronization signal. As shown in FIG. 7, in this embodiment, three display circuits 74A / 74B / 74C for executing the above operations in parallel are provided, and each display circuit 74A / 74B / 74C corresponds to each. The image data of the frame buffer FBa / FBb / FBc is read out, and the above final image processing is executed. However, in this embodiment, the display circuit 74C and the frame buffer FBc are not used as described above.

As shown in FIG. 7, the output selection unit 79 transmits the output signal of the display circuit 74A to the LVDS unit 80a, and transmits the output signal of the display circuit 74B to the LVDS unit 80b. Then, the LVDS unit 80a and the LVDS unit 80b convert the image data (a total of 24-bit digital RGB signals) into an LVDS signal, add a pair for transmitting the clock signal, and display each as a total of five pairs of differential signals. It is outputting to the devices DS1 and DS2. The display device DS1 has a built-in LVDS signal conversion receiving unit RV, which restores an RGB signal from the LVDS signal and duplicates three or more types of images (moving images and still images) in the maximum state. it's shown. However, the image data to be output does not necessarily have to be an LVDS signal, and when the transmission distance is not long as in a game machine, the digital RGB signal is displayed as it is via the digital RGB unit 80c. It is also suitable to transmit to.

Next, the SMC unit 78 (Serial Management Controller) is a composite controller having a built-in LED controller and Motor controller. Then, while outputting the LED drive signal and the motor drive signal in synchronization with the clock signal to the LED / Motor driver (driver IC with a built-in shift register) mounted on the external board, the latch pulse is output at an appropriate timing. It is configured to be outputable.

Regarding the internal circuit of the VDP circuit 52 and its operation, the operation content to be executed by the internal circuit is defined by the operation parameter (set value) set by the image control CPU 63 in the register group 70, and the execution state of the VDP circuit 52. Can be specified by READ the operation status value of the register group 70. The register group 70 means a large number of registers mapped in a memory space (0 to FFFFFH) of about 1 Mbyte on the memory map of the image control CPU 63, and the image control CPU 63 has operation parameters via the CPU IF unit 81. The WRITE (setting) operation and the READ operation of the operation status value are executed (see FIG. 6B).

The register group 70 is a setting related to data transfer processing by the data transfer circuit 72 between the "system control register" in which initial setting values related to system operation such as interrupt operation are written and the internal circuit of the image control CPU 63 and the VDP circuit 52. A "data transfer register" in which values are written, a "GDEC register" in which the execution status including an error in the graphics decoder 75 can be specified, and a "drawing" in which drawing commands and setting values related to the drawing circuit 76 are written. A "register", a "preloader register" in which setting values related to the operation of the preloader 73 are written, a "display register" in which setting values related to each operation of the display circuits A / B / C divided into three are written, and an LED. An "LED control register" in which setting values related to the controller (SMC unit 78) are written and a "motor control register" in which setting values related to the Motor controller (SMC unit 78) are written are included, and these control registers are included. Each consists of a plurality of bytes in length.

More specifically, in the "preloader register", (1) the setting of whether the preload area is set in the DRAM 54 or the VRAM 84, (2) the start address of the preload area, and (3) the preload data area are set. The number of frames to use, (4) the data size per frame, etc. are set. Further, a data transfer source and a data transfer destination are set in the "data transfer register", and the start position of the frame buffer FBa / FBb / FBc corresponds to the display circuit A / B / C in the "display register". In the buffer size, each frame buffer FBa / FBb / FBc, a time-switching drawing area and display area switching instruction, a scaler vertical / horizontal enlargement ratio, and the like are set. Further, the "drawing register", "preloader register", and "data transfer register" are instructed to start execution of each operation for the drawing operation, the preload operation, and the data transfer operation.

In any case, the internal operation of the VDP circuit 52 is realized by the image control CPU 63 writing an appropriate set value to any of the register group 70. Therefore, the image control CPU 63 realizes the image effect based on the display list DL based on the display list DL updated at an appropriate time interval and the set values for the registers constituting the register group 70 described above. In this embodiment, since the effect control CPU 40 of the effect control board 22 is in charge of the lamp effect and the motor effect, the SMC unit 78 is not used and the set values are written in the LED control register and the motor control register. It will not be.

Subsequently, regarding the control operation of the image effect executed by using the display devices DS1 and DS2, referring to the flowcharts of FIGS. 9A to 9D and the operation explanatory diagrams of FIGS. 8 and 10. explain. These image effects are realized by an image control CPU 63 that receives a control command CMD'from the effect control CPU 40, and a VDP circuit 52 that functions by being instructed by the image control CPU 63. Then, the instruction from the image control CPU 63 to the VDP circuit 52 is specified by the operation parameter written in the register group 70.

As shown in FIG. 9, the image effect operation is the update process of the display list DL (FIGS. 9A to 9B) executed by the image control CPU 63 at predetermined time intervals, and the display list received from the image control CPU 63. It is realized by each sequence operation (FIGS. 9 (c) to 9 (d)) of the drawing circuit 76 that operates based on the DL and the display circuit 74. The image control CPU 63 sets necessary operation parameters in the register group 70 at the time of power reset or at a necessary timing thereafter so that the drawing circuit 76 and the display circuit 74 realize the sequence operation described below. are doing. For example, at the moving image reproduction timing in which the vertically elongated reduced data is used, the enlargement ratio of the frame data (horizontal 1 / W times, vertical 1 / H times) is set in the display register.

Explaining based on the above, the image control CPU 63 starts the update process of the display list DL every 1/60 second every fixed time δ (for example, 1/30 second) defined by the V blank interrupt (ST1). , The drawing circuit 76 and the display circuit 74 have started the sequence operation (ST2). As described with respect to FIG. 6, the V blank interrupt means that the output operation of the display circuit 74A has ended, but based on the processing of step ST2, the drawing circuit 76 and the display circuits 74A / 74B are intermittently It executes its own operation in parallel (see FIG. 10).

First, with reference to FIG. 10, the sequence operation of the drawing circuit 76 and the display circuit 74 will be schematically described. First, the display list DL generated by the CPU 63 in the execution cycle starting from T1 is interpreted by the drawing circuit 76 in the execution cycle starting from T1 + δ, and the image data generated by the drawing circuit 76 is created in the frame buffer FB. Then, this image data is output by the display circuit 74 in an execution cycle starting from T1 + 2δ. Therefore, in this embodiment, the one-unit operation for the image effect is completed after three execution cycles.

The above relationship is also as described in FIG. 8, and based on the display list DL transferred to the DRAM 54 at the timing of T1', the CG data of the CGROM 55 is read into the VRAM 71 at the timing of T1 + δ (however, when necessary). (Limited), image data is created in the frame buffer FB in the same execution cycle (timing T1 + δ'). Then, this image data is output to the display device DS1 and the display device DS2 at the timing of T1 + 2δ.

Next, the operation of the display circuit 74 will be specifically described by limiting it to moving image reproduction. As shown in FIG. 10, the display circuit 74A continuously outputs each frame (A1, A2, ... A6) of a normal moving image that is updated at regular intervals of δ for a certain period of time. On the other hand, the display circuit 74B duplicately outputs each frame of the auxiliary moving image, which is updated in two cycles of 2δ, twice (B1, B1, B2, B2, B3, B3 ...). .. Although moving image playback is described here, a background image or a still image that moves in time is displayed when necessary, overlapping with a normal moving image or an auxiliary moving image. Therefore, it goes without saying that the term "one frame" does not necessarily mean the entire frame of the display devices DS1 and DS2. This point is the same in the following description.

As described above, in the image production of this embodiment, a normal moving image of 30 fps and an auxiliary moving image of 15 pfs are used, but by repeating the operation of FIG. 9 (a) every 1/30 second (ST1). , Up to 30 fps normal moving image can be played. However, if the execution cycle δ is set short (for example, 1/60 second), moving image reproduction exceeding 30 fps can be realized.

Since the outline has been described above, the process of step ST2 will be specifically described subsequently with reference to FIG. 9B. The image control CPU 63 first determines whether or not the sub-display device DS2 is playing the auxiliary moving image based on this effect timing (ST10). Then, during playback of the auxiliary moving image, the toggle variable NUM is toggled between 0 and 1 (ST11), and it is determined whether or not the toggle variable NUM = 0 (ST12).

This process is for switching the display operation of the display circuit 74B every 1/15 second in order to appropriately reproduce the auxiliary moving image of 15 pfs at a low speed. That is, if the toggle variable NUM = 0, the display area of the frame buffer FBb of the display circuit 74B is switched by writing an appropriate set value to the display register that defines the operation of the display circuit 74B (ST13).

As shown in FIG. 7, the frame buffer FB has a double buffer structure (0/1), one of which is a drawing area to be accessed by the drawing circuit 76, and the other is an access target of the display circuit 74. Is the display area. Then, by the processing of step ST13, the drawing area and the display area are exchanged, and the image data for one frame generated by the drawing circuit 76 in the frame buffer FBb up to that point is subordinated by the display circuit 74B in this execution cycle. It will be output to the display device DS2.

As shown in FIG. 10, in this embodiment, the operation cycle of the display circuits A / B is set to 1/60 second, whereas the operation cycle of the image control CPU 63 is 1/30 second. , The display circuit A also actually outputs the same image data twice. That is, the main display device DS1 that normally displays a moving image also displays the same frame twice in succession (reproduction operation at 30 fps).

Next, the image control CPU 63 instructs the display circuit 74B to execute the display operation if the timing is during playback of the auxiliary moving image (ST14). For convenience of explanation, the display operation of the display circuit 74B is permitted every time during playback of the auxiliary video (ST14), but in reality, it is permitted only once at the start of the auxiliary video (low-speed playback). It is only set. Similarly, at the end of playback of the auxiliary moving image, the display operation of the display circuit 74B is set to stop.

As a result of the processing in step ST13, the display circuit 74B repeats the output processing every 1/30 second, but at the timing not passing through the processing in step ST13, the immediately preceding image data is output twice again. .. As a result, the auxiliary moving image having a reproduction time of M seconds in N frames is reproduced at a low speed in 2 × M seconds.

As described above, the display circuit 74B switches and outputs the image data every 1/15 second (ST13 to ST14), but the display circuit 74A has the display area of the frame buffer FBa every 1/30 second. Is switched (ST15). Next, the drawing register that defines the operation of the drawing circuit 76 is instructed to start the operation of the drawing operation (ST16).

As a result, the drawing circuit 76 also starts a predetermined operation every 1/30 second. As described above, the operation contents to be executed by the drawing circuit 76 and the display circuit 74 are set in the drawing register and the display register by the image control CPU 63 at the time of power reset and the necessary timing thereafter. is there.

Continuing the description from FIG. 9B to FIG. 9A, the image control CPU 63 instructs the sequence operation of the drawing circuit 76 and the display circuit 74 in the process of step ST2 described above, and then the image effect scenario. Create a display list DL for the next frame based on. Here, the image effect scenario embodies the image effect specified by the control command CMD'received from the effect control CPU 40.

That is, the image production scenario includes (1) a series of moving images that are continued for a certain period of time and still images (including background images and preview images) in which the drawing position, the arrangement posture, and the enlargement / reduction ratio are appropriately defined. The start time and end time of the movie production, (2) which still image is drawn at what time, at what position, and how are specified. It should be noted that the moving image effect only changes the drawn image of the display device quickly and smoothly, and draws the same or different next image data (frame image data) on the display device at regular intervals. It is the same as a still image in that it does.

Then, the image control CPU 63 refers to the production scenario having such a configuration, and issues a group of drawing commands for specifying the display images of the display devices DS1 and DS2 at each timing (T1, T1 + δ, T1 + 2δ, ...). Generate the listed display list DL. The display list DL specifies which part of the moving image that progresses in time is specified for the moving image by specifying the storage position of the CGROM, and the still image such as the sprite image is stored in the CGROM where. It stipulates where and how to draw the image on the display device.

In FIG. 10, the display list for generating the frame Ai and the frame Bj is also referred to as Ai and Bj for convenience. Then, the display list Ai identifies one frame (A1, A2, ... A6) of a normal moving image or a still image, and the display list Bj is one frame (B1, B2, B3) of an auxiliary moving image played at low speed. Is specified. As described above, the update cycle of the display list Bj is twice that of the other update cycles.

Then, the display list DL (= Ai + Bj) created in this way is transferred from the built-in RAM 59 to the external DRAM 54 by the data transfer circuit 72 instructed by the image control CPU 63 (ST4). The arrow at the timing T1'in FIG. 8 illustrates this operation. The image control CPU 63 does not need to generate one display list DL that specifies one frame of each display device for each operation cycle, and a plurality of display lists DL1, DL2 that specify the display contents at a plurality of timings.・ May be collectively generated in one operation cycle.

Further, in FIG. 10, the process of step ST15 by the image control CPU 63 is indicated by a vertical arrow from the CPU 63 to the drawing circuit 76, and the process of steps ST13 to ST15 by the image control CPU 63 is indicated by the display circuit A / from the CPU 63. It is indicated by a vertical arrow pointing to B.

Subsequently, with reference to FIGS. 9 (c) to 9 (d) and FIG. 10, a drawing operation executed in cooperation with the drawing circuit 76, the graphics decoder 75, the geometry engine 77, and the like will be empirically described. As shown in FIG. 10, this drawing operation is repeated at regular time intervals (δ), but for convenience, in the following description, drawing after the timing T1 + 2δ executed based on the rewritten display list DL (= A1 + B1). The operation will be described.

The drawing circuit 76 sequentially analyzes the drawing commands described in the display list DL (= A1 + B1), which is the oldest unprocessed display list among the display lists stored in the external DRAM 54 (FIG. 6). 9 (c) SS20), the graphics decoder 75 and the geometry engine 77 are made to function for the still images and moving images specified by the drawing command.

Then, the still image data and the moving image data decoded by the graphics decoder 75 are expanded and expanded in the still image decoding area and the moving image decoding area secured in the built-in VRAM 71, respectively (SS22 to SS23). Next, the decoding process is executed by writing the decoded still image data and moving image data to a predetermined position in the frame buffer FB (FBa, FBb) of the VRAM 71 in the drawing mode defined by the drawing command (the drawing process is executed). SS24). The drawing mode includes the drawing position in the frame buffer FB (FBa, FBb), but in the case of a sprite image or the like, the drawing posture, the enlargement / reduction ratio, etc. may be further defined, and the geometry engine 77 works.

When two types of display list DLs (= Ai + Bj) exist, the decoded data of still images and moving images are written to predetermined positions of the frame buffers FBa and FBb based on each display list DL (= Ai + Bj). As a result, the drawing operation is realized (SS24). As described above, the frame buffer FBa / FBb has a double buffer structure divided into a drawing area and a display area, respectively, and in the drawing operation (SS24), more accurately, the drawing area of the frame buffer FBa / FBb. The decoded data will be written at the predetermined position in.

In any case, after the processing of step SS22 or step SS23, a necessary image is drawn at a predetermined position of a predetermined frame buffer FBa / FBb based on the decoded data (moving image / still image) (SS24). Then, since this process is executed from the beginning to the end of the display list DL in the order in which the drawing commands are described, the image drawn first is subsequently overwritten by the image drawn in the same area. .. Normally, a still image is drawn on a background image having an area for the entire frame of the display device, and a moving image is further drawn on the background image.

When the drawing processing for all the drawing commands is completed in this way, the drawing operation is intermittently started and waits until the next drawing operation (SS25). In FIG. 8, it is described by an arrow that a necessary image is drawn in the frame buffer FB (FBa + FBb) at the timing T1 + δ'.

Finally, the operation of the display circuit 74 will be described with reference to FIG. 9D. This display operation is also repeated at regular time intervals (δ), but for convenience, the display operation after the timing T1 + 2δ shown in FIG. 10 will be described in the following description. As described above, at this timing, the image data based on the display list DL (= A1 + B1) is secured in the drawing area of the frame buffer FBa / FBb. Then, this drawing area functions as a display area in the display operation after the timing T1 + 2δ.

As shown in FIG. 9D, the display circuits 74A / 74B read out the image data (A1, B1) stored in the display area of the frame buffers FBa / FBb corresponding to each, and output the image data (A1, B1) to the output selection unit 79. (SS30).

After that, based on the operation of the output selection unit 79, the image data (A1) of the frame buffer FBa output by the display circuit 74A is transmitted to the main display device DS1 via the LVDS unit 80a, and is output by the display circuit 74B. Since the image data (B1) of the frame buffer FBb is transmitted to the sub display device DS2 via the LVDS unit 80b, one frame (A1) of a normal moving image or a still image and one frame (B1) of an auxiliary moving image are used. Will be displayed on each display device DS1 and DS2.

The above is the same not only for the display operation starting from timing T1 + 2δ but also for the display operation starting from timing T1 + 3δ. However, in the display operation starting from timing T1 + 3δ, the display circuit 74B outputs unupdated image data, so that one frame (A2) of a normal moving image or a still image and one frame (B1) of an auxiliary moving image are each display device. It will be displayed on DS1 and DS2. Hereinafter, since the same operation is repeated, the normal moving image is reproduced at 30 fps, and the auxiliary moving image is reproduced at a low speed at 15 fps.

An embodiment of displaying a normal moving image of 30 fps on the main display device DS1 and displaying an auxiliary moving image of 15 pfs on the sub display device DS2 has been described above, but the present invention is not particularly limited. It is also preferable to display an auxiliary moving image. FIG. 11 is a drawing for explaining such an embodiment, and shows an operating state in which a normal moving image and an auxiliary moving image are displayed on the same display device DS1 at the same time.

In order to realize such an operation, the drawing circuit 76 of this embodiment is configured so that the immediately preceding decoded data can be used again. That is, one frame of a moving image or a still image is decoded and expanded in the work area (temporary storage), and this is transferred to the frame buffer FB, but the data in the work area can be reused. In this specification, the drawing command for realizing such an operation is particularly referred to as a reuse command.

Then, in the case of adopting such a configuration, the immediately preceding decoded data can be used again by the reuse command written in the display list B1', B2', B3'... Therefore, at the timing when the drawing circuit 76 receives the display lists B1', B2', B3' ..., The drawing circuit 76 writes the decoded data immediately before that to the frame buffer FBa.

Therefore, for example, in the operation cycle starting from T1 + δ and the operation cycle starting from T1 + 2δ, the same frame B1 of the auxiliary moving image is repeatedly stored in the drawing area of the frame buffer FBa. Since the switching between the display area and the drawing area in the frame buffer FBa is executed every execution cycle δ, in the operation cycle starting from T1 + 2δ, the image data of the same frame B1 is stored in the two areas of the double buffer. It will be stored.

Therefore, the display circuit 47A repeatedly outputs the same frame B1 of the auxiliary moving image to the main display device DS1 in the operation cycle starting from T1 + 2δ and the operation cycle starting from T1 + 3δ. During the two execution cycles, the display device DS1 displays the frames A1 and A2 of the normal moving image together with the frames C1 and C2 of the still image. Therefore, in the end, the normal moving image of 30 fps and the auxiliary moving image of 15 fps are displayed. Will be played back simultaneously on the same display device DS1.

Although the first embodiment in which the preloader 73 does not function has been described above, it is also preferable to utilize the preloader 73 in order to cover the weak points of sequential access to the CGROM 55. FIGS. 12 and 13 use the preloader 73. The second embodiment is shown. Also in this second embodiment, the normal moving image and the auxiliary moving image are displayed on the main display device DS1, and when the auxiliary moving image is played back at a low speed, a series of display lists are displayed at an appropriate frequency (for example, twice). The reuse command is described in (once in).

As shown in FIG. 12, the image effect operation of the second embodiment is based on the display list update process (FIG. 12A) executed by the image control CPU 63 at predetermined time intervals and the display list received from the image control CPU 63. It is realized by each sequence operation (FIGS. 12 (b) to 12 (d)) of the preloader 73, the drawing circuit 76, and the display circuit 74 that operate in the same manner. As for the preloader 73, similarly to the drawing circuit 76 and the display circuit 74, the image control CPU 63 sets the necessary operation parameters at the time of power reset and at the necessary timing thereafter so as to realize the sequence operation described below. It is set in the register group 70.

The image control CPU 63 starts the list update process (ST1) at predetermined time δ intervals, and starts the sequence operation of the preloader 73, the drawing circuit 76, and the display circuit 74 (ST2). As shown in FIG. 13A, the image control CPU 63, the preloader 73, the drawing circuit 76, and the display circuit 74 intermittently execute their own operations in parallel at regular time (δ) intervals. Become. Note that FIG. 13B schematically shows the contents of the internal RAM 59 of the CPU circuit, the internal VRAM 71 of the VDP circuit, the external DRAM 54, and the CGROM 55.

Continuing the description of the operation of the image control CPU 63, following the process of step ST2, the image control CPU 63 updates the display list DL based on the effect scenario (ST3). Then, the image control CPU 63 lists a group of drawing commands for specifying the display image of the display device DS1 at each timing (T1, T1 + δ, T1 + 2δ, ...) With reference to the production scenario having such a configuration. Display lists DL1, DL2, ... Are generated.

As described above, when the auxiliary moving image is played back at a low speed, the reuse command is described in the even-numbered display list (DL2, DL4 ...).

Next, the display list DL configured in this way is transferred to the specified area of the external DRAM 54 and waits for the next list update timing to be reached (ST4). 13 (a) and 13 (b) show that the display list DL1 is generated as a result of the operation of the image control CPU 63 started from the timing T1 and is transferred to the external DRAM 54 at the timing T1'. Has been done.

In the second embodiment, the display list DL1 is rewritten by the preloader 73 at the timing T1 + δ delayed by one timing, and is rewritten by the drawing circuit 76 based on the display list DL1 after the rewriting at the timing T1 + 2δ further delayed by one timing. The drawing process is performed. Then, at the timing T1 + 3δ further delayed by one timing, the display screen specified by the display list DL1 appears on the main display device DS1 based on the display operation of the display circuit 74.

As described above, in the second embodiment, the preloader 73, the drawing circuit 76, and the display circuit 74 are configured to operate with a delay of one timing at a time. Therefore, the preloader 73 started from the timing T1 processes the unprocessed and oldest display list of the external DRAM 54, and specifically, processes the display list generated at the timing immediately before. become. In other words, the display list DL1 generated by the image control CPU 63 at the timing T1 is processed as follows based on the operation of the preloader 73 started from the timing T1 + δ.

Hereinafter, the timing T1 + δ and subsequent steps will be described. The preloader 73 analyzes the display list DL1 which is the oldest unprocessed display list stored in the specified area of the external DRAM 54. Then, when a drawing command required by the CG data of the CG ROM is detected in the display list DL1, the CG bus IF unit obtains the necessary information in order to acquire the group of CG data in the CG data area of the external DRAM 54. Tell 82. Further, the storage position of the CG data in the drawing command related to the preload processing is rewritten from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 (SS10).

The above operation is repeatedly executed every time a drawing command that requires CG data of the CGROM is detected, and all the CG data (compressed data) for constructing one frame of the display device DS1 are from the CGROM 55 to the DRAM 54. It will be secured in the CG data area. Since the CG data once secured in the CG data area of the DRAM 54 is managed to be usable after that, the preload process (SS11) is skipped when the CG data secured at the timing before that is used. Then, only the process (SS10) of rewriting the storage position of the CG data from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 is executed (see the broken line in FIG. 12B).

Then, for the display list DL1 that specifies each frame of the display device DS1, for all the drawing commands described therein, if the necessary CG data transfer process to the DRAM 54 and the day playlist rewrite process are completed, the process is completed. It will wait until the next preload operation that is started intermittently (SS12). In FIG. 13B, the state in which the necessary CG data is transferred from the CGROM 55 to the external DRAM 54 at the timing T1 + δ is indicated by an arrow. The transferred CG data remains in the compressed state.

Regarding the drawing operation (SS20 to SS24) and the output operation (SS30), the operation contents are the same as those in the first embodiment except that the operation timing is delayed. In addition, in FIG. 13B, it is described by an arrow that a necessary image is drawn in the frame buffer FBa at the timing T1 + 2δ and output to the timing T1 + 3δ. The display operation of the display circuit 74 is also repeated at regular time intervals (δ), but the normal moving image is normally reproduced at a speed of 30 fps, and the auxiliary moving image is reproduced at a low speed of 15 fps.

In this embodiment, the processes of steps SS10 to SS11 are not necessarily limited to a single display list DL, and may be sequentially executed for a plurality of n display list DLi. In this case, the image control CPU 63 generates a plurality of display list DLis and transfers them to the DRAM 54 in one operation cycle δ, and the preloader 73 interprets and executes the plurality of display list DLis as early as possible. Become.

As described above, in the second embodiment, the preloader 73, the drawing circuit 76, and the display circuit 74 interlock to execute a series of operations in parallel, so that the processing in charge of each is executed in parallel, so that the image quality is high and the speed is high. It is possible to realize a large-screen image production that changes to the above without any trouble.

Although the examples of the present invention have been described in detail above, the specific description contents are not particularly limited to the present invention. For example, in each of the above-described embodiments, simple moving image reproduction has been described, but in particular, for I-stream moving images, reverse reproduction and seek reproduction are executed on the display devices DS1 and DS2 as needed. Such an operation is performed by updating the display list (B1, B2, ... Bn), which is normally updated in the forward direction, in the reverse direction (Bn, Bn-1, ... B1). It is realized by starting the update from (Bi, Bi + 1, ... Bn).

Further, in each of the above embodiments, the low-speed reproduction of 1/2 times has been described, but the operation of "no switching instruction + operation instruction" in FIG. 10 and the use of the reuse command in FIG. 11 are continuously performed M times. Then, 1 / (M + 1) times slower playback is possible. Further, although regular low-speed playback has been described, during normal playback, the operation of "no switching instruction + operation instruction" in FIG. 10 and the use of the reuse command in FIG. 11 can be continued as many times as necessary. For example, it is possible to realize video playback that is paused at a suitable place.

As a mode of pausing, for example, an operation such as moving quickly and stopping for a while can be exemplified. In any case, by including 1 / (M + 1) times slower playback and pause operation according to the content of the effect, the effect of the effect can be enhanced while suppressing the data capacity of the moving image data. Needless to say, the present invention can be suitably used not only for ball game machines but also for other game machines with image effects such as rotating cylinder game machines.

GM game machine 23 Sub control means DS1, DS2 Display device 51 Image production control means (built-in CPU circuit)
55 Data storage means 52 Image generation means ST3 List generation means 76 Drawing means 74 Output means

Claims (2)

A gaming machine provided with a sub-control means for executing an image effect corresponding to a lottery result of a lottery process executed due to a predetermined switch signal based on a control command received from another control means. The sub control means
Image production control means that centrally controls image production,
A data storage means for storing compressed data that is a component of a still image and / or a moving image that constitutes an image effect, and
It is configured to include an image generation means that realizes an image effect by outputting image data generated from compressed data based on an instruction of the image effect control means to one or a plurality of display devices.
While the image effect control means is provided with a list generation means for generating a drawing list that specifies an image display for one frame of the display device, the image effect control means is provided.
The image generation means receives a drawing circuit that generates image data for one frame corresponding to the drawing list generated by the list generation means, and image data generated by the drawing circuit, and performs necessary processing. An output circuit that receives the image data output by the display circuit and outputs the image data to the display device in a predetermined signal format is provided.
The list generation means and the drawing circuit are operating intermittently with a predetermined operation cycle, and the drawing list generated by the list generation means is an integer N times of the predetermined operation cycle ( N> 0) It is configured so that the image data specified by the drawing list is generated by being interpreted by the drawing circuit at a delayed timing.
Corresponding to the drawing list, the drawing circuit generates image data in the first frame buffer for the first display device and the second frame buffer for the second display device, respectively, when necessary. The display circuit includes a first display circuit that reads out and processes the image data of the first frame buffer, and a second display circuit that reads out and processes the image data of the second frame buffer. ,
Both the first frame buffer and the second frame buffer have a double buffer structure in which the functions are exchangeably switched, and the display is performed at the timing when the drawing circuit generates image data in one of the double buffers. The image effect control means outputs a switching instruction so that the circuit reads out the other stored content of the double buffer.
The reduced data stored in the data storage means by reducing the horizontal direction to W (W <1) times and the vertical direction to H (H ≦ 1) times is transferred to the second frame buffer via the second frame buffer. 2 In a predetermined effect state in which the display circuit magnifies the horizontal direction by 1 / W times and the vertical direction by 1 / H times and outputs it as enlarged image data, the switching instruction to the second frame buffer is the first frame. A gaming machine characterized in that it is configured to output at twice the cycle of the switching instruction to the buffer. A gaming machine provided with a sub-control means for executing an image effect corresponding to a lottery result of a lottery process executed due to a predetermined switch signal based on a control command received from another control means. The sub control means
Image production control means that centrally controls image production,
A data storage means for storing compressed data that is a component of a still image and / or a moving image that constitutes an image effect, and
It is configured to include an image generation means that realizes an image effect by outputting image data generated from compressed data based on an instruction of the image effect control means to one or a plurality of display devices.
While the image effect control means is provided with a list generation means for generating a drawing list that specifies an image display for one frame of the display device, the image effect control means is provided.
The image generation means receives a drawing circuit that generates image data for one frame corresponding to the drawing list generated by the list generation means, and image data generated by the drawing circuit, and performs necessary processing. An output circuit that receives the image data output by the display circuit and outputs the image data to the display device in a predetermined signal format is provided.
The list generation means and the drawing circuit are operating intermittently with a predetermined operation cycle, and the drawing list generated by the list generation means is an integer N times of the predetermined operation cycle ( N> 0) It is configured so that the image data specified by the drawing list is generated by being interpreted by the drawing circuit at a delayed timing.
Corresponding to the drawing list, the drawing circuit generates image data in the first frame buffer for the first display device and the second frame buffer for the second display device, respectively, when necessary. The display circuit includes a first display circuit that reads out and processes the image data of the first frame buffer, and a second display circuit that reads out and processes the image data of the second frame buffer. ,
Both the first frame buffer and the second frame buffer have a double buffer structure in which the functions are exchangeably switched, and the display is performed at the timing when the drawing circuit generates image data in one of the double buffers. The image effect control means outputs a switching instruction so that the circuit reads out the other stored content of the double buffer.
In a predetermined effect state in which the auxiliary moving image is reproduced at 1/2x speed, the auxiliary image data for reproducing the auxiliary moving image is generated in the first frame buffer together with other normal image data, while the auxiliary image is generated. A gaming machine characterized in that the drawing list is configured so that the data update cycle is twice the update cycle of the normal image data.

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