JP6828528B2 - Information processing device, control method of information processing device, and control program of information processing device - Google Patents

Description

The present invention relates to an information processing device, a control method of the information processing device, and a control program of the information processing device.

Recently, an information processing device that makes a programmable device such as an FPGA (Field-Programmable Gate Array) capable of dynamically reconfiguring logic function as an accelerator has attracted attention. In this type of information processing apparatus, when it is determined whether the processing is executed by software or hardware and the processing is executed by hardware, a method of constructing logic in FPGA and executing the processing is known (for example). , Patent Document 1).

For example, the logic to be built in FPGA is generated by sequentially converting a source file written in a high-level language into a control flow graph representation and a control data flow graph representation, and then converting the control data flow graph representation into a hardware description language. (See, for example, Patent Document 2). Further, there is known a method in which a compiler determines a portion of a source file to be executed by software and a portion to be executed by hardware (see, for example, Patent Document 3).

On the other hand, in a data processing device including a plurality of arithmetic units that execute arithmetic processing in parallel, a data access pattern is analyzed in advance by executing a program, and data to be processed by the plurality of arithmetic units is specified based on the analysis result. To. When the cache memory is connected to each of the plurality of arithmetic units, the specified data is stored in the cache memory corresponding to the arithmetic unit that processes the data (see, for example, Patent Document 4).

Japanese Unexamined Patent Publication No. 2004-21426 Special Table 2006-505055 Special Table 2005-535055 Japanese Unexamined Patent Publication No. 2011-8485

By the way, in a domain-oriented information processing apparatus in which a data processing unit that executes data processing for a specific application is mounted on the FPGA, the pattern of memory access by the data processing unit mounted on the FPGA differs for each application. Therefore, when a general-purpose cache memory is used, the cache efficiency such as the cache hit rate may decrease. For example, the data held in the cache memory is replaced according to the LRU (Least Recently Used) method. However, since the various applications executed by the domain-oriented information processing apparatus have different memory access characteristics, the LRU method is not always suitable for all applications. However, in a domain-oriented information processing device, a method of optimizing the cache efficiency for each application has not been proposed.

In one aspect, the present invention aims to optimize cache efficiency according to the characteristics of memory access by the data processing unit programmed in the programmable unit.

In one embodiment, the information processing apparatus includes a storage unit that stores data, a data processing unit that processes data stored in the storage unit, a cache memory unit that stores data used by the data processing unit, and data. A cache control unit that determines whether the data read from the storage unit by the processing unit is stored in the cache memory unit based on the cache control information, and a cache control that generates cache control information based on a memory access request issued by the data processing unit. The programmable unit in which the switching unit is programmed, the analysis unit that analyzes the access address pattern included in the memory access request issued by the data processing unit programmed in the programmable unit, and the access address pattern analyzed by the analysis unit. Based on this, the decision unit that determines the logic of the cache control switching unit to be programmed in the programmable unit, the data processing unit, the cache memory unit, and the cache control unit are programmed into the programmable unit, and the cache control switching unit determined by the determination unit is used. It is provided with a configuration control unit to be programmed in the programmable unit.

In one aspect, the invention can optimize cache efficiency depending on the characteristics of memory access by the data processing unit programmed into the programmable unit.

It is a figure which shows one Embodiment of the information processing apparatus, the control method of an information processing apparatus, and the control program of an information processing apparatus. It is a figure which shows an example of the operation flow of the information processing apparatus shown in FIG. It is a figure which shows an example of the operation of the information processing apparatus shown in FIG. It is a figure which shows the information processing apparatus, the control method of an information processing apparatus, and another embodiment of the control program of an information processing apparatus. It is a figure which shows an example of the chip structure of the programmable part shown in FIG. It is a figure which shows an example of the data processing part programmed in the programmable part shown in FIG. It is a figure which shows an example of the process which constructs the environment which executes the 2nd program shown in FIG. It is a figure which shows an example of the operation of the cache circuit including the cache control switching part generated in step S24 shown in FIG. It is a figure which shows an example of the feature extraction table used in step S22 shown in FIG. It is a figure which shows an example of the process of step S22 shown in FIG. It is a figure which shows an example of the process which constructs the environment which executes the 2nd program in another embodiment of an information processing apparatus. It is a figure which shows an example of the operation of the cache circuit including the cache control switching part generated in step S24 shown in FIG. It is a figure which shows an example of the process which constructs the environment which executes the 2nd program in another embodiment of an information processing apparatus. It is a figure which shows an example of the process which constructs the environment which executes the 2nd program in another embodiment of an information processing apparatus. It is a figure which shows an example of the process which constructs the environment which executes the 2nd program in another embodiment of an information processing apparatus.

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 shows an embodiment of an information processing device, a control method of the information processing device, and a control program of the information processing device. The information processing device 100 shown in FIG. 1 is, for example, a domain-oriented server, and includes a programmable unit 1 such as an FPGA, a storage unit 2 such as a memory module, and an arithmetic processing unit 3 such as a CPU (Central Processing Unit). The information processing device 100 may have an HDD (Hard Disk Drive), a communication interface, and the like in addition to the elements shown in FIG.

The programmable unit 1 is programmed with circuits such as a data processing unit 1a and a cache circuit 1b that process data used in a specific application, for example. The cache circuit 1b includes a cache control switching unit 1c, a cache control unit 1d, and a cache memory unit 1e. The data used by the data processing unit 1a is stored in the cache memory unit 1e. The cache control unit 1d executes control to access the storage unit 2 based on the memory access request issued by the data processing unit 1a. Further, the cache control unit 1d determines whether or not to store the data read from the storage unit 2 by the data processing unit 1a in the cache memory unit 1e based on the cache control information CINF. The cache control switching unit 1c generates cache control information CINF based on the memory access request (read access request or write access request) issued by the data processing unit 1a.

For example, when the cache memory unit 1e holds the data read from the storage unit 2 by the data processing unit 1a, the cache control switching unit 1c provides the cache control information CINF indicating "S" (Shared) based on the read access request. Generate. When the cache memory unit 1e does not hold the data read from the storage unit 2 by the data processing unit 1a, the cache control switching unit 1c generates cache control information CINF indicating "I" (Invalid) based on the read access request. ..

When the cache control information CINF received in response to the read access request is "S", the cache control unit 1d outputs the read access request to the storage unit 2. Then, the cache control unit 1d stores the data read from the storage unit 2 in the cache memory unit 1e and outputs the data to the data processing unit 1a. When the data to be read from the storage unit 2 is already held in the cache memory unit 1e, the cache control unit 1d holds the data in the cache memory unit 1e without outputting the read access request to the storage unit 2. The generated data is output to the data processing unit 1a. When the cache control information CINF received in response to the read access request is "I", the cache control unit 1d outputs the read access request to the storage unit 2. Then, the cache control unit 1d outputs the data read from the storage unit 2 to the data processing unit 1a without storing the data in the cache memory unit 1e.

The cache control unit 1d may generate the cache control information CINF when the data processing unit 1a issues a write access request for writing data to the storage unit 2. For example, when the write data output from the data processing unit 1a is held in the cache memory unit 1e, the cache control switching unit 1c generates cache control information CINF indicating "M" (Modified) based on the write access request. .. When the cache memory unit 1e does not hold the data to be written by the data processing unit 1a in the storage unit 2, the cache control switching unit 1c generates the cache control information CINF indicating "I" based on the write access request.

When the cache control information CINF received in response to the write access request is "M", the cache control unit 1d stores the data output from the data processing unit 1a in the cache memory unit 1e and does not write it in the storage unit 2. .. When the cache control information CINF received in response to the write access request is "I", the cache control unit 1d stores the data output from the data processing unit 1a in the storage unit 2 without storing it in the cache memory unit 1e. Write. The cache control information CINF indicating "M" or "I" generated in response to the write access request issued by the data processing unit 1a is an example of the first information.

The storage unit 2 includes a semiconductor memory such as an SDRAM (Synchronous Dynamic Random Access Memory), a SRAM, or a flash memory. The storage unit 2 has a data area 2a, a program area 2b, and a configuration information area 2c. The data area 2a holds data to be processed by the data processing unit 1a, data used by the arithmetic processing unit 3, and the like. The program area 2b holds the first program 2d, the second program 2e, the control program 2f, and the like. The first program 2d is used when a predetermined data process is executed without using the data processing unit 1a. For example, the first program 2d is a source program including a process equivalent to a process to be executed by the data processing unit 1a.

The second program 2e is used when a predetermined data process is executed by using the data processing unit 1a. For example, the second program 2e is generated by deleting a process equivalent to the process executed by the data processing unit 1a from the first program 2d and adding a process for calling the data processing unit 1a. Therefore, the data processing executed by the first program 2d and the data processing executed by the data processing unit 1a according to the instruction of the second program 2e are equivalent to each other. The first program 2d is an example of a processing program. An example of the operation by the first program 2d and the second program 2e is shown in FIG.

The control program 2f is executed by the arithmetic processing unit 3a to realize the functions of the analysis unit 3b, the determination unit 3c, and the configuration control unit 3d. The control program 2f may be stored in a computer-readable recording medium 4 such as a CD-ROM (Compact Disc Read Only Memory), a DVD (Digital Versatile Disc), or a USB (Universal Serial Bus) memory. In this case, the control program 2f stored in the recording medium 4 is transferred from the recording medium 4 to the program area 2b via an input / output interface (not shown) provided in the information processing apparatus 100. The control program may be transferred from the recording medium 4 to an HDD (not shown) and then transferred from the HDD to the program area 2b.

The configuration information area 2c holds configuration information of various circuits programmed in the programmable unit 1. The configuration information may be generated in advance, or may be generated by the arithmetic processing unit 3 according to the processing performance required for the information processing device 100. The configuration information may be stored in a storage area other than the storage unit 2 of the information processing device 100, or may be stored in a storage area outside the information processing device 100.

The arithmetic processing device 3 includes an arithmetic processing unit 3a such as a CPU core, an analysis unit 3b, a determination unit 3c, and a configuration control unit 3d realized by executing the control program 2f. At least one of the analysis unit 3b, the determination unit 3c, and the configuration control unit 3d may be mounted on the information processing device 100 as hardware (circuit). In this case, at least one of the analysis unit 3b, the determination unit 3c, and the configuration control unit 3d may be realized by using the programmable unit 1.

The arithmetic processing unit 3a executes arithmetic processing by executing programs such as the first program 2d, the second program 2e, and the control program 2f, and realizes the function of the information processing apparatus 100.

The analysis unit 3b indirectly detects the memory access request issued by the data processing unit 1a without operating the data processing unit 1a based on the execution of the first program 2d by the arithmetic processing unit 3a, and the memory access request. Analyze the pattern of access addresses contained in.

The determination unit 3c generates the configuration information of the cache control switching unit 1c that is optimal for the memory access by the data processing unit 1a based on the access address pattern analyzed by the analysis unit 3b, and thereby the cache programmed in the programmable unit 1. The control switching unit 1c is determined. The configuration information of the cache control switching unit 1c generated by the determination unit 3c is stored in the configuration information area 2c. The determination unit 3c programs the programmable unit 1 by selecting the configuration information to be programmed in the programmable unit 1 from the configuration information of the plurality of cache control switching units 1c already stored in the configuration information area 2c. The cache control switching unit 1c may be determined.

The configuration control unit 3d executes a control of reading the configuration information of the cache control switching unit 1c generated by the determination unit 3c from the configuration information area 2c and programming it in the programmable unit 1.

FIG. 2 shows an example of the operation flow of the information processing apparatus 100 shown in FIG. In the flow shown in FIG. 2, an instruction to cause the data processing unit 1a to execute a part of the data processing executed by the arithmetic processing unit 3a is received from the administrator who manages the information processing device 100 or the user who uses the information processing device 100. It starts based on what you have done.

First, in step S1, the information processing apparatus 100 starts execution of the first program 2d that executes predetermined data processing without using the data processing unit 1a. Next, in step S2, the analysis unit 3b of the information processing apparatus 100 indirectly detects the memory access request issued by the data processing unit 1a based on the execution of the first program 2d, and is included in the memory access request. Analyze access address patterns. By using the first program, the access address pattern can be analyzed before the data processing unit 1a and the cache circuit 1b are programmed into the programmable unit 1.

Next, in step S3, the information processing apparatus 100 shifts the process to step S4 when the analysis of the access address pattern by the analysis unit 3b is completed, and processes when the analysis of the access address pattern is not completed. To step S2. For example, the analysis unit 3b completes the analysis of the access address pattern when the characteristics of the access address pattern included in the memory access request issued by the data processing unit 1a are found.

In step S4, the determination unit 3c of the information processing apparatus 100 generates the configuration information of the cache control switching unit 1c based on the pattern of the access address analyzed by the analysis unit 3b, thereby programming the cache control switching in the programmable unit 1. Part 1c is determined.

Next, in step S5, the configuration control unit 3d of the information processing apparatus 100 transfers the cache control switching unit 1c determined by the determination unit 3c to the programmable unit 1 together with the data processing unit 1a, the cache control unit 1d, and the cache memory unit 1e. Program. The processes from step S2 to step S5 show an example of a control method of the information processing device 100 and an example of a control program of the information processing device 100.

Next, in step S6, the information processing apparatus 100 stops the execution of the first program 2d, and starts the execution of the second program 2e from the place corresponding to the place where the execution is stopped. This makes it possible to switch from the first program 2d to the second program 2e without duplicating or missing data processing.

FIG. 3 shows an example of the operation of the information processing apparatus 100 shown in FIG. That is, FIG. 2 shows an example of a control method of the information processing apparatus 100. In FIG. 3, the white square wave indicates the processing executed by the arithmetic processing unit 3a. The shaded rectangles indicate data processing equivalent to the data processing executed by the data processing unit 1a, or data processing executed by the data processing unit 1a. The shaded rectangles indicate the processes executed by the cache control switching unit 1c.

First, the information processing device 100 starts execution of the first program 2d that executes a predetermined data process without using the data processing unit 1a (FIG. 3A). The first program 2d executes data processing equivalent to the data processing executed by the data processing unit 1a (FIG. 3B). In other words, the first program 2d executes data processing using the same data as the data used by the data processing unit 1a in the data processing. The data processing executed by the data processing unit 1a is an example of the first data processing. The data processing executed by the first program 2d is an example of the second data processing. The numbers in parentheses at the left end of FIG. 3 show an example of the operation when the data processing is continued by the first program 2d.

The analysis unit 3b monitors the access (that is, the memory access request) of the data area 2a by the equivalent data processing, and analyzes the pattern of the access address (FIG. 3C). That is, the analysis unit 3b analyzes the access address pattern based on the access to the storage unit 2 when a part of the data processing is executed by the first program 2d. Here, since the first program 2d executes data processing using the same data as the data used by the data processing unit 1a in the data processing, the analysis unit 3b analyzes the characteristics of the memory access by the data processing unit 1a. be able to.

The determination unit 3c determines to generate the configuration information of the cache control switching unit 1c based on the characteristics of the access address pattern analyzed by the analysis unit 3b, and programs the generated cache control switching unit 1c into the programmable unit 1. Decide to do (Fig. 3 (d)). The configuration control unit 3d programs the cache control switching unit 1c generated by the determination unit 3c into the programmable unit 1 together with the data processing unit 1a, the cache control unit 1d, and the cache memory unit 1e (FIG. 3E). The data processing unit 1a, the cache control unit 1d, and the cache memory unit 1e may be programmed in the programmable unit 1 before the cache control switching unit 1c is generated (that is, before the start of the operation of FIG. 3).

After the cache control switching unit 1c is programmed in the programmable unit 1, the information processing apparatus 100 stops the execution of the first program 2d, and starts the execution of the second program 2e from the location corresponding to the location where the execution is stopped. (Fig. 3 (f)). Then, the second program 2e calls the data processing unit 1a, and causes the data processing unit 1a to execute the unexecuted processing among the data processing executed by the first program 2d (FIG. 3 (g)).

While the data processing unit 1a is operating, the cache control switching unit 1c, the cache control unit 1d, and the cache memory unit 1e operate based on the memory access request issued by the data processing unit 1a (FIG. 3 (h)). The cache control switching unit 1c generates the cache control information CINF based on the memory access request, and the cache control unit 1d operates based on the cache control information CINF. Here, since the cache control information CINF is generated according to the memory access characteristics of the data processing unit 1a, the cache hit rate of the cache circuit 1b should be improved as compared with the case where another cache control switching unit is used. Can be done. Further, due to the improvement of the cache hit rate, the frequency of the evacuation process of writing back data from the cache memory unit 1e to the data area 2a in order to secure a storage area for storing new data is reduced. As a result, the cache efficiency can be improved by reducing unnecessary memory access to the data area 2a, and the processing performance of the information processing apparatus 100 can be improved.

The data processing by the data processing unit 1a is executed by the hardware programmed in the programmable unit 1. Therefore, the efficiency of data processing by the data processing unit 1a is higher than the efficiency of data processing by the first program 2d (software). Therefore, the data processing by the data processing unit 1a is completed earlier than the case where the data processing equivalent to the data processing executed by the data processing unit 1a is executed by the first program 2d (FIG. 3 (i)).

After the data processing by the data processing unit 1a is completed, the second program 2e executes the processing by the software (FIG. 3 (j)). After that, the second program 2e calls the data processing unit 1a in order to cause the data processing unit 1a to execute the data processing, and the data processing unit 1a executes the data processing (FIG. 3 (k)). Similar to the above, the data processing by the data processing unit 1a is completed earlier by the first program 2d than the data processing (FIG. 3 (l)). Then, after the data processing by the data processing unit 1a is completed, the second program 2e executes the processing by the software, and the entire processing is completed (FIG. 3 (m)). As shown in FIG. 3, the entire processing executed by the second program 2e including the data processing by the data processing unit 1a is completed earlier than the entire processing executed by the first program 2d.

As described above, in the embodiment shown in FIGS. 1 to 3, the information processing apparatus 100 analyzes the pattern of the access address included in the memory access request output by the data processing unit 1a, and obtains the cache control information CINF based on the analysis result. Generate the cache control switching unit 1c to be output. For example, the first program 2d executed by the information processing apparatus 100 executes data processing using the same data as the data used by the data processing unit 1a in the data processing. Therefore, the analysis unit 3b can analyze the characteristics of the memory access by the data processing unit 1a without operating the data processing unit 1a. Thereby, the cache efficiency such as the cache hit rate of the cache circuit 1b can be optimized according to the characteristics of the memory access of the data processing unit 1a before being mounted on the programmable unit 1. As a result, useless memory access to the data area 2a can be reduced, cache efficiency can be improved, and the processing performance of the information processing apparatus 100 can be improved.

The information processing device 100 uses a first program, which is a source program including a process to be executed by the data processing unit 1a, so that the data processing unit 1a and the cache circuit 1b can be accessed before being mounted on the programmable unit 1. The pattern can be analyzed. When the analysis of the access address pattern is completed, the second program is made to execute the continuation of the processing by the first program, thereby eliminating the waste of executing the same processing in the first program and the second program in duplicate. Can be done. By generating the logic of the cache control switching unit 1c based on the analysis result of the access address pattern, the cache control switching unit 1c can be installed in the programmable unit 1 without preparing the logic of a plurality of types of cache control switching units 1c in advance. Can be programmed.

FIG. 4 shows another embodiment of the information processing device, the control method of the information processing device, and the control program of the information processing device. Elements that are the same as or similar to the elements described in the embodiments shown in FIGS. 1 to 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The information processing device 100A shown in FIG. 4 is, for example, a domain-oriented server. The information processing device 100A includes a programmable unit 10 such as an FPGA, a main memory 20, an arithmetic processing device 30 such as a CPU, an input / output interface 40, an HDD 50, and a communication interface 60.

The programmable unit 10 is programmed with circuits such as a data processing unit 10a and a cache circuit 10b that process data used in a specific application. The data processing unit 10a operates based on the control of the application program (second program) executed by the CPU core 30a, and executes data processing in place of the CPU core 30a. The data processing unit 10a is an example of a data processing unit that processes data. The data processing executed by the data processing unit 10a is an example of the first data processing. Access to the main memory 20 (data read or data write) by the data processing unit 10a is executed via the cache circuit 10b and the LLC (Last Level Cache) 30b.

Similar to the cache circuit 1b shown in FIG. 1, the cache circuit 10b includes a cache control switching unit 10c, a cache control unit 10d, and a cache memory unit 10e. The cache control switching unit 10c determines the cache hint and burst length to be output to the cache control unit 10d based on the memory access request (read access request or write access request) issued by the data processing unit 10a. The cache hint includes information on whether or not to hold the data received from the LLC 30b in the cache memory unit 10e based on the read access request when the data processing unit 10a issues a read access request. Further, the cache hint includes information indicating whether the write data is written to the cache memory unit 10e or output to the LLC 30b when the data processing unit 10a issues a write access request together with the write data.

The burst length includes information indicating the length of data received from the LLC 30b when the data processing unit 10a issues a read access request. The cache hint and burst length are examples of cache control information output by the cache control switching unit 10c. The burst length is an example of the second information in the cache control information.

For example, the cache circuit 10b uses a MESI (Modified, Exclusive, Shared, Invalid) protocol to perform control to maintain data consistency. In the MESI protocol, "Modified" indicates that the data held in the cache memory unit 10e is updated (rewritten) and is different from the data held by the LLC 30b or the main memory 20. “Exclusive” indicates a state in which the data to be accessed is held only in the cache memory unit 10e and the data is not updated. “Shared” indicates a state in which the data to be accessed is held in, for example, the LLC 30b and the cache memory unit 10e, and the data is not updated. "Invalid" indicates that the data held in the cache memory unit 10e is invalid.

When the cache control unit 10d receives the read access request from the data processing unit 10a, the cache control unit 10d determines whether or not the access target data is held in the cache memory unit 10e. When the target data is held in the cache memory unit 10e (cache hit), the cache control unit 10d reads the data from the cache memory unit 10e and outputs the read data to the data processing unit 10a.

When the target data is not held in the cache memory unit 10e (cache miss), the cache control unit 10d issues a read access request to the LLC 30b and receives the data output from the LLC 30b. After that, the cache control unit 10d operates as follows according to the cache hint received from the cache control switching unit 10c in response to the read access request.

When the cache hint is "S", the cache control unit 10d outputs the data received from the LLC 30b to the data processing unit 10a and stores it in the cache memory unit 10e. When there is no free area for storing data in the cache memory unit 10e, the cache control unit 10d executes an evacuation process for writing back any of the data held by the cache memory unit 10e to the LLC 30b. The eviction process includes a write access request to write the data back to the LLC 30b.

When the cache hint is "I", the cache control unit 10d outputs the data received from the LLC 30b to the data processing unit 10a without storing it in the cache memory unit 10e. When a cache miss occurs, the cache control unit 10d issues a read access request to the LLC 30b to read data of a length corresponding to the burst length output from the cache control switching unit 10c in response to the read access request from the LLC 30b. To do.

On the other hand, when the cache control unit 10d receives the write access request together with the write data from the data processing unit 10a, the cache control unit 10d determines whether or not the access target data is held in the cache memory unit 10e. When the target data is held in the cache memory unit 10e (cache hit), the cache control unit 10d operates as follows according to the cache hint received from the cache control switching unit 10c in response to the write access request. To do.

When the cache hint is "M", the cache control unit 10d overwrites the target data of the cache hit held by the cache memory unit 10e with the write data, and does not issue a write access request to the LLC 30b. When the cache hint is "I", the cache control unit 10d deletes the target data of the cache hit held by the cache memory unit 10e, and issues a write access request to the LLC30b to write the write data to the LLC30b. The "M" or "I" cache hint output by the cache control unit 10d based on the write access request is an example of the first information.

When the target data is not held in the cache memory unit 10e (cache miss), the cache control unit 10d operates as follows according to the cache hint received from the cache control switching unit 10c in response to the write access request. To do.

When the cache hint is "M", the cache control unit 10d issues a data read request corresponding to the write data to the LLC30b, replaces the data received from the LLC30b with the write data, and stores the data in the cache memory unit 10e. Here, when the bit width of the write data is smaller than the bit width of the data received from the LLC 30b, a part of the data received from the LLC 30b is replaced with the write data. When the cache hint is "I", the cache control unit 10d issues a write access request to the LLC30b to write the write data to the LLC30b.

The cache memory unit 10e has a plurality of entries (cache lines) that are units of data input / output, and data input / output to the LLC 30b is executed in units of cache lines. When the burst length is "1", the data corresponding to one cache line is accessed. When the burst length is "2", the data corresponding to the two cache lines is accessed. When the burst length is "4", the data corresponding to the four cache lines is accessed.

The main memory 20 is, for example, a memory module in which a plurality of SDRAMs are mounted, and has a data area 20a, a program area 20b, and a configuration information area 20c. The main memory 20 is an example of a storage unit. The data area 20a holds data to be processed by the data processing unit 10a, data used by the arithmetic processing unit 30, and the like.

The program area 20b holds various programs 20d such as an OS, a management program, and an application program, and a control program 20e and the like. For example, any of the application programs is a first program that executes predetermined data processing without using the data processing unit 10a. The first program is an example of a processing program including a function of executing data processing equivalent to the data processing executed by the data processing unit 10a. The data processing executed by the first program is an example of the second data processing.

Any other of the application programs is a second program that executes predetermined data processing using the data processing unit 10a. For example, the various programs 20d and the control program 20e stored in the program area 20b are stored in the HDD 50 via a computer-readable recording medium 70 such as a CD-ROM, a DVD, or a USB memory or a network NW. After that, the various programs 20d and the control program 20e are transferred from the HDD 50 to the main memory 20.

The configuration information area 20c holds configuration information of various circuits programmed in the programmable unit 10. By writing the configuration information to the programmable unit 10, the programmable unit 10 realizes the functions of the data processing unit 10a, the cache circuit 10b, and the like. The configuration information may be generated in advance, or may be generated by a logic synthesis program or the like executed by the arithmetic processing unit 30 according to the processing performance required for the information processing device 100A. The configuration information may be stored in a storage area other than the main memory 20, or may be stored in a storage area outside the information processing apparatus 100A.

The arithmetic processing device 30 has a plurality of CPU cores 30a, LLC30b, and MMU (Memory Management Unit) 30c capable of executing various programs in parallel. The programmable unit 10 is connected to the LLC 30b of the arithmetic processing unit 30 via the bus BUS 1, and the main memory 20 is connected to the MMU 30c of the arithmetic processing unit 30 via the bus BUS 2.

The arithmetic processing device 30 controls the overall operation of the information processing device 100A by executing an OS (Operating System) and a management program by the CPU core 30a. Further, the arithmetic processing device 30 functions as a domain-oriented server by executing an application program by the CPU core 30a.

Further, the arithmetic processing device 30 functions as an analysis unit 30d, a determination unit 30e, and a configuration control unit 30f when the CPU core 30a executes the control program 20e. The analysis unit 30d, the determination unit 30e, and the configuration control unit 30f may be mounted on the information processing apparatus 100A as hardware (circuits).

The LLC 30b is a type of cache memory, and is the cache memory farthest from the CPU core 30a (that is, closest to the main memory 20). The MMU 30c manages memory access to the main memory 20. For example, the MMU 30c converts the virtual address output by the CPU core 30a into the physical address assigned to the main memory 20.

The functions of the analysis unit 30d, the determination unit 30e, and the configuration control unit 30f are the same as the functions of the analysis unit 3b, the determination unit 3c, and the configuration control unit 3d described with reference to FIGS. 1 to 3. The operations of the analysis unit 30d, the determination unit 30e, and the configuration control unit 30f will be described with reference to FIGS. 7 to 10.

One of the input / output interfaces 40 has a connector that is connected to an optical drive device to which a recording medium 70 such as a DVD is mounted, or a USB memory or the like is mounted. The other input / output interface 40 is connected to an input device such as a mouse and a keyboard (not shown) and an output device such as a display (not shown).

The HDD 50 stores programs, configuration information, and the like stored in the main memory 20. The communication interface 60 is connected to a network NW such as the Internet or an intranet, and inputs / outputs information to / from the network NW. The input / output interface 40, the HDD 50, and the communication interface 60 are connected to the arithmetic processing unit 30 via the bus BUS3.

FIG. 5 shows an example of the chip configuration of the programmable unit 10 shown in FIG. The programmable unit 10 includes a plurality of input / output terminal IOs indicated by shaded rectangles, a plurality of ALMs (Adaptive Logic Modules) indicated by white rectangles, a plurality of memories M1, a plurality of memories M2, and a plurality of DSPs (Digital Signal Processors). ). Logic is programmed in the ALM based on the configuration information transferred to the programmable unit 10. Although not particularly limited, the storage elements of the memories M1 and M2 and the internal circuit of the DSP are built in advance in the programmable unit 10, and the connection wiring is built by transferring the configuration information.

For example, the data processing unit 10a shown in FIG. 4 is constructed on the programmable unit 10 by using a predetermined number of input / output terminal IOs, a predetermined number of ALMs, a predetermined number of memories M1, and a predetermined number of DSPs. The cache memory unit 10e is constructed on the programmable unit 10 by using a predetermined number of ALMs and a predetermined number of memories M1 and M2. Each of the cache control unit 10d and the cache control switching unit 10c is constructed on the programmable unit 10 by using a predetermined number of ALMs, a predetermined number of memories M1, and a predetermined number of DSPs.

FIG. 6 shows an example of the data processing unit 10a programmed in the programmable unit 10 shown in FIG. The data processing unit 10a logically synthesizes the data processing portion to be executed by the programmable unit 10 from the first program in which the data processing is completed only by the CPU core 30a, and generates configuration information. For example, the data processing to be executed by the programmable unit 10 is a portion surrounded by a broken line, which is a data processing that takes more time than other data processing and has repeatability. The data processing unit 10a is constructed in the programmable unit 10 by programming the configuration information in the programmable unit 10. That is, a part of the data processing executed by the CPU core 30a by the program is offloaded to the programmable unit 10.

Then, the second program in which the data processing portion by the logically synthesized data processing unit 10a is removed from the first program and the call processing of the data processing unit 10a is added is executed after the data processing unit 10a is programmed in the programmable unit 10. To. As a result, the programmable unit 10 operates as an accelerator of the arithmetic processing unit 30, and the arithmetic processing unit 30 and the programmable unit 10 execute data processing.

FIG. 7 shows an example of a process for constructing an environment for executing the second program shown in FIG. First, as a preliminary preparation, in step S10, the cache control unit 10d and the cache memory unit 10e are logically synthesized to generate configuration information. In step S12, the portion of the first program to be processed by the programmable unit 10 is logically synthesized as the data processing unit 10a, and configuration information is generated.

In step S14, a second program (source program) for causing the logically synthesized data processing unit 10a to execute data processing is generated. Then, by compiling the source program, an object file of the second program that can be executed by the CPU core 30a is generated. In step S16, the first program (source program) is compiled and the object file of the first program is generated.

Note that steps S10, S12, S14, and S16 may be executed in an order other than that shown in FIG. 7, except that steps S12 and S14 are sequentially executed. Further, the advance preparation may be executed by the information processing apparatus 100A, or may be executed by using another tool.

After the preparation is completed, the construction process for constructing an environment for executing the data process on the information processing apparatus 100A using the data processing unit 10a is executed. The construction process is based on receiving an instruction to cause the data processing unit 10a to execute a part of the data processing executed by the CPU core 30a from the administrator who manages the information processing device 100A or a user who uses the information processing device 100A. Is started.
First, in step S20, the information processing device 100A causes the arithmetic processing unit 30 to start executing the first program.

Next, in step S22, the analysis unit 30d of the information processing apparatus 100A analyzes the instruction corresponding to the operation of the data processing unit 10a in the first program, and extracts the characteristics of the memory access instruction. Here, the instruction corresponding to the operation of the data processing unit 10a is an instruction included in the portion surrounded by the broken line in the first program shown in FIG.

Next, in step S24, the determination unit 30e of the information processing apparatus 100A generates the logic of the cache control switching unit 10c based on the features extracted in step S22, so that the cache control switching unit programmed in the programmable unit 10 10c is determined.

Next, in step S26, the configuration control unit 30f of the information processing device 100A programs the configuration information of the cache circuit 10b and the configuration information of the data processing unit 10a in the programmable unit 10. The cache circuit 10b includes a cache control switching unit 10c, a cache control unit 10d, and a cache memory unit 10e. That is, the information processing apparatus 100A converts the configuration information of the cache control unit 10d, the cache memory unit 10e, and the data processing unit 10a prepared in advance and the configuration information of the cache control switching unit 10c generated in step S24 into the programmable unit 10. Program to. Then, the construction process for constructing the environment for executing the data processing using the data processing unit 10a is completed. This makes it possible to execute the second program.

The processes from step S22 to step S26 show an example of the control method of the information processing device 100A and an example of the control program of the information processing device 100A, and correspond to the processes shown in FIGS. 3A to 3E. .. In other words, by replacing the data processing unit at the right end of FIG. 3 with the data processing unit 10a and changing the reference numerals of the respective elements, FIG. 3 shows an example of the operation of the information processing apparatus 100A.

For example, the analysis unit 30d analyzes the access address pattern based on the access to the main memory 20 when a part of the data processing is executed by the first program executed by the CPU core 30a. The determination unit 30e determines to generate the cache control switching unit 10c based on the characteristics of the access address pattern analyzed by the analysis unit 30d, and to program the generated cache control switching unit 1c in the programmable unit 10. The configuration control unit 30f programs the cache control switching unit 10c generated by the determination unit 30e into the programmable unit 10 together with the data processing unit 10a, the cache control unit 10d, and the cache memory unit 10e.

After the cache control switching unit 10c is programmed in the programmable unit 1, the information processing apparatus 100A stops the execution of the first program, and starts the execution of the second program from the location corresponding to the location where the execution is stopped. Then, the second program calls the data processing unit 10a, and causes the data processing unit 10a to execute the unexecuted processing among the data processing executed by the first program. While the data processing unit 10a is operating, the cache control switching unit 10c, the cache control unit 10d, and the cache memory unit 10e operate based on the memory access request issued by the data processing unit 10a. The cache control switching unit 10c generates a cache hint and a burst length based on the memory access request, and the cache control unit 10d operates based on the cache hint and the burst length.

The configuration information of the cache control unit 10d, the cache memory unit 10e, and the data processing unit 10a may be programmed in the programmable unit 10 before starting the process of step S20. In this case, in advance preparation, an interface specification for connecting the data processing unit 10a and the cache control switching unit 10c to each other and an interface specification for connecting the cache control switching unit 10c and the cache control unit 10d to each other are determined. Then, the determination unit 30e generates the logic of the cache control switching unit 10c according to the interface specifications determined in advance.

FIG. 8 shows an example of the operation of the cache circuit including the cache control switching unit 10c generated in step S24 shown in FIG. The left column shows an instruction group (source program) equivalent to the process executed by the data processing unit 10a and its line number. The instruction group shown in FIG. 8 shows an example of an instruction executed within the frame of the broken line of the first program of FIG. For example, the instruction group includes the processing of three processes A, B, and C.

"LD" indicates a load instruction, "ST" indicates a store instruction, an instruction with "EXE" indicates an arithmetic instruction, and "BR" indicates a branch instruction. For example, "LD A1, Da1" on the first line indicates that data is read from the memory area at address A1 and stored in the register Da1. The fourth line "ST A3, Da3" indicates that the data held in the register Da3 is stored in the memory area of the address A3. The third line "EXE1 Da3 (Da1, Da2)" indicates that the data held in the registers Da1 and Da2 are calculated and the calculation result is stored in the register Da3. “BR Da3 BC” on the 5th line indicates that the 6th line or the 21st line branches depending on the value stored in the register Da3. "B" and "C" indicate labels.

The central column shows an example of the operation of the cache circuit 10b, and the cache hint and the burst length are generated by the cache control switching unit 10c for each memory access request (load instruction LD or store instruction ST). The column on the right shows an example of the operation of another cache circuit that does not have the cache control switching unit 10c, the cache hint is fixed to "S" (read access) and "M" (write access), and the burst length is "". It is fixed at 1 ”. In the center column and the right column, "miss" indicates the occurrence of a cache miss, "hit" indicates the occurrence of a cache hit, and the number indicated by "expulsion occurrence" is the number of cache lines that expel data. Is shown.

In the operation of the cache circuit 10b, in the read access (address A1) executed by the data processing unit 10a corresponding to the load instruction LD on the first line, the cache control switching unit 10c caches the cache hint (= "I"). Output to the control unit 10d. When the data processing unit 10a does not execute the read access (address A1) after that, the data output from the LCC 30b based on the read access does not have to be held in the cache memory unit 10e.

In this case, by setting the cache hint to "I", it is possible to prevent the cache line from being unnecessarily expelled from the cache memory unit 10e. On the other hand, in the operation of other cache circuits, the cache hint is "S" in the read access (address A1) executed by the data processing unit 10a corresponding to the load instruction LD on the first line, so that the cache line. Useless eviction occurs.

In the read access (address A2) executed by the data processing unit 10a in response to the load instruction LD on the second line, the cache control switching unit 10c outputs a cache hint (= "S") to the cache control unit 10d. The load instruction LD (address A2) is also executed on the 22nd line. When the data processing unit 10a executes read access of the same address a plurality of times, by setting the cache hint of the first read access to "S", the second and subsequent read accesses can be cache hit.

In the write access (address A3) executed by the data processing unit 10a in response to the store instruction ST on the fourth line, the cache control switching unit 10c has a cache hint (= "M") and a burst length (= "1"). Is output to the cache control unit 10d. The store instruction ST (address A3) is also executed on the 25th line. When the data processing unit 10a executes the write access of the same address a plurality of times, the frequency of the write access request issued to the LLC 30b can be reduced by setting the cache hint of the write access to "M".

In the read access (address B1) executed by the data processing unit 10a in response to the load instruction LD on the 7th line, the cache control switching unit 10c has a cache hint (= "S") and a burst length (= "2"). Is output to the cache control unit 10d. The read access address B2 executed by the data processing unit 10a in response to the load instruction LD on the eighth line is continuous with the address B1. In this case, by setting the burst length to "2", the read access (address B2) can be cache-hit, and the frequency of access requests to the LLC 30b can be reduced.

On the other hand, in the operation of other cache circuits, the burst length of the read access (address B1) executed by the data processing unit 10a corresponding to the load instruction LD on the 7th line is set to "1". Therefore, a cache error occurs in the read access (address B2) executed by the data processing unit 10a in response to the load instruction LD on the eighth line, and the cache control unit 10d issues a useless read access request to the LLC 30b. ..

In the write access (address B3) executed by the data processing unit 10a in response to the store instruction ST on the 10th line, the cache control switching unit 10c has a cache hint (= "I") and a burst length (= "1"). Is output to the cache control unit 10d. When the data processing unit 10a does not execute the write access (address B3) after that, the write data output by the data processing unit 10a together with the write access does not have to be held in the cache memory unit 10e. In this case, by setting the cache hint to "I" and writing the write data directly to the LLC30b, it is possible to prevent the cache line from being unnecessarily expelled from the cache memory unit 10e.

On the other hand, in the operation of another cache circuit, the cache hint of the write access (address B3) executed by the data processing unit 10a corresponding to the store instruction ST on the 10th line is set to "M". Therefore, useless data that is not used in the subsequent access is held in the cache memory unit 10e, and useless evacuation of the cache line occurs.

In the read access (address C1) executed by the data processing unit 10a in response to the load instruction LD on the 23rd line, the cache control switching unit 10c caches the cache hint (= "I") as in the first line. Output to the control unit 10d. When the data processing unit 10a does not execute the read access (address C1) after this, the cache hint can be set to "I" to prevent the cache line from being unnecessarily expelled from the cache memory unit 10e. it can.

In this way, the cache control switching unit 10c generated based on the characteristics of the access address pattern of the data processing unit 10a causes the cache circuit 10b to generate unnecessary eviction processing and unnecessary access request to the LLC 30b. It can be deterred. As a result, the usage efficiency of the bus BUS 1 shown in FIG. 4 can be improved and the processing performance of the information processing apparatus 100A can be improved as compared with other cache circuits.

FIG. 9 shows an example of the feature extraction table TBL used in step S22 shown in FIG. The feature extraction table TBL is used to record the features of the memory access instruction extracted by the analysis unit 30d. The feature extraction table TBL has a plurality of entries including an area for storing an access type, an access address, a cache hint, and a burst length.

In the access type area, information indicating read is stored when the memory access instruction from which the feature is extracted is a read instruction, and information indicating write is stored when the memory access instruction from which the feature is extracted is a write instruction. To. In the access address area, the address included in the memory access instruction from which the feature is extracted is stored.

In the cache hint area, the cache hint used by the cache control unit 10d is stored. The cache hint stores "S" indicating "Shared", "M" indicating "Modified", "I" indicating "Invalid", or "E" indicating "Exclusive".

When the access type is read, the cache hint indicates whether or not the cache control unit 10d holds the data received from the LLC 30b in the cache memory unit 10e based on the read access request corresponding to the read instruction. When the access type is write, the cache hint is such that the cache control unit 10d stores the write data included in the write access request in the cache memory unit 10e or outputs the write data to the LLC30b based on the write access request corresponding to the write instruction. Indicates whether to do it.

In the burst length area, a burst length indicating the number of data input to the cache memory unit 10e by the memory access instruction is stored. The burst length indicates the number of accesses of the cache line, which is an access unit of the cache memory unit 10e.

The analysis unit 30d sequentially stores the access type and the access address in the feature extraction table TBL for each memory access instruction until the features of the memory access instruction can be extracted. Then, while extracting the characteristics of the memory access instruction, the optimum cache hint and burst length for the memory access request stored in each entry are determined, and the determined cache hint and burst length are stored in each entry.

FIG. 10 shows an example of the process of step S22 shown in FIG. 7. First, in step S222, the analysis unit 30d initializes the feature extraction table TBL. For example, an invalid value is stored in the access type and access address area. "I" is stored in the cache hint area, and "1" is stored in the burst length area.

Next, in step S224, the analysis unit 30d detects a memory access instruction from the instructions that are sequentially executed. The memory access instruction to be detected is a memory access instruction included in a portion surrounded by a broken line to be processed by the data processing unit 10a in the first program shown in FIG.

Next, in step S226, the analysis unit 30d shifts the process to step S228 when the detected memory access instruction is a store instruction, and if the detected memory access instruction is not a store instruction, it is a load instruction, so that the process is performed. The process proceeds to step S232.

In step S228, when the address included in the store instruction detected this time is the same as the address included in the previously detected store instruction, the analysis unit 30d shifts the process to step S230. When the address included in the detected store instruction is different from the address included in the previously detected store instruction, the analysis unit 30d shifts the process to step S240.

In step S230, the analysis unit 30d stores the information indicating the write, the address value, and the cache hint = "M" in the feature extraction table TBL corresponding to the store instructions having the same address, and performs processing. The process proceeds to step S240.

On the other hand, in step S232, when the address included in the load instruction detected this time is the same as the address included in the previously detected load instruction, the analysis unit 30d shifts the process to step S234. If the address included in the detected load instruction is different from the address included in the previously detected load instruction, the analysis unit 30d shifts the process to step S236.

In step S234, the analysis unit 30d stores the information indicating the read, the address value, and the cache hint = "S" in the feature extraction table TBL in response to the load instructions having the same addresses, and performs processing. The process proceeds to step S236.

In step S236, when the addresses of the current load instruction and the immediately preceding load instruction are the same, the analysis unit 30d shifts the process to step S238, and when the addresses of the current load instruction and the immediately preceding load instruction are different from each other. , The process proceeds to step S240. In step S238, the analysis unit 30d displays the read indicating information, the address value, and the cache hint = "S" in the feature extraction table TBL corresponding to the load instruction having the same address as the immediately preceding load instruction. Burst length = "2" is stored. After this, the process proceeds to step S240.

In step S240, when the analysis unit 30d determines that the features of the memory access instruction are extracted and the cache hit rate of the cache memory unit 10e can be improved based on the information stored in the feature extraction table TBL, the analysis unit 30d ends the process. When the analysis unit 30d determines that the extraction of the characteristics of the memory access instruction is insufficient, the process returns to step S224 and the extraction of the characteristics of the memory access instruction is continued. In this way, the analysis unit 30d extracts the characteristics of the memory access request instruction issued from the data processing unit 10a by using the memory access instruction generated by the execution of the first program.

For example, the feature extraction table TBL in which the features of the memory access instruction are stored is programmed in the memory M1 (FIG. 5) in the programmable unit 10 as a part of the cache control switching unit 10c. The feature extraction table TBL in which the features of the memory access instruction are stored may be programmed in the ALM in the programmable unit 10 as a part of the cache control switching unit 10c.

As described above, even in the embodiments shown in FIGS. 4 to 10, the same effects as those in the embodiments shown in FIGS. 1 to 3 can be obtained. For example, the cache efficiency of the cache circuit 10b can be optimized according to the characteristics of the memory access of the data processing unit 10a, and the processing performance of the information processing apparatus 100A can be improved. The access address pattern can be analyzed before the data processing unit 10a and the cache circuit 10b are mounted on the programmable unit 10. It is possible to eliminate the waste of executing the same process in the first program and the second program in duplicate, or to prevent the process from being omitted.

FIG. 11 shows an example of a process for constructing an environment for executing the second program in another embodiment of the information processing apparatus. Detailed description of the same elements as in FIG. 7 will be omitted. In FIG. 11, step S22A is executed instead of step S22 of FIG. The process except step S22A is the same as that in FIG.

The processes shown in steps S22A, S24, and S26 are executed by the control program executed by the information processing apparatus. That is, the processes shown in steps S22A, S24, and S26 show an example of the control method of the information processing device and an example of the control program of the information processing device.

The information processing device that executes steps S20, S22A, S24, and S26 is the same as the information processing device 100A shown in FIG. 4, except that the control program 20e shown in FIG. 4 is different. In other words, the information processing apparatus that executes steps S20, S22A, S24, and S26 is different from the information processing apparatus 100A shown in FIG. 4, except that the processes executed by the analysis unit 30d and the determination unit 30e shown in FIG. 4 are different. The same is true.

In step S22A, the analysis unit 30d of the information processing apparatus 100A analyzes an instruction corresponding to the operation of the data processing unit 10a in the first program, and detects a branch destination having a higher probability of branching in the branch instruction. Then, the analysis unit 30d extracts the characteristics of the memory access executed at the branch destination having a higher probability of branching than the others. That is, the analysis unit 30d analyzes the access address pattern of the plurality of processes A, B, and C shown in FIG. 12, which are executed more frequently than the other processes. Next, in step S24, the determination unit 30e generates the logic of the cache control switching unit 10c based on the features extracted in step S22A.

FIG. 12 shows an example of the operation of the cache circuit 10b including the cache control switching unit 10c generated in step S24 shown in FIG. Detailed description of the same or similar elements as in FIG. 8 will be omitted. The instruction group (source program) equivalent to the processing executed by the data processing unit 10a shown in the left column is the same as that in FIG.

The central column shows the operation of the cache circuit including the cache control switching unit generated based on the extraction of the characteristics of the memory access executed in the process B in the branch instruction BR on the fifth line. That is, the central column shows the operation of the cache circuit including the cache control switching unit generated when the probability of branching to the label B is higher than the probability of branching to another label B.

The column on the right side shows the operation of the cache circuit including the cache control switching unit generated based on the extraction of the characteristics of the memory access executed in the process C in the branch instruction BR on the fifth line. That is, the column on the right side shows the operation of the cache circuit including the cache control switching unit generated when the probability of branching to the label C is higher than the probability of branching to another label C.

In the branch instruction BR on the 5th line, when the probability of branching to the label B is high, the burst length of the read access (address B1) executed by the data processing unit 10a corresponding to the load instruction LD on the 7th line is "2". Is set to. As a result, the next read access (address B2) can be cache-hit, and the frequency of access requests to the LLC30b can be reduced. In this example, the cache hint is set to "S" and the burst length is set to "2" for all read accesses so that the cache efficiency in process B is high.

On the other hand, when the probability of branching to the label C is high in the branch instruction BR on the fifth line, for example, in order to improve the access efficiency of the load instruction LD (address A2) on the 22nd line, the load instruction (address) on the second line The cache hint of A2) is set to "S". Further, since the load instruction LD (address A1) on the first line and the load instruction (address B2) on the eighth line are not executed in the process C, the cache hint is set to "I".

Further, since the read access of the address B1 is executed in the process C after the load instruction LD (address B1) on the 7th line is executed (not shown), the cache hint of the load instruction on the 7th line is ". It is set to "S". Since the data read by the load instruction LD (address C1) on the 23rd line is not used in the subsequent process C, the cache hint of the load instruction LD on the 23rd line is set to "I".

As a result, the load instruction LD on the 22nd line can be made a cache hit, and it is possible to prevent unnecessary evacuation of the cache line based on the load instruction LD on the 23rd line. In addition, it is possible to prevent unnecessary eviction of the cache line from occurring in other processes (first and eighth lines) that execute processes related to process C.

In the operation shown in FIG. 12, the write access executed by the data processing unit 10a in response to the store instruction ST has the cache hint set to "M" and the burst length set to "M" as in the right column of FIG. It is set to "1".

As described above, also in the embodiments shown in FIGS. 11 and 12, the same effects as those in the embodiments shown in FIGS. 1 to 3 can be obtained. For example, the cache efficiency of the cache circuit 10b can be optimized according to the characteristics of the memory access of the data processing unit 10a, and the processing performance of the information processing apparatus 100A can be improved. The access address pattern can be analyzed before the data processing unit 10a and the cache circuit 10b are mounted on the programmable unit 10. It is possible to eliminate the waste of executing the same process in the first program and the second program in duplicate, or to prevent the process from being omitted.

Further, in the embodiment shown in FIGS. 11 and 12, the cache efficiency of the cache circuit 10b can be optimized according to the characteristics of the access address pattern of the processing having a higher execution frequency than the others. Thereby, for example, the cache efficiency of the cache circuit 10b can be optimized by specializing in the process C or the process C.

FIG. 13 shows an example of a process for constructing an environment for executing the second program in another embodiment of the information processing apparatus. Detailed description of the same elements as in FIG. 7 will be omitted. In FIG. 13, in advance preparation, step S11B for logically synthesizing a plurality of cache control switching units is added to FIG. 7. Further, step S24B is executed instead of step S24 in FIG. 7. Other processing is the same as in FIG.

The processes shown in steps S22, S24B, and S26 are executed by the control program executed by the information processing apparatus. That is, the processes shown in steps S22, S24B, and S26 show an example of the control method of the information processing device and an example of the control program of the information processing device. The information processing device that executes steps S20, S22, S24B, and S26 is the same as the information processing device 100A shown in FIG. 4, except that the control program 20e shown in FIG. 4 is different. In other words, the information processing device that executes steps S20, S22, S24B, and S26 is the same as the information processing device 100A shown in FIG. 4, except that the processing executed by the determination unit 30e shown in FIG. 4 is different.

In step S11B, a plurality of types of cache control switching units that match the characteristics of various memory accesses are logically synthesized to generate configuration information. The advance preparation may be executed by the information processing apparatus 100A, or may be executed by using another tool. Step S11B may be arranged at another location in the preparatory flow.

In step S24B, the determination unit 30e of the information processing apparatus 100A determines the cache control in which the memory access efficiency is higher than the others among the plurality of types of cache control switching units generated in step S11B based on the features extracted in step S22. Select the switching unit 10c. Note that step S22A shown in FIG. 11 is executed instead of step S22, and in step S24B, the cache control switching unit 10c in which the determination unit 30e has a higher memory access efficiency than the others based on the features extracted in step S22A. May be selected.

Since the determination unit 30e can use the configuration information of the cache control switching unit generated in advance, the process of generating the cache control switching unit 10c based on the analysis result of the access address pattern can be omitted. As a result, the number of instructions of the first program executed before preparing the cache control switching unit 10c to be programmed in the programmable unit 10 can be minimized. As a result, the operating rate of the data processing unit 10a used for the data processing executed by the information processing apparatus 100A can be improved, and the processing performance of the data processing can be improved.

As described above, even in the embodiment shown in FIG. 13, the same effect as that of the embodiment shown in FIGS. 1 to 3 can be obtained. For example, the cache efficiency of the cache circuit 10b can be optimized according to the characteristics of the memory access of the data processing unit 10a, and the processing performance of the information processing apparatus 100A can be improved. The access address pattern can be analyzed before the data processing unit 10a and the cache circuit 10b are mounted on the programmable unit 10. It is possible to eliminate the waste of executing the same process in the first program and the second program in duplicate, or to prevent the process from being omitted.

Further, in the embodiment shown in FIG. 13, by using the configuration information of the cache control switching unit generated in advance preparation, the first execution is executed until the cache control switching unit 10c to be programmed in the programmable unit 10 is prepared. The number of program instructions can be minimized. As a result, the operating rate of the data processing unit 10a used for the data processing executed by the information processing apparatus 100A can be improved, and the processing performance of the data processing can be improved.

FIG. 14 shows an example of a process for constructing an environment for executing the second program in another embodiment of the information processing apparatus. Detailed description of the same elements as in FIG. 7 will be omitted. In FIG. 14, step S24C is executed in place of step S24 in FIG. 7, and step S23C is added after step S22 in FIG. The processing except for steps S23C and S24C is the same as in FIG.

The processes shown in steps S22, S23C, S24C, and S26 are executed by the control program executed by the information processing apparatus. That is, the processes shown in steps S22, S23C, S24C, and S26 show an example of the control method of the information processing device and an example of the control program of the information processing device. The information processing device that executes steps S20, S22, S23C, S24C, and S26 is the same as the information processing device 100A shown in FIG. 4, except that the control program 20e shown in FIG. 4 is different. In other words, the information processing device that executes S20, S22, S23C, S24C, and S26 operates in the same manner as the information processing device 100A shown in FIG. 4, except that the processing executed by the determination unit 30e shown in FIG. 4 is different. To do.

In step S23C, the determination unit 30e detects a free area in which the cache control switching unit can be programmed in the programmable unit 10. For example, the determination unit 30e detects the number of unused ALMs, the number of unused memories M1, and the number of unused DSPs in the programmable unit 10 shown in FIG.

Next, in step S24C, the determination unit 30e generates the logic of the cache control switching unit 10c of a scale programmable in the free area based on the features extracted in step S22. That is, the determination unit 30e generates a circuit-scale cache control switching unit 10c that can be mounted by using the unused ALM, memory M1, and DSP.

The performance of the cache control switching unit 10c increases as the circuit scale increases, and decreases as the circuit scale decreases. Here, the performance of the cache control switching unit 10c is higher as the cache hit rate is higher, and is higher as the cache line ejection frequency is lower. As described above, in steps S23C and S24C, the cache control switching unit 10c having the optimum performance according to the free area of the programmable unit 10 can be mounted on the programmable unit 10. Further, it is possible to solve the problem that the cache control switching unit 10c is not programmed in the programmable unit 10 due to the limitation of the free area.

As in step S22A shown in FIG. 11, the analysis unit 30d may extract the characteristics of the memory access executed at the branch destination having a higher probability of branching than the others. Further, as in step S24B shown in FIG. 13, instead of generating the logic of the cache control switching unit 10c, the determination unit 30e has a higher memory access efficiency than the others from among the plurality of cache control switching units generated in advance. A higher cache control switching unit may be selected. In this case, the determination unit 30e selects the cache control switching unit according to the free area of the programmable unit 10. Further, in addition to the determination unit 30e selecting the cache control switching unit having a higher memory access efficiency than the others, as shown in FIG. 11, the memory at the branch destination where the analysis unit 30d has a higher probability of branching than the others. Access features may be extracted.

As described above, even in the embodiment shown in FIG. 14, the same effect as that of the embodiment shown in FIGS. 1 to 3 can be obtained. For example, the cache efficiency of the cache circuit 10b can be optimized according to the characteristics of the memory access of the data processing unit 10a, and the processing performance of the information processing apparatus 100A can be improved. The access address pattern can be analyzed before the data processing unit 10a and the cache circuit 10b are mounted on the programmable unit 10. It is possible to eliminate the waste of executing the same process in the first program and the second program in duplicate, or to prevent the process from being omitted.

Further, in the embodiment shown in FIG. 14, the cache control switching unit 10c having the optimum performance according to the free area of the programmable unit 10 can be mounted on the programmable unit 10. Further, it is possible to solve the problem that the cache control switching unit 10c is not programmed in the programmable unit 10 due to the limitation of the free area.

FIG. 15 shows an example of a process for constructing an environment for executing a second program in another embodiment of the information processing apparatus. Detailed description of the same elements as in FIG. 7 will be omitted. In FIG. 15, steps S11D, S13D, and 17D for logically synthesizing a plurality of cache control switching units are added to FIG. 7 in advance preparation. Further, steps S20D, S22D, S24D, and S26D are executed instead of steps S20, S22, S24, and S26 in FIG. Other processing is the same as in FIG.

The processes shown in steps S22D, S24D, and S26D are executed by the control program executed by the information processing apparatus. That is, the processes shown in steps S22D, S24D, and S26D show an example of the control method of the information processing device and an example of the control program of the information processing device. The information processing apparatus that executes steps S20D, S22D, S24D, and S26D is the information processing apparatus shown in FIG. 4, except that the control program 20e shown in FIG. 4 is different and the analysis unit 30d is arranged in the programmable unit 10. It is the same as 100A. In other words, the information processing apparatus that executes steps S20D, S22D, S24D, and S26D operates in the same manner as the information processing apparatus 100A shown in FIG. 4, except that the processing executed by the determination unit 30e shown in FIG. 4 is different. ..

In step S11D, the default cache control switching unit that generates the standard cache hint and the burst length is logically synthesized, and the configuration information is generated. In step S13D, the analysis circuit that analyzes the characteristics of the memory access of the data processing unit 10a shown in FIG. 4 is logically synthesized, and the configuration information is generated. After step S14, in step S17D, the data processing unit 10a, the cache control unit 10d, the cache memory unit 10e, the default cache control switching unit, and the analysis circuit are programmed in the programmable unit 10. In addition, steps S11D and S13D may be arranged at other places in the flow of advance preparation. The advance preparation may be executed by the information processing apparatus 100A, or may be executed by using another tool.

After the preparation is completed, in step S20D, the information processing device 100A causes the arithmetic processing unit 30 to start executing the second program. Next, in step S22D, the analysis unit 30d programmed in the programmable unit 10 extracts the characteristics of the memory access request output by the data processing unit 10a which is called and operates by the second program. That is, by mounting the analysis unit 30d in the programmable unit 10, it is possible to directly analyze the characteristics of the memory access of the data processing unit 10a called by the second program without executing the first program. Since the memory access request output by the data processing unit 10a (hardware) can be directly analyzed, the time required for extracting the characteristics of the memory access request can be shortened as compared with the method shown in FIG. 7. As in step S22A shown in FIG. 11, the analysis unit 30d may extract the characteristics of the memory access executed at the branch destination having a higher probability of branching than the others.

Next, in step S24D, the determination unit 30e generates the logic of the cache control switching unit 10c based on the features extracted by the analysis unit 30d on the programmable unit 10. Similar to step S24D shown in FIG. 14, the determination unit 30e may generate the logic of the cache control switching unit 10c of a programmable scale in the free area based on the features extracted in step S22D. Further, the analysis unit 30d extracts the characteristics of the memory access at the branch destination where the probability of branching is higher than the others, and the determination unit 30e generates the logic of the cache control switching unit 10c of a scale programmable in the free area. May be good.

Further, as in step S24B shown in FIG. 13, instead of generating the logic of the cache control switching unit 10c, the determination unit 30e has a higher memory access efficiency than the others from among the plurality of cache control switching units generated in advance. A higher cache control switching unit may be selected. In this case, the analysis unit 30d may extract the characteristics of the memory access at the branch destination having a higher probability of branching than the others, and the determination unit 30e generates the logic of the cache control switching unit 10c of a programmable scale in the free area. You may. Further, the analysis unit 30d extracts the characteristics of the memory access at the branch destination where the probability of branching is higher than the others, and the determination unit 30e generates the logic of the cache control switching unit 10c of a scale programmable in the free area. May be good.

Next, in step S26D, the configuration control unit 30f replaces the default cache control switching unit programmed in the programmable unit 10 with the cache control switching unit 10c generated in step S24D. Then, the information processing apparatus 100A continues the execution of the second program.

As described above, even in the embodiment shown in FIG. 15, the same effect as that of the embodiment shown in FIGS. 1 to 3 can be obtained. For example, the cache efficiency of the cache circuit 10b can be optimized according to the characteristics of the memory access of the data processing unit 10a, and the processing performance of the information processing apparatus 100A can be improved.

Further, in the embodiment shown in FIG. 15, by mounting the analysis unit 30d in the programmable unit 10, the memory access feature of the data processing unit 10a called by the second program is directly characterized without executing the first program. Can be analyzed. Since the memory access request output by the data processing unit 10a (hardware) can be directly analyzed, the time required for extracting the characteristics of the memory access request can be shortened as compared with the method according to FIG.

The following additional notes will be further disclosed with respect to the above embodiments shown in FIGS. 1 to 10.
(Appendix 1)
A storage unit that stores data and
A data processing unit that processes data stored in the storage unit, a cache memory unit that stores data used in the data processing unit, and data read from the storage unit by the data processing unit are stored in the cache memory unit. A programmable unit in which a cache control unit that determines whether to use the cache control information is programmed, a cache control switching unit that generates the cache control information based on a memory access request issued by the data processing unit, and a programmable unit are programmed.
An analysis unit that analyzes the pattern of access addresses included in the memory access request issued by the data processing unit programmed in the programmable unit, and an analysis unit.
A determination unit that determines the logic of the cache control switching unit programmed into the programmable unit based on the access address pattern analyzed by the analysis unit.
The data processing unit, the cache memory unit, and the cache control unit are programmed into the programmable unit, and the cache control switching unit determined by the determination unit is programmed into the programmable unit. Information processing device.
(Appendix 2)
It is provided with an arithmetic processing unit that executes a processing program including a function of executing a second data processing equivalent to the first data processing executed by the data processing unit.
The information processing apparatus according to Appendix 1, wherein the analysis unit analyzes the pattern of the access address based on the access to the storage unit generated by the execution of the second data processing by the processing program.
(Appendix 3)
When the analysis of the access address pattern by the analysis unit is completed during the execution of the second data processing by the processing program,
The configuration control unit programs the cache control switching unit determined by the determination unit in the programmable unit.
The information processing apparatus according to Appendix 2, wherein the arithmetic processing unit causes the data processing unit to execute unexecuted processing of the second data processing as a part of the first data processing.
(Appendix 4)
The analysis unit is programmed into the programmable unit.
The configuration control unit programs the data processing unit, the analysis unit, and the default cache control switching unit in the programmable unit, and the analysis unit determines the access address based on the memory access request issued by the data processing unit. The information processing apparatus according to Appendix 1, wherein the default cache control switching unit is replaced with the cache control switching unit determined by the determination unit after analyzing the pattern.
(Appendix 5)
The data processing executed by the data processing unit includes a plurality of processes.
The information processing according to any one of Supplementary note 1 to Supplementary note 4, wherein the analysis unit analyzes the pattern of the access address by a process whose execution frequency is higher than that of the other processes among the plurality of processes. apparatus.
(Appendix 6)
The determination unit generates configuration information of the cache control switching unit determined based on the pattern of the access address analyzed by the analysis unit.
The information processing device according to any one of Supplementary note 1 to Supplementary note 5, wherein the configuration control unit programs the configuration information of the cache control switching unit generated by the determination unit into the programmable unit.
(Appendix 7)
The determination unit selects one of the configuration information of the plurality of types of the cache control switching unit corresponding to each of the plurality of types of the access address patterns based on the access address pattern analyzed by the analysis unit.
The information processing device according to any one of Supplementary note 1 to Supplementary note 5, wherein the configuration control unit programs the configuration information of the cache control switching unit selected by the determination unit into the programmable unit.
(Appendix 8)
Addendum 1 to 7 are characterized in that the determination unit determines the logic of the cache control switching unit programmable in the free area of the programmable unit based on the pattern of the access address analyzed by the analysis unit. The information processing apparatus according to any one of the above items.
(Appendix 9)
The cache control information output by the cache control switching unit includes first information indicating whether or not to store the data in the cache memory unit instead of writing the data in the storage unit.
The information processing apparatus according to any one of Supplementary note 1 to Supplementary note 8, wherein the cache control unit writes data to the storage unit or the cache memory unit according to the first information.
(Appendix 10)
The cache control information output by the cache control switching unit includes second information indicating the length of data transferred in response to the memory access request issued by the data processing unit.
The information processing device according to any one of Supplementary note 1 to Supplementary note 9, wherein the cache control unit reads data having a length corresponding to the second information from the storage unit.
(Appendix 11)
A storage unit for storing data and a programmable unit are provided, and the programmable unit includes a data processing unit for processing data stored in the storage unit, a cache memory unit for storing data used in the data processing unit, and the above-mentioned The cache control unit that determines whether the data processing unit stores the data read from the storage unit in the cache memory unit based on the cache control information, and the cache control information based on the memory access request issued by the data processing unit. In the control method of the information processing device in which the cache control switching unit is programmed to generate
The information processing device
The pattern of the access address included in the memory access request issued by the data processing unit programmed in the programmable unit is analyzed.
Based on the analyzed access address pattern, the logic of the cache control switching unit to be programmed in the programmable unit is determined.
A control method for an information processing apparatus, wherein the data processing unit, the cache memory unit, and the cache control unit are programmed into the programmable unit, and the determined cache control switching unit is programmed into the programmable unit.
(Appendix 12)
A storage unit for storing data and a programmable unit are provided, and the programmable unit includes a data processing unit for processing data stored in the storage unit, a cache memory unit for storing data used in the data processing unit, and the above-mentioned The cache control unit that determines whether the data processing unit stores the data read from the storage unit in the cache memory unit based on the cache control information, and the cache control information based on the memory access request issued by the data processing unit. In the control program of the information processing device in which the cache control switching unit is programmed to generate
The pattern of the access address included in the memory access request issued by the data processing unit programmed in the programmable unit is analyzed.
Based on the analyzed access address pattern, the logic of the cache control switching unit to be programmed in the programmable unit is determined.
Control for causing the information processing apparatus to execute a process of programming the data processing unit, the cache memory unit, and the cache control unit in the programmable unit, and programming the determined cache control switching unit in the programmable unit. program.
(Appendix 13)
A storage unit for storing data and a programmable unit are provided, and the programmable unit includes a data processing unit for processing data stored in the storage unit, a cache memory unit for storing data used in the data processing unit, and the above-mentioned The cache control unit that determines whether the data processing unit stores the data read from the storage unit in the cache memory unit based on the cache control information, and the cache control information based on the memory access request issued by the data processing unit. In the recording medium on which the control program of the information processing device in which the cache control switching unit is programmed is recorded.
The pattern of the access address included in the memory access request issued by the data processing unit programmed in the programmable unit is analyzed.
Based on the analyzed access address pattern, the logic of the cache control switching unit to be programmed in the programmable unit is determined.
To have the information processing apparatus execute a process of programming the data processing unit, the cache memory unit, and the cache control unit in the programmable unit, and programming the cache control switching unit determined by the program in the programmable unit. A recording medium on which a control program is recorded.

The above detailed description will clarify the features and advantages of the embodiments. It is intended that the claims extend to the features and advantages of the embodiments as described above, without departing from their spirit and scope of rights. Also, anyone with ordinary knowledge in the art should be able to easily come up with any improvements or changes. Therefore, there is no intention to limit the scope of the embodiments having invention to those described above, and it is possible to rely on suitable improvements and equivalents included in the scope disclosed in the embodiments.

1 ... Programmable unit; 1a ... Data processing unit; 1b ... Cache circuit; 1c ... Cache control switching unit; 1d ... Cache control unit; 1e ... Cache memory unit; 2 ... Storage unit; 2a ... Data area; 2b ... Program area; 2c ... configuration information area; 2d ... first program; 2e ... second program; 2f ... control program; 3 ... arithmetic processing unit; 3a ... arithmetic processing unit; 3b ... analysis unit; 3c ... determination unit; 3d ... configuration control unit 4 ... Recording medium; 10 ... Programmable unit; 10a ... Data processing unit; 10b ... Cache circuit; 10c ... Cache control switching unit; 10d ... Cache control unit; 10e ... Cache memory unit; 20 ... Main memory; 20a ... Data area 20b ... program area; 20c ... configuration information area; 20d ... program; 20e ... control program; 30 ... arithmetic processing unit; 30a ... CPU core; 30b ... LLC; 30c ... MMU; 30d ... analysis unit; 30e ... determination unit; 30f ... Configuration control unit; 40 ... Input / output interface; 50 ... HDD; 60 ... Communication interface; 70 ... Recording medium; 100, 100A ... Information processing device; BUS1, BUS2, BUS3 ... Bus; CPU ... Cache control information; NW ... Network; TBL ... Feature extraction table

Claims (10)

A storage unit that stores data and
A data processing unit that processes data stored in the storage unit, a cache memory unit that stores data used in the data processing unit, and data read from the storage unit by the data processing unit are stored in the cache memory unit. A programmable unit in which a cache control unit that determines whether to use the cache control information is programmed, a cache control switching unit that generates the cache control information based on a memory access request issued by the data processing unit, and a programmable unit are programmed.
An analysis unit that analyzes the pattern of access addresses included in the memory access request issued by the data processing unit programmed in the programmable unit, and an analysis unit.
A determination unit that determines the logic of the cache control switching unit programmed into the programmable unit based on the access address pattern analyzed by the analysis unit.
The data processing unit, the cache memory unit, and the cache control unit are programmed into the programmable unit, and the cache control switching unit determined by the determination unit is programmed into the programmable unit. Information processing device. It is provided with an arithmetic processing unit that executes a processing program including a function of executing a second data processing equivalent to the first data processing executed by the data processing unit.
The information processing apparatus according to claim 1, wherein the analysis unit analyzes the pattern of the access address based on the access to the storage unit generated by the execution of the second data processing by the processing program. When the analysis of the access address pattern by the analysis unit is completed during the execution of the second data processing by the processing program,
The configuration control unit programs the cache control switching unit determined by the determination unit in the programmable unit.
The information processing apparatus according to claim 2, wherein the arithmetic processing unit causes the data processing unit to execute unexecuted processing of the second data processing as a part of the first data processing. The analysis unit is programmed into the programmable unit.
The configuration control unit programs the data processing unit, the analysis unit, and the default cache control switching unit in the programmable unit, and the analysis unit determines the access address based on the memory access request issued by the data processing unit. The information processing apparatus according to claim 1, wherein the default cache control switching unit is replaced with the cache control switching unit determined by the determination unit after analyzing the pattern. The data processing executed by the data processing unit includes a plurality of processes.
The method according to any one of claims 1 to 4, wherein the analysis unit analyzes the pattern of the access address by a process whose execution frequency is higher than that of the other processes among the plurality of processes. Information processing device. The determination unit generates configuration information of the cache control switching unit determined based on the pattern of the access address analyzed by the analysis unit.
The information processing device according to any one of claims 1 to 5, wherein the configuration control unit programs the configuration information of the cache control switching unit generated by the determination unit into the programmable unit. The determination unit selects one of the configuration information of the plurality of types of the cache control switching unit corresponding to each of the plurality of types of the access address patterns based on the access address pattern analyzed by the analysis unit.
The information processing device according to any one of claims 1 to 5, wherein the configuration control unit programs the configuration information of the cache control switching unit selected by the determination unit into the programmable unit. Claim 1 to claim 1, wherein the determination unit determines the logic of the cache control switching unit programmable in a free area of the programmable unit based on the pattern of the access address analyzed by the analysis unit. Item 6. The information processing apparatus according to any one of Item 7. A storage unit for storing data and a programmable unit are provided, and the programmable unit includes a data processing unit for processing data stored in the storage unit, a cache memory unit for storing data used in the data processing unit, and the above-mentioned The cache control unit that determines whether the data processing unit stores the data read from the storage unit in the cache memory unit based on the cache control information, and the cache control information based on the memory access request issued by the data processing unit. In the control method of the information processing device in which the cache control switching unit is programmed to generate
The information processing device
The pattern of the access address included in the memory access request issued by the data processing unit programmed in the programmable unit is analyzed.
Based on the analyzed access address pattern, the logic of the cache control switching unit to be programmed in the programmable unit is determined.
A control method for an information processing apparatus, wherein the data processing unit, the cache memory unit, and the cache control unit are programmed into the programmable unit, and the determined cache control switching unit is programmed into the programmable unit. A storage unit for storing data and a programmable unit are provided, and the programmable unit includes a data processing unit for processing data stored in the storage unit, a cache memory unit for storing data used in the data processing unit, and the above-mentioned The cache control unit that determines whether the data processing unit stores the data read from the storage unit in the cache memory unit based on the cache control information, and the cache control information based on the memory access request issued by the data processing unit. In the control program of the information processing device in which the cache control switching unit is programmed to generate
The pattern of the access address included in the memory access request issued by the data processing unit programmed in the programmable unit is analyzed.
Based on the analyzed access address pattern, the logic of the cache control switching unit to be programmed in the programmable unit is determined.
Control for causing the information processing apparatus to execute a process of programming the data processing unit, the cache memory unit, and the cache control unit in the programmable unit, and programming the determined cache control switching unit in the programmable unit. program.

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