JP6802512B1 - Information processing equipment, programs, and information processing systems - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly safe information processing system capable of determining whether or not a fan operates normally before starting a platform. An information processing device according to a first aspect of the present invention has a connection unit to which an external information processing device can be connected and the connection unit prior to activation of an external control unit included in the external information processing device. Receives an operation signal indicating the operating state of the cooling fan of the external control unit from the external information processing device via an expansion pin other than the pin used for communication according to the communication standard among the pins possessed by the external information processing apparatus. Based on the operation signal, it is determined whether or not the fan is operating normally, and when it is determined that the fan is operating normally, a control unit that instructs the external control unit to start the fan. , Equipped with. [Selection diagram] Fig. 3

Description

The present invention relates to information processing devices, programs, and information processing systems.

Communicates with a platform (an example of an external information processing device) and a platform that has a slot (an example of a connection unit) to which the platform can be connected and is connected to the slot according to a communication standard such as PCIe (Peripheral Component Interconnect Express). An information processing system equipped with a relay device (an example of an information processing device) is being developed. The cooling fan of the microcomputer (an example of the external control unit) mounted on each platform of such an information processing system is controlled by the platform itself. Usually, each platform is equipped with one fan controller for one fan, and the fan is controlled by the fan controller.

Japanese Unexamined Patent Publication No. 2008-41027 Special Table 2012-504835

However, when the cooling fan of the microcomputer mounted on the platform is controlled by the platform itself, it is difficult to check whether the fan operates normally before starting the platform. It is also possible to install a fan controller dedicated to the fan on the platform, but as many fan controllers as there are fans are required.

In one aspect, the present invention is an information processing apparatus capable of determining whether or not a fan operates normally before starting a platform, and providing a highly secure information processing system. The purpose is to provide a program and an information processing system.

The information processing device according to the first aspect of the present invention has a connection unit to which an external information processing device can be connected and a pin of the connection unit prior to activation of the external control unit of the external information processing device. An operation signal indicating the operating state of the cooling fan of the external control unit is received from the external information processing device via an expansion pin other than the pin used for communication in accordance with the communication standard, and the operation signal is used as the operation signal. Based on this, it is determined whether or not the fan is operating normally, and when it is determined that the fan is operating normally, a control unit that instructs the external control unit to start, and a plurality of the above A signal switching circuit that receives the operation signal from the fan of each of the external information processing devices and selects the operation signal received from the fan of the abnormality detection target among the received operation signals. The control unit determines whether or not the fan is operating normally based on the operation signal selected by the signal switching circuit .

The program according to the second aspect of the present invention sets the computer as a communication standard among the pins of the connection unit to which the external information processing device can be connected prior to the activation of the external control unit of the external information processing device. An operation signal indicating the operating state of the cooling fan of the external control unit is received from the external information processing device via an expansion pin other than the pin used for the corresponding communication, and the operation signal is based on the operation signal. It is determined whether or not the fan is operating normally, and when it is determined that the fan is operating normally, the external control unit is made to function as a control unit that instructs the external control unit to start, and the control unit operates. , The signal switching that receives the operation signal from the fan of each of the plurality of external information processing devices and selects the operation signal received from the fan of the abnormality detection target among the received operation signals. Based on the operation signal selected by the circuit, it is determined whether or not the fan is operating normally .

The information processing system according to the third aspect of the present invention is an information processing system including a first information processing device and a second information processing device, and the first information processing device includes a first control unit and a first control unit. The second information processing apparatus includes a cooling fan of the first control unit, and the second information processing apparatus includes a connection portion to which the first information processing apparatus can be connected and a first control unit included in the first information processing apparatus. Prior to activation, the operation of the cooling fan of the first control unit from the first information processing device via an expansion pin other than the pin used for communication in accordance with the communication standard among the pins of the connection unit. When the operation signal indicating the state is received, it is determined whether or not the fan is operating normally based on the operation signal, and it is determined that the fan is operating normally, the first control unit The operation signal is received from the second control unit that instructs the second control unit to start the information processing device and the fan of each of the plurality of first information processing devices, and among the received operation signals, the abnormality detection target is said to be. A signal switching circuit for selecting the operating signal received from the fan is provided, and the second control unit determines whether or not the fan is operating normally based on the operating signal selected by the signal switching circuit. To judge .

According to the above aspect of the present invention, it is possible to determine whether or not the fan operates normally before starting the platform, and it is possible to provide a highly secure information processing system.

FIG. 1 is a diagram showing an example of the overall configuration of the information processing system according to the present embodiment. FIG. 2 is a diagram showing an example of the hardware configuration of each device of the information processing system according to the present embodiment. FIG. 3 is a diagram showing an example of the hardware configuration of the platform and the power supply control board included in the information processing system according to the present embodiment. FIG. 4 is a diagram for explaining an example of FAN_TACH signal switching processing by the TACH signal switching circuit according to the present embodiment. FIG. 5 is a diagram for explaining an example of switching processing of the temperature detection result input to the internal microcomputer by the temperature sensor switching circuit according to the present embodiment. FIG. 6 is a sequence diagram showing an example of the flow of activation processing of the external microcomputer in the information processing system according to the present embodiment.

Hereinafter, an example of the information processing apparatus, program, and information processing system according to the present embodiment will be described with reference to the attached drawings.

FIG. 1 is a diagram showing an example of the overall configuration of the information processing system according to the present embodiment. The information processing system 1 connects a platform 10-1 having an interface corresponding to active insertion / removal, which is an insertion / removal at the time of power-on, and a plurality of platforms 10-2 to 10-8 so as to be able to communicate with each other via a relay device 30. It is an information processing system. As shown in FIG. 1, the information processing system 1 according to the present embodiment includes platforms 10-1 to 10-8 and a relay device 30.

Platforms 10-1 to 10-8 are communicably connected via a relay device 30. Platforms 10-1 to 10-8 are inserted, for example, into slots (an example of connection) on a board provided with a relay device 30. Further, any of the plurality of slots may be in an empty state in which platforms 10-1 to 10-8 are not inserted. In the following description, it is not necessary to distinguish each platform 10-1 to 10-8, and when any platform 10-1 to 10-8 is indicated, it is described as platform 10.

Platform 10-1 is a main information processing device that manages platforms 10-2 to 10-8 and causes platforms 10-2 to 10-8 to execute various processes.

A monitor 21 and an input device 22 are connected to the platform 10-1. The monitor 21 displays various screens such as a liquid crystal display device. The input device 22 accepts various operations such as a keyboard and a mouse.

Platforms 10-2 to 10-8 are sub-information processing devices that execute, for example, AI (Artificial Intelligence) inference processing, image processing, and the like based on the requirements of platform 10-1. Further, the platforms 10-2 to 10-8 may have different functions, or may have a function for each of a plurality of platforms 10.

Platforms 10-1 to 10-8 have a root complex (RC: Root Complex) 11-1 to 11-8 that can operate as a host side. In the following description, it is not necessary to distinguish each route complex 11-1 to 11-8, and when an arbitrary route complex 11-1 to 11-8 is indicated, it is described as the root complex 11.

The route complex 11 executes communication with each endpoint 31-1 to 1-31-8 of the relay device 30. That is, the platform 10 and the relay device 30 are communicably connected by a communication standard such as PCIe (Peripheral Component Interconnect Express). The platform 10 and the relay device 30 are not limited to PCIe and may be connected by other communication standards.

The relay device 30 has a plurality of endpoints (EPs: End Points) 31-1 to 1-31-8. Further, the relay device 30 relays communication between a plurality of platforms 10 having a route complex 11 connected to endpoints 31-1 to 1-31-8.

Endpoints 31-1 to 1-31-8 perform communication with the root complex 11 of platform 10. In the following description, it is not necessary to distinguish each endpoint 31-1 to 1-31-8, and when an arbitrary endpoint 31-1 to 1-31-8 is indicated, it is described as endpoint 31.

FIG. 2 is a diagram showing an example of the hardware configuration of each device of the information processing system according to the present embodiment. Next, an example of the hardware configuration of each device of the information processing system 1 will be described with reference to FIG. Here, the hardware configuration of platform 10-1 will be described as an example. However, platforms 10-2 to 10-8 have a similar configuration.

Platform 10-1 is a computer that performs arithmetic processing such as AI processing and image processing. Platform 10-1 includes a root complex 11-1 and a microcomputer (hereinafter referred to as an external microcomputer) 16-1. The external microcomputer 16-1 includes a processor 12-1, a memory 13-1, a storage unit 14-1, and a communication unit 15-1. Further, the route complex 11-1, the processor 12-1, the memory 13-1, the storage unit 14-1, and the communication unit 15-1 are communicably connected via the bus. In the following description, it is not necessary to distinguish between the external microcomputers 16-1 to 16-8, and when any external microcomputer 16-1 to 16-8 is shown, it is described as the external microcomputer 16.

Processor 12-1 controls the entire platform 10-1. Processor 12-1 may be a multiprocessor. Further, the processor 12-1 includes, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), and a PLD (Programmable Logic Device). ), FPGA (Field Programmable Gate Array) may be one of them. Further, the processor 12 may be a combination of two or more types of elements of the CPU, MPU, GPU, DSP, ASIC, PLD, and FPGA. In the following description, it is not necessary to distinguish processors 12-1 to 12-8, and when any processor 12-1 to 12-8 is indicated, it is referred to as processor 12.

The memory 13-1 is a storage memory including a ROM (Read Only Memory) and a RAM (Random Access Memory). Various software programs and data for this program are written in the ROM of the memory 13-1. The software program on the memory 13-1 is appropriately read and executed by the processor 12. Further, the RAM of the memory 13-1 is used as a primary storage memory or a working memory. In the following description, it is not necessary to distinguish between the memories 13-1 to 13-8, and when an arbitrary memory 13-1 to 13-8 is indicated, it is described as the memory 13.

The storage unit 14-1 is a storage device such as a hard disk drive (HDD: Hard Disk Drive), SSD (Solid State Drive), and storage class memory (SCM: Storage Class Memory), and stores various data. is there. For example, various software programs are stored in the storage unit 14-1. In the following description, it is not necessary to distinguish between the storage units 14-1 to 14-8, and when any storage unit 14-1 to 14-8 is indicated, it is described as the storage unit 14.

In the platform 10, various functions are realized by the processor 12 executing a software program stored in the memory 13 and the storage unit 14.

The various software programs described above do not necessarily have to be stored in the memory 13 or the storage unit 14. For example, the platform 10 may read and execute a program stored in a storage medium that can be read by a medium reader or the like. The storage medium that can be read by the platform 10 corresponds to, for example, a CD-ROM, a DVD disk, a portable recording medium such as a USB (Universal Serial Bus) memory, a semiconductor memory such as a flash memory, a hard disk drive, or the like. Further, the information processing program may be stored in a device connected to a public line, the Internet, a LAN, or the like, and the platform 10 may read and execute the information processing program from these.

The communication unit 15-1 is an interface for executing communication with the power supply control board 40 of the relay device 30. For example, the communication unit 15-1 executes communication according to a communication standard such as I2C (Inter-Integrated Circuit). In the following description, it is not necessary to distinguish the communication units 15-1 to 15-8, and when any communication unit 15-1 to 15-8 is indicated, it is described as the communication unit 15.

Next, the relay device 30 will be described. The relay device 30 includes an endpoint 31-1 to 1-31-8 provided for each platform 10, a processor 32, a memory 33, a storage unit 34, an internal bus 35, a PCIe bus 36, and a power supply control board 40. It is an information processing device including. In the following description, it is not necessary to distinguish each endpoint 31-1 to 1-31-8, and when an arbitrary endpoint 31-1 to 1-31-8 is indicated, it is described as endpoint 31.

The endpoint 31 is provided for each platform 10 and executes data transmission / reception. For example, when the endpoint 31 receives data from the connected platform 10, it transmits the received data to the endpoint 31 connected to the destination platform 10 via the PCIe bus 36.

For example, the route complex 11 transmits data to another platform 10 by DMA (Direct Memory Access) transfer. Further, the endpoint 31 transmits the received data to the connected platform 10 when the data is received from the endpoint 31 connected to the platform 10 from which the data is transmitted via the PCIe bus 36.

The processor 32 controls the entire relay device 30. The processor 32 may be a multiprocessor. Further, the processor 32 may be, for example, any one of CPU, MPU, GPU, DSP, ASIC, PLD, and FPGA. Further, the processor 32 may be a combination of two or more types of elements of the CPU, MPU, GPU, DSP, ASIC, PLD, and FPGA.

The memory 33 is a storage device including a ROM and a RAM. Various software programs and data for this program are written in the ROM. The program stored in the memory 33 is read into the processor 32 and executed. In addition, RAM is used as a working memory.

The storage unit 34 is a storage device such as a hard disk drive, SSD, and storage class memory, and stores various data. For example, various software programs are stored in the storage unit 34.

The internal bus 35 communicatively connects the processor 32, the memory 33, the storage unit 34, and the PCIe bus 36.

The PCIe bus 36 communicatively connects a plurality of endpoints 31 and an internal bus 35. That is, the PCIe bus 36 connects the plurality of endpoints 31 so that data can be transferred. Further, the PCIe bus 36 is, for example, a bus conforming to the PCIe standard.

The power supply control board 40 includes a microcomputer 41 (hereinafter referred to as an internal microcomputer; an example of a second microcomputer) 41 that controls the supply of electric power to the platform 10 and the activation of the external microcomputer 16. The power supply control board 40 is, for example, an integrated circuit having a microcomputer or a microcontroller. The power control board 40 also supplies power to the platform 10 when the relay device 30 is restarted. Further, the power supply control board 40 is connected to the platform 10 and the processor 32 of the relay device 30.

FIG. 3 is a diagram showing an example of the hardware configuration of the platform and the power supply control board included in the information processing system according to the present embodiment. Next, an example of the hardware configuration of the platform 10 (platforms 10-2 to 10-7) and the power supply control board 40 will be described with reference to FIG.

First, an example of the hardware configuration of the platform 10 (an example of an external information processing device or a first information processing device) will be described. As shown in FIG. 3, the platform 10 includes an external microcomputer 16 (an example of an external control unit or a first control unit), a cooling fan 17, a temperature sensor 18, and a DCDC converter 19. Further, the platform 10 operates by receiving power of 12.0V and 3.3V from the PSU (Power Supply Unit) 50 via the power supply control board 40.

The cooling fan 17 is an example of a cooling fan for the external microcomputer 16. In the present embodiment, the cooling fan 17 operates by receiving power of 5.0 V from the PSU 50 via the DCDC converter 19. Further, in the present embodiment, the cooling fan 17 rotates according to the rotation speed indicated by the FAN_PWM (Pulse Width Modulation) _OUT signal transmitted from the power supply control board 40 via the expansion pin of the slot S of the relay device 30. , Cool the external microcomputer 16. Here, the expansion pin is a pin other than the pin of the slot S provided on the board of the relay device 30 and used for communication with the platform 10 according to the PCIe communication standard (hereinafter, referred to as a PCIe pin). Further, here, the FAN_PWM_OUT signal is an example of a control signal of the cooling fan 17, and is, for example, a drive signal indicating the rotation speed of the cooling fan 17. Further, in the present embodiment, the cooling fan 17 outputs a FAN_TACH (Tachometer) signal to the power supply control board 40. Here, the FAN_TACH signal is an example of an operation signal indicating the operating state of the cooling fan 17, and is, for example, a signal indicating the measurement result of the rotation speed of the cooling fan 17.

The DCDC converter 19 converts the voltage of the electric power supplied from the PSU 50 to the cooling fan 17. In the present embodiment, the DCDC converter 19 converts the 12.0V electric power supplied from the PSU 50 into 5.0V electric power and supplies it to the cooling fan 17. The temperature sensor 18 detects the temperature of the external microcomputer 16. Then, the temperature sensor 18 outputs the temperature detection result of the external microcomputer 16 to the power supply control board 40. In the present embodiment, the temperature sensor 18 outputs the temperature detection result of the external microcomputer 16 to the power supply control board 40 by serial communication such as I2C (Inter-Integrated Circuit).

The external microcomputer 16 is a microcomputer that executes arithmetic processing such as AI processing and image processing. In the present embodiment, the external microcomputer 16 executes the activation process according to the PCIE_P_BTN signal transmitted from the power supply control board 40. Here, the PCIE_P_BTN signal is an example of an activation signal instructing the activation of the external microcomputer 16. In the present embodiment, the PCIE_P_BTN signal is high when the external microcomputer 16 is started, and low when the external microcomputer 16 is stopped.

Further, in the present embodiment, the external microcomputer 16 transmits a PCIE_STATE signal to the power supply control board 40. Here, the PCIE_START signal is a signal indicating the activation state of the external microcomputer 16 itself. In the present embodiment, the PCIE_STATE signal is high when the start processing of the external microcomputer 16 is completed, and low when the start processing of the external microcomputer 16 is not completed.

Next, an example of the hardware configuration of the power supply control board 40 included in the relay device 30 (an example of the second information processing device) will be described. As shown in FIG. 3, the power supply control board 40 includes an internal microcomputer 41, a temperature sensor switching circuit 42, a TACH signal switching circuit 43, a bridge board fan 44, a temperature sensor 45, an inverting circuit 46, DCDC converters 47 and 48, and a switch. It has 49,52.

The switch 49 is a switch that turns on or off the supply of 12.0 V power from the PSU 50 to the platform 10. In the present embodiment, the switch 49 turns on or off the power supply to the platform 10 according to the PCIE_SW_ON signal input from the internal microcomputer 41. Here, the PCIE_SW_ON signal is a signal instructing on or off of the power supply to the platform 10. In this embodiment, the PCIE_SW_ON signal is high when the power supply to the platform 10 is turned on and low when the power supply to the platform 10 is turned off. The power control board 40 has switches 49 for the number of slots S of the relay device 30.

The DCDC converter 47 converts the voltage of the electric power supplied from the PSU 50 to the platform 10. In the present embodiment, the DCDC converter 47 converts the 12.0 V power supplied from the PSU 50 into 3.3 V power and supplies it to the platform 10. In the present embodiment, the DCDC converter 47 uses the PCIE_SW_ON signal input from the internal microcomputer 41 to control the power supply of 12.0 V supplied from the PSU 50 to 3 when the power supply to the platform 10 is instructed to be turned on. It is converted into power of .3V and supplied to the platform 10. The power supply control board 40 has DCDC converters 47 for the number of slots S of the relay device 30.

The DCDC converter 48 converts the voltage of the standby power supplied from the PSU 50. In the present embodiment, the DCDC converter 48 constantly (that is, whether or not the platform 10 is connected to slot S) uses 11.0 V standby power supplied from the PSU 50 as a 3.3 V standby power. Convert to. The power supply control board 40 has DCDC converters 48 for the number of slots S of the relay device 30.

The switch 52 is a switch that turns on or off the supply of standby power from the PSU 50 to the platform 10. In the present embodiment, the switch 52 turns on the supply of standby power from the PSU 50 to the platform 10 when the PCIE_PRESS signal input from the platform 10 indicates that the platform 10 is connected to the slot S. On the other hand, the switch 52 turns off the supply of standby power from the PSU 50 to the platform 10 when the PCIE_PRESS signal input from the platform 10 indicates that the platform 10 is not connected to the slot S. The power supply control board 40 has switches 52 for the number of slots S of the relay device 30.

Here, the PCIE_PRESENT signal is a signal indicating whether or not the platform 10 is connected to the slot S. In this embodiment, the PCIE_PRESENT signal is high when platform 10 is connected to slot S and low when platform 10 is not connected to slot S. PCIE_PRESENT signals corresponding to the number of slots S included in the relay device 30 are input to the power supply control board 40. The inverting circuit 46 inverts the level of the PCIE_PRESENT signal input from the platform 10.

The bridge board fan 44 is an example of a fan for cooling the internal microcomputer 41. In the present embodiment, the bridge board fan 44 rotates according to the rotation speed indicated by the FAN_PWM_IN signal input from the internal microcomputer 41 to cool the internal microcomputer 41. Here, the FAN_PWM_IN signal is an example of a control signal of the bridge board fan 44, and is, for example, a drive signal indicating the rotation speed of the bridge board fan 44. Further, in the present embodiment, the bridge board fan 44 outputs a FAN_TACH signal to the internal microcomputer 41. Here, the FAN_TACH signal is a signal indicating the operating state of the bridge board fan 44, and is, for example, a signal indicating the measurement result of the rotation speed of the bridge board fan 44.

The TACH signal switching circuit 43 receives the FAN_TACH signal from the cooling fan 17 of each platform 10, selects the FAN_TACH signal received from the cooling fan 17 to be abnormally detected, from the received FAN_TACH signal, and selects the FAN_TACH signal received from the cooling fan 17 to be detected as an abnormality. This is an example of a signal switching circuit to be input to 41. In the present embodiment, the TACH signal switching circuit 43 receives the FAN_TACH signal from the bridge board fan 44 in addition to the cooling fan 17 of each platform 10, and the FAN_TACH signal received from the cooling fan 17 and the bridge board fan 44. Among them, the FAN_TACH signal received from the cooling fan 17 to be detected as abnormal is selected and input to the internal microcomputer 41.

In the present embodiment, the TACH signal switching circuit 43 has two FAN_TACH signals (FAN_TACH1 signal and FAN_TACH2 signal) out of the FAN_TACH signal received from the bridge board fan 44 and the FAN_TACH signal received from the cooling fan 17 of each platform 10. ) Is input to the internal microcomputer 41 by I2C serial communication. Further, in the present embodiment, the TACH signal switching circuit 43 receives the FAN_TACH signal received from the bridge board fan 44 and the cooling fan 17 of each platform 10 according to the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal input from the internal microcomputer 41. Of the FAN_TACH signals, two FAN_TACH signals to be input to the internal microcomputer 41 are selected. Here, the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal are signals for instructing switching of the FAN_TACH signal input to the internal microcomputer 41.

For example, as shown in Table 1, the TACH signal switching circuit 43 receives from the cooling fan 17 of the platform 10-2 connected to the slot of slot number: 2 when both the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal are low. The FAN_TACH signal (FAN_TACH1 signal) and the FAN_TACH signal (FAN_TACH2 signal) received from the cooling fan 17 of the platform 10-6 connected to the slot of slot number 6 are input to the internal microcomputer 41.

Further, as shown in Table 1, when the PCIE_FAN_SEL1 signal is low and the PCIE_FAN_SEL2 signal is high, the TACH signal switching circuit 43 is connected to the cooling fan 17 of the platform 10-4 connected to the slot of slot number 4. The FAN_TACH signal (FAN_TACH1 signal) to be received and the FAN_TACH signal (FAN_TACH2 signal) received from the platform 10-1 connected to the slot of slot number 0 are input to the internal microcomputer 41.

Further, as shown in Table 1, when the PCIE_FAN_SEL1 signal is high and the PCIE_FAN_SEL2 signal is low, the TACH signal switching circuit 43 is connected to the cooling fan 17 of the platform 10-3 connected to the slot of slot number 3. The FAN_TACH signal (FAN_TACH1 signal) to be received and the FAN_TACH signal (FAN_TACH2 signal) received from the cooling fan 17 of the platform 10-7 connected to the slot of slot number 7 are input to the internal microcomputer 41.

Further, as shown in Table 1, the TACH signal switching circuit 43 receives from the cooling fan 17 of the platform 10-5 connected to the slot of slot number 5 when both the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal are high. The FAN_TACH signal (FAN_TACH1 signal) and the FAN_TACH signal (FAN_TACH2 signal) received from the bridge board fan 44 are input to the internal microcomputer 41.

The temperature sensor 45 detects the temperature of the internal microcomputer 41. Then, the temperature sensor 45 outputs the temperature detection result of the internal microcomputer 41 to the internal microcomputer 41. In the present embodiment, the temperature sensor 45 outputs a data signal indicating the temperature detection result of the internal microcomputer 41 and a clock signal to the internal microcomputer 41 by I2C serial communication.

The temperature sensor switching circuit 42 inputs to the internal microcomputer 41 the temperature detection result of the external microcomputer 16 input from the temperature sensor 18 of each platform 10 and the temperature detection result of the internal microcomputer 41 input from the temperature sensor 45. .. In the present embodiment, the temperature sensor switching circuit 42 inputs a data signal (I2C_SDA_MCU_SW1 signal) and a clock signal (I2C_SCL_MCU_SW1 signal) indicating the temperature detection results by the temperature sensors 18 and 45 to the internal microcomputer 41 by I2C serial communication. To do. Further, in the present embodiment, the temperature sensor switching circuit 42 detects the temperature input to the internal microcomputer 41 among the temperature detection results input from the temperature sensors 18 and 45 according to the PCIE_I2C_SEL signal input from the internal microcomputer 41. Switch the result. Here, the PCIE_I2C_SEL signal is a signal instructing switching of the temperature detection result input to the internal microcomputer 41.

For example, as shown in Table 2, the temperature sensor 18 mounted on each of the platforms 10-1 to 10-8 and the temperature sensor 45 mounted on the power supply control board 40 have a 7-bit slave address (for example, 48h). , 49h, 4Ah, 4Bh) are assigned. When the PCIE_I2C_SEL signal is low, the temperature sensor switching circuit 42 detects the temperature by the temperature sensor 45 mounted on the power supply control board 40, and the slot number of the slot S of the relay device 30: 2 to 2. A data signal (I2C_SDA_MCU_SW1 signal) and a clock signal (I2C_SCL_MCU_SW1 signal) indicating the temperature detection result by the temperature sensor 18 mounted on the platforms 10-2 to 10-4 connected to the slots S of 4 are input to the internal microcomputer 41. To do.

On the other hand, when the PCIE_I2C_SEL signal is high, the temperature sensor switching circuit 42 is mounted on the platform 10-1, 10-5 to 10-7 connected to the slot S of slot number 0,5 to 7. A data signal (I2C_SDA_MCU_SW1 signal) and a clock signal (I2C_SCL_MCU_SW1 signal) indicating the temperature detection result by the sensor 18 are input to the internal microcomputer 41.

In the internal microcomputer 41, a CPU, a processor such as an MPU, GPU, DSP, ASIC, PLD, or FPGA executes a software program stored in the storage unit to supply power to the platform 10 as described above. , And control the activation of the external microcomputer 16. Here, the storage unit corresponds to, for example, a portable recording medium such as a CD-ROM, a DVD disk, or a USB memory, a semiconductor memory such as a flash memory, a hard disk drive, or the like. Further, the information processing program may be stored in a device connected to a public line, the Internet, a LAN, or the like, and the platform 10 may read and execute the information processing program from these. In the present embodiment, the internal microcomputer 41 realizes the supply of power to the platform 10 and the control of starting the external microcomputer 16 by executing the software program stored in the storage unit by the processor. It is not limited to the above, and can be realized by hardware such as a circuit board. In the present embodiment, the internal microcomputer 41 controls the supply of electric power from the PSU 50 to the platform 10 by outputting the PCIE_SW_ON signal to the switch 49 and the DCDC converter 47.

Further, in the present embodiment, the internal microcomputer 41 transmits a PCIE_P_BTN signal to the external microcomputer 16 to instruct the external microcomputer 16 to start. Further, in the present embodiment, the internal microcomputer 41 receives the PCIE_STATE signal from the external microcomputer 16 and determines whether or not the activation process of the external microcomputer 16 is completed based on the PCIE_STATE signal.

By the way, conventionally, a fan for cooling a microcomputer mounted on a platform is controlled by the platform itself. For example, each platform is equipped with one fan controller for one fan, and the fan is controlled by the fan controller. However, when the cooling fan mounted on the platform is controlled by the platform itself, it is difficult to check whether the fan operates normally before starting the platform. It is also possible to install a fan controller dedicated to the cooling fan on the platform, but as many fan controllers as there are fans are required.

Therefore, in the present embodiment, the internal microcomputer 41 (an example of the control unit or the second control unit) prior to changing the PCIE_P_BTN signal from low to high to the external microcomputer 16 (that is, prior to starting the external microcomputer 16). The FAN_TACH signal is received from the cooling fan 17 of the platform 10 via the expansion pin, and it is determined whether or not the cooling fan 17 is operating normally based on the FAN_TACH signal.

Then, when the internal microcomputer 41 determines that the cooling fan 17 is operating normally, the internal microcomputer 41 changes the PCIE_P_BTN signal from low to high (that is, instructs the external microcomputer 16 to start). As a result, even if the external microcomputer 16 is not started, it is possible to instruct the external microcomputer 16 to start after determining whether or not the cooling fan 17 operates normally. As a result, it becomes possible to provide a highly secure information processing system.

Further, in the present embodiment, the internal microcomputer 41 also receives the FAN_TACH signal from the bridge board fan 44, and determines whether or not the bridge board fan 44 is operating normally based on the FAN_TACH signal.

Further, in the present embodiment, the internal microcomputer 41 is mounted on each of the platforms 10-2 to 10-8 when determining whether or not the cooling fan 17 mounted on the platform 10 is operating normally. Among the cooling fans 17, it is determined in order from the cooling fan 17 of the platform 10 connected to the slot S having the lower slot number whether or not it is operating normally.

Specifically, the internal microcomputer 41 first sets both the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 to low. As a result, the TACH signal switching circuit 43 selects the FAN_TACH signal received from the cooling fan 17 of the platform 10-2 connected to the slot S of slot number: 2 and inputs it to the internal microcomputer 41 as the FAN_TACH1 signal. Then, the internal microcomputer 41 determines whether or not the cooling fan 17 of the platform 10-2 is operating normally based on the FAN_TACH1 signal.

Next, the internal microcomputer 41 sets the PCIE_FAN_SEL1 signal to high and the PCIE_FAN_SEL2 signal to low. As a result, the TACH signal switching circuit 43 selects the FAN_TACH signal received from the cooling fan 17 of the platform 10-3 connected to the slot S of the slot number: 3 and inputs it to the internal microcomputer 41 as the FAN_TACH1 signal. Then, the internal microcomputer 41 determines whether or not the cooling fan 17 of the platform 10-3 is operating normally based on the FAN_TACH1 signal. Thereby, among the cooling fans 17 of the plurality of platforms 10, it is possible to determine whether or not the cooling fan 17 for cooling the external microcomputer 16 of any platform 2 is operating normally.

Next, the internal microcomputer 41 sets the PCIE_FAN_SEL1 signal to low and the PCIE_FAN_SEL2 signal to high. As a result, the TACH signal switching circuit 43 selects the FAN_TACH signal received from the cooling fan 17 of the platform 10-4 connected to the slot S of the slot number: 4 and inputs it to the internal microcomputer 41 as the FAN_TACH1 signal. Then, the internal microcomputer 41 determines whether or not the cooling fan 17 of the platform 10-4 is operating normally based on the FAN_TACH1 signal.

Next, the internal microcomputer 41 sets both the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal to high. As a result, the TACH signal switching circuit 43 selects the FAN_TACH signal received from the cooling fan 17 of the platform 10-5 connected to the slot S of the slot number: 5 and inputs it to the internal microcomputer 41 as the FAN_TACH1 signal. Then, the internal microcomputer 41 determines whether or not the cooling fan 17 of the platform 10-5 is operating normally based on the FAN_TACH1 signal.

Next, the internal microcomputer 41 sets both the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal to low. As a result, the TACH signal switching circuit 43 selects the FAN_TACH signal received from the cooling fan 17 of the platform 10-6 connected to the slot S of the slot number: 6 and inputs it to the internal microcomputer 41 as the FAN_TACH2 signal. Then, the internal microcomputer 41 determines whether or not the cooling fan 17 of the platform 10-6 is operating normally based on the FAN_TACH2 signal.

Next, the internal microcomputer 41 sets the PCIE_FAN_SEL1 signal to high and the PCIE_FAN_SEL2 signal to low. As a result, the TACH signal switching circuit 43 selects the FAN_TACH signal received from the cooling fan 17 of the platform 10-7 connected to the slot S of the slot number: 7 and inputs it to the internal microcomputer 41 as the FAN_TACH2 signal. Then, the internal microcomputer 41 determines whether or not the cooling fan 17 of the platform 10-7 is operating normally based on the FAN_TACH2 signal.

Further, the internal microcomputer 41 transmits a FAN_PWM_OUT signal to the cooling fan 17. Then, the internal microcomputer 41 determines whether or not the cooling fan 17 is operating normally based on the rotation speed indicated by the FAN_PWM_OUT signal and the rotation speed indicated by the FAN_TACH signal received from the cooling fan 17. To do. As a result, it is possible to prevent the external microcomputer 16 from starting when the cooling fan 17 is not rotating at a rotation speed equal to or higher than the rotation speed instructed by the internal microcomputer 41. As a result, even though the cooling fan 17 is not operating normally, it is possible to prevent the external microcomputer 16 from starting and the external microcomputer 16 not being sufficiently cooled, causing a problem in the external microcomputer 16. In the present embodiment, when the internal microcomputer 41 determines whether or not the cooling fan 17 is operating normally, the duty ratio of the FAN_PWM_OUT signal is set to a preset ratio (for example, 0% to 100%). 20%). Then, when the rotation speed indicated by the FAN_TACH signal received from the cooling fan 17 of the internal microcomputer 41 is the rotation speed indicated by the duty ratio of the FAN_PWM_OUT signal: 100%: 900 rpm or more, the cooling fan 17 is normally used. Judge that it is working. On the other hand, the internal microcomputer 41 operates the cooling fan 17 when the rotation speed indicated by the FAN_TACH signal output from the cooling fan 17 is less than the rotation speed: 900 rpm indicated by the duty ratio of the FAN_PWM_OUT signal: 100%. Judge that there is something wrong with.

Further, in the present embodiment, the internal microcomputer 41 is subject to abnormality detection according to the PCIE_PRESENT signal input from each platform 10 prior to determining whether or not the cooling fan 17 of each platform 10 is operating normally. It is determined whether or not the platform 10 on which the cooling fan 17 is mounted is connected to the slot S. Then, when the PCIE_PRESENT signal input from the platform 10 on which the cooling fan 17 to be detected for abnormality is mounted is high, the internal microcomputer 41 determines that the platform 10 is connected to the slot S and detects the abnormality. It is determined whether or not the target cooling fan 17 is operating normally.

For example, the internal microcomputer 41 controls the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal every time the duty ratio of the FAN_PWM_OUT signal reaches 100% to switch the cooling fan 17 to be detected as an abnormality, and the abnormality detection target is From the cooling fan 17, the FAN_TACH signal, which is the measurement result of the rotation speed for a preset time (for example, 2 seconds) when the duty ratio of the FAN_PWM_OUT signal is set to 100%, is received. Then, when the rotation speed indicated by the received FAN_TACH signal is equal to or higher than a preset rotation speed (for example, 900 rpm), the internal microcomputer 41 determines that the cooling fan 17 to be detected for abnormality is operating normally. .. On the other hand, when the rotation speed indicated by the received FAN_TACH signal is less than the preset rotation speed, the internal microcomputer 41 determines that the operation of the cooling fan 17 to be detected as abnormal is abnormal. The internal microcomputer 41 repeats the above processing for all the cooling fans 17 to be detected as abnormalities.

Further, the internal microcomputer 41 outputs a FAN_PWM_IN signal to the bridge board fan 44. Then, the internal microcomputer 41 determines whether or not the bridge board fan 44 is operating normally based on the rotation speed indicated by the FAN_PWM_IN signal and the rotation speed indicated by the FAN_TACH signal received from the bridge board fan 44. To do. In the present embodiment, the internal microcomputer 41 determines whether or not the bridge board fan 44 is operating normally in the same manner as the cooling fan 17.

Further, the internal microcomputer 41 receives the temperature detection result of the external microcomputer 16 of each platform 10 from the temperature sensor 18 of each platform 10. Then, the internal microcomputer 41 determines the rotation speed of the cooling fan 17 of each platform 10 according to the highest temperature detection result of the temperature received from the temperature sensor 18 of each platform 10, and instructs the determined rotation speed. FAN_PWM_OUT signal is transmitted to the cooling fan 17. As a result, the cooling fan 17 can be rotated at a speed at which the external microcomputers 16 of all the platforms 10 can be cooled. Therefore, the external microcomputer 16 that is not sufficiently cooled by the cooling fan 17 is generated, and the external microcomputer 16 is generated. It is possible to prevent a malfunction from occurring in the microcomputer 16.

In the present embodiment, the internal microcomputer 41 receives the temperature detection result of the internal microcomputer 41 itself by the temperature sensor 45 included in the power supply control board 40. Then, the internal microcomputer 41 determines the rotation speed of the bridge board fan 44 according to the temperature detection result of the internal microcomputer 41, and transmits the FAN_PWM_IN signal instructing the determined rotation speed to the bridge board fan 44.

For example, the internal microcomputer 41 first sets the PCIE_I2C_SEL signal to low. Next, the internal microcomputer 41 accesses the temperature sensor (temperature sensor 45 included in the power supply control board 40) having the slave address: 48h, and receives the temperature detection result by the temperature sensor 45. Then, the internal microcomputer 41 stores the temperature detection result by the temperature sensor 45 in the register of the internal microcomputer 41 as internal information. Further, the internal microcomputer 41 collates the temperature detection result of the temperature sensor 45 with the bridge board fan table, and transmits a FAN_PWM_IN signal having a duty ratio corresponding to the temperature detection result to the bridge board fan 44. .. Here, the bridge board fan table is a table that associates the temperature of the internal microcomputer 41 with the duty ratio of the FAN_PWM_IN signal suitable for the temperature.

Next, the internal microcomputer 41 keeps the PCIE_I2C_SEL signal set to low, and the temperature sensors of slave addresses: 49h, 4Ah, and 4Bh (slot numbers: 2, 3, and 4 are connected to the slots S of the platform 10-2). The temperature sensors 18) of 10 to 4-4 are accessed to receive the temperature detection result by the temperature sensor 18. Then, the internal microcomputer 41 stores the temperature detection results of the respective temperature sensors 18 of the platforms 10-2 to 10-4 in the register as internal information.

Subsequently, the internal microcomputer 41 sets the PCIE_I2C_SEL signal to high. Next, the internal microcomputer 41 uses the temperature sensors of the slave addresses: 49h, 4Ah, 4Bh (the temperatures of the platforms 10-1, 10-5 to 10-7 connected to the slots S of the slot numbers: 0, 5, 6, 7). The sensor 18) is accessed to receive the temperature detection result by the temperature sensor 18. Then, the internal microcomputer 41 stores the temperature detection result by the temperature sensor 18 of the platforms 10-1, 10-5 to 10-7 as internal information in the register.

After that, the internal microcomputer 41 identifies the highest temperature among the temperature detection results (temperature detection results by the temperature sensor 18 of the platforms 10-2 to 10-7) stored as internal information in the register. Further, the internal microcomputer 41 collates the specified temperature with the cooling fan table, and outputs a FAN_PWM_OUT signal having a duty ratio corresponding to the temperature to each cooling fan of the platforms 10-2 to 10-7. Output to 17. Here, the cooling fan table is a table that associates the temperature of the external microcomputer 16 with the duty ratio of the FAN_PWM_OUT signal suitable for the temperature. The internal microcomputer 41 repeats the setting of the duty ratios of the FAN_PWM_IN signal and the FAN_PWM_OUT signal according to the temperature detection results by the temperature sensors 18 and 45 described above every preset time (for example, 1 second). ..

Further, the internal microcomputer 41 periodically determines whether or not the cooling fan 17 is operating normally based on the FAN_TACH signal received from the cooling fan 17. This makes it possible to prevent the external microcomputer 16 from continuing to operate while the cooling fan 17 has an abnormality after the external microcomputer 16 is started. In the present embodiment, the internal microcomputer 41 has the bridge board fan 44 and the cooling fan 17 based on the FAN_TACH signal received from the bridge board fan 44 and the cooling fan 17 even after the start processing of the external microcomputer 16 is completed. Judge whether it is operating normally. Then, when the bridge board fan 44 is not operating normally, the internal microcomputer 41 terminates the operation of the internal microcomputer 41 itself. Further, the internal microcomputer 41 terminates the operation of the external microcomputer 16 mounted on the platform 10 in which the cooling fan 17 is not operating normally.

For example, the internal microcomputer 41 sets a timer for a determination interval for determining whether or not the cooling fan 17 and the bridge board fan 44 are operating normally. Then, every time the countdown of the determination interval by the timer is completed, the internal microcomputer 41 is sent from the cooling fan 17 and the bridge board fan 44, among the cooling fans 17, where the power is turned on and the duty ratio of the FAN_PWM_IN signal is not 0%. Based on the received FAN_TACH signal, it is determined whether or not the cooling fan 17 and the bridge board fan 44 are operating normally. At that time, the internal microcomputer 41 determines whether or not all the cooling fans 17 are operating normally while switching the cooling fans 17 to be determined in the same manner as before the external microcomputer 16 is started.

FIG. 4 is a diagram for explaining an example of FAN_TACH signal switching processing by the TACH signal switching circuit according to the present embodiment. Next, an example of the FAN_TACH signal switching process by the TACH signal switching circuit 43 will be described with reference to FIG.

In the present embodiment, the TACH signal switching circuit 43 includes a first switching circuit 431, a second switching circuit 432, and a third switching circuit 433, as shown in FIG.

The first switching circuit 431 has FAN_TACH signals (FAN_TACH_PCIE2, FAN_TACH_PCIE3, FAN_TACH_PCIE4, FAN_TACH_PCIE5) transmitted from the respective cooling fans 17 of platforms 10-2 to 10-5 connected to slots S of slot numbers 2 to 5. ), And the PCIE_FAN_SEL1 signal is input. When the PCIE_FAN_SEL1 signal is low, the first switching circuit 431 transmits the FAN_TACH signal (FAN_TACH_PCIE2, FAN_TACH_PCIE4) received from the cooling fans 17 of the platforms 10-2 and 10-4 to the third switching circuit 433. Output. On the other hand, when the PCIE_FAN_SEL1 signal is high, the first switching circuit 431 transmits the TACH signal (FAN_TACH_PCIE3, FAN_TACH_PCIE5) received from the cooling fans 17 of the platforms 10-3 and 10-5 to the third switching circuit 433. Output.

The second switching circuit 432 has a FAN_TACH signal (FAN_TACH_INTER) transmitted from each cooling fan 17 of the platforms 10-1, 10-6, 10-7 connected to the slot S of slot numbers 0, 6, and 7. , FAN_TACH_PCIE6, FAN_TACH_PCIE7), FAN_TACH signal (FAN_TACH_PCIE_FRONT) transmitted from the bridge board fan 44, and PCIE_FAN_SEL1 signal are input. Then, when the PCIE_FAN_SEL1 signal is low, the second switching circuit 432 transmits the TACH signal (FAN_TACH_PCIE6, FAN_TACH_INTER) received from the respective cooling fans 17 of the platforms 10-1 and 10-6 to the third switching circuit 433. Output. On the other hand, when the PCIE_FAN_SEL1 signal is high, the second switching circuit 432 receives the FAN_TACH signal (FAN_TACH_PCIE7) received from the cooling fan 17 of the platform 10-7 and the FAN_TACH signal (FAN_TACH_PCIE_FRONT) received from the bridge board fan 44. Output to the third switching circuit 433.

The FAN_TACH signal and the PCIE_FAN_SEL2 signal output from the first switching circuit 431 and the second switching circuit 432 are input to the third switching circuit 433. When both the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal are low, the third switching circuit 433 inputs the FAN_TACH_PCIE2 input from the first switching circuit 431 and the FAN_TACH_PCIE6 input from the second switching circuit 432 into the internal microcomputer 41. To do. When the PCIE_FAN_SEL1 signal is low and the PCIE_FAN_SEL2 signal is high, the third switching circuit 433 transmits the FAN_TACH_PCIE4 input from the first switching circuit 431 and the FAN_TACH_INTER input from the second switching circuit 432 to the internal microcomputer 41. input.

When the PCIE_FAN_SEL1 signal is high and the PCIE_FAN_SEL2 signal is low, the third switching circuit 433 transmits the FAN_TACH_PCIE3 input from the first switching circuit 431 and the FAN_TACH_PCIE7 input from the second switching circuit 432 to the internal microcomputer 41. input. When both the PCIE_FAN_SEL1 signal and the PCIE_FAN_SEL2 signal are high, the third switching circuit 433 inputs the FAN_TACH_PCIE5 input from the first switching circuit 431 and the FAN_TACH_FRONT input from the second switching circuit 432 into the internal microcomputer 41. To do. Through the above processing, the TACH signal switching circuit 43 executes the switching processing of the FAN_TACH signal input to the internal microcomputer 41.

FIG. 5 is a diagram for explaining an example of switching processing of the temperature detection result input to the internal microcomputer by the temperature sensor switching circuit according to the present embodiment. Next, an example of the switching process of the temperature detection result input to the internal microcomputer 41 by the temperature sensor switching circuit 42 will be described with reference to FIG.

In the present embodiment, the temperature sensor switching circuit 42 receives the temperature from the temperature sensor 45 and the temperature sensors 18 of the platforms 10-1 to 10-7 connected to the slots S of the slot numbers 0, 2 to 7. The data signal (I2C_SDA_MCU) indicating the temperature detection result by the sensors 18 and 45 and the clock signal (I2C_SCL_MCU) are received.

When the PCIE_I2C_SEL signal input from the internal microcomputer 41 is low, the temperature sensor switching circuit 42 includes a data signal (I2C_SDA_MCU_BB) indicating the temperature detection result by the temperature sensor 45 and a temperature sensor of platforms 10-2 to 10-4. A data signal (I2C_SDA_MCU_SW1) including a data signal (I2C_SDA_MCU_CN2, I2C_SDA_MCU_CN3, I2C_SDA_MCU_CN4) indicating a temperature detection result by 18, a clock signal from the temperature sensor 45 (I2C_SCL_MCU_BB), and a temperature sensor The clock signal (I2C_SCL_MCU_SW1) including the clock signal (I2C_SCL_MCU_CN2, I2C_SCL_MCU_CN3, I2C_SCL_MCU_CN4) is input to the internal microcomputer 41.

On the other hand, when the PCIE_I2C_SEL signal input from the internal microcomputer 41 is high, the temperature sensor switching circuit 42 is a data signal (I2C_SDA_MCU_PC) indicating the temperature detection result by the temperature sensor 18 of the platforms 10-1, 10-5 to 10-7. , I2C_SDA_MCU_CN5, I2C_SDA_MCU_CN6, I2C_SDA_MCU_CN7) and data signals (I2C_SDA_MCU_SW1) and clock signals from temperature sensors 18 on platforms 10-1, 10-5-10-7 (I2C_SCL_MCU_PC I2C_SCL_MCU_SW1) and are input to the internal microcomputer 41.

FIG. 6 is a sequence diagram showing an example of the flow of activation processing of the external microcomputer in the information processing system according to the present embodiment. Next, an example of the flow of the activation process of the external microcomputer 16 in the information processing system according to the present embodiment will be described with reference to FIG.

The switch 52 is turned on when the PCIE_PRESENT signal is high to supply 3.3 V of standby power to the platform 10 connected to the slot S to which the PCIE_PRESENT signal is input. After that, when the power button for turning on the power of the PSU 50 is pressed, the PSU 50 starts supplying 12.0 V power from the PSU 50 to the power control board 40 (step S601).

The internal microcomputer 41 receives the FAN_TACH signal from the bridge board fan 44 via the TACH signal switching circuit 43, and determines whether or not the bridge board fan 44 is operating normally based on the FAN_TACH signal. The process is executed (step S602). Then, when it is determined that the bridge board fan 44 is operating normally, the internal microcomputer 41 activates the power supply control board 40 (step S603).

Further, the internal microcomputer 41 sets the PCIE_P_BTN signal transmitted to the external microcomputer 16 mounted on the platform 10-1 which functions as the main information processing device connected to the slot S of slot number: 1 to high, and sets the PCIE_P_BTN signal high. The external microcomputer 16 is started. The external microcomputer 16 of the platform 10-1 is activated when the PCIE_BTN signal received from the internal microcomputer 41 becomes high, and executes the POST (Power On Self Test) process (step S604).

Based on the PCIE_PRESENT signal, the internal microcomputer 41 determines whether or not another platform 10 is connected to a slot S other than the slot S to which the platform 10-1 is connected (step S605). Then, the internal microcomputer 41 sets the PCIE_SW_ON signal output to the switch 49 and the DCDC converter 47 to high, and starts supplying power from the PSU 50 to the platform 10 connected to the slot S (step S606).

The cooling fan 17 receives power from the PSU 50 and rotates according to the FAN_PWM_OUT signal transmitted from the internal microcomputer 41 via the expansion pin. The internal microcomputer 41 executes a check process for determining whether or not the cooling fan 17 is operating normally based on the FAN_TACH signal input from the cooling fan 17 of the platform 10 connected to the slot S ( Step S607).

Then, the internal microcomputer 41 outputs a PCIE_P_BTN signal to the external microcomputer 16 of the platform 10 determined to be operating normally among the platforms 10 connected to the slot S, and activates the external microcomputer 16. (Step S608). After that, when the PCIE_START signal input from the external microcomputer 16 becomes high, the internal microcomputer 41 determines that the activation process of the external microcomputer 16 is completed (step S609).

As described above, according to the information processing system 1 according to the present embodiment, even if the external microcomputer 16 is not started, after determining whether or not the cooling fan 17 operates normally, the external microcomputer 16 is contacted. Can be instructed to start. As a result, it becomes possible to provide a highly secure information processing system 1.

Further, according to the information processing system 1 according to the present embodiment, it is possible to prevent the external microcomputer 16 from starting when the cooling fan 17 is not rotating at a rotation speed equal to or higher than the rotation speed instructed by the internal microcomputer 41. Therefore, even though the cooling fan 17 is not operating normally, it is possible to prevent the external microcomputer 16 from starting and the external microcomputer 16 not being sufficiently cooled, causing a problem in the external microcomputer 16.

Further, according to the information processing system 1 according to the present embodiment, among the cooling fans 17 of the plurality of platforms 10, whether or not the cooling fan 17 for cooling the external microcomputer 16 of any platform 2 is operating normally. Can be determined.

Further, according to the information processing system 1 according to the present embodiment, the cooling fan 17 can be rotated at a rotation speed that can cool the external microcomputers 16 of all the platforms 10, so that the cooling fan 17 is sufficient. It is possible to prevent the external microcomputer 16 that is not cooled from being generated and causing a problem in the external microcomputer 16.

Further, according to the information processing system 1 according to the present embodiment, it is possible to prevent the external microcomputer 16 from continuing to operate while the cooling fan 17 has an abnormality after the external microcomputer 16 is started.

In the above-described embodiment, PCIe has been described as an example of the I / O interface of each part, but the interface is not limited to PCIe. For example, the interface of each part may be a technology capable of transferring data between a device (peripheral control controller) and a processor by a data transfer bus. The data transfer bus may be a general-purpose bus capable of transferring data at high speed in a local environment (for example, one system or one device) provided in one housing or the like. The interface may be either a parallel interface or a serial interface.

In the case of serial transfer, the I / O interface may be configured so that point-to-point connection is possible and data can be transferred on a packet basis. The I / O interface may have a plurality of lanes in the case of serial transfer. The layer structure of the I / O interface may include a transaction layer that generates and decodes packets, a data link layer that performs error detection, and a physical layer that converts serial and parallel. The I / O interface also includes a root complex at the top of the hierarchy with one or more ports, endpoints that are I / O devices, switches to increase ports, bridges that translate protocols, and so on. It's fine. The interface may transmit the data to be transmitted and the clock signal multiplexed by a multiplexer. In this case, the receiving side may separate the data and the clock signal by a demultiplexer.

1 Information processing system 10-1 to 10-8 Platform 16-1 to 16-8 External microcomputer 17 Cooling fan 18,45 Temperature sensor 19,47,48 DCDC converter 30 Relay device 40 Power supply control board 41 Internal microcomputer 42 Temperature sensor Switching circuit 43 TACH signal switching circuit 44 Bridge board fan 46 Inverting circuit 49, 52 Switch 50 PSU
S slot (example of connection part)

Claims (6)

A connection unit that can connect an external information processing device,
Prior to the activation of the external control unit of the external information processing device, the external information processing device can be used from the external information processing device via an expansion pin other than the pins used for communication according to the communication standard among the pins of the connection unit. It receives an operation signal indicating the operating state of the cooling fan of the external control unit, determines whether or not the fan is operating normally based on the operating signal, and the fan operates normally. If it is determined that there is, the control unit that instructs the external control unit to start, and
A signal switching circuit that receives the operation signal from the fan of each of the plurality of external information processing devices and selects the operation signal received from the fan to be detected for abnormality among the received operation signals. And with
The control unit is an information processing device that determines whether or not the fan is operating normally based on the operation signal selected by the signal switching circuit . The operation signal indicates the measurement result of the rotation speed of the fan.
The control unit transmits a fan control signal indicating the rotation speed of the fan to the fan, and the fan is normal based on the rotation speed indicated by the fan control signal and the rotation speed indicated by the operation signal. The information processing apparatus according to claim 1, wherein it is determined whether or not the information processing device is operating. The control unit receives the temperature detection result of the external control unit by the temperature sensor from the external information processing device, and determines the rotation speed of the fan according to the highest temperature among the received temperature detection results. The information processing device according to claim 2, wherein the fan control signal indicating the determined rotation speed is transmitted to the fan. The information processing device according to any one of claims 1 to 3 , wherein the control unit periodically determines whether or not the fan is operating normally based on the operation signal. Computer,
Prior to the activation of the external control unit of the external information processing device, an expansion pin other than the pin used for communication according to the communication standard among the pins of the connection unit to which the external information processing device can be connected is used. An operation signal indicating the operating state of the cooling fan of the external control unit is received from the external information processing device, and based on the operation signal, it is determined whether or not the fan is operating normally. When it is determined that the fan is operating normally, it is made to function as a control unit that instructs the external control unit to start .
The control unit receives the operation signal from the fan of each of the plurality of external information processing devices, and among the received operation signals, the operation signal received from the fan to be detected for abnormality is used. A program that determines whether or not the fan is operating normally based on the operation signal selected by the selected signal switching circuit . An information processing system having a first information processing device and a second information processing device.
The first information processing device is
1st control unit and
The cooling fan of the first control unit and
With
The second information processing device is
A connection unit to which the first information processing device can be connected and
Prior to the activation of the first control unit included in the first information processing apparatus, the first information processing apparatus has an expansion pin other than the pins used for communication in accordance with the communication standard among the pins possessed by the connection portion. , The operation signal indicating the operation state of the cooling fan of the first control unit is received, and based on the operation signal, it is determined whether or not the fan is operating normally, and the fan operates normally. If it is determined that the information is being processed, the second control unit that instructs the first control unit to start the system and
A signal switching circuit that receives the operation signal from the fan of each of the plurality of first information processing devices and selects the operation signal received from the fan whose abnormality is detected among the received operation signals. And with
The second control unit is an information processing system that determines whether or not the fan is operating normally based on the operation signal selected by the signal switching circuit .

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