JP6788249B2 - Generator, generation method and program - Google Patents

Description

The present invention relates to a generator, a generator and a program.

Inductive Logic Programming (ILP), which is a machine learning method using a logic program, has been conventionally known (Non-Patent Document 1). Inductive logic programming is a technique for estimating a logic program that is consistent with given training data (hereinafter, also referred to as "training example"). Therefore, by inductive logic programming, it is possible to acquire a logic program that is consistent with these training examples only by giving training examples without manually designing the logic program.

Yamamoto, "Basic Theory of Inductive Logic Programming and Its Development", Computer Software, Vol.23, No. 2, pp. 29-44, 2006.

Here, in the conventional inductive logic programming algorithm, the purpose is to acquire one logic program (solution) that does not contradict the given training example. However, in reality, there may be many solutions that are consistent with the training examples.

Therefore, in the conventional inductive logic programming, it is not possible to enumerate a plurality of solutions that do not contradict the given training example. For example, the optimum logic program that does not contradict the given training example satisfies the desired condition. It was difficult to meet the demands such as seeking a logic program.

An embodiment of the present invention has been made in view of the above points, and an object of the present invention is to obtain all solutions of inductive logic programming.

In order to achieve the above object, an embodiment of the present invention is a generator that generates information indicating each of hypotheses Σ representing a logical program that is a solution to a problem of inductive logic programming, and is positive with background knowledge B. When a set of basic atomic formulas ε ⁺ showing an example training example and a set P of reduced deterministic clauses that can be included in the hypothesis Σ are input, for each basic atomic formula E included in the set ε ^+. First, construct a first dichotomy diagram representing a logical function f corresponding to hypothesis Σ ₁ such that the basic atomic formula E is a logical conclusion of the sum set of the background knowledge B and hypothesis Σ ₁ . When the means for generating the above, the background knowledge B, the set ε ⁻ of the basic atomic formulas showing the training example of the negative example, and the set P are input, each basic atomic formula included in the set ε ⁻ is input. For E, a second dichotomous diagram representing the logical function g corresponding to the hypothesis Σ ₂ is constructed such that the basic atomic formula E is the logical result of the sum set of the background knowledge B and the hypothesis Σ ₂ . A third generation means for generating a third dichotomy diagram by performing an Apply operation on each of the second generation means, the first dichotomy diagram, and each of the second dichotomy diagrams. [E], the first generation means and the second generation means include a logical function [E] expressing a set of hypotheses having the basic atomic formula E as a logical consequence, in the set P. each reduced definite clause a ← _B 1, ···, of the _{B n,} reduction definite clause a ← _B 1 satisfying E = A.theta. relative assignment theta, · · ·, a set of subscripts _{B n J E} As a result, the first dichotomy diagram and the second dichotomy diagram are constructed by recursively performing an Apply operation on a predetermined formula.

You can get all the solutions of inductive logic programming.

It is a figure which shows an example of the binary decision diagram. It is a figure which shows an example of the functional structure of the generation apparatus in embodiment of this invention. It is a flowchart which shows an example of the flow of the process executed by the generation processing part in embodiment of this invention. It is a figure which shows an example of the hardware composition of the generation apparatus in embodiment of this invention.

Hereinafter, embodiments of the present invention will be described. In the embodiment of the present invention, it is an object of the inductive logic programming to obtain all the logic programs that are consistent with the given training example. However, the number of logical programs that can be the solution of inductive logic programming can increase exponentially. Therefore, a system that outputs all these logical programs may not work with realistic settings. Therefore, instead of outputting all the logical programs, a binary decision diagram (BDD) representing a set of all the solutions is constructed to realize an enumeration of all these logical programs. For BDD, refer to Reference 1 below.

[Reference 1]
Bryant, RE, "Graph-Based Algorithms for Boolean Function Manipulation", IEEE Trans. Computers, Vol.C-35, No.8, pp.677-691, 1986.
BDD is a data structure that can represent a set of logical programs as a graph. By expressing a set of logical programs using BDD, a huge number of sets of logical programs can be compressed and indexed, so that they can be stored in a storage medium of a computer or the like. Further, it is possible to efficiently execute an operation such as extracting one logical program satisfying a certain condition from the set of logical programs represented by BDD.

Therefore, in the embodiment of the present invention, the generation device 10 that generates and outputs a BDD representing an index of a set of all logical programs consistent with a given training example will be described.

First, some terms and the like will be described before the generator 10 according to the embodiment of the present invention is described.

<First-order predicate logic>
A term in first-order logic is a symbol string formed by (1) a variable, (2) a constant symbol, and (3) a function symbol f of arity n and n terms t ₁ , ..., T _n. It is f (t ₁ , ..., T _n ).

Further, the symbol string P (t ₁ , ..., T _n ) formed by the predicate symbol P of the arity n and the n terms t ₁ , ..., T _n is called an atomic formula. Atomic formula A and its negation ¬A are called literals, in particular A is called a "positive literal" and ¬A is called a "negative literal". A logical expression obtained by binding all the variables that appear in literal paraphrases (that is, "∨") is called a clause.

The truth value of a formula in first-order predicate logic is determined by interpretation. The interpretation I of first-order predicate logic for language L is determined by the non-empty set (domain) D. That is, according to Interpretation I, the constant symbol is assigned to the element of D, the function symbol of arity n is assigned to the mapping from D ⁿ to D, and the predicate symbol of arity n is the boolean value {True, false} from D ⁿ . Assigned to a mapping to.

If the formula φ is true under Interpretation I, then Interpretation I is said to be a model of φ. If any model of the set Σ of the formula is a model of the formula φ, then the formula φ is said to be the logical conclusion of the formula set Σ.

と表す。一方で、論理式φが、論理式の集合Σの論理的帰結でない場合は、

It is expressed as. On the other hand, if the formula φ is not a logical conclusion of the set Σ of the formulas,

と表す。

It is expressed as.

Atomic formulas that do not include variables are called basic atomic formulas. Similarly, literals that do not contain variables are called basic literals. A clause that does not contain variables is called a basic clause.

In first-order predicate logic, substituting variables x ₁ , ..., X _m with terms t ₁ , ..., T _m is called substitution. Such substitution is expressed as θ = {x ₁ / t ₁ , ..., X _m / t _m }. Further, all the variables x ₁ , ..., X _m included in the section C of the first-order predicate logic are replaced with the terms t ₁ , ..., T _m at the same time, and are expressed as Cθ.

Here, inductive logic programming is a finite set of clauses.

が与えられた場合に、全ての節Ｅ∈ε^＋に対して、以下の式１が成り立ち、

Given, the following equation 1 holds for all clauses E ∈ ε ⁺ ,

、かつ、全ての節Ｅ∈ε⁻に対して、以下の式２が成り立つような節の有限集合Σを求める問題のことである。なお、以降では、節の有限集合のことを仮説とも呼ぶ。

And, for all clauses E ∈ ε ⁻ , it is a problem to find a finite set Σ of clauses such that the following equation 2 holds. In the following, the finite set of clauses will also be called a hypothesis.

ここで、

here,

は背景知識とも呼ばれる。この背景知識を、以降では、「背景知識Ｂ」とも表す。また、ε^＋は正例、ε⁻は負例とも呼ばれる。

Is also called background knowledge. Hereinafter, this background knowledge will also be referred to as "background knowledge B". In addition, ε ⁺ is also called a positive example, and ε ⁻ is also called a negative example.

For example

が与えられたとすると、仮説Σ＝｛Ｐ（０）←，Ｐ（ｓ（ｓ（Ｘ）））←Ｐ（ｘ）｝は、この機能論理プログラミングの問題の１つの解である。なお、Ｐは述語記号、ｓは関数記号である。また、Ｐ（０）←、Ｐ（ｓ（ｓ（Ｘ）））←Ｐ（ｘ）は確定節を表す。

Given, the hypothesis Σ = {P (0) ←, P (s (s (X))) ← P (x)} is one solution to this functional logic programming problem. Note that P is a predicate symbol and s is a function symbol. Further, P (0) ← and P (s (s (X))) ← P (x) represent definite clauses.

A definite clause is a clause that contains exactly one positive literal. The definite clause is expressed as A ← B ₁ , ..., B _n or A ← using the atomic formulas A, B ₁ , ..., B _n . The definite clause expressed in the form of A ← is called a unit clause. A definite clause that does not include variables is called a basic definite clause, and a unit clause that does not include variables is called a basic unit clause.

Further, the total number of function symbols, constant symbols and variable symbols included in a certain atomic formula A is expressed as | A |. When | Aθ | ≧ | B _i θ | is satisfied for arbitrary substitution θ and i = 1, ···, n, the definite clause A ← B ₁ , ···, B _n is called the reduced definite clause.

<Binary building diagram>
A binary decision diagram (BDD) is a data structure that represents a logical function as a directed acyclic graph. As an example, FIG. 1 shows a BDD expressing a logical function (x ₁ ∧ x ₂ ) ∨ (x ₁ ∧ x ₃ ) ∨ (x ₂ ∧ x ₃ ).

BDD has two types of nodes, a terminal node and a branch node. A terminal node is a node that does not have a branch (arc) starting from the node. In the example shown in FIG. 1, the terminal node is a node represented by a quadrangle (node n5 and node n6). The terminal nodes include ⊥ terminal node (hereinafter referred to as "first terminal node") and

（以下、「第２終端ノード」という。）との２種類のノードがある。１つのＢＤＤには、第１終端ノードと第２終端ノードとがそれぞれ高々１つずつ存在する。

There are two types of nodes (hereinafter referred to as "second terminal node"). There is at most one first terminal node and one second terminal node in one BDD.

On the other hand, a branch node is a node that is not a terminal node. In the example shown in FIG. 1, the branch node is a node represented by a circle (node n1, node n2, node n3 and node n4). Each branch node is given a label representing an element corresponding to the branch node in the set of all variables of the logical function represented by BDD. In the example shown in FIG. 1, the node n1, the element 1 representing the variable x ₁ is assigned as a label. Similarly, the node n2 and the node n3 are given an element 2 representing the variable x ₂ as a label. Similarly, the node n4, the elements 3 representing the variable x ₃ is assigned as a label.

In addition, each branch node always has two branches starting from the branch node, and are called lo branch and hi branch, respectively. In the example shown in FIG. 1, the lo branch is represented by a broken line and the hi branch is represented by a solid line, the lo branch of node n1 points to node n2, and the hi branch points to node n3. In this case, node n1 is a parent node, and nodes n2 and n3 are child nodes.

Similarly, the lo branch of node n2 points to node n5 and the hi branch points to node n4. In this case, node n2 is a parent node, and nodes n5 and n4 are child nodes. Similarly, for the other nodes, the lo branch and the hi branch of the node n3 refer to the node n4 and the node n6, respectively, and the node n3 is the parent node and the node n4 and the node n6 are the child nodes. The lo branch and the hi branch of the node n4 refer to the node n5 and the node n6, respectively, and the node n4 is a parent node and the node n5 and the node n6 are child nodes.

There is always only one node in BDD that does not have a parent node, and it is called a root node. In the example shown in FIG. 1, node n1 is the root node.

Each path from the root node to the second terminal node corresponds to the assignment of variables such that the logical function represented by BDD is true. Each path of BDD shall be represented by _three variables (x ₁ , x ₂ , x ₃ ), the value of each variable shall be 0 or 1, and the value of the variable shall be 1 when the path passes through the hi branch. Therefore, assuming that the value of the variable is 0 in the case of the route passing through the lo branch, in the BDD shown in FIG. 1, the allocation of the variable corresponding to each route from the root node to the second terminal node is a value ( It can be expressed by 1,1, *), (1,0,1), (0,1,1). Here, * corresponds to assigning a value of either 0 or 1.

For example, (1, 1, *) represents a route following node n1, node n3, and node n6 in the BDD shown in FIG. Here, in this case, but not follow node label elements 3 representing the variable x ₃ is given, this is because the redundant nodes in BDD shown in FIG. 1 has been deleted (i.e., FIG. The BDD shown in 1 is irreducible.)

Similarly, (1, 0, 1) represents a route following node n1, node n3, node n4, and node n6 in the BDD shown in FIG. Similarly, (0,1,1) represents a route following node n1, node n2, node n4, and node n6 in the BDD shown in FIG.

A BDD in which the order of variables represented by each path from the root node to the second terminal node (and the first terminal node) is the same is also referred to as "ordered BDD". The BDD shown in FIG. 1 is an ordered BDD (more precisely, an irreducible ordered BDD). In embodiments of the present invention, the BDD is an ordered BDD (and an irreducible ordered BDD).

Each node of BDD represents a partial BDD having the node as a root node, and the partial BDD represents one logical function. In the example shown in FIG. 1, for example, part BDD to the node n2 and the root node, expresses the partial logical function _{x 2} ∧X ₃ defined for the variables _{x 2} and _{x 3.} The first terminal node corresponds to the truth value of the logical function represented by BDD being 0, and the second terminal node corresponds to the truth value of the logical function represented by BDD being 1. It shall be.

In the following, it is assumed that there are B BDD nodes, and each node is referred to as b ₁ , ..., B _B. Also, the root node _{b 1,} a _{b B} a second terminal node, for any two nodes _{b i} and _{b j,} i <j if _{b i} is that not be a child node of _{b j} And.

BDD can be expressed by four sets of (node ID, label, node ID pointed to by the hi branch, and node ID pointed to by the lo branch) for each node. Since the BDD shown in FIG. 1 has 6 nodes,

と表現することができる。

Can be expressed as.

<Apply operation>
The logical function f∨ obtained by applying a binary operation between the logical functions f and g, where the BDD representing the logical function f is Z (f) and the BDD representing the logical function g is Z (g). The BDDs expressing g and f∧g are expressed as Z (f∨g) and Z (f∧g), respectively. The operation for obtaining Z (f∨g) or Z (f∧g) from Z (f) and Z (g) is called an Apply operation. It is known that the Apply operation can be executed in an operation time proportional to the magnitudes of Z (f) and Z (g). For the Apply operation, refer to Reference 1 above.

<Generator 10>
Next, the generator 10 according to the embodiment of the present invention will be described.

≪Functional configuration≫
First, the functional configuration of the generator 10 according to the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a diagram showing an example of the functional configuration of the generator 10 according to the embodiment of the present invention.

As shown in FIG. 2, the generation device 10 according to the embodiment of the present invention has a generation processing unit 100. The generation processing unit 100 is realized by a process of causing a CPU (Central Processing Unit) or the like to execute one or more programs installed in the generation device 10.

The generation processing unit 100 inputs the background knowledge B, the sets ε ⁺ and ε ^{− of} the training example, and the set P of the clauses that can be included in the hypothesis Σ. Here, it is assumed that all the training examples are basic unit clauses, and the background knowledge B, the set ε ⁺ , the set ε ^−, and the set P are finite sets. Further, all the clauses included in the set P are reduced fixed clauses, and the number of reduced fixed clauses included in the set P is N. The set ε ⁺ is a set of positive training examples, and the set ε ⁻ is a set of negative training examples.

At this time, the generation processing unit 100 obtains a set of hypotheses Σ such that the above equations 1 and 2 hold, based on the input sets ε ⁺ and ε ⁻ and the background knowledge B. The hypothesis Σ is a subset of the set P.

In the embodiment of the present invention, the hypothesis Σ is expressed using an N-dimensional binary vector x. The i-th component of the binary vectors x and _{x i.} Then, if the i-th reduced definite clause included in the set P is included in the hypothesis Σ, x _i = 1, and if the i-th reduced definite clause is not included in the hypothesis Σ, x _i = 0. By expressing the hypothesis Σ by this N-dimensional binary vector x, the set of the hypothesis Σ can be expressed as a logical function. That is, all the logical functions f such that f (x) = 1 when the binary vector x representing the hypothesis Σ is the solution of the inductive logic programming problem and f (x) = 0 when it is not the solution are all. It can be regarded as representing a set of solutions.

Therefore, if each variable x _i constituting this binary vector x is regarded as a variable representing BDD (that is, if i labels given to each node of BDD represent each variable x _i , respectively. ), A set of hypotheses Σ can be expressed by BDD expressing the logical function f. At this time, each of the paths from the root node of BDD to the second terminal node represents a hypothesis that is a solution to the problem of inductive logic programming. On the other hand, each of the paths from the root node of BDD to the first terminal node represents a hypothesis that does not solve the problem of inductive logic programming.

This means that the allocation of variables corresponding to each route of BDD can be regarded as an index of hypotheses corresponding to the route.

That is, the generation processing unit 100 constructs the BDD Z (h) based on the input sets ε ⁺ and ε ⁻ and the background knowledge B. Then, the generation processing unit 100 outputs the constructed BDD Z (h). The assignment of variables corresponding to the path from the root node of Z (h) to the second terminal node is the index of hypothesis Σ, which is the solution of inductive logic programming. Therefore, the generation processing unit 100 generates an index of hypothesis Σ, which is a solution of inductive logic programming, by constructing BDD Z (h) based on the input sets ε ⁺ and ε ⁻ and background knowledge B. You can also say that.

The generation processing unit 100 may output the constructed BDD Z (h) as an index of the hypothesis Σ which is the solution of inductive logic programming, or the second terminal node from the root node of the BDD Z (h). You may output a set of variable assignments corresponding to the path leading up to.

Here, the generation processing unit 100 includes a first hypothesis set generation unit 101, a second hypothesis set generation unit 102, and a third hypothesis set generation unit 103.

The first hypothesis set generation unit 101 includes a background knowledge B, a set of training examples epsilon ^+, and inputs the set P, all of the basic atomic formula E∈ipushiron ^+, hypotheses that satisfies the above Equation 1 Σ A BDD that represents a logical function corresponding to a set of ₁ is constructed. That is, assuming that ε ⁺ contains M basic atomic formulas, the first hypothesis set generation unit 101 performs the i-th basic atomic formula E for each i (i = 1, ..., M). _{For i}

となるような仮説Σ_１の集合を表現する論理関数ｆ_ｉを表すＢＤＤ Ｚ（ｆ_ｉ）を構築する。ＢＤＤの構築方法については後述する。なお、ε^＋に含まれる訓練例は全て基礎単位節であることから、これらは全て基礎原子論理式である。

Building a BDD Z _{(f i)} representative of the logic function _{f i} that represents the set of hypotheses sigma ₁ such that. The method of constructing BDD will be described later. Since all the training examples included in ε ⁺ are basic unit clauses, these are all basic atomic formulas.

The second hypothesis set generation unit 102 includes a background knowledge B, a set of training examples epsilon ^- and, by entering a set P, all atomic formulas E∈ipushiron ^- for hypothesis sigma ₂ satisfying the formula 1 above Build a BDD that represents the logical function corresponding to the set of. That is, assuming that ε ⁻ contains K basic atomic formulas, the second hypothesis set generation unit 102 uses the i-th basic atomic formula E for each i (i = 1, ..., K). _{For i}

となるような仮説Σ_２の集合を表現する論理関数ｇ_ｉを表すＢＤＤ Ｚ（ｇ_ｉ）を構築する。ＢＤＤの構築方法については後述する。なお、ε⁻に含まれる訓練例は全て基礎単位節であることから、これらは全て基礎原子論理式である。

Building a BDD Z _{(g i)} which represents the logical function _{g i} which represents the set of hypotheses sigma ₂ such that. The method of constructing BDD will be described later. Since all the training examples included in ε ⁻ are basic unit clauses, they are all basic atomic formulas.

Here, in the above, the negative examples in which training examples E _i ∈ε ^- was constructed BDD also represent the logic function g _i corresponding to a set of sigma ₂ satisfying the formula 1 above for Z (g _i). This, in Formula 3 described later, in order to impart logic symbol (¬) showing a negative for each logic function g _i. In Expression 3 to be described later, if no grant logic symbol indicating a negative for each logic function g _i (¬), the second hypothesis set generation unit 102, hypothesis sigma ₂ satisfying the formula 2 above You may construct a BDD that represents a logical function corresponding to a set.

The third hypothesis set generation unit 103, and Z were constructed by first hypothesis set generation unit 101 _{(f i),} by entering the Z _{(g i)} constructed in the second hypothesis set generation unit 102, these BDD By performing the Apply operation of, BDD Z (h) representing the logical formula h shown in the following formula 3 is constructed.

≪処理の流れ≫
次に、本発明の実施の形態における生成処理部１００が実行する処理の流れについて、図３を参照しながら説明する。図３は、本発明の実施の形態における生成処理部１００が実行する処理の流れの一例を示すフローチャートである。なお、以降では、背景知識Ｂと、訓練例の集合ε^＋及びε⁻と、集合Ｐとが生成処理部１００に入力されたものとする。

≪Processing flow≫
Next, the flow of processing executed by the generation processing unit 100 according to the embodiment of the present invention will be described with reference to FIG. FIG. 3 is a flowchart showing an example of a flow of processing executed by the generation processing unit 100 according to the embodiment of the present invention. In the following, it is assumed that the background knowledge B, the sets ε ⁺ and ε ^{− of} the training example, and the set P are input to the generation processing unit 100.

Step S101: The first hypothesis set generation unit 101 of the generation processing unit 100 inputs the background knowledge B, the set ε ⁺ of the training example of the positive example, and the set P, and i = 1, ..., M. respect, to construct a Z _{(f i)} described above.

The following describes how to build a BBD Z _{(f i).} Hereinafter, the method of constructing Z (f) will be described by fixing the subscript _i of fi and simply expressing it as “f”.

Let [E] be a logical function that expresses a set of hypotheses whose logical conclusion is a certain basic atomic formula E. Further, assuming that the subscript i (i = 1, ..., N) is added to each reduced fixed clause included in the set P, each reduced fixed clause A ← B ₁ ,. _Let J _E be a set of subscripts of reduced definite clauses that satisfy E = A θ for a certain substitution θ among B _n . Then, [E] is

となる。ここで、θ_ｉはｉ番目の縮小確定節に対してＥ＝Ａθ_ｉとなるような代入を表す。このような代入は各縮小確定節に対して一意に決定される。また、ｎ_ｉはｉ番目の縮小確定節を表す原子論理式Ｂ_１，・・・，Ｂ_ｎの数である。ｉ番目の縮小確定節は、原子論理式Ａ，Ｂ_１，・・・，Ｂ_ｎｉを用いて、Ａ←Ｂ_１，・・・，Ｂ_ｎｉと表される（ただし、「ｎｉ」は、実際には「ｉ」を下付きで表した「ｎ_ｉ」である。）。

Will be. Here, θ _i represents an assignment such that E = Aθ _i for the i-th reduced definite clause. Such substitutions are uniquely determined for each reduced definite clause. Further, _ni is the number of atomic formulas B ₁ , ..., B _n representing the i-th reduced definite clause. The i-th reduced definite clause is expressed as A ← B ₁ , ..., B _ni using the atomic formulas A, B ₁ , ..., B _ni (however, "ni" is actually Is "ni", which is a subscript of " _i ").

Equation 4 above represents that the logical function [E] is recursively obtained by the logical function [B _j θ _i ]. Due to the nature of the reduced definite clause, B _j θ _i is always a basic atomic formula, and its magnitude | B _j θ _i | is always smaller than | E |. On the other hand, since the background knowledge B, the set ε ^{+ of} the positive example, and the set P are all finite sets, the function symbols, constant symbols, and predicate symbols included in these sets are also finite. Therefore, among the basic atomic formulas composed of these function symbols, constant symbols, and predicate symbols, the set of those smaller than the maximum basic atomic formula contained in ε ⁺ is always finite. For each basic atomic formula E having such a magnitude equal to or less than a certain value, a BDD representing the logical function [E] is constructed by recursively executing an Apply operation according to the above formula 4. For each atomic formula E contained in ε ⁺ , a BDD Z (f) representing a logical function f = [E] can be constructed.

Step S102: The second hypothesis set generation unit 102 of the generation processing unit 100 inputs the background knowledge B, the set ε ⁻ of the training example of the negative example, and the set P, and i = 1, ..., K. relative to build the Z a _{(g i)} above.

The following describes how to build a BBD Z _{(g i).} Hereinafter, the method of constructing Z (g) will be described by fixing the subscript _i of gi and simply expressing it as “g”. Since the method for constructing Z (g) is the same as the method for constructing Z (f) described above, the description will be simplified.

Let [E] be a logical function that expresses a set of hypotheses whose logical conclusion is a certain basic atomic formula E. Moreover, the reduced definite clause A ← B ₁ contained in the set _P, · · ·, of B _n, and J _E the set of indices of the reduced definite clauses which satisfy E = A.theta. For a certain assignment θ To do. Then, [E] becomes the above equation 4.

Further, since the set ε ^{− of} negative examples is also a finite set, among the basic atomic formulas composed of the background knowledge B, the set ε ^{− of} negative examples, and the function symbols, constant symbols, and predicate symbols included in the set P, The set of things smaller than the largest basic atomic formula contained in ε ⁻ is always finite. Therefore, for each basic atomic formula E whose magnitude is less than or equal to a certain value, a BDD representing the logic function [E] is constructed by recursively executing an Apply operation according to the above formula 4. Therefore, BDD Z (g) representing the logical function g = [E] can be constructed for each atomic formula E contained in ε ⁻ .

Step S103: third hypothesis set generation unit 103 of the generation processing unit 100 includes a Z constructed in the first hypothesis set generation unit 101 _{(f i),} was constructed by the second hypothesis set generation unit 102 Z and _{(g i)} Is input to perform the Apply calculation of these BDDs, thereby constructing the BDD Z (h) representing the logical formula h shown in the above formula 3.

As a result, the generation processing unit 100 allocates variables corresponding to the path from the root node of Z (h) or the Z (h) to the second terminal node as an index of the hypothesis Σ which is the solution of inductive logic programming. The set of is output.

As described above, in the generator 10 according to the embodiment of the present invention, the set of indexes of the hypothesis Σ, which is the solution of inductive logic programming, corresponds to the path from the BDD or the root node of the BDD to the second terminal node. It can be output as a set of variable assignments. Therefore, according to the generator 10 in the embodiment of the present invention, a set of solutions of inductive logic programming, which may be a huge number, can be compressed and indexed as BDD and enumerated in total. .. By indexing and expressing the set of all solutions as BDD in this way, for example, it is possible to easily select and use a solution satisfying a desired condition from these solutions. Become.

≪Hardware configuration≫
Finally, the hardware configuration of the generator 10 according to the embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram showing an example of the hardware configuration of the generator 10 according to the embodiment of the present invention.

As shown in FIG. 4, the generation device 10 according to the embodiment of the present invention includes an input device 201, a display device 202, an external I / F 203, a RAM (Random Access Memory) 204, and a ROM (Read Only Memory). It has 205, a CPU 206, a communication I / F 207, and an auxiliary storage device 208. Each of these hardware is connected so as to be able to communicate with each other via the bus B.

The input device 201 is, for example, a keyboard, a mouse, a touch panel, or the like, and is used for a user to input various operations. The display device 202 is, for example, a display or the like, and displays the processing result of the generation device 10. The generation device 10 does not have to have at least one of the input device 201 and the display device 202.

The external I / F 203 is an interface with an external device. The external device includes a recording medium 203a and the like. The generation device 10 can read or write the recording medium 203a or the like via the external I / F 203. A program or the like that realizes each function of the generation device 10 may be recorded on the recording medium 203a.

The recording medium 203a includes, for example, a flexible disk, a CD (Compact Disc), a DVD (Digital Versatile Disk), an SD memory card (Secure Digital memory card), a USB (Universal Serial Bus) memory card, and the like.

The RAM 204 is a volatile semiconductor memory that temporarily holds programs and data. The ROM 205 is a non-volatile semiconductor memory that can hold programs and data even when the power is turned off. The ROM 205 stores, for example, OS (Operating System) settings, network settings, and the like.

The CPU 206 is an arithmetic unit that reads programs and data from the ROM 205, the auxiliary storage device 208, and the like onto the RAM 204 and executes processing.

The communication I / F 207 is an interface for connecting the generator 10 to the communication network. The program that realizes each function of the generation device 10 may be acquired (downloaded) from a predetermined server device or the like via the communication I / F 207.

The auxiliary storage device 208 is, for example, an HDD (Hard Disk Drive), an SSD (Solid State Drive), or the like, and is a non-volatile storage device that stores programs and data. The programs and data stored in the auxiliary storage device 208 include, for example, an OS, an application program that realizes various functions on the OS, a program that realizes each function of the generation device 10, and the like.

The generation device 10 according to the embodiment of the present invention can realize the above-mentioned various processes by having the hardware configuration shown in FIG. Note that FIG. 4 describes a case where the generation device 10 according to the embodiment of the present invention is realized by one device, but the present invention is not limited thereto. The generation device 10 according to the embodiment of the present invention may be realized by a plurality of devices.

The present invention is not limited to the above-described embodiment disclosed specifically, and various modifications and modifications can be made without departing from the scope of claims.

10 Generation device 101 1st hypothesis set generation unit 102 2nd hypothesis set generation unit 103 3rd hypothesis set generation unit

Claims (4)

It is a generator that generates information indicating each of the hypotheses Σ that represent the logical program that solves the problem of inductive logic programming.
When the background knowledge B, the set ε ⁺ of the basic atomic formulas showing the training examples of the positive examples, and the set P of the reduced definite clauses that can be included in the hypothesis Σ are input, each of them included in the set ε ^+. For the basic atomic formula E, the first dichotomy representing the logical function f corresponding to the hypothesis Σ ₁ such that the basic atomic formula E is the logical conclusion of the sum set of the background knowledge B and the hypothesis Σ _1. The first generation means to construct the figure and
When the background knowledge B, the set ε ⁻ of the basic atomic formulas showing the training examples of negative examples, and the set P are input, the basics of each basic atomic formula E included in the set ε ^−. A second generation means for constructing a second dichotomy diagram representing a logical function g corresponding to hypothesis Σ ₂ such that the atomic formula E is the logical conclusion of the sum set of the background knowledge B and hypothesis Σ ₂ . When,
A third generation means for generating a third binary diagram by performing an Apply operation on each of the first binary determination diagram and each of the second binary determination diagram.
Have,
The first generation means and the second generation means
[E] is a logical function that expresses a set of hypotheses whose logical conclusion is the basic atomic formula E, and is substituted from each of the reduced definite clauses A ← B ₁ , ..., B _n included in the set P. Let J _{E be} the set of subscripts of reduced definite clauses A ← B ₁ , ..., B _n that satisfy E = A θ with respect to θ.

The generator is characterized in that the first dichotomous diagram and the second dichotomy diagram are constructed by recursively performing an Apply operation. The third generation means is
The M logical functions representing each of the first binary determination diagrams are f ₁ , ... f _M , and the K logical functions representing each of the second binary determination diagrams are g ₁ , ... G. _{As K}

The generator according to claim 1, wherein the third binary decision diagram represented by the above is generated by an Apply operation. A computer that generates information indicating each of the hypotheses Σ that represent the logical program that solves the problem of inductive logic programming
When the background knowledge B, the set ε ⁺ of the basic atomic formulas showing the training examples of the positive examples, and the set P of the reduced definite clauses that can be included in the hypothesis Σ are input, each of them included in the set ε ^+. For the basic atomic formula E, the first dichotomy representing the logical function f corresponding to the hypothesis Σ ₁ such that the basic atomic formula E is the logical conclusion of the sum set of the background knowledge B and the hypothesis Σ _1. The first generation procedure to build the diagram and
When the background knowledge B, the set ε ⁻ of the basic atomic formulas showing the training examples of negative examples, and the set P are input, the basics of each basic atomic formula E included in the set ε ^−. A second generation procedure for constructing a second dichotomy diagram representing a logical function g corresponding to hypothesis Σ ₂ such that the atomic formula E is the logical conclusion of the sum set of the background knowledge B and hypothesis Σ ₂ . When,
A third generation procedure for generating a third binary diagram by performing an Apply operation on each of the first binary diagram and each of the second binary diagram.
And run
The first generation procedure and the second generation procedure
[E] is a logical function that expresses a set of hypotheses whose logical conclusion is the basic atomic formula E, and is substituted from each of the reduced definite clauses A ← B ₁ , ..., B _n included in the set P. Let J _{E be} the set of subscripts of reduced definite clauses A ← B ₁ , ..., B _n that satisfy E = A θ with respect to θ.

The generation method is characterized in that the first binary decision diagram and the second binary decision diagram are constructed by recursively performing an Apply operation. A program for causing a computer to function as each means in the generator according to any one of claims 1 or 2.

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