JP6762733B2 - D / A conversion device and D / A conversion method - Google Patents

Description

The present invention is the gray generated by A / D conversion in which a gray code is generated in a predetermined stage according to the magnitude relationship between a calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. It relates to a D / A conversion device and a D / A conversion method for converting a code into analog data.

As a conventional D / A conversion device, for example, a resistance string type, a resistance ladder type, a capacitance array type, a ΔΣ (delta sigma) type, a current source switch type (current source type), and the like are known.

When the resolution is N bits, the resistance string type takes the form of connecting 2 ^N- 1 resistance elements in series and connecting the necessary parts with an analog switch (see Patent Document 1). This resistance string type D / A conversion device has a demerit that the number of resistance elements increases exponentially as the resolution is increased.

Therefore, in the D / A conversion device shown in Patent Document 1, in order to deal with the problem that the layout pattern area becomes large in the resistance string type, the resistance element and the switching element are reduced by dividing the D / A conversion process into the number of stages, and the layout is performed. Ingenuity such as reducing the pattern area is shown. As described above, in the resistance string type D / A conversion device, there is a fundamental problem that the number of switching elements and resistance elements increases as the resolution bits increase, and the layout pattern area increases.

A D / A converter of the weight resistance type D / A converter type is shown in FIG. When making an n-bit D / A converter, this D / A converter is a resistor having a wide range of resistance values of R / 2 ^{n-1 to} R, and a resistor having twice the resistance value with high accuracy. Since it is necessary, it is not suitable for high-precision D / A conversion.

A ladder type (ladder type) D / A conversion device is shown in FIG. Since this type of D / A conversion device can be configured with only two types of resistance values, R and 2R, it has the characteristics of high accuracy, good temperature characteristics, and easy IC conversion. It is used in D / A conversion ICs.

In the conventional D / A conversion device for connecting the resistance elements as described above, there is a problem that the circuit scale becomes large because more resistance elements are required in order to increase the resolution. Further, the D / A conversion device has a problem that there is a great concern about accuracy deviation due to inconsistency of resistance elements. Furthermore, if it is desired to change the resolution, it is necessary to change the hardware such as changing or adding an element, and it is not possible to make a flexible change in terms of software.

On the other hand, Patent Document 2 discloses an improved ladder type (ladder type) D / A conversion device. The one disclosed in Patent Document 2 introduces a device for averaging the variation of each resistance element, and it is necessary to increase the resistance element as the resolution is increased, which affects the accuracy of D / A conversion. Is a problem.

Further, a current source switch (current source) type D / A conversion device is suitable for high-speed operation. This D / A conversion device employs a configuration in which weighted current sources (current sources) are arranged and converted into analog values by driving a switch according to an input digital value. A resolution of 8 to 16 bits and a sampling rate of about 1 G sample / sec can be obtained. However, there is a problem that the circuit scale and power consumption increase.

In addition, there is a delta-sigma type D / A conversion device for applications that require high resolution. This ΔΣ type D / A conversion device is a type that utilizes ΔΣ modulation, and can obtain a high resolution of 18 to 24 bits. However, there is a problem that the sampling speed is low.

As described above, each D / A conversion device has advantages and disadvantages, and it is necessary to use them properly depending on the application. FIG. 3 shows the features of each D / A conversion device.

As described above, the conventional commonly used resistance string type, resistance ladder type, and capacitance array type D / A conversion circuits are prepared by preparing a number of resistance elements or capacitance elements according to the resolution and using an operational amplifier. It is configured to perform addition and D / A conversion. Therefore, the higher the resolution, the larger the circuit scale because it is necessary to increase the number of resistance elements and capacitive elements, and there is a problem that the resolution accuracy is affected by the mismatch of the elements.

Japanese Unexamined Patent Publication No. 2009-005051 Japanese Unexamined Patent Publication No. 2012-23458

By the way, the inventor of the present application has filed an application for an A / D converter using a calculation of a tent map (Japanese Patent Application No. 2014-159978). This A / D converter is based on the following facts. For example, in a tent mapping with a slope of 2, a tent mapping operation is performed from a certain initial value, and when the mapping takes a value of 0.5 or more, bit "1" is acquired, and when it is less than 0.5, bit "0" is acquired. To do. Under such an agreement, the range of possible initial values is evenly divided, and when the initial value is started from within each of the above equally divided ranges and the bit value is acquired, the above gray code corresponding to each range is output. It is known (for example, "Hidetoshi Okutomi," About the nature of the initial value estimation method for pseudo-random bit strings obtained from tent maps, "published January 30, 2012, 2012 Cryptography and Information Security Symposium (SCIS2012). ), Proceedings CD-ROM [2F3-6] ").

From the A / D converter using the relationship between the tent map and the Gray code as described above, the inventor of the present application performs an operation of reversing the tent map based on the information of the Gray code as a digital value. It was concluded that a D / A converter can be obtained that derives an analog voltage value corresponding to the value X ₀ .

The present invention has been made by the research and efforts of the inventor of the present application as described above, and the purpose of the present invention is to reduce the number of required elements, reduce the concern about accuracy deterioration due to element variation, and reduce the circuit mounting area. It is an object of the present invention to provide a D / A conversion device capable of converting a digital value to an analog voltage value.

The D / A conversion device according to the present invention is an A / D that generates a Gray code at a predetermined stage according to the magnitude relationship between the calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. In a D / A conversion device that converts the gray code generated by the conversion into analog data,
Based on the Gray code generated for each operation, a control means for performing a function specifying process for specifying each function used when generating the Gray code, and
The first and second inverse calculation means, which performs an inverse calculation based on a function specified by the control means on the calculation result of each stage and performs an inverse calculation process for obtaining the calculation result of the previous stage. A second MOSFET transistor of the same size is connected in cascade, a source and a gate of the first MOSFET transistor are connected to supply power to the circuit to this source, and the gate of the second MOSFET transistor is used as an input. Inverse arithmetic means including an analog arithmetic circuit that obtains output from the connection point of the source and drain of two NMOS transistors, and
Equipped with
The control means sequentially specifies a function from the final stage to the first stage, and the inverse calculation means is a circuit that performs a calculation including the analog calculation circuit according to the specified function, or the analog calculation circuit. Switch whether to use a circuit that does not include
When the function is first specified by the control means, the inverse operation means performs the inverse operation of the first stage on the operation result of the final stage based on the specified function to obtain the inverse operation result of the previous stage. Then, when the function is next specified by the control means, the inverse operation of the second stage based on the specified function is applied to the inverse operation result of the first stage to obtain the inverse operation result of the previous stage. Then, the reverse calculation process is repeated in the same manner as described below, and the final result of the reverse calculation process is controlled to be output as analog data.

In the D / A conversion device according to the present invention, the control means is the nth (integer of 1 or more), n-1, ..., The nth, n-1, ... Obtained from the first-stage calculation. .. Generates the nth, n-1, ..., 1st stage gray code based on the 1st stage gray code generated from the 1st stage calculation result. The nth, n-1, ... Used when the first stage function is specified, the function specifying process is performed, and the inverse calculation means is the nth stage calculation result, n-1, ... The inverse calculation result of the first stage is obtained from the n-1, n-1, ... By the inverse calculation based on the first stage function, and the inverse calculation result of the first stage is obtained from the n-1, n-2, ... It is characterized in that it performs an inverse calculation process so as to obtain it.

In the D / A conversion device according to the present invention, when the tent mapping function is composed of N (two or more integers) functions, the inverse calculation means is opposite to the calculation by the N functions. The control means is composed of N inverse calculation circuits that perform the calculation of n (an integer of 1 or more), n-1, ..., The nth obtained from the calculation of the first stage. n-1, ... Based on the first-stage gray code generated from the first-stage calculation result, one of the N inverse calculation circuits is selected. , N-1, n-1, ... By applying the first-stage calculation result to the selected inverse calculation circuit, the first-stage calculation result is obtained. The number of calculations performed during the A / D conversion by inputting the first-stage calculation results to the N inverse calculation circuits. It is characterized in that a control means that repeatedly performs arithmetic control until n is configured, and the result of the finally obtained inverse arithmetic processing is output as analog data.

The D / A conversion device according to the present invention includes a switch for switching between the output of the N inverse arithmetic circuits as the final output and the feedback to the input of the N inverse arithmetic circuits, and the control means. By switching the switch, the operation is repeatedly controlled by the number of operations n performed during the A / D conversion.

In the D / A conversion device according to the present invention, the N inverse arithmetic circuits are cascade-connected in n stages, and the control means is any of the N inverse arithmetic circuits in the N inverse arithmetic circuits of each n stages. It is characterized in that it controls whether or not to select, and controls the transmission of signals between n stages.

In the D / A conversion device according to the present invention, the N inverse calculation circuits are cascaded in k (n = k × m: k, m is an integer) stage, and the N inverse calculation circuits in the kth stage are connected. The control means includes a switch for switching between the final output of the circuit and the feedback to the input of the N inverse arithmetic circuits in the first stage, and the control means has N inverse arithmetic in each k stage. By controlling whether to select any of the N inverse arithmetic circuits in the circuit and controlling the transmission of signals between k stages, and by switching the switch, the N pieces connected in cascade of the k stages. It is characterized in that control is performed so that m times of repetitive calculation are performed in the inverse calculation circuit of.

In the D / A conversion device according to the present invention, N is 2, one inverse arithmetic circuit is a circuit that calculates X _i = X _{i + 1/2} , and the other inverse arithmetic circuit is X _i = 1. It is characterized in that it is a circuit that performs a calculation of − (X _{i +} 1/2).

The D / A conversion device according to the present invention is characterized in that a sample hold amplifier or a capacitor is provided at the output ends of the N inverse arithmetic circuits.

The D / A conversion device according to the present invention generates a gray code by using an inequality of the magnitude relationship between the calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. In the D / A conversion device that converts the gray code generated by the above to analog data, the nth stage generated from the nth stage calculation result obtained from the operation of the nth (1 or more integer) stage. Based on the eye gray code, a function specifying process for specifying the nth stage function used when generating the nth stage gray code is performed, and the nth stage operation result is based on the nth stage function. By applying it to the inverse calculation, the n-1st stage calculation result is obtained, and based on the inequality that the nth stage calculation result should satisfy, the inequality that the n-1st stage calculation result should satisfy is obtained. The inequality detection process is performed, and then, based on the n-1st stage gray code generated from the n-1st stage calculation result obtained from the n-1th stage calculation, the n-1th stage is concerned. A function specifying process for specifying the n-1st stage function used when generating the stage gray code is performed, and the n-1th stage operation result is converted into an inverse operation based on the n-1th stage function. By applying this, the n-2nd stage calculation result is obtained, and the inequality detection process is performed so that the inequality that the n-1st stage calculation result should satisfy is obtained based on the inequality obtained in the inequality detection process. Then, the function identification process and the inequality detection process are repeated until the number of operations n performed during the A / D conversion is reached, and the value in the finally obtained inequality range is output as analog data. It is characterized by doing.

The D / A conversion device according to the present invention is generated by A / D conversion in which a gray code is generated according to the magnitude relationship between the calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. In the D / A conversion device that converts the gray code to be converted into analog data, the nth stage gray generated from the nth stage calculation result obtained from the operation of the nth (1 or more integer) stage. Based on the code, a function specifying process for specifying the nth stage function used when generating the nth stage Gray code is performed, and the nth stage calculation result is an inverse calculation based on the nth stage function. The inverse calculation process is performed so as to obtain the calculation result of the n-1st stage, and then the n-th generated from the calculation result of the n-1st stage obtained from the calculation of the n-1th stage. Based on the 1st stage Gray code, a function specifying process for specifying the n-1st stage function used when generating the n-1st stage Gray code is performed, and the n-1th stage calculation result is obtained. Inverse calculation processing is performed so that the n-2nd stage calculation result is obtained by the inverse calculation based on the n-1st stage function, and the number of operations n performed at the time of the A / D conversion is obtained below. It is characterized in that the function specifying process and the inverse operation process are repeated until the last obtained result of the inverse operation process is output as analog data.

In the D / A conversion device according to the present invention, one bit of Gray code is generated by the A / D conversion according to the magnitude relationship between the calculation result obtained by calculating the analog data by the tent mapping function and the predetermined threshold value. It is characterized by that.

The D / A conversion method according to the present invention is an A / D in which a gray code is generated at a predetermined stage according to the magnitude relationship between the calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. In the D / A conversion method for converting the gray code generated by the conversion into analog data, each function used when generating the gray code is specified based on the gray code generated for each operation. The control means that performs the function identification process and the first and second analog transistors of the same size are connected in series, and the source and gate of the first analog transistor are connected to supply power to the circuit to this source. It includes an analog arithmetic circuit in which the gate of the second NMOS transistor is used as an input and an output is obtained from the connection point between the source and drain of the two NMOS transistors, and the arithmetic result of each stage is controlled by the control means. Using an inverse calculation means that performs an inverse calculation based on the specified function and performs an inverse calculation process that obtains the calculation result of the previous stage, the control means sequentially performs the function from the final stage to the first stage. It is specified, and the inverse calculation means is switched between a circuit that performs an calculation including the analog calculation circuit and a circuit that performs a calculation that does not include the analog calculation circuit according to the specified function. When the function is first specified by the control means by the inverse calculation means, the inverse calculation of the first stage is applied to the calculation result of the final stage based on the specified function to obtain the inverse calculation result of the previous stage. When the function is next specified by the control means, the inverse operation of the second stage based on the specified function is applied to the inverse operation result of the first stage to obtain the inverse operation result of the previous stage. , The following is characterized in that the inverse calculation process is repeated in the same manner and the finally obtained result of the inverse calculation process is controlled to be output as analog data.

In the D / A conversion method according to the present invention, the control means is the nth (integer of 1 or more), n-1, ..., The nth, n-1, ... Obtained from the first-stage calculation. .. Generates the nth, n-1, ..., 1st stage gray code based on the 1st stage gray code generated from the 1st stage calculation result. The nth, n-1, ..., Used for the operation, the function specifying process for specifying the first-stage function is performed, and the inverse calculation means is the n, n-1, ... The first-stage calculation result is obtained by the inverse operation based on the first-stage function of the n-, n-1, ..., 1st-stage operation. It is characterized in that it performs inverse arithmetic processing.

The D / A conversion method according to the present invention is an A / D conversion in which a gray code is generated by using an inequality of the magnitude relationship between the calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. In the D / A conversion method for converting the gray code generated by the above into analog data, the nth stage generated from the nth stage calculation result obtained from the operation of the nth (1 or more integer) stage. Based on the eye gray code, a function specifying process for specifying the nth stage function used when generating the nth stage gray code is performed, and the nth stage operation result is based on the nth stage function. By applying it to the inverse calculation, the n-1st stage calculation result is obtained, and based on the inequality that the nth stage calculation result should satisfy, the inequality that the n-1st stage calculation result should satisfy is obtained. The inequality detection process is performed, and then, based on the n-1st stage gray code generated from the n-1st stage calculation result obtained from the n-1th stage calculation, the n-1th stage is concerned. A function specifying process for specifying the n-1st stage function used when generating the stage gray code is performed, and the n-1th stage operation result is converted into an inverse operation based on the n-1th stage function. By applying this, the n-2nd stage calculation result is obtained, and the inequality detection process is performed so that the inequality that the n-1st stage calculation result should satisfy is obtained based on the inequality obtained in the inequality detection process. Then, the function identification process and the inequality detection process are repeated until the number of operations n performed during the A / D conversion is reached, and the value in the finally obtained inequality range is output as analog data. It is characterized by doing.

The D / A conversion method according to the present invention is generated by A / D conversion in which a gray code is generated according to the magnitude relationship between the calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. In the D / A conversion method for converting the Gray code to analog data, the nth stage gray generated from the nth stage calculation result obtained from the operation of the nth (1 or more integer) stage. Based on the code, a function specifying process for specifying the nth stage function used when generating the nth stage Gray code is performed, and the nth stage calculation result is an inverse calculation based on the nth stage function. The inverse calculation process is performed so as to obtain the calculation result of the n-1st stage, and then the n-th generated from the calculation result of the n-1st stage obtained from the calculation of the n-1th stage. Based on the 1st stage Gray code, a function specifying process for specifying the n-1st stage function used when generating the n-1st stage Gray code is performed, and the n-1th stage calculation result is obtained. Inverse calculation processing is performed so that the n-2nd stage calculation result is obtained by the inverse calculation based on the n-1st stage function, and the number of operations n performed at the time of the A / D conversion is obtained below. It is characterized in that the function specifying process and the inverse operation process are repeated until the last obtained result of the inverse operation process is output as analog data.

According to the D / A conversion device according to the present invention, an accurate D / A conversion value can be obtained by a relatively simple calculation that traces back the tent map.

According to the D / A conversion device according to the present invention, the number of required elements can be reduced, the concern about accuracy deterioration due to element variation can be suppressed to a low level, and a small circuit mounting area can be used to convert a digital value to an analog voltage value. Conversion is possible.

The block diagram of the weight resistance type D / A converter type D / A conversion apparatus which concerns on a prior art example. The block diagram of the ladder type (ladder type) D / A conversion apparatus which concerns on a conventional example. The figure which described the feature of each D / A conversion apparatus which concerns on a prior art example. The figure which shows the return map by an example of a tent map. The figure which shows the time series graph of the calculation by the tent mapping shown in FIG. The figure which shows the range of the initial value X ₀ when the resolution is 4 bits in the tent map shown in FIG. The figure which shows the range of the initial value X ₀ of the tent map at the resolution 4 bit corresponding to FIG. 6, and the Gray code. The figure which shows the calculation process of the Gray code "0110" of the bit string for 4 bits generated from the tent map shown in FIG. The figure which shows the structure of the D / A conversion apparatus or D / A conversion method of 1st Embodiment which concerns on this invention. The figure which shows the structure of the D / A conversion apparatus or D / A conversion method of the 2nd Embodiment which concerns on this invention. The block diagram of the binary code / Gray code conversion circuit which can be used in the D / A conversion apparatus of this embodiment which concerns on this invention. The figure which shows the structure of the 3rd D / A conversion apparatus which concerns on this invention. The figure which shows the structure of the inverse calculation means used in the 3rd D / A conversion apparatus of this invention which concerns on this invention. The figure which shows the main part structure of the inverse arithmetic circuit used in the 3rd D / A conversion apparatus of this invention which concerns on this invention. The figure which shows the result of having performed DC analysis of the inverse calculation circuit of FIG. The figure which shows the structure of the D / A conversion apparatus of the 4th Embodiment of this invention which concerns on this invention. The waveform diagram of the result of simulating the operation of the 4th D / A conversion apparatus of this invention which concerns on this invention with a resolution of 4 bits. The block diagram of the D / A conversion apparatus which generates a gray code from the A / D conversion by a tent map, outputs an analog signal by the D / A conversion circuit which performs the inverse calculation from the gray code, and restores it. The figure which shows the main part structure of the D / A conversion apparatus of FIG. The waveform diagram of the result of simulating the operation of the D / A conversion apparatus of FIG. 18 with a resolution of 6 bits. The figure which shows the structure of the 5th D / A conversion apparatus which concerns on this invention. The figure which shows the structure of the 6th D / A conversion apparatus which concerns on this invention. The figure which shows the structure of the inverse calculation means used in the D / A conversion apparatus which concerns on embodiment of this invention. The waveform diagram of the result of simulating the operation of the D / A conversion apparatus configured by using the inverse calculation means of FIG. 23 with a resolution of 4 bits.

Hereinafter, embodiments of the D / A conversion device according to the present invention will be described with reference to the accompanying drawings. In each figure, the same components are designated by the same reference numerals, and duplicate description will be omitted.

principle

About the tent map An example of the tent map is defined by the following equation (1).
The return map of the above tent map is shown in FIG. 4, and a time series graph according to Eq. (1) with i on the horizontal axis and X _{i on} the vertical axis is shown in FIG.

A / D conversion by tent mapping

A / D conversion is possible by configuring the execution of equation (1) with an analog arithmetic circuit. As shown in FIG. 5, the digital value of the A / D conversion acquires bit “1” when the calculation result is 0.5 or more, and acquires bit “0” when the calculation result is less than 0.5. By continuously executing such bit acquisition, the gray code corresponding to the initial value X ₀ is output. As an example, in the case of a resolution of 4 bits, the gray code corresponding to the initial value X ₀ in each range from "circle 1" to "circle 16" shown in FIG. 6 is output with 4 bits as shown in FIG. Will be done. By binary-converting the output Gray code, a digital value that is regarded as a voltage value for sampling the initial value X ₀ can be obtained. Details of the A / D conversion circuit based on the tent map are shown in "Japanese Patent Application No. 2014-159978" according to the invention of the inventor of the present application.

Calculation method of initial value X0 range

Based on the above Gray code value output from the calculation of the tent map, the range of the initial value X ₀ can be obtained by tracing the map in reverse. In the present embodiment, as an example, it is assumed that the gray code of the bit string for 4 bits generated from the tent map is "0110". The calculation process of the tent map from the bit string acquired here is as shown in FIG.

It is assumed that the Gray code bit strings generated from the tent map are generated in order from the top as shown by the arrow on the right side in FIG. It can be seen that the mapping expression selected at that time is transitioning by always executing the expression on the “○” side represented by “○” and “×”. Considering from the final solution "X ₄ " of the tent map, the range of the map X _i is a closed interval [0, 1], so it is always included in any of the ranges of "0 ≤ X ₄ ≤ 1".

That is, in the A / D conversion, the gray code is generated by using the inequality of the magnitude relation between the calculation result obtained by performing the calculation by the tent mapping function on the analog data and the predetermined threshold value. Then, the D / A conversion device of the present embodiment converts the Gray code generated by the A / D conversion into analog data.

Since the gray code bit string of the expression (function) that generated "X ₄ " is "0", it is specified that the function "X ₄ = 2X ₃ " is being executed, and which is "X ₃ "? Is it a range, or if you get an inequality,
Therefore, it can be seen that "X ₃ " is always calculated from this range.

Next, when considering "X ₃ ", it can be seen that the function "X ₃ = 2 (1-X ₂ )" is selected because the bit string of the Gray code is "1". Substituting this into the inequality "0 ≤ X ₃ ≤ 0.5"
Therefore, the range of "X ₂ " can be narrowed down.

Similarly, since the bit string of the next Gray code is "1", it is specified that the function "X ₂ = 2 (1-X ₁ )" is selected, and the range of "X ₁ " is
Will be.

Finally, in the range of the initial value "X ₀ ", it is specified that the function "X ₁ = 2X ₀ " is selected from the gray code bit string "0", and the range of "X ₀ " is
Will be.

From the above, it can be seen that the initial value "X ₀ " started from any of the range of 0.25 to 0.3125, which corresponds to the range of "circle 5" in FIG. 7, and the initial value within this range. For the value "X ₀ ", it is shown that "0110" is always obtained by executing the tent mapping equation (1) and generating the Gray code. Strictly speaking, the boundary of the initial value X ₀ does not include the upper limit value, and “0.25 ≦ X ₀ <0.3125” as shown in FIG. 7 “Circle 5”. As a D / A conversion device, the values in the range of the inequality will be output as analog data.

As described above, the D / A conversion device of the first embodiment first obtains the nth stage obtained from the calculation of the nth stage (an integer of 1 or more, which is 4 in this embodiment). Based on the nth stage Gray code generated from the result of the eye calculation, a function specifying process (A1 in FIG. 9) for specifying the nth stage function used when generating the nth stage Gray code is performed.

Next, by applying the nth stage operation result to the inverse operation based on the nth stage function, the n-1st stage operation result is obtained, and the inequality that the nth stage operation result should satisfy is obtained. Based on this, an inequality detection process (A2 in FIG. 9) is performed so that the inequality to be satisfied by the calculation result of the first stage n-1 is obtained.

Next, the n-1st stage gray code is generated based on the n-1th stage gray code generated from the n-1th stage calculation result obtained from the n-1th stage calculation. The function specifying process (A3 in FIG. 9) for specifying the n-1st stage function used in the case is performed.

Further, by applying the n-1st stage calculation result to the inverse calculation based on the n-1th stage function, the n-2nd stage calculation result is obtained, and the inequality obtained in the inequality detection process is obtained. Based on the above, the inequality detection process (A4 in FIG. 9) is performed so that the inequality to be satisfied by the calculation result of the first stage n-1 is obtained.

Hereinafter, the function identification process and the inequality detection process are repeated until the number of operations n performed during the above A / D conversion is reached, and the value in the finally obtained inequality range is output as analog data (Fig.). 9 A5).

The above embodiment will be described as an embodiment based on the idea of inverse operation of the mapping function of the equation (1). When these are formulas the image back in mapping of the formula (1), the bit sequence of Gray code _{{b 0, b 1, ...} , b i, ..., b n-1} as, expressed by the following equation (2) it can.

Here, the number of bits of the Gray code is n, because the minimum and maximum values of _{"X n"} is initiated from the _{"0 ≦ X n ≦ 1"} , the first (i = n-1), the inequality ""the right side of _the" X _n "and the left side _{is" X} n = 1 can be calculated as a range of minimum and maximum values for "finally Yuki performed as computed _{separately" X n = 0 X 0 "} .

When considering that the calculation of equation (2) is performed by an analog calculation circuit as D / A conversion, if the intermediate value between the final minimum value and maximum value of "X ₀ " is output, the analog after D / A conversion It can be a voltage value, but if you start with "0.5", which is an intermediate value between the maximum value "1.0" and the minimum value "0.0", you can obtain an intermediate value without performing separate calculations. be able to.

In the present embodiment, considering “0110” for 4 bits of the gray code bit string,
Starting from "X ₄ = 0.5", the function "X ₄ = 2X ₃ " is executed from the information of the gray code bit string "0", so "X ₃ " is
Will be.

Next, when considering "X ₃ ", it can be seen from the information of the gray code bit string "1" that the function "X ₃ = 2 (1-X ₂ )" is selected, so this is "X ₃ = 0". By substituting for .25 "
Will be.

Hereinafter, in the same manner, since it is known that the function “X ₂ = 2 (1-X ₁ )” is selected because of the gray code bit string “1”, “X ₁ ” is
Will be.

Finally, since it can be seen that the function "X ₁ = 2X ₀ " is selected from the gray code bit string "0", the initial value "X ₀ " is
It can be confirmed that the value is an intermediate value of the solution “0.25 ≦ X ₀ ≦ 0.3125” in the range of the initial value “X ₀ ”.

The processing of the equation (2) can be output as an analog voltage value by constructing an analog arithmetic circuit based on the Gray code as a digital value.

As is clear from the above description, the D / A conversion device according to the present embodiment is a D / A conversion device that converts a Gray code into analog data. The Gray code can be generated by A / D conversion in which the Gray code is generated according to the magnitude relationship between the calculation result obtained by performing the calculation by the tent mapping function on the analog data and the predetermined threshold value. The D / A conversion device according to the present embodiment is a D / A conversion device that converts the Gray code into analog data, and is configured as follows.

First, the D / A conversion device according to the present embodiment is based on the nth stage Gray code generated from the nth stage calculation result obtained from the operation of the nth stage (integer of 1 or more). A function specifying process (A11 in FIG. 10) for specifying the nth stage function used when generating the nth stage Gray code is performed.

Next, an inverse calculation process (A12 in FIG. 10) is performed so that the nth stage calculation result is obtained by the inverse calculation based on the nth stage function to obtain the n-1th stage calculation result.

Next, the n-1st stage gray code is generated based on the n-1th stage gray code generated from the n-1th stage calculation result obtained from the n-1th stage calculation. A function specifying process (A13 in FIG. 10) for specifying the n-1st stage function used in the case is performed.

Further, an inverse calculation process (A14 in FIG. 10) is performed so that the n-1st stage calculation result is obtained by the inverse calculation based on the n-1th stage function to obtain the n-2nd stage calculation result.

Hereinafter, the function specifying process and the inverse operation process are repeated until the number of operations performed during the A / D conversion is n, and the finally obtained result of the inverse operation process is output as analog data (Fig.). 10 A15).

When the digital value to be D / A converted is a binary code, the binary code of the digital value to be converted may be converted to Gray code, and then the procedure of the equation (2) may be performed.

The Gray code can be obtained by converting the binary code by the following equation (3). Here, the digital value "b" is a binary bit string.
Equation (3) is realized by the B / G conversion circuit 10 of FIG. The B / G conversion circuit 10 that converts a binary code into a Gray code is provided in front of A1 in FIG. 9, and is provided in front of A11 in FIG.

Next, FIG. 12 shows a configuration diagram of a D / A conversion device according to a third embodiment using an inverse calculation circuit that realizes the equation (2). The D / A conversion device of this embodiment has a control means 40 that performs a function specifying process and an inverse calculation means 20 that performs an inverse calculation process as main components. In the present embodiment, the output of the B / G conversion circuit 10 shown in FIG. 11 is connected to the Gray code input terminal 13 of the control means 40, but the gray code is obtained from the circuit performing the processing using the Gray code. The B / G conversion circuit 10 is unnecessary if the configuration directly captures.

This D / A conversion device is generated by the A / D conversion in which a gray code is generated according to the magnitude relationship between the calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. Convert Gray code to analog data.

The control means 40 is generated from the first-stage calculation results of the nth n (integer of 1 or more), n-1, ... Nth, n-1, ... Based on the first-stage Gray code, the nth, n-1, ..., Nth, n-1 used to generate the first-stage Gray code. , ... Performs a function specifying process for specifying the first-stage function.

The inverse calculation means 20 obtains the first-stage calculation results of the n-, n-1, ..., The first-stage calculation result by the inverse calculation based on the first-stage function, n-1, ... n-2, ... Performs an inverse calculation process for obtaining the first-stage calculation result.

When the control means 40 performs the process based on the nth stage gray code, the control means 40 specifies the nth stage function, and the nth stage operation result is the n-1th stage n-1 by the inverse operation based on the nth stage function. The inverse calculation means is controlled so as to obtain the calculation result of the first stage, and when the processing is based on the gray code of the n-1th stage, the function of the n-1th stage is specified and the calculation result of the n-1th stage is described above. The inverse operation means is controlled so as to obtain the n-2nd stage operation result by the inverse operation based on the n-1st stage function, and hereinafter, the number of operations n performed at the time of the A / D conversion is defined as Until then, the control of the function specifying process and the inverse operation process is repeated, and the finally obtained result of the inverse operation process is controlled to be output as analog data.

FIG. 13 shows a specific configuration of the inverse calculation means 20. The inverse calculation means 20 is composed of N inverse calculation circuits that perform an operation opposite to the operation by the above N functions when the tent mapping function is composed of N (integer of 2 or more) functions. To. Since the inverse calculation means 20 realizes the equation (2), N = 2.

But Gray code is "1" or _"0", since the calculation of _{"X i +} 1/2" is always performed, employs a configuration which divides in half the voltage level _{"X i + 1"} by the resistance element R1, R2, This part is the first inverse calculation circuit. Since the maximum voltage level “X _{i + 1} ” is 1.0 [V], it always becomes “(X _{i + 1/2)} ≦ 0.5” after the voltage is divided by the resistance element.

When the gray code is "1", "1- (X _{i +} 1/2)" is selected, so that the resistance elements R1 and R2 are half of the voltage level "X _{i + 1} " [V]. A circuit for subtracting the voltage value "X _{i +} 1/2" divided into two is performed by an inverse arithmetic circuit 21 composed of two NMOS transistors. This part is the second inverse calculation circuit.

As shown in FIG. 14, the inverse operation circuit 21 is composed of NMOS transistors 22a and 22b connected by diodes with NMOS transistors of the same size. When the voltage value at the connection between the gate and the source of the NMOS transistor 22a is Vgs, the voltage level of the output Vout is relative to the Vin and Vs of the NMOS transistor 22b whose gate is connected to Vin and whose source is connected to Vs. , "Vout = Vgs-Vin + Vs (however, Vin≤Vgs / 2)".

FIG. 15 shows the result of DC analysis of the inverse arithmetic circuit 21 composed of the two NMOS transistors 22a and 22b of FIG. FIG. 15 shows the voltage level of Vout when Vin is changed from 0.0 [V] to 1.0 [V]. In the range of "Vin ≤ Vgs / 2 (= 0.5 [V])" (static characteristic pentode (saturated) region of the NMOS transistors 22a and 22b), Vout is Vin at 0.5 [V]. The voltage level of is linearly subtracted from Vgs = 1.0 [V]. The voltage conditions for DC analysis are Vgs = 1.0 [V] and Vs = 0.0 [V].

As shown in FIG. 13, the connection points of the resistance elements R1 and R2 are connected to the non-inverting terminal of the sample hold amplifier 23 via the switch SW0. Further, the output terminal Vout of the inverse calculation circuit 21 is connected to the non-inverting terminal of the sample hold amplifier 23 via the switch SW1. The switches SW0 and SW1 are on / off controlled by the control means 40 that specifies the function based on the Gray code. That is, when the gray coat is "0", the switch SW0 is in the on (conducting) state and the switch SW1 is in the off (disconnecting) state. When the Gray code is "1", the switch SW0 is turned off (disconnected) and the switch SW1 is turned on (conducted). As a result, the equation (2) is executed once by the analog operation according to the Gray code.

In this way, the gray code generated by the A / D conversion in which the gray code is generated in a predetermined stage according to the magnitude relationship between the calculation result obtained by performing the calculation of the analog data by the tent mapping function and the predetermined threshold value. It is a D / A conversion device that converts a code into analog data. The control means 40 performs a function specifying process for specifying each function used when generating the Gray code based on the Gray code generated for each operation by the tent mapping function when performing A / D conversion. Do. Further, the inverse calculation means 20 performs an inverse calculation based on the function specified by the control means on the calculation result of each of the above stages, and performs an inverse calculation process for obtaining the calculation result of the previous stage.

The level of the voltage value output via the switch SW0 or the switch SW1 is stored in the sample hold amplifier 23, and is input to the same circuit as in FIG. 13 again to perform the iterative calculation of the equation (2). That is, the control of the function specifying process and the inverse operation process is repeated until the number of operations n performed during the A / D conversion is reached. The repetition of the number of operations n means that the calculation is performed for the resolution, and finally the sample hold amplifier 23 is output as the analog voltage of the D / A conversion result.

In other words, the control means 40 sequentially specifies the function from the final stage to the first stage, and the inverse calculation means 20 is specified when the function is first specified by the control means 40. Based on the function, the inverse operation of the first stage is applied to the operation result of the final stage to obtain the inverse operation result of the previous stage, and then the function is specified next by the control means 40. The inverse operation of the second stage based on the function is applied to the inverse operation result of the first stage to obtain the inverse operation result of the previous stage, and the inverse operation process is repeated in the same manner as follows, and finally obtained. Control so that the result of the inverse operation processing is output as analog data.

FIG. 16 shows the configuration of the D / A conversion device 100 according to the fourth embodiment. The D / A conversion device 100 is an iterative device that performs the calculation of the equation (2) once in synchronization with one clock. The D / A conversion device 100 includes switches SWnext and SWout for switching between the final output of the output of the N inverse arithmetic circuits and the feedback to the input of the N inverse arithmetic circuits, and the control thereof. By switching the switches SWnext and SWout, the control circuit 41 of the means 40 repeatedly performs arithmetic control by the number of arithmetic operations n performed during the A / D conversion.

A sample hold amplifier 42 is provided in the feedback path. A steady-state voltage of 0.5 V is applied to the non-inverting terminal of the sample hold amplifier 42 via the switch SWin. The control circuit 41 of the control means 40 controls the switch SWin on and off. The iterative D / A conversion device 100 performs one D / A conversion process by giving the number of clock pulses corresponding to the resolution from the control circuit 41. With only one inverse calculation means 20 shown in FIG. 13, the result of one calculation is given as an input voltage again and the calculation is repeated, and the number of times for the resolution (the number of calculations performed during the A / D conversion n). ) Is calculated and finally output as an analog voltage.

At the start of the calculation, the switch SWin is turned on, 0.5 [V] is given to the sample hold amplifier 42, and the voltage value is held. Next, when the clock CLK gray is given from the control circuit 41 in the High state, the function identification process becomes possible, and the switch SW0 or the switch SW1 in FIG. 13 is turned on via the AND circuit according to the information of the first Gray code. The calculation of the equation (2) is performed by the inverse calculation means 20, and the inverse calculation result is held as a voltage value in the sample hold amplifier 23 of FIG. This voltage value becomes the output “X _i ” in FIG. 16, and when the Gray code is “0”, the function of the equation (2) is “X _{i +} 1/2”, and the calculation result is 0.25 [V]. It becomes.

FIG. 17 shows the waveform of the result of simulating the D / A conversion with a resolution of 4 bits in the configuration of the D / A conversion device 100. The signal Gray shown in FIG. 16 is shown as the value in the top column in FIG. That is, it indicates that the Gray code is serially input as the digital value to be D / A converted. A calculation result obtained by the calculation of the first stage 0.25 [V], in the waveform of FIG. 17 are shown as X _i.

Next, the clock CLKgray is output from the control circuit 41 in the Low state, and after a slight time difference between the switch SW0 and the switch SW1 being turned off, the High signal CLKnext is given to the switch SWnext to turn it on. At this time, the signal CLKin that controls the switch SWin is Low, and the switch SWin is in the off state. As a result, 0.25 [V] is transferred and held to the sample hold amplifier 42 of FIG.

The clock CLK gray is set to the High state again, and the switch SW0 and the switch SW1 are controlled via the AND circuit according to the information of the next Gray code. Here, since the Gray code is "1", the inverse operation circuit 21 that calculates the function "1- (X _{i +} 1/2)" of the equation (2) is selected, the inverse operation is performed, and the calculation result is used. A certain voltage value of 0.875 [V] is held by the sample hold amplifier 23 of FIG.

Further, the control signal CLKnext for the switch SWnext is set to High, the switch SWnext is turned on, and the voltage value held by the sample hold amplifier 23 is transferred to the sample hold amplifier 42 of FIG. By repeating such an operation, the desired number of resolution bits (the number of operations n performed during A / D conversion) is calculated, and finally the control signal CLKout for the switch SWout is set to High to switch. An analog voltage is output when SWout is turned on.

As shown in the waveform of FIG. 17, when the control signal CLKout is output to the switch SWout in the High state and at the same time the control signal CLKin to the switch SWin is also set to the High state, the sample hold amplifier 42 shown in FIG. The initial voltage value of 0.5 [V] for performing the calculation of the equation (2), which is the round of the above, is set, and the process as described above is repeated again from here to proceed with the D / A conversion.

FIG. 17 shows the processing of two samples. In the first round, the gray code string “0110” is processed, and in the second round, the gray code string “1101” is processed. The voltage levels "0.28125 [V]" and "0.84375 [V]" corresponding to the initial value X ₀ of the tent map, which are the calculation results, are output, respectively. For the simulation, "LTspice IV" provided by Linear Technology Co., Ltd., which is known as a free analog circuit simulator, was used.

FIG. 17 shows the detailed flow of the iterative D / A conversion, but in order to further verify it globally, a Gray code is generated from the A / D conversion by the tent mapping from the voltage level of the analog input signal, and the gray code is generated. A simulation was performed with a resolution of 6 bits to output an analog signal by a D / A converter that performs the calculation of equation (2) from the code and restore it. The circuit diagram used for this simulation is shown in FIG. 18, and the simulation result waveform is shown in FIG.

The circuit of FIG. 18 holds an analog signal in the sample hold amplifier 3 and sends the held analog signal to a tent mapping calculation circuit 4-0 to 4-4 and a comparator 5 connected in a 5-stage cascade, and is a batch type circuit. A gray code is obtained by performing A / D conversion in the configuration. Further, this circuit includes an A / D conversion unit that stores the Gray code obtained in the above in the register (D-FF) groups 6-0 to 6-5. Each of the tent mapping calculation circuits 4-0 to 4-4 adopts the configuration shown in FIG. The tent mapping calculation circuit shown in FIG. 19 is shown in FIG. 18 of Japanese Patent Application No. 2014-159978, and detailed description thereof will be omitted here.

The Gray code held in the register (D-FF) group 6-0 to 6-5 is sent to the AND circuit 7-0 to 7-5 of the parallel / serial conversion unit 8. A high control signal is given from the control circuit 9 to the AND circuits 7-0 to 7-5, and the gray code is serially taken out by the or circuit 8A and given to the iterative D / A converter 100 shown in FIG. It is composed. The control circuit 9 sends a high control signal to the AND circuits 7-0 to 7-5 in order of one pulse each so as to synchronize with the clock CLK gray of the control circuit 41 shown in FIG.

Every time a pulse is generated in the clock CLKtent of FIG. 18, A / D conversion corresponding to the analog voltage value is collectively performed at the same time as sampling the analog signal to generate a Gray code. As shown in FIG. 20, a gray code corresponding to the voltage level of the input analog signal is generated in synchronization with the clock CLKtent and stored in the register (D-FF) group 6-0 to 6-5. V (q0) to V (q5) in FIG. 20 correspond to the output signals Q0 to Q5 of the register (D-FF) group 6-0 to 6-5 in FIG. The Gray code stored in the register (D-FF) groups 6-0 to 6-5 is continuously converted into a single row of Gray code signals by the parallel / serial conversion unit 8 and sent to the D / A conversion device 100. By being transmitted, the calculation of equation (2) is performed with a resolution of 6 bits, and the analog voltage level is output.

In the above processing process, the Gray code generated by the tent map A / D conversion is held in the register (D-FF) group 6-0 to 6-5 of FIG. 18 in the order of generation, and is output serially. At the time of this output, the output values Q5 to Q4 ⇒ Q3 ⇒ Q2 ⇒ Q1 ⇒ Q0 of the register (D-FF) group 6-5 to 6-0 are given to the D / A converter 100 in this order, and the initial value X _0. Is required. That is, the data processing order in the register (D-FF) groups 6-0 to 6-5 takes the form of LIFO (Last In First Out).

As shown in FIG. 20, the analog signal V (ain) input to the A / D converter by a sine wave is returned to the original analog voltage level V (out) by the D / A converter 100 and output. .. The waveform of the output analog signal V (out) is rattling in a rectangular shape, but this waveform should be made smooth by filtering with a smoothing circuit as is done with a general D / A converter. Can be done.

As a merit, the fourth embodiment described above is arbitrary without increasing the number of elements by preparing one inverse calculation means 20 which is the calculation circuit of FIG. 13 for the iterative calculation of the equation (2) and using it repeatedly. D / A conversion for the digital bit length of is possible. For this reason, it is a method suitable for miniaturization, and because it is configured to perform calculations many times using the same element, unlike a D / A conversion device using a large number of different elements, the calculation accuracy depends on the inconsistency of each element. It can be expected that the concern can be lowered and the calculation accuracy can be kept high.

Next, as a fifth embodiment, a batch type D / A conversion device is shown in FIG. The D / A conversion device according to the present embodiment is configured by cascading the inverse arithmetic means 20 shown in FIG. 13 in series in a number corresponding to the required resolution, and each of them is the same as the inverse arithmetic means 20. Inverse calculation means 20-1 to 20-4 having a configuration are provided. Further, each of the inverse calculation means 20-1 to 20-4 is provided with a circuit composed of two AND circuits and an inverter in the control means 40, and these are controlled by the control circuit 41A, as shown in FIG. The function of the control means 40 (function specific function) is realized. This D / A conversion device can realize D / A conversion at a higher speed than the iterative D / A conversion device shown as the fourth embodiment.

In the D / A conversion device according to the fifth embodiment, when the synchronization signal GCTRL is output as the High level from the control circuit 41A, the gray code information to be D / A converted is the two AND circuits and the inverter. A logical operation is performed by a circuit composed of. The result of the logical operation is transmitted as an on / off control signal in parallel to the switch SW0 and the switch SW1 corresponding to the inverse operation means 20-1 to 20-4, respectively. The inverse calculation means 20-1 to 20-4 perform the calculation of the equation (2) on the signal sent from the previous stage. As a result, the required resolution is calculated in a batch. After this calculation, the control circuit 41A outputs a control signal for the switch SWOUT as a high level. As a result, the analog voltage level generated by the inverse calculation means 20-4 in the final stage is output, and D / A conversion is performed with one clock pulse. Although the number of elements is increased as compared with the iterative D / A conversion device, there is an advantage that D / A conversion can be performed at high speed.

Next, FIG. 22 shows a D / A conversion device according to a combination of an iterative type and a batch type as a sixth embodiment. The D / A conversion device according to the present embodiment is configured by cascading the inverse arithmetic means 20 shown in FIG. 13 in series by the required number (2 in this case), and the inverse arithmetic means 20-1 and 20. -2 is provided. Further, each of the inverse calculation means 20-1 and 20-2 is provided with a circuit having the same function as that of FIG. 21 composed of two AND circuits and an inverter, and these are controlled by the control circuit 41B. The function of the control means 40 shown in 16 is realized.

Further, a path for feeding back the output signal _{X i} of the inverse calculation unit 20-2 as the input signal _{X i + 1} of the first-stage reverse calculation means 20-1. The feedback in the path, the sample and hold amplifier 25 for feedback to hold the output signal X _i of the inverse calculation unit 20-2 are provided. Between the output of the inverse calculation means 20-2 and the sample hold amplifier 25, switches SWnext and SWout for selecting whether to feed back or output as an analog signal of the D / A conversion result of a predetermined resolution are provided, and these switches are provided. SWnext and SWout are on / off controlled by the control circuit 41B.

In this embodiment, in general, N inverse arithmetic circuits are connected in an n-stage cascade, and the control means connects any of the N inverse arithmetic circuits in the N inverse arithmetic circuits of each n stages. It controls whether to select and controls the transmission of signals between n stages. In this embodiment, 2-bit D / A conversion is performed with one clock pulse. In the iterative type, four clock pulses are required for D / A conversion with a resolution of 4 bits, whereas in the present embodiment in which two are cascaded, the number of clock pulses is only two. Therefore, there is an advantage that the response time (latency) becomes faster. In the D / A conversion device of the present embodiment in which the iterative type and the batch type are combined in this way, a trade-off configuration that can be matched with the circuit area and the conversion speed can be selected.

The inverse calculation means 20 shown in FIG. 13 has a configuration in which the result of the equation (2) is given to the sample hold amplifier 23 to hold the voltage level. On the other hand, as shown in FIG. 23, the sample hold amplifier 23 that holds the voltage level can be replaced with the inverse calculation means 20A of the type that holds the voltage level in the capacitor 28.

FIG. 24 shows the result of simulating the inverse calculation means 20 of FIG. 16 with the reverse calculation means 20A of FIG. 23 and the same gray code (digital value) pattern as shown in FIG.

Since the capacitor causes charge leakage with the passage of time, in the inverse calculation means 20A of FIG. 23, switching of the switching element in consideration of the CR (capacitance / resistance) time constant and charge leakage, or a substitute for the sample hold amplifier 23. The capacitance of the capacitor 28 to be used is increased, and the other capacitors are tuned to reduce the capacitance in order to reduce the influence. In the simulation, the capacitance of the capacitor Cout in FIG. 16 is 20f [F], and the capacitance of the capacitor Csample is 0.5p [F]. Here, f is a femto ( ^10-15 ) and p is a pico ( ^10-12 ).

The inverse calculation means 20A having a configuration in which the sample hold amplifier 23 is replaced with a capacitor 28 as shown in FIG. 23 has lower D / A conversion accuracy than the configuration in which the sample hold amplifier 23 holds the voltage level as shown in FIG. There are disadvantages such as. However, since the inverse calculation means 20A having this configuration does not need to use the sample hold amplifier 23, it has an advantage that the circuit configuration can be simplified and the circuit area can be reduced.

A repetitive D / A conversion device that realizes D / A conversion by executing the above-described equation (2) repeats with a fixed number of elements without preparing a plurality of resistance elements or capacitive elements having a predetermined value. Since D / A conversion can be performed by changing the resolution by increasing the number of times, a D / A conversion device having high resolution can be realized even with a small circuit area. Further, since the circuit is repeatedly used with resistors and transistors under the same physical conditions, highly accurate D / A conversion can be expected with little influence of element variation.

In the conventional D / A conversion device, if it is desired to change the resolution, it is necessary to change the hardware such as changing or adding an element, whereas in the D / A conversion device according to the present embodiment, the element Since no change is required, it can be changed flexibly by a soft method of controlling the number of iterations.

Since the D / A conversion device according to the present embodiment has a configuration for D / A conversion of the Gray code, when it is applied to a system or the like that adopts the Gray code as digital data and performs processing, the binary conversion is performed. There is an advantage that D / A conversion can be performed without increasing the circuit scale because no configuration is required.

When it is desired to generate the intermediate potential required in analog circuit design, there is a scene in which a resistance string type voltage is divided to generate a desired reference voltage and supplied to the analog circuit. The D / A conversion device according to the present embodiment is suitable for such a scene because a reference voltage can be generated with a desired resolution by applying a control pulse from a control circuit using the minimum necessary elements.

In the embodiment shown above, the tent map is shown in FIG. 4, but the present invention is not limited to this. For example, it is also applicable when a tent map as shown in FIG. 14 of Japanese Patent Application No. 2014-159978 is used. In this case, the function is specified based on the 2-bit gray code in one operation, and the tent mapping function is composed of four functions, which is the opposite of the operation by the above four functions. The inverse arithmetic means is configured by the four inverse arithmetic circuits that perform the above.

3 Sample hold amplifier 4-0-4-4 Tent mapping calculation circuit 5 Comparator 6-0-6-5 Register (D-FF) group 7-0-7-5 AND circuit 8 Parallel / serial converter 8A Or circuit 9 Control circuit 10 B / G conversion circuit 20, 20A Inverse calculation means 21 Inverse calculation circuit 23, 25 Sample hold amplifier 40 Control means 41, 41A, 41B Control circuit 42 Sample hold amplifier 100 D / A conversion device

Claims (13)

The gray code generated by the A / D conversion in which the gray code is generated in a predetermined stage according to the magnitude relationship between the calculation result obtained by performing the calculation of the analog data by the tent mapping function and the predetermined threshold is analog. In the D / A conversion device that converts data
Based on the Gray code generated for each operation, a control means for performing a function specifying process for specifying each function used when generating the Gray code, and
The first and second inverse calculation means, which performs an inverse calculation based on a function specified by the control means on the calculation result of each stage and performs an inverse calculation process for obtaining the calculation result of the previous stage. A second MOSFET transistor of the same size is connected in cascade, a source and a gate of the first MOSFET transistor are connected to supply power to the circuit to this source, and the gate of the second MOSFET transistor is used as an input. Inverse arithmetic means including an analog arithmetic circuit that obtains output from the connection point of the source and drain of two NMOS transistors, and
Equipped with
The control means sequentially specifies a function in each stage of the operation from the final stage operation to the first stage operation, and the inverse calculation means performs the A / D conversion of the stage according to the specified function . When the generated gray code is 1, control is performed so as to realize a circuit that performs an operation including the analog arithmetic circuit, and when the generated gray code is 0, an operation that does not include the analog arithmetic circuit. It controls to realize the circuit that performs
When the function is first specified by the control means, the inverse operation means performs the inverse operation of the first stage on the operation result of the final stage based on the specified function to obtain the inverse operation result of the previous stage. Then, when the function is next specified by the control means, the inverse operation of the second stage based on the specified function is applied to the inverse operation result of the first stage to obtain the inverse operation result of the previous stage. Te, and so repeat the inverse operation processing, and finally the results of the inverse processing to operate to output the analog data D / a converter according to claim. The control means is generated from the first-stage calculation results of the n-th (integer of 1 or more), n-1, ... Nth, n-1, ... Based on the first-stage Gray code, the nth, n-1, ..., Nth, n-1 used to generate the first-stage Gray code. , ... Performs function identification processing to specify the first stage function,
The inverse calculation means performs an inverse calculation based on the nth-stage calculation result, n-1, ..., The first-stage inverse calculation result, and the n-th, n-1, ..., 1st-stage function. The D / A conversion device according to claim 1, wherein the inverse calculation process is performed so as to obtain the first-stage inverse calculation result. When the tent mapping function is composed of N (integer of 2 or more) functions, the inverse calculation means is provided by N inverse calculation circuits that perform operations opposite to those by the N functions. It is composed and
The control means is generated from the results of the first-stage calculation of n, n-1, ..., Obtained from the first-stage calculation of n (an integer of 1 or more), n-1, ... N, n-1, ..., 1st stage Based on the gray code, any one of the N inverse arithmetic circuits is selected, and the n, n-1, ..., 1st stage By applying the calculation result to the selected inverse calculation circuit, the first-stage calculation results are controlled to be obtained, and the n-1, n-2, ... ..., A control means is configured which inputs the first-stage calculation result to the N inverse calculation circuits and repeatedly performs calculation control until the number of calculations performed during the A / D conversion is n.
The D / A conversion device according to claim 2, wherein the finally obtained result of the inverse arithmetic processing is output as analog data. It is provided with a switch for switching between the output of the N inverse arithmetic circuits as the final output and the feedback to the input of the N inverse arithmetic circuits.
The D / A conversion device according to claim 3, wherein the control means repeatedly performs operation control by the number of operations n performed during the A / D conversion by switching the switch. The N inverse arithmetic circuits are connected in an n-stage cascade,
The control means is characterized in that it controls whether to select any of the N inverse arithmetic circuits in each of the n inverse arithmetic circuits and controls the transmission of signals between the n stages. The D / A conversion device according to claim 3. The N inverse arithmetic circuits are connected in a k (n = k × m: k, m is an integer) stage cascade.
It is provided with a switch for switching between the output of the N inverse arithmetic circuits in the kth stage as the final output and the feedback to the input of the N inverse arithmetic circuits in the first stage.
The control means controls whether to select any of the N inverse arithmetic circuits in each k-stage N inverse arithmetic circuits, controls the transmission of signals between the k-stages, and controls the switch. The D / A conversion device according to claim 3, wherein the D / A conversion device is controlled so that m times of repetitive calculation are performed in the N inverse calculation circuits connected in a k-stage cascade by switching. N is 2
One inverse operation circuit is a circuit that calculates Xi = Xi + 1/2.
The D / A conversion device according to any one of claims 3 to 5, wherein the other inverse calculation circuit is a circuit that performs calculation of Xi = 1- (Xi + 1/2). The D / A conversion device according to any one of claims 3 to 6, wherein a sample hold amplifier or a capacitor is provided at the output terminal of the N inverse arithmetic circuits. The gray code generated by the A / D conversion that generates the gray code according to the magnitude relationship between the calculation result obtained by performing the calculation by the tent mapping function and the predetermined threshold value is converted into analog data. In the D / A conversion device
The nth stage gray code used when generating the nth stage gray code based on the nth stage gray code generated from the nth stage calculation result obtained from the operation of the nth stage (integer of 1 or more). Perform function identification processing to specify the nth stage function,
An inverse calculation process is performed so that the nth stage calculation result is obtained by the inverse calculation based on the nth stage function to obtain the n-1th stage calculation result.
Next, the n-1st stage gray code is generated based on the n-1th stage gray code generated from the n-1th stage calculation result obtained from the n-1th stage calculation. Perform the function identification process to specify the n-1st stage function used in the case,
An inverse calculation process is performed so that the n-1st stage calculation result is obtained by the inverse calculation based on the n-1st stage function to obtain the n-2nd stage calculation result.
Hereinafter, the until operation number n performed in the A / D conversion, by repeating the functions specific processing and reverse processing, and outputs the result of the finally obtained inverse operation processing as analog data D / A converter,
In the inverse calculation process of each stage from the nth stage to the n-1 stage, ..., The calculation result of each stage is subjected to an inverse calculation based on the function specified by the control means. It is an inverse arithmetic means that performs inverse arithmetic processing to obtain the arithmetic result of the previous stage, and connects the first and second NMOS transistors of the same size in cascade, and connects the source and gate of the first NMOS transistor. An inverse operation including an analog arithmetic circuit in which the gate of the second NMOS transistor is used as an input and an output is obtained from the connection point between the source and the drain of the two NMOS transistors while supplying the power of the circuit to this source. By means,
A function is sequentially specified in each stage of calculation from the nth stage to the n-1 stage, ..., And the inverse calculation means is used in the A / D conversion of the stage according to the specified function. When the generated Gray code is 1, control is performed so as to realize a circuit that performs an operation including the analog arithmetic circuit, and when the generated Gray code is 0, an operation that does not include the analog arithmetic circuit. A control means that controls to realize a circuit that performs
A D / A conversion device characterized by being provided. Claims 1 to 9 are characterized in that, by the A / D conversion, one bit of Gray code is generated according to the magnitude relationship between the calculation result obtained by performing an operation on analog data by a tent mapping function and a predetermined threshold value. The D / A conversion device according to any one of the above items. The gray code generated by the A / D conversion in which the gray code is generated in a predetermined stage according to the magnitude relationship between the calculation result obtained by performing the calculation of the analog data by the tent mapping function and the predetermined threshold is analog. In the D / A conversion method for converting to data
Based on the Gray code generated for each operation, a control means for performing a function specifying process for specifying each function used when generating the Gray code, and
The first and second MOSFET transistors of the same size are connected in series, and the source and gate of the first MOSFET transistor are connected to supply the power of the circuit to this source, and the gate of the second MOSFET transistor is input. An analog arithmetic circuit that obtains an output from the connection point between the source and drain of the two NMOS transistors is included, and the inverse arithmetic based on the function specified by the control means is performed on the arithmetic result of each stage. Then, using an inverse arithmetic means that performs inverse arithmetic processing to obtain the arithmetic result of the previous stage,
The control means sequentially specifies a function in each stage of the operation from the final stage operation to the first stage operation , controls the inverse calculation means according to the specified function, and A / D of the stage. When the gray code generated in the conversion is 1, a circuit that includes the analog calculation circuit is realized, and when the generated Gray code is 0, the calculation that does not include the analog calculation circuit is performed. Realize the circuit,
When a function is first specified by the control means by the inverse calculation means, the inverse calculation of the first stage is applied to the calculation result of the final stage based on the specified function to obtain the inverse calculation result of the previous stage. Then, when the function is next specified by the control means, the inverse operation of the second stage based on the specified function is applied to the inverse operation result of the first stage to obtain the inverse operation result of the previous stage. Te, following repeat the inverse operation processing, D / a conversion method, wherein a result of the finally obtained inverse processing operates to output as analog data. The control means is generated from the first-stage calculation results of the n-th (integer of 1 or more), n-1, ... Nth, n-1, ... Based on the first-stage Gray code, the nth, n-1, ..., Nth, n-1 used to generate the first-stage Gray code. , ... Performs function identification processing to specify the first stage function,
The inverse calculation means obtains the first-stage calculation result of the n-, n-1, ..., The n-th, n-1, ... By the inverse calculation based on the first-stage function. n-2, ... The D / A conversion method according to claim 11 , wherein the inverse calculation process is performed so as to obtain the first-stage calculation result. The gray code generated by the A / D conversion that generates a gray code according to the magnitude relationship between the calculation result obtained by performing the calculation by the tent mapping function and the predetermined threshold value is converted into analog data. In the D / A conversion method
The nth stage gray code used when generating the nth stage gray code based on the nth stage gray code generated from the nth stage calculation result obtained from the operation of the nth stage (integer of 1 or more). Perform function identification processing to specify the nth stage function,
An inverse calculation process is performed so that the nth stage calculation result is obtained by the inverse calculation based on the nth stage function to obtain the n-1th stage calculation result.
Next, the n-1st stage gray code is generated based on the n-1th stage gray code generated from the n-1th stage calculation result obtained from the n-1th stage calculation. Perform the function identification process to specify the n-1st stage function used in the case,
An inverse calculation process is performed so that the n-1st stage calculation result is obtained by the inverse calculation based on the n-1st stage function to obtain the n-2nd stage calculation result.
Hereinafter, the function specifying process and the inverse operation process are repeated until the number of operations n performed during the A / D conversion is reached, and the finally obtained result of the inverse operation process is output as analog data. / A conversion method,
In the inverse calculation process of each stage from the nth stage to the n-1 stage, ..., The calculation result of each stage is subjected to an inverse calculation based on the function specified by the control means. It is an inverse arithmetic means that performs inverse arithmetic processing to obtain the arithmetic result of the previous stage, and connects the first and second NMOS transistors of the same size in cascade, and connects the source and gate of the first NMOS transistor. An inverse operation including an analog arithmetic circuit in which the gate of the second NMOS transistor is used as an input and an output is obtained from the connection point between the source and the drain of the two NMOS transistors while supplying the power of the circuit to this source. By means,
A function is sequentially specified in each stage of calculation from the nth stage to the n-1 stage, ..., And the inverse calculation means is used in the A / D conversion of the stage according to the specified function. When the generated Gray code is 1, control is performed so as to realize a circuit that performs an operation including the analog arithmetic circuit, and when the generated Gray code is 0, an operation that does not include the analog arithmetic circuit. A D / A conversion method characterized by controlling so as to realize a circuit that performs the above .