JP6752304B2 - Field effect transistor - Google Patents

Description

The present application relates to field effect transistors. In particular, the present invention relates to a high electron mobility transistor manufactured by using a nitride semiconductor.

In recent years, commercialization of electric field effect transistors using nitride semiconductors centered on GaN-based HEMTs represented by AlGaN / GaN High Electron Mobility Transistors (abbreviated as HEMT). Is progressing, and its application to amplifiers for mobile phone base stations is a typical example, and it is expected that it will continue to spread and expand into the market field related to high-frequency communication equipment.

With respect to the above-mentioned GaN-based HEMT, it is difficult to control the gate leak current, and therefore the leak current becomes large and the quality cannot be maintained. Therefore, a GaN-based HEMT having a more stable and smaller gate leak current is required.
The reason for this is that in a GaN-based HEMT, the gate leak current fluctuates greatly due to the influence of wet treatment or dry treatment in the wafer process process, or the gate leak is affected by the insulating film that protects the semiconductor epi layer surface. Since many cases in which the current fluctuates significantly have already been reported, it is considered that the sensitivity of the semiconductor epilayer surface is a major factor.

Conventionally, it has been said that a nitride semiconductor field-effect transistor having a small gate leakage current can be obtained by the compressive stress of the silicon oxide formed on the electron supply layer (see, for example, Patent Document 1).

Further, conventionally, in the inside of the opening of the insulating film formed on the semiconductor operating layer and in the gate electrode structure formed so as to ride on the insulating film, the side surface of the opening is inclined in a tapered shape (insulation). By making the surface side of the film opening inclined toward the drain side), the withstand voltage can be improved (that is, the gate leak current becomes smaller) due to the effect of relaxing the electric field concentration at the opening end of the gate electrode (for example, patented). Reference 2).

Japanese Unexamined Patent Publication No. 2008-244001 Japanese Unexamined Patent Publication No. 2004-253620

However, as described later, as a result of simulating the influence of the residual stress of the insulating film on the electrical characteristics of the GaN-based HEMT, there is a concern that the gate leak current may increase with respect to the technique described in Patent Document 1 above. , It turned out that there is a problem that sufficient effect cannot be expected. Further, regarding the technique described in Patent Document 2, it was found that the gate leakage current can be further reduced by considering not only the shape (inclination angle) of the opening of the gate electrode but also the residual stress of the insulating film. It was.

The present application discloses a technique for solving the above-mentioned problems, and reduces the gate leak current without being influenced by the state of the semiconductor surface or the film quality of the insulating protective film that protects the surface. The purpose is to obtain a possible field effect transistor.

The field effect transistor disclosed in the present application is
A field-effect transistor having a gate electrode, a source electrode, and a drain electrode formed on the surface of an electron supply layer.
Having a tensile stress, the first insulating film formed on the surface of the electron supply layer, and has a compressive stress, a second insulating film formed on the surface of those first insulating film, having a said An insulating film that covers the electron supply layer and
An opening of the insulating film formed in a region forming the gate electrode in the insulating film and having a trapezoidal square columnar contour surface which is in contact with the electron supply layer on one surface.
With
The gate electrode is Schottky-bonded to the electron supply layer in a region where the electron supply layer is exposed by the opening.
The insulating film is in contact with the gate electrode on a surface opposite to the trapezoidal square columnar contour surface of the opening and the surface in contact with the electron supply layer.
The cross-sectional shape of the trapezoidal square columnar contour surface of the opening is characterized in that the inclination angle of the electron supply layer with respect to the surface is set in the range of 60 degrees to 75 degrees.

According to the field effect transistor disclosed in the present application,
A field-effect transistor that can uniformly reduce the gate leakage current can be obtained without being affected by the state of each layer constituting the field-effect transistor or the film quality of the insulating film that protects the surface.

It is sectional drawing which shows an example of the field effect transistor according to Embodiment 1. FIG. It is sectional drawing which shows an example of the field effect transistor according to Embodiment 2. FIG. It is sectional drawing which shows an example of the field effect transistor according to Embodiment 3. FIG. It is a figure which shows the experimental result of the gate leak current when the field effect transistor of FIG. 2 is used. It is a figure which shows the experimental result of the gate leak current when the field effect transistor of FIG. 3 is used. It is sectional drawing which shows an example of the field effect transistor according to Embodiment 4. FIG. It is a figure for demonstrating the influence of the opening shape on the gate leak current characteristic of a field effect transistor. It is a figure for demonstrating the influence of the opening shape (when the opening has a rectangular parallelepiped contour surface) related to the crystal distortion of a field effect transistor. It is a figure for demonstrating the influence of the opening shape (when the opening has a trapezoidal square columnar contour surface) related to the crystal distortion of a field effect transistor. It is a figure for demonstrating the influence of the opening shape (when the opening has a rectangular parallelepiped contour surface) related to the electric field strength of a field effect transistor. It is a figure for demonstrating the influence of the opening shape (when the opening has a trapezoidal square columnar contour surface) which concerns on the electric field strength of a field effect transistor. It is a figure for demonstrating the influence of the residual stress of an insulating film on the gate leak current characteristic of a field effect transistor.

Before concretely explaining the embodiment of the present application, first, the contents examined when determining the configuration of the field effect transistor shown in the embodiment of the present application will be described. This is because the content of this study is important for understanding the structure of the present application.

First, in order to systematically understand the effect of the residual stress of the insulating film on the electrical characteristics of the GaN-based HEMT, an analysis using device simulation was performed.
Specifically, the residual stress of the insulating film formed directly above the semiconductor surface (which can be rephrased as the surface of the electron supply layer shown in FIG. 1 to be described later) is compressive stress (residual stress value is -1 GPa), no residual stress, and tensile stress (remaining stress). The residual stress value was set in the range of +1 GPa), and it was formed so as to ride on the inside of the opening of the insulating film and on the insulating film, which is currently widely used as the structure of the gate electrode portion of the GaN-based HEMT. When the gate electrode structure is used and the cross-sectional shape of the opening is rectangular (when the opening of the insulating film has a rectangular contour surface, the contour line of the cross section orthogonal to the semiconductor surface is orthogonal to the semiconductor surface. When the cross-sectional shape of the opening is trapezoidal with the upper base larger than the lower base (when the opening of the insulating film has a trapezoidal square columnar contour surface, the contour line of the cross section orthogonal to the semiconductor surface) Depends on the gate leak current value when the inclination angle of the two straight lines intersecting the semiconductor surface with respect to the semiconductor surface is 45 degrees. It was calculated whether it showed sex.

The result is shown in FIG. FIG. 7A shows the result when the opening has a rectangular parallelepiped contour surface. In this case, when the residual stress of the insulating film is tensile stress (see the curve shown by "+1 GPa" in the figure. The same applies hereinafter), the gate leak current is reduced and the residual stress of the insulating film is the compressive stress (in the figure). , Refer to the curve shown by "-1 GPa" as the value of residual stress. The same applies hereinafter), the gate leak current increased. In the figure, the curve indicated by “0 Pa” as the residual stress value is the value of the gate leak current when the residual stress is zero (the same applies hereinafter).

On the other hand, as shown in FIG. 7B, when the opening has a trapezoidal square columnar contour surface (when the inclination angle of the contour line of the opening with respect to the semiconductor surface is 45 degrees), the residual stress of the insulating film Calculation that the gate leak current decreases when is compressive stress (-1 GPa), and increases when tensile stress (see the curve shown by "+1 GPa" as the value of residual stress in the figure. The same applies hereinafter). The result was.

The cause of this will be described with reference to FIGS. 8 to 11. First, FIGS. 8 and 9 show the YY component of crystal strain (see the one-point chain line Ps in FIG. 1) at a depth of 0.5 nm from the semiconductor surface (specifically, AlGaN) in the gate electrode region toward the substrate. Distortion of a semiconductor crystal (specifically, AlGaN) in the vertical direction (vertical direction on the paper surface) in FIG. 1. The reference numerals indicate the direction in which the crystal expands when it is positive, and the direction in which the crystal shrinks when it is negative). This is the calculation result by device simulation. FIG. 8 shows the result when the opening has a rectangular parallelepiped contour surface. Further, FIG. 9 shows the result when the opening has a trapezoidal square columnar contour surface (when the inclination angle of the contour line of the opening with respect to the semiconductor surface is 45 degrees). In both FIGS. 8 and 9, the alternate long and short dash line S for position reference and the alternate long and short dash line D are shown together. The alternate long and short dash line S indicates the position of the gate opening end on the source electrode side, and the alternate long and short dash line D indicates the position of the gate opening end on the drain electrode side (the alternate long and short dash line S and the alternate long and short dash line D are as follows. The same applies to FIGS. 10 and 11 described in FIG.

From these results, when the opening of the gate electrode has a rectangular parallelepiped contour surface and when the opening has a trapezoidal square columnar contour surface (when the inclination angle of the contour line of the opening with respect to the semiconductor surface is 45 degrees). It was found that the change in the value of the YY component of the crystal strain at the open end of the gate electrode depending on the position was characteristically different. In the former case (when the opening has a rectangular parallelepiped contour surface), the place where the sign of the crystal strain is reversed is located at the gate opening end. On the other hand, in the latter case (when the opening has a trapezoidal square columnar contour surface), it was found that the position is closer to the source electrode or the drain electrode than the gate opening end, that is, the position is on the semiconductor surface. In the latter case, it was estimated that the crystal strain component tends to increase at the gate opening end where the largest electric field is applied, that is, it tends to be easily affected by the residual stress of the insulating film. ..

Therefore, next, the electric field strength near the open end of the gate electrode was calculated by device simulation. The results are shown in FIGS. 10 and 11. FIG. 10 shows the electric field strength near the opening end when the opening has a rectangular parallelepiped contour surface. In FIG. 10, FIG. 10 (b) is an enlarged view of a portion surrounded by a dotted line indicated by reference numeral E in FIG. 10 (a). Further, FIG. 11 shows the electric field strength near the opening end when the opening has a trapezoidal square columnar contour surface (when the inclination angle of the contour line of the opening with respect to the semiconductor surface is 45 degrees). In FIG. 11, FIG. 11B is an enlarged view of a portion surrounded by a dotted line indicated by reference numeral F in FIG. 11A.

As shown in FIG. 10, when the change in the crystal strain component near the opening end of the gate electrode has an effect and the opening has a rectangular contour surface, the electric field strength near the opening end of the gate electrode is determined. When the residual stress of the insulating film was tensile stress (+1 GPa), the electric field strength near the opening end of the gate electrode was relatively low, and when it was compressive stress (-1 GPa), it increased.

On the other hand, when the opening has a trapezoidal square columnar contour surface (when the inclination angle of the contour line of the opening with respect to the semiconductor surface is 45 degrees), as shown in FIG. 11, the result of FIG. 10 is different. On the contrary, when the residual stress of the insulating film was compressive stress (-1 GPa), the electric field strength near the open end of the gate electrode was relatively low, and when it was tensile stress (+1 GPa), it increased.

As described above, a series of simulations newly show that the electric field strength at the opening end of the gate electrode is affected by the residual stress of the insulating film and the shape (tilt angle) of the opening of the gate electrode, and the gate leakage current increases or decreases. found.

Therefore, the effect of the residual stress of the insulating film formed directly above the semiconductor surface on the gate leak current was examined by simulation. The result is shown in FIG. As shown in FIG. 12 (horizontal axis), the residual stress is the inclination of the opening of the gate electrode in the cross-sectional view in each case of compressive stress (-1 GPa), no residual stress, and tensile stress (+1 GPa). Using the angle as a parameter, the gate leak current was calculated when the temperature was changed in the range of 25 to 75 degrees with respect to the semiconductor surface.

As a result, as shown in FIG. 12, when the angle parameter of the inclination angle is 45 degrees or less, the gate leak current is smaller in the insulating film having compressive stress (-1 GPa), and the reverse is true. It was found that the gate leak current of the insulating film having a tensile stress (+1 GPa) is smaller at 45 degrees or higher.

The above results suggest that a GaN-based HEMT having a smaller gate leakage current can be provided by optimally designing the residual stress of the insulating film and the shape (inclination angle) of the opening of the gate electrode.

Based on the above, next, the embodiment of the present application will be specifically described with reference to the drawings.
Embodiment 1.
Hereinafter, the field effect transistor according to the first embodiment will be described with reference to FIG. In FIG. 1, examples of the semiconductor substrate 101 used in the GaN-based HEMT include a SiC substrate, a GaN substrate, a Si substrate, and a sapphire substrate. A grown channel layer 102 is formed on the semiconductor substrate 101, and a GaN layer is typical as a channel layer used for a GaN-based HEMT. The grown electron supply layer 103 is formed on the channel layer 102, and the AlGaN layer is typical as the electron supply layer used for the GaN-based HEMT. The Al composition and film thickness are adjusted to obtain a sheet carrier concentration Ns suitable for the target performance of the product in the range of 2 × 10 ¹² / cm ² to 4 × 10 ¹³ / cm ² . A layer called a GaN cap layer that stabilizes the semiconductor surface may be formed on the AlGaN layer.

Further, an ohmic-bonded source electrode 104 and an ohmic-bonded drain electrode 105 are formed on the semiconductor surface. Further, an insulating film 106 that directly covers the semiconductor surface is formed on the semiconductor surface. The insulating film 106 is characterized by having a compressive stress, and a SiN film (same as a silicon nitride film; the same applies hereinafter) is widely used in a GaN-based HEMT.

Further, a Schottky-bonded gate electrode 108 is formed on the semiconductor surface, and as shown in FIG. 1, in the region where the insulating film 106 between the source electrode 104 and the drain electrode 105 is opened, and partly on the insulating film. It has a T-shaped shape (pseudo-T-shaped shape).

Further, as shown in the portion surrounded by the broken line in FIG. 1, the opening of the insulating film 106 of the gate electrode portion has a tapered shape, specifically, the surface side of the insulating film opening is the drain side and the source side. It is formed so as to have an inclined shape. An insulating protective film 109 for protecting the operating portion of the transistor is formed so as to cover the gate electrode 108 and the insulating film 106, and a SiN film is widely used for the insulating protective film 109 in the GaN-based HEMT.

Further, a wiring electrode 110 for connecting to an external circuit (not shown) connected to the source electrode 104, the drain electrode 105, and the gate electrode 108 drawn out by extending to the outside of the operating portion of the transistor is formed. ..

Next, the method for manufacturing the field-effect transistor shown in FIG. 1 will be described in detail below. The field-effect transistor of FIG. 1 can be manufactured by, for example, a general manufacturing method of a GaN-based HEMT described below.

First, by the MOCVD (Metal Organic Chemical Vapor Deposition) method, the AlN nucleation layer (not shown), the undoped channel layer 102 (here, the GaN channel layer), and the undoped are undoped on the SiC substrate 101. The electron supply layer 103 (here, the AlGaN electron supply layer) is sequentially laminated. Two-dimensional electron gas is generated at the hetero interface of AlGaN / GaN, and this becomes a current traveling layer in the semiconductor layer. In order to obtain a sheet carrier concentration Ns suitable for the target performance of the product in the range of 2 × 10 ¹² / cm ² to 4 × 10 ¹³ / cm ² , the Al composition and film thickness of the above AlGaN electron supply layer are adjusted. For example, the Al composition is often adjusted in the range of 10% to 30%, and the film thickness is often adjusted in the range of 10 nm to 40 nm. If necessary, an undoped GaN cap layer or an n-GaN cap layer may be further laminated on the AlGaN electron supply layer.

Sapphire, Si, and GaN can also be used as the substrate for obtaining the GaN-based HEMT, and an epitaxial layer suitable for the substrate material may be grown, and this is not limited in the present application.

Next, Ti / Al / Ti / Au is laminated on the produced semiconductor surface layer through the openings of the photoresist that has been patterned by a general photolithography process, for example, by a general vapor deposition method. Form metal. Then, after the photoresist is peeled off by lift-off, a heat treatment (800 ° C. to 950 ° C.) is performed at the interface between the semiconductor surface and the Ti / Al / Ti / Au laminated metal to obtain ohmic contact. From the above, the source electrode 104 and the drain electrode 105 are obtained.

Next, the insulating film 106 that covers the semiconductor surface is formed. SiN films are widely used in GaN-based HEMTs. As a method for forming the insulating film, a plasma CVD method, a thermal CVD method, a catalytic CVD (Cat-CVD) method, an ECR sputtering method or the like is used to form the insulating film. At this time, since a SiN film, which is one of the insulating films of different materials, is formed on the semiconductor surface, residual stress is generated. The stress changes depending on the film formation method and growth conditions. The SiN film used in this experiment was a film produced by a plasma CVD method or an ECR sputtering method, and a single-layer film or a laminated film was formed according to the purpose.

Next, on the insulating film 106, a tapered gate opening 111 for forming the gate electrode 108 is formed through a photoresist opening patterned by a general photolithography process. To do. The method for forming the opening 111 is, for example, wet etching using buffered hydrofluoric acid (BHF), RIE (Reactive Ion Etching) method, ECR (Electron Cyclotron Resonance) method, or ICP (Inductive Coupled Plasma) method. Dry etching by is common.

As a means for obtaining the opening 111 having the tapered shape shown in FIG. 1, which is a feature of this time, in the present application, an opening having a higher dry etching rate than the insulating film 106 between the insulating film 106 and the photoresist. A sacrificial insulating film (SiN film) for forming the 111 was formed with a predetermined film thickness by plasma CVD, and then the opening 111 was formed by dry etching by the ICP method.

According to this method, the side etching from the opening of the photoresist proceeds earlier in the sacrificial insulating film than in the insulating film 106 (by utilizing the difference in the dry etching rate), so that the sacrificial insulating film Depending on the thickness of the insulating film 106, the surface side of the opening of the insulating film 106 has a tapered shape (trapezoidal square columnar contour surface) having a desired angle (25 degrees to 75 degrees) inclined toward the drain side and the source side. Obtainable.

Next, a good Schottky junction in a GaN-based HEMT is performed in the region of the opening 111 through the opening of the photoresist that has been patterned by a general photolithography process, for example, by a general vapor deposition method. As an effective laminated metal for obtaining the above, for example, any one of Ni / Au, Pt / Au, and Pt / Ti / Au is selected and formed to obtain the gate electrode 108.

Next, an insulating protective film 109 for protecting the operating portion of the transistor is formed, and further, after opening the insulating protective film 109 at a predetermined position by a general photolithography step, the source electrode 104 and the drain electrode 105 , And the gate electrode 108 drawn out by extending to the outside of the operating portion of the transistor, and the wiring electrode 110 formed for connecting to each connected (not shown) external circuit are formed to form the GaN of FIG. A field effect transistor of the system HEMT can be obtained.

In order to confirm the operation and effect of the first embodiment, an AlGaN / GaN HEMT transistor was actually prototyped and the gate leak current was evaluated.
First, in the experiment, a SiN film having a compressive stress of -2 GPa was used as the insulating film 106. The SiN film formed by the plasma CVD method has a range of a compressive stress of −400 MPa to a tensile stress of 400 MPa, which is a general adjustment range.

Therefore, this time, this was realized by using an ECR sputtering apparatus to obtain an insulating film 106 having a compressive stress of -2 GPa. The film thickness of the insulating film 106 was 80 nm. However, when the residual stress of the insulating film becomes large, there is a growing concern that problems such as cracking or peeling of the insulating film will occur. In this series of verifications, problems such as cracking or peeling of the insulating film occur even at 200 nm, which is assumed to be the maximum film thickness applied to the insulating film 106, up to a compressive stress of at least -3 GPa. There wasn't. Further, in the present manufacturing process, the inclination angle of the tapered portion of the opening indicated by reference numeral 111 in FIG. 1 was 60 degrees.

Here, as one problem, the GaN-based HEMT is affected by the wet treatment or the dry treatment in the wafer process process, and the gate leakage current fluctuates greatly, or is affected by the insulating film that protects the semiconductor epi surface. There are cases where the gate leak current fluctuates greatly.

Furthermore, when the stress value of the insulating film is adjusted by changing the growth conditions of various film forming devices, if the gate leak current changes, is it due to the film quality or the stress of the insulating film? Separation is actually quite difficult.

Therefore, this time, in order to eliminate the influence of the wafer process on the semiconductor surface or the influence of the film quality of the insulating film to the utmost limit, in addition to the transistor structure of FIG. 1, the transistor structures as shown in FIGS. 2 and 3 are combined. I decided to evaluate it.

In the structure of the gate portion shown in FIG. 2, with respect to the region of the insulating film 106 in FIG. 1, directly above the electron supply layer 203, above the first insulating film 206 having compressive stress and the first insulating film 206. Was formed by being divided into two layers and laminated with a second insulating film 207 having tensile stress. The total thickness was unified to 80 nm in FIG. 1 so that there would be no difference in gate leakage current due to the film thickness.

3 according to FIG. 2 so that the film thickness ratio of the first insulating film 206 having compressive stress and the second insulating film 207 having tensile stress is any one of 10 nm / 70 nm, 20 nm / 60 nm, and 30 nm / 50 nm. Two field effect transistors were made.
The second insulating film 207 having a tensile stress was formed by plasma CVD, and the stress value was 130 MPa. Here, the compressive stress of the first insulating film 206 is -2 GPa. The angle of inclination of the tapered opening 211 surrounded by the broken line of the circle in FIG. 2 is 60 degrees.

On the other hand, in the structure of the gate portion shown in FIG. 3, the first insulating film 307 having a tensile stress directly above the electron supply layer 303 and the first insulating film 307 with respect to the region of the insulating film 106 in FIG. It was formed by laminating it in two layers with a second insulating film 306 having compressive stress. The total thickness was unified to 80 nm in FIG. 1 so that there would be no difference in gate leakage current due to the film thickness.

The film thickness ratios of the first insulating film 307 having tensile stress and the second insulating film 306 having compressive stress are 10 nm / 70 nm, 20 nm / 60 nm, and 80 nm / 0 nm (in this case, the second insulating film 306 is Three field-effect transistors according to FIG. 3 were manufactured so as to be one of (not formed).

The first insulating film 307 having a tensile stress was formed by plasma CVD, and the stress value was 130 MPa. The stress value of the second insulating film 306 having a compressive stress is -2 GPa. The inclination angle of the tapered opening 311 in FIG. 3 is 60 degrees.

The film thickness ratios of the first insulating film 206 having compressive stress and the second insulating film 207 having tensile stress are 10 nm / 70 nm, 20 nm / 60 nm, 30 nm / 50 nm, and 80 nm / 0 nm (in this case, tensile stress). The measurement result of the gate leak current when the insulating film is not formed (see the structure of FIG. 1) is shown in FIG. In FIG. 4, tensile stress is generated in the upper insulating film and compressive stress is generated in the lower insulating film. The dotted frame indicated by reference numeral A in the figure is the film thickness ratio corresponding to the transistor structure shown in FIG. 2, and the circled dotted frame indicated by reference numeral B corresponds to the transistor structure shown in FIG. To do. Further, the triangular symbol indicates the evaluated leak current value when the corresponding film thickness ratio is set. As shown in FIG. 4, as the film thickness of the insulating film having compressive stress (see the value of the lower lower insulating film) increases, the gate leakage current becomes smaller.

Next, the film thickness ratios of the first insulating film 307 having tensile stress and the second insulating film 306 having compressive stress are 10 nm / 70 nm, 20 nm / 60 nm, and 80 nm / 0 nm (in this case, the second). The measurement result of the gate leak current when the insulating film 306 is not formed) is shown in FIG. In FIG. 5, compressive stress is generated in the upper insulating film and tensile stress is generated in the lower insulating film. The dotted line frame indicated by the reference numeral C in the drawing is the film thickness ratio corresponding to the transistor structure shown in FIG. The circles in the frame are the values of the gate leak current evaluated in each of the above three film thickness ratios.

As shown in FIG. 5, the gate leakage current increased as the film thickness of the insulating film having tensile stress increased, that is, the gate leak current decreased as the film thickness of the insulating film having compressive stress increased.

From the results shown in FIGS. 4 and 5, the gate leakage current becomes uniformly smaller when the film thickness of the insulating film having compressive stress is increased regardless of the fact that the insulating film is formed directly on the semiconductor surface. It is clear that the action of reducing the electric current strength due to the residual stress of the film worked.

Further, when a field effect transistor having a structure in which the film thickness ratio of the first insulating film 206 having the compressive stress and the second insulating film 207 having the tensile stress in FIG. 2 is 70 nm / 10 nm is tentatively manufactured, FIG. The field-effect transistor having a structure in which the film thickness ratio of the first insulating film 307 having the tensile stress and the second insulating film 306 having the compressive stress is 10 nm / 70 nm has a film thickness ratio of 70 nm / 10 nm in FIG. It is clear from the results of FIGS. 4 and 5 described above that the gate leakage current is larger than that of the transistor. This is an interesting result that strongly suggests that the type of insulating film formed directly on the semiconductor surface may have an effect.

According to the results of this experiment, even if the inclination angle of the tapered opening of the insulating film is 60 degrees, the insulating film having compressive stress is more effective in reducing the gate leakage current.

On the other hand, in the simulation result of FIG. 12, when the inclination angle of the tapered opening of the insulating film is 60 degrees, the larger the tensile stress value, the smaller the gate leak current, and the absolute value is the above experiment. There is a discrepancy with the result.

However, the device simulation is a result calculated based on the structure of the given field effect transistor and the physical property values of various materials constituting the structure, and the action on the gate leak current caused by the structure of the gate and the residual stress of the material is exerted. It should be understood that the qualitative tendency is universal because the physical property value is examined as a parameter.

On the other hand, experimentally, even if the inclination angle of the tapered opening of the insulating film is 75 degrees, it is judged that the insulating film having compressive stress can reduce the gate leakage current (not shown). Obtained separately.

As already explained above, the crystal strain on the semiconductor surface at the gate end changes due to the combination of the inclination angle of the insulating film opening and the residual stress of the insulating film, and when a predetermined condition is satisfied, the gate end The effect of relaxing the electric field strength of the above is obtained.

By considering the contents described above, a field effect transistor capable of uniformly reducing the gate leakage current can be obtained without being affected by the state of the semiconductor surface or the film quality of the insulating protective film that protects the surface.

Embodiment 2.
With respect to the region of the insulating film 106 in FIG. 1 described above, as shown in FIG. 2, a first insulating film 206, which is an insulating film having compressive stress, and the first insulating film 206 directly above the electron supply layer 203 A form of a gate structure formed by dividing into two layers and laminating a second insulating film 207, which is an insulating film having tensile stress, on the insulating film 206 of 1 can be considered. The first insulating film 206 is laminated after, for example, the channel layer 202 composed of the GaN layer and the electron supply layer 203 composed of the AlGaN layer are laminated in this order.
In designing or manufacturing a field effect transistor, an insulating film other than the first insulating film 206 and the second insulating film 207 is often formed (for example, insulation protection for protecting the surface of the gate electrode 208). The film 209 is often formed from the viewpoint of ensuring long-term reliability. That is, as shown in FIG. 2, the gate electrode 208 and the second insulating film 207 are both formed by the insulating protective film 209. The surface is covered and protected), and a tensile stress film must be used in the process to control the stress determined by the total thickness of the insulating film that protects the transistor within a predetermined range. It is conceivable to use the insulating film having the two-layer laminated structure of the embodiment.

As shown in the experimental results of FIG. 4, it can be seen that the same operation as that of the first embodiment can be obtained even with the configuration of the second embodiment.

As described above, the deterioration of the gate leakage current can be minimized by using the insulating film with compressive stress.

Embodiment 3.
As described above, the first insulating film 307 having a tensile stress directly above the electron supply layer 303 and the first insulating film 307 with respect to the region of the insulating film 106 in FIG. 1 shown in FIG. A form of a gate structure formed by dividing into two layers and laminating with a second insulating film 306 having compressive stress can be considered. In the figure, the first insulating film 307 is laminated after, for example, the channel layer 302 composed of the GaN layer and the electron supply layer 303 composed of the AlGaN layer are laminated in this order. Further, the surfaces of the second insulating film 306 and the gate electrode 308 are covered and protected by the insulating protective film 309.

It has already been mentioned that the performance or reliability of GaN-based HEMTs is strongly influenced by the state of the semiconductor surface or the film quality of the insulating film that protects the surface. Due to restrictions determined by the type of film, film thickness, film formation process, etc., it may be necessary to use an insulating film with tensile stress on the semiconductor surface side.

As shown in the experimental results of FIG. 5, it can be seen that the same operation as that of the first embodiment can be obtained even with the configuration of the third embodiment.

As described above, it can be seen that the deterioration of the gate leakage current can be minimized by using the insulating film having compressive stress.

Embodiment 4.
It has already been mentioned that the performance or reliability of GaN-based HEMTs is strongly influenced by the state of the semiconductor surface or the film quality of the insulating film that protects the surface. Furthermore, it may be necessary to adopt an insulating film having tensile stress on the semiconductor surface side due to restrictions determined by the type of film, the film thickness, the process of film formation, and the like.

In such a case, the simulation result of FIG. 12 is useful. Specifically, as shown in FIG. 6, the semiconductor surface is directly coated with the insulating film 407, and the insulating film 407 is an insulating film having tensile stress. The opening of the insulating film 407 is 90 degrees with respect to the upper surface of the electron supply layer 403 (when the opening has a rectangular parallelepiped contour surface), or an inclination angle of 75 degrees to less than 90 degrees when viewed from the upper surface of the electron supply layer 403. (When the opening has a trapezoidal square columnar contour surface. See the opening 411 indicated by the dotted circle in the figure). In the figure, the insulating film 407 is laminated after, for example, the channel layer 402 composed of the GaN layer and the electron supply layer 403 composed of the AlGaN layer are laminated in this order. Further, both the insulating film 407 and the gate electrode 408 are protected by covering the surface thereof with the insulating protective film 409.

According to the results of the simulations of FIGS. 10 and 11, the transistor produced according to the fourth embodiment has a lower electric field strength at the gate end than the transistor formed of the insulating film having compressive stress on the insulating film 407. The action is obtained.

Further, according to the result of the simulation of FIG. 12, a field effect transistor (specifically, a field effect transistor) capable of uniformly reducing the gate leakage current regardless of the state of the semiconductor surface or the film quality of the insulating protective film that protects the surface. , See the case where the angle parameter in FIG. 12 is 75 degrees).

Although the present application describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more of the embodiments are applicable to particular embodiments. However, the present invention is not limited to this, and can be applied to the embodiments alone or in various combinations.
Therefore, innumerable variations not illustrated are envisioned within the scope of the techniques disclosed herein. For example, it is assumed that at least one component is modified, added or omitted, and further, at least one component is extracted and combined with the components of other embodiments.

101 Semiconductor substrate, 102, 202, 302, 402 channel layer, 103, 203, 303, 403 electron supply layer, 104 source electrode, 105 drain electrode, 106 insulating film, 108, 208, 308, 408 gate electrode, 109, 209 , 309, 409 Insulation protective film, 110 Wiring electrode, 111, 211, 311, 411 openings, 206, 307 First insulating film, 207, 306 Second insulating film, 407 Insulating film (with tensile stress)

Claims (6)

A field-effect transistor having a gate electrode, a source electrode, and a drain electrode formed on the surface of an electron supply layer.
Having a tensile stress, the first insulating film formed on the surface of the electron supply layer, and has a compressive stress, a second insulating film formed on the surface of those first insulating film, having a said An insulating film that covers the electron supply layer and
An opening of the insulating film formed in a region forming the gate electrode in the insulating film and having a trapezoidal square columnar contour surface which is in contact with the electron supply layer on one surface.
With
The gate electrode is Schottky-bonded to the electron supply layer in a region where the electron supply layer is exposed by the opening.
The insulating film is in contact with the gate electrode on a surface opposite to the trapezoidal square columnar contour surface of the opening and the surface in contact with the electron supply layer.
A field-effect transistor characterized in that the cross-sectional shape of the trapezoidal square columnar contour surface of the opening is set in an inclination angle of 60 degrees to 75 degrees with respect to the surface of the electron supply layer. The field-effect transistor according to claim 1, wherein the stress of the second insulating film is set in a range larger than -2 GPa and less than 0 . The field-effect transistor according to claim 1 or 2, wherein the insulating film is a silicon nitride film. The electric field effect according to any one of claims 1 to 3, wherein the electron supply layer is formed on a channel layer formed on a semiconductor substrate made of SiC, GaN, or sapphire. Type transistor. The field effect transistor according to any one of claims 1 to 4, which is a GaN-based high electron mobility transistor. The field effect transistor according to claim 5, wherein the GaN-based high electron mobility transistor is an AlGaN / GaN high electron mobility transistor.

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