JP6665429B2 - Arithmetic processing device, information processing device, and control method for information processing device - Google Patents

Description

  The present invention relates to an arithmetic processing device, an information processing device, and a control method of the information processing device.

  An information processing device such as a PC (Personal Computer) or a server includes an arithmetic processing device such as a CPU (Central Processing Unit) that performs arithmetic processing on data read from a memory. In such an information processing apparatus, the latency from when a CPU, which is an endpoint, issues a fetch request as a read request to a memory to when the CPU receives response data corresponding to the read request is an important factor in processing performance. One of the factors.

  Further, a multiprocessor system in which a plurality of CPUs are communicably connected to each other may be used as the information processing apparatus. In such a multiprocessor system, in recent years, as shown in FIG. 14, for example, a plurality of CPUs and routers are connected to each other via a network using high-speed serial transmission. By employing high-speed serial transmission, high communication throughput can be realized.

JP 2010-124448 A JP 2010-116228 A

  In a network using high-speed serial transmission, transmission errors are checked by a CRC (Cyclic Redundancy Check). When a transmission error is detected, the end of the packet is rewritten to EDB (end bad). Therefore, unless the end point (CPU) receives all data up to the end of the packet including the response data, it cannot determine whether the packet is normal.

  Therefore, in the CPU that has issued the fetch request, all the data up to the end of the packet including the response data corresponding to the fetch request is temporarily stored in the reception buffer, and then the data in the reception buffer is sequentially stored in the CPU core from the top. Will be sent to

  However, since the reception buffer is a FIFO (First In First Out), reading of the processing target data (one unit data; for example, 8 byte data) requested by the CPU core from the reception buffer is performed immediately before the unit data. Wait until data is read. For this reason, there is a case where the communication latency increases as viewed from the CPU core, and the processing performance decreases.

  In one aspect, the invention disclosed in the present specification aims to reduce the read latency of data to be processed.

The arithmetic processing device of the present case is connected to another arithmetic processing device, and has a processing unit, a communication unit, a buffer, a writing unit, and a reading unit. The processing unit generates a read request for processing target data. The communication unit transmits the read request generated by the processing unit to the another arithmetic processing device, and receives a data block including the processing target data corresponding to the transmitted read request from the other arithmetic processing device. I do. The buffer stores the data block. The writing unit sequentially writes a plurality of unit data included in the data block by the communication unit has received in the buffer. The reading unit preferentially reads the processing target data, which is at least one of the plurality of unit data, from the buffer. Further, the reading unit is address information of the processing target data recorded by the another processing unit in a response header attached to the data block, and the processing target data is selected from the plurality of unit data. After reading the processing target data corresponding to the address information from the buffer with reference to the information for specifying the address information, unit data other than the processing target data is sequentially read from the buffer.

  According to the embodiment, the read latency of the data to be processed can be reduced.

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus including an arithmetic processing unit (CPU) according to a first embodiment and a second embodiment of the present invention. FIG. 3 is a diagram illustrating packet routing when a fetch request is made from one CPU to another CPU in the information processing apparatus according to the first embodiment. FIG. 4 is a diagram illustrating a format of a header of a fetch response packet in the first embodiment. FIG. 3 is a block diagram illustrating a configuration of a reception buffer included in a router and a packet write / read process for the reception buffer in the CPU according to the first embodiment (a write unit and a read unit). FIG. 5 is a block diagram illustrating in detail a configuration (reading unit) relating to a packet reading process illustrated in FIG. 4. 6 is a flowchart illustrating an operation of a configuration (reading unit) according to the packet reading process illustrated in FIG. 5. FIG. 7 is a time chart illustrating an operation when a configuration (reading unit) relating to the packet reading process illustrated in FIGS. 4 and 5 first reads the tenth data according to the flowchart illustrated in FIG. 6. (A) is a diagram showing a format of a header of a fetch request packet in the second embodiment, and (B) is a diagram showing a format of a header of a fetch response packet in the second embodiment. FIG. 14 is a diagram illustrating packet routing when a fetch request is made from one CPU to another CPU in the information processing apparatus according to the second embodiment. FIG. 13 is a block diagram illustrating a configuration of a reception buffer included in a router and a packet writing / reading process for the reception buffer (a writing unit and a reading unit) in the CPU according to the second embodiment; FIG. 11 is a block diagram illustrating in detail a configuration (reading unit) relating to a packet reading process illustrated in FIG. 12 is a flowchart illustrating an operation of a configuration (reading unit) related to the packet reading process illustrated in FIG. 13 is a time chart showing an operation when the configuration (reading unit) relating to the packet reading process shown in FIGS. 10 and 11 reads out the second, sixth, tenth, and fourteenth data first in accordance with the flowchart shown in FIG. FIG. 2 is a block diagram illustrating an example of a configuration of a multiprocessor system (information processing device). FIG. 3 is a block diagram illustrating an example of a configuration of a multi-core processor (CPU, arithmetic processing device). FIG. 15 is a diagram illustrating packet routing when a fetch request is made from one CPU to another CPU in the multiprocessor system shown in FIG. 14. (A) is a diagram showing a format of a packet without data, and (B) is a diagram showing a format of a packet with data. (A) is a diagram showing a format of a header of a fetch request packet, and (B) is a diagram showing a format of a header of a fetch response packet. FIG. 16 is a block diagram illustrating a configuration related to a reception buffer included in a router and a packet write / read process for the reception buffer in the CPU (multi-core processor) illustrated in FIG. 15. 20 is a flowchart illustrating an operation of a configuration related to the packet writing process illustrated in FIG. 20 is a flowchart illustrating an operation of a configuration related to the packet reading process illustrated in FIG. 19. 20 is a time chart showing the operation in the shortest case in the configuration relating to the packet write / read processing shown in FIG. FIG. 20 is a time chart illustrating an operation when the end of a received packet is EDB in the configuration related to the packet writing process illustrated in FIG. 19.

  Hereinafter, an embodiment of an arithmetic processing device, an information processing device, and a control method of an information processing device disclosed in the present application will be described in detail with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude various modified examples and applications of technology not explicitly described in the embodiment. That is, the present embodiment can be implemented with various modifications without departing from the spirit thereof. In addition, each drawing is not intended to include only the components illustrated in the drawings, but may include other functions. The embodiments can be appropriately combined within a range that does not contradict processing contents.

[1] Technology Related to the Present Embodiment First, a technology related to the present embodiment will be described with reference to FIGS.
In recent years, in a multiprocessor system (information processing device), as shown in FIG. 14, a plurality of CPUs and routers are interconnected by a high-speed serial transmission network (see reference numeral 30 in FIG. 16) in order to achieve high communication throughput. ). FIG. 14 is a block diagram illustrating an example of a configuration of a multiprocessor system.

  In recent years, a multi-core processor having a plurality of cores has been generally used as a CPU. Here, an example of a configuration of each CPU (multi-core processor, arithmetic processing unit) 10 configuring the multiprocessor system illustrated in FIG. 14 will be described with reference to FIG. FIG. 15 is a block diagram illustrating an example of the configuration of the CPU 10.

  As shown in FIG. 15, in the CPU 10, a plurality of cores 11 are connected via a shared cache (tertiary cache) 12. In FIG. 15, the core 11 includes N + 1 cores # 0 to #N (N is an integer of 1 or more). In FIG. 15, a primary cache (not shown) and a secondary cache (not shown) are built in each core 11, and a tertiary cache is used as the shared cache 12, but a primary cache is built in each core 11, A secondary cache may be used as the shared cache 12.

  In addition to the core 11, a MAC (Memory Access Controller) 13 and a router (Router) 14 are connected to the shared cache 12. The MAC 13 is connected to a DIMM (Dual Inline Memory Module) 20 functioning as a main memory, and functions as a control unit that controls data exchange with the DIMM 20. The router 14 is connected to another CPU 10 or another router (for example, a large scale integrated circuit (LSI) for routing), and functions as a communication unit that performs data communication with the other CPU 10 by a packet.

  In such a CPU 10, a case where one of the cores 11 requests reading (fetching) of memory data (a case of issuing a fetch request) will be considered. The core 11 specifies an address indicating 8-byte data (processing target data) required by the core 11 and first accesses a cache (a primary cache and a secondary cache) built in the core 11. As a result, when a cache hit occurs, the core 11 reads the 8-byte data from the internal cache.

  On the other hand, when a cache miss occurs in the built-in memory, the core 11 accesses a shared cache (a tertiary cache in FIG. 15) 12 shared by a plurality of cores. However, if a cache miss occurs in the shared cache 12, access to the main memory 20 is performed. Since the cache line size of the shared cache 12 is, for example, 128 bytes, the MAC 13 is required to read a 128-byte data block including the 8-byte processing target data requested by the core 11.

  Next, the core 11 is configured such that memory data (for example, 8 bytes) of another CPU 10 (for example, CPU # 1 of FIGS. 14 and 16) different from the CPU 10 to which the core 11 belongs (for example, CPU # 0 of FIGS. 14 and 16). The case of requesting the reading of (processing target data) will be described with reference to FIG. FIG. 16 is a diagram illustrating packet routing when a fetch request is issued from one CPU # 0 to another CPU # 1 in the multiprocessor system shown in FIG.

  In this case, as shown in FIG. 16, the core 11 in the CPU # 0 transmits a fetch request packet to another CPU # 1 via the router 14 and the network 30. The CPU # 1 that has received the fetch request packet reads a data block including the requested memory data (8-byte processing target data) from the DIMM 20 of the CPU # 1, and returns the data block as a fetch response packet. At this time, the size of the data block is 128 bytes.

  Here, the fetch request packet and the fetch response packet will be described with reference to FIGS. 17A and 17B. FIG. 17A is a diagram showing the format of a packet without data (fetch request packet), and FIG. 17B is a diagram showing the format of a packet with data (fetch response packet).

  The packet includes a packet without data as shown in FIG. 17A and a packet with data as shown in FIG. The fetch request packet transmitted from CPU # 0 to CPU # 1 is a packet without data, and the fetch response packet for the fetch request packet is a packet with data. The head cycle of the packet is a header (HDD) on which information for determining the contents and destination of the packet is placed.

  Furthermore, the headers of the fetch request packet and the fetch response packet will be described with reference to FIGS. FIG. 18A is a diagram showing the format of the header of the fetch request packet, and FIG. 18B is a diagram showing the format of the header of the fetch response packet.

  As shown in FIG. 18A, the header of the fetch request packet includes an Opcode (opcode; OPC) indicating the type of the packet, a Physical Address (physical address; PA or pa) of the memory data requested by the core 11, and the like. , A request ID (RQID) which is an identifier for identifying a packet. As shown in FIG. 18B, the header of the fetch response packet contains information such as OPC and RQID. Note that RSV (reserve) is an unused bit.

  As shown in FIG. 17B, the 128-byte data block including the processing target data requested by the core 11 is divided into 8-byte data after the header and transmitted over 16 cycles. In the fetch response packet, the 8-byte data in each cycle corresponds to the data Data0, Data1,..., DataF at the physical address pa [6: 3] = 0000, 0001,.

  The CPU # 0 (router 14) that has received the fetch response packet from the CPU # 1 registers the data block attached to the fetch response packet in the shared cache 12 of the CPU # 0 and sends the data block to the core 11 that has issued the fetch request. send.

  On the other hand, a transmission error between the CPUs # 0 and # 1 is detected by checking the CRC attached to the packet on the packet receiving side. When a transmission error is detected, packets subsequent to the packet in which the transmission error is detected are discarded, and a NACK (Negative Acknowledgment) is transmitted by using a DLLP (Data Link Layer Packet), whereby the packet is transmitted to the transmitting CPU # 1. Retransmission is required.

  If a packet in which a transmission error has been detected cannot be discarded at the relay point (router; see FIG. 14) or the receiving CPU # 0, the packet is sent with the end of the packet set to EDB.

The router 14 in the receiving CPU # 0 temporarily stores the fetch response packet received from the other CPU # 1 in a buffer (see reference numeral 141 in FIG. 19) in the router 14. The buffer is called a reception buffer. The reception buffer is a FIFO buffer. Here, the reception buffer 141 and packet write / read processing for the reception buffer 141 will be described with reference to FIGS.

  FIG. 19 is a block diagram showing a configuration relating to the reception buffer 141 included in the router 14 and the packet writing / reading process for the reception buffer 141 in the CPU 10 shown in FIG. As shown in FIG. 19, on the write side of the reception buffer 141, WDR (Write Data Register), HDWP (Header Write Pointer) and WP (Write Pointer) are provided. Is provided. The read side of the reception buffer 141 includes an RDR (Read Data Register) and an RP (Read Pointer).

  The WDR is a register for temporarily storing write target data (one unit of data; for example, 8 bytes of data) to be written to the reception buffer 141. The WP controls writing of a packet to be written, and is a pointer that specifies a write destination address in the reception buffer 141 of the write target data stored in the WDR. The WP is set to 0 in an initial state, and is incremented by one every cycle when a write target packet is written to the reception buffer 141. The write target data stored in the WDR is written to an address specified by the WP. HDWP is a pointer that specifies the address of the header of the packet to be written, and is set to 0 in the initial state.

  The RDR is a register for temporarily storing read data (one unit data; for example, 8 byte data) read from the reception buffer 141. The RP controls reading of data from the reception buffer 141, and is a pointer that specifies an address of data to be read from the reception buffer 141. RP is set to 0 in an initial state, and is incremented by one every cycle when data is read from the reception buffer 141. The data at the address specified by the RP is read from the reception buffer 141, temporarily stored in the RDR, registered in the shared cache 12, and transmitted to the core 11 that has issued the fetch request as described above.

  The operation of the configuration (router 14 in CPU # 0) related to the packet writing process shown in FIG. 19 will be described with reference to the flowchart (steps S101 to S107) shown in FIG. The router 14 waits for reception of the header (HD) or data (DT) at the time of writing the packet (NO route in step S101), and receives the header (HD) or data (DT) (YES route in step S101). ), It is determined whether or not EDB has been received (step S102).

  If the EDB has not been received (NO route in step S102), the router 14 determines whether an END indicating the last cycle of the packet has been received (step S103). When the END is received (YES route in step S103), the router 14 sets WP + 1 in HDWP as a value designating the start address (header address) of the next packet to be written (step S104). Thereafter, the router 14 writes the data (or header) in the WDR into the entry of the reception buffer 141 specified by the WP (step S105), then increments the WP by 1 (step S106), and performs the process of step S101. Return to

  When it is determined in step S102 that the EDB has been received (YES route), the router 14 sets HDWP as WP (step S107), and returns to the processing of step S101. As a result, the current packet to be written (the packet with the EDB set at the end) is again written to the reception buffer 141 in order from the beginning (header).

  Next, the operation of the configuration (router 14 in CPU # 0) related to the packet reading process shown in FIG. 19 will be described with reference to the flowchart (steps S111 to S113) shown in FIG. The router 14 determines whether or not the value of the RP matches the value of the HDWP (step S111). When the value of the RP matches the value of the HDWP (YES route in step S111), the router 14 determines that the packet to be written is being written, and returns to the process in step S111.

  When the value of the RP does not match the value of the HDWP (NO route in step S111), the router 14 determines that the writing of the packet to be written is completed, and starts reading the packet from the reception buffer 141 (FIG. 22 timing T18). That is, the router 14 reads an entry (one unit data) of the reception buffer 141 specified by the RP from the reception buffer 141 via the RDR (step S112). Thereafter, the router 14 increments the RP by 1 (step S113), and returns to the process of step S111.

  Here, FIG. 22 shows a time chart of the shortest case of the write / read processing of the fetch response packet to / from the reception buffer 141. As shown in FIG. 22, in the initial state (see timing T0), WE (Write Enable) and RE (Read Enable) are set to the Low state, and WP, HDWP, and RP are set to 0. The packet writing process is started by setting the WE to the high state, and first, the header HD is written to the reception buffer 141 via the WDR (see timing T1).

  Thereafter, every time WP is incremented by one, 16 data DT0 to DTF are sequentially written to the reception buffer 141 via WDR (see timings T2 to T17; see steps S105 and S106 from the NO route of step S103 in FIG. 20). ).

  Then, when the data DTF and END indicating the last cycle of the packet are received at timing T17, WE is set to a low state and RE is set to a high state. Accordingly, at timing T18, a value WP + 1 = 17 indicating the address of the header of the next packet is set as the value of HDWP (from the YES route of step S103 in FIG. 20 to step S104). As a result, the value 17 of the HDWP does not match the value 1 of the RP (NO route of step S111 in FIG. 21), and the packet reading process is started. First, the header HD is read from the reception buffer 141 via the RDR ( (See timing T18).

  Thereafter, every time the RP is incremented by one, 16 data DT0 to DTF are sequentially read from the reception buffer 141 via the RDR (see timings T19 to T34; see steps S112 and S113 from the NO route of step S111 in FIG. 21). . Such a reading process is executed until the value of HDWP matches the value of RP at timing T34 (that is, until it is determined as YES in step S111 in FIG. 21). In the example shown in FIG. 22, the value of HDWP and the value of RP coincide at 17 at timing T34.

  As described above with reference to FIGS. 20 to 22, the packet reading process is started after the last unit data is written in the last cycle of the packet. This is because if the last cycle (end) of the packet is EDB, the packet needs to be discarded.

  Next, a time chart when the end of the received fetch response packet is EDB is shown in FIG. FIG. 23 illustrates a case where EDB is detected at the timing of writing timing T10 of packet data DT8 according to the same procedure as in FIG. In this case, at timing T11, the value of HDWP (0 in FIG. 23) is stored as the value of WP (see step S107 from the YES route of step S102 in FIG. 20).

  As a result, the current packet to be written (the packet with the EDB set at the end) is again written to the reception buffer 141 in order from the beginning (header) without performing the reading process from the reception buffer 141. At that time, the packet with the EDB set at the end is overwritten by the subsequent packet.

[2] Overview of the present embodiment As described above, in the network 30 using high-speed serial transmission, transmission errors are checked by CRC. When a transmission error is detected, the end of the packet is rewritten to EDB. Therefore, the endpoint (CPU # 0) cannot determine whether the packet is normal unless all data up to the end of the packet including the response data (processing target data) is received.

  Therefore, in the CPU # 0 which has issued the fetch request, all data up to the end of the packet including the response data corresponding to the fetch request is temporarily stored in the reception buffer 141, and then the data in the reception buffer 141 From the core 11.

  However, since the reception buffer 141 is a FIFO, when the processing target data (one unit data; for example, 8 byte data) requested by the core 11 is read from the reception buffer 141, the data immediately before the unit data is read. Wait until. For this reason, the communication latency increases when viewed from the core 11, and the processing performance of the CPU # 0 and the processing performance of the information processing apparatus (multiprocessor system) including the CPU # 0 may be reduced.

  Therefore, in a multiprocessor system connected by the high-speed serial transmission network 30, it is desired to reduce the read latency of data to be processed requested by the core 11.

  Therefore, in the present embodiment (first and second embodiments), for example, of the 128-byte data block in the fetch response packet read and transferred from another CPU 10, the 8-byte data block required by the core 11 is used. The processing target data is first read from the reception buffer 141 and sent to the core 11. As a result, the communication latency (read latency of data to be processed) viewed from the core 11 is reduced.

  That is, in the information processing apparatus according to the first embodiment to be described later, all the response packets to the fetch request are written to the reception buffer 141 of the endpoint similarly to the related art described above. The endpoint is the receiving CPU 10A (see FIG. 1; first processing unit, CPU # 0) connected to the high-speed serial transmission network 30 and receiving the fetch response packet. However, in the information processing apparatus according to the first embodiment, as described later with reference to FIGS. 1 to 7, when reading a packet from the reception buffer 141 after writing the packet, the order in which the packet is written into the reception buffer 141 is as follows. Instead, the 8-byte process target data requested by the core 11 is read first.

  Since the information processing apparatus according to the first embodiment, which will be described later, first reads 8-byte processing target data requested by the core 11, the fetch response packet includes a physical address (pa [6]) indicating the processing target data requested by the core 11. : 3]) (see FIGS. 2 and 3). At the end point, an HDRP (header read pointer), a Length register, and a CycleCT (cycle counter), which will be described later, are added to the configuration (see RP and RDR in FIG. 19) relating to the packet read processing of the related art described above. (See the reading unit 143 in FIGS. 4 and 5). By controlling the RP using the HDRP, the Length register, and the CycleCT, the 8-byte processing target data required by the core 11 can be read first (see FIGS. 5 to 7).

  In this way, by reading the data to be processed requested from the core 11 of the CPU 10A from the reception buffer 141 at the head, the read latency is reduced. For example, when the processing target data requested by the core 11 is the tail of the packet, by reading the processing target first, the latency can be reduced by [the number of cycles of the data portion of the packet −1]. Conversely, if the processing target data is at the head of the packet, the latency does not change. In other words, the number of cycles of latency reduction varies depending on the order of the packet data to be processed. Therefore, on average, it is possible to reduce the latency by about [the number of cycles of the data portion of the packet-1] / 2.

  In a second embodiment described later with reference to FIG. 1 and FIGS. 8 to 13, in stride access generated by matrix calculation or the like, necessary unit data (processing target data) is included in one packet with data. This is a technique corresponding to a case where there are a plurality of. When handling an array in a matrix calculation or the like, the core 11 requests a plurality of unit data at addresses spaced at a fixed interval shorter than the packet length, and the plurality of unit data are included in one packet.

  In such a case, in the second embodiment, when reading out a packet from the reception buffer 141, a necessary plurality of unit data is packed before the other unit data (leading side) and transmitted, so that a necessary plurality of unit data are transmitted. Is read out before the other unit data. As a result, the latency as viewed from the core 11 of the CPU 10A is significantly reduced.

[3] Information Processing Device of First Embodiment With reference to FIG. 1, the configuration of an information processing device (multiprocessor system) 1 including arithmetic processing units (CPUs) 10A and 10B as a first embodiment of the present invention will be described. explain. FIG. 1 is a block diagram showing the configuration.

  As shown in FIG. 1, the information processing apparatus 1 according to the first embodiment is a multiprocessor system having a plurality of (two in FIG. 1) CPUs 10A and 10B, and is, for example, a PC or a server. The CPU 10A corresponds to a first arithmetic processing device, and may be referred to as a receiving CPU or CPU # 0 in some cases. The CPU 10B corresponds to a second arithmetic processing unit, and may be referred to as a transmitting CPU or a CPU # 1 in some cases. Although the information processing apparatus 1 according to the first embodiment includes two CPUs, the present invention is not limited to this, and may include three or more CPUs.

  The CPU 10A and the CPU 10B are communicably connected to each other via a network 30 using high-speed serial transmission.

  The CPU 10A is a multi-core processor including a plurality of cores 11A, like the CPU 10 shown in FIG. In the CPU 10A, a plurality of cores 11 are connected via a shared cache (tertiary cache) 12A. In FIG. 1, N + 1 cores # 0 to #N (N is an integer of 1 or more) are provided as the core 11A. In FIG. 1, a primary cache (not shown) and a secondary cache (not shown) are built in each core 11, and a tertiary cache is used as a shared cache 12A. However, a primary cache is built in each core 11A, A secondary cache may be used as the shared cache 12A.

  The MAC 13A and the router 14A are connected to the shared cache 12A in addition to the core 11A. The MAC 13A is connected to the DIMM 20A functioning as a main memory, and functions as a control unit that controls data exchange with the DIMM 20A. The router 14A is connected to another CPU 10B or another router (for example, a routing LSI; see FIG. 14), and functions as a first communication unit that performs data communication with the other CPU 10B by a packet.

  The CPU 10B has a core 11B, a shared cache (tertiary cache) 12B, a MAC 13B, and a router 14B. The core 11B, the shared cache 12B, the MAC 13B, and the router 14B are the same as the above-described core 11A, shared cache 12A, MAC 13A, and router 14A of the CPU 10A, respectively. However, the MAC 13B is connected to the DIMM 20B functioning as a main memory, and functions as a control unit that controls data exchange with the DIMM 20B. The router 14B is connected to another CPU 10A or another router (for example, a routing LSI; see FIG. 14), and functions as a second communication unit that performs data communication with the other CPU 10A by a packet.

  At least one of the plurality of cores (processing units) 11A in the CPU 10A generates a read request for necessary processing target data (for example, 8-byte unit data). Hereinafter, the read request may be referred to as a fetch request.

  The router (first communication unit) 14A in the CPU 10A transmits a fetch request generated by one core 11A to the CPU 10B by a fetch request packet (see FIGS. 2 and 17A). Further, the router (first communication unit) 14A receives from the CPU 10B a fetch response packet (see FIGS. 2 and 17B) to which a data block including data to be processed corresponding to the fetch request is attached.

  On the other hand, the router (second communication unit) 14B in the CPU 10B receives a fetch request from the CPU 10A by a fetch request packet (see FIGS. 2 and 17A). Further, the router (second communication unit) 14B transmits to the CPU 10A a fetch response packet (see FIGS. 2 and 17B) to which a data block including processing target data corresponding to the fetch request is attached.

  In particular, in the first embodiment, the router (second communication unit) 14B of the CPU 10B performs processing extracted from the address information (see PA in FIG. 18A) included in the fetch request (the header of the fetch request packet). A response header recording the address information pa [6: 3] of the target data is added to the data block. Here, the response header is, for example, a header of a fetch response packet described later with reference to FIG. Then, the router (second communication unit) 14B transmits the data block to which the response header is added to the CPU 10A as a fetch response packet (see FIGS. 2 and 17B).

  The router (first communication unit) 14A of the CPU 10A includes a reception buffer 141, a writing unit 142, and a reading unit 143. In the first embodiment, the receiving buffer 141, the writing unit 142, and the reading unit 143 are provided in the router 14A of the CPU 10A, but may be provided in the CPU 10A.

  The reception buffer (buffer) 141 stores a packet with data to which a data block is attached as unit data (for example, 8 bytes).

  The writing unit 142 sequentially writes a plurality of unit data included in the packet (header and data block) received by the router 14A into the reception buffer 141. The writing unit 142 of the first embodiment has the same configuration as the related art shown in FIG. 19, as described later with reference to FIG.

  The reading unit 143 preferentially reads, from the reception buffer 141, the processing target data that is at least one of the plurality of unit data included in the packet. In particular, the reading unit 143 of the first embodiment refers to the address information pa [6: 3] of the processing target data recorded in the response header attached to the data block. Then, the reading unit 143 first reads the processing target data corresponding to the referenced address information pa [6: 3] from the reception buffer 141, and then sequentially reads unit data other than the processing target data from the reception buffer 141. . The reading unit 143 of the first embodiment is configured as described below with reference to FIGS. 4 and 5, and operates as described below with reference to FIGS. 6 and 7.

  In the first embodiment, the CPU 10A has a function as a first communication unit and a function as a reception buffer 141, a writing unit 142, and a reading unit 143, and the CPU 10B has a function as a second communication unit. The case of having a function is described. However, each of the plurality of CPUs 10A and 10B may have a function as the first and second communication units and a function as the reception buffer 141, the writing unit 142, and the reading unit 143.

  Here, with reference to FIG. 2, a description will be given of packet routing when the information processing device 1 shown in FIG. 1 issues a fetch request for the memory data of the other CPU 10B from the core 11A of one CPU 10A.

  In this case, as shown in FIG. 2, a fetch request packet (data-less packet) for reading necessary processing target data is issued and transmitted from the CPU 10A, and the memory 20B holding the processing target data via the network 30. Is routed to the CPU 10B having Upon receiving the fetch request packet by the router 14B, the CPU 10B reads a data block including the requested processing target data from the memory 20B, generates a fetch response packet (packet with data), and transmits the fetch response packet to the CPU 10A.

  At this time, the format of the header (response header) of the fetch response packet generated by the CPU 10B is shown in FIG. As shown in FIG. 3, in the first embodiment, a 4-bit physical address pa [6: 3] capable of specifying the unit data (processing target data) to be fetched is placed in the header of the fetch response packet. I have. The 4-bit physical address pa [6: 3] specifies which unit data of a plurality of unit data (for example, 16 8-byte data) in the data block included in the fetch response packet is requested by the core 11A on the CPU 10A side. This is information for identifying whether or not the information has been written.

  When the CPU 10B generates the fetch response packet, the physical address PA (see FIG. 18A) described in the header of the fetch request packet indicates the 4-bit physical address pa [6] that can specify the unit data to be fetched. : 3] is taken out. By including the extracted physical address pa [6: 3] in the header described above with reference to FIG. 18B, a response header having a format as shown in FIG. 3 is generated. The fetch response packet having the response header generated in this way is routed and transmitted to the CPU 10A that has issued the fetch request, as shown in FIG.

  The fetch response packet received by the CPU 10A is first written into the reception buffer 141 provided in the router 14A by the writing unit 142 (see FIGS. 1 and 4) once for each unit data. Thereafter, by controlling the value of the RP (the address of the unit data to be read) in the reading unit 143 ′, the processing target data requested by the core 11A among the packets written in the reception buffer 141 is transmitted from the reception buffer 141. Read out preferentially. FIG. 4 is a block diagram showing reception buffer 141 included in router 14A in CPU 10A shown in FIG. 1 and a configuration (a writing unit 142 and a reading unit 143) relating to packet writing / reading processing for reception buffer 141.

  As illustrated in FIG. 4, the writing unit 142 according to the first embodiment has the same WDR, HDWP, and WP as the configuration related to the packet writing process on the reception buffer 141 according to the related art illustrated in FIG. Further, the reading unit 143 of the first embodiment includes an HDRP (Header Read Pointer) in addition to the same RDR and RP as the configuration related to the packet writing process to the reception buffer 141 of the related art shown in FIG. , Length register and CycleCT (Cycle Counter).

  The WDR is a register for temporarily storing write target data (one unit of data; for example, 8 bytes of data) to be written to the reception buffer 141. The WP controls writing of a packet to be written, and is a pointer that specifies a write destination address in the reception buffer 141 of the write target data stored in the WDR. The WP is set to 0 in an initial state, and is incremented by one every cycle when a write target packet is written to the reception buffer 141. The write target data stored in the WDR is written to an address specified by the WP. HDWP is a pointer that specifies the address of the header of the packet to be written, and is set to 0 in the initial state.

  The RDR is a register for temporarily storing read data (one unit data; for example, 8 byte data) read from the reception buffer 141. The RP controls reading of data from the reception buffer 141, and is a pointer that specifies an address of data to be read from the reception buffer 141. RP is set to 0 in an initial state, and is incremented by one every cycle when data is read from the reception buffer 141. The data at the address specified by the RP is read from the reception buffer 141, temporarily stored in the RDR, registered in the shared cache 12A and transmitted to the core 11 that has issued the fetch request as described above.

  HDRP is a pointer indicating the address of the header of the packet being read from the reception buffer 141, and is set to 0 in the initial state. In the Length register, the data length (packet length) Length of the packet being read from the reception buffer 141 is set. The data length Length set in the Length register is generated and set from the Opcode (packet type) in the header by the Length generation unit 143a (see FIG. 5) when the header is read from the reception buffer 141. CycleCT is a counter indicating the number of unit data of the unit data of the packet being read from the reception buffer 141, and is incremented by one every cycle, that is, each time one unit data is read.

  Next, the configuration related to the packet reading process shown in FIG. 4, that is, the reading unit 143 will be described in more detail with reference to FIG. FIG. 5 is a block diagram illustrating a detailed configuration of the reading unit 143. The reading unit 143 shown in FIG. 5 operates as described later with reference to FIGS. As shown in FIG. 5, the reading unit 143 of the first embodiment includes a length generating unit 143a, 1 adders 143b and 143d, adders 143c, 143e and 143f, and a selector 143g.

  As described above with reference to FIG. 4, when reading the header from the reception buffer 141, the Length generation unit 143a generates the data length Length of the packet being read from the reception buffer 141 from the Opcode in the header, Set in the Length register.

  The 1 adder (+1) 143b adds 1 to a value indicated by HDRP (hereinafter, referred to as HDRP).

  The adder 143c adds the data length Length in the Length register and the value HDRP + 1 from the one adder 143b, and sets the obtained value HDRP + Length + 1 to HDRP (see step S24 in FIG. 6). The operation timing of the adder 143c is the timing at which the value indicated by CycleCT (hereinafter, referred to as CycleCT) becomes the data length Length and resets (initializes) CycleCT (see step S22 in FIG. 6 and timing T34 in FIG. 7). is there.

  The one adder (+1) 143d adds 1 to a value indicated by RP (hereinafter, referred to as RP).

  The adder 143e adds the physical address pa [6: 3] specifying the processing target data requested by the core 11A and the value RP + 1 from the one adder 143d, and obtains the obtained value RP + pa [6: 3] +1. Is set to the RP (see step S16 in FIG. 6). The physical address pa [6: 3] is read from the header of the packet being read via the RD-BUS (read bus). The operation timing of the adder 143e is the timing of reading the header from the fetch response packet (YES route in step S15 in FIG. 6; see timing T18 in FIG. 7). At this timing, the selector 143g performs a switching operation to set the value RP + pa [6: 3] +1 obtained by the adder 143e to RP (see (1) in FIGS. 5 to 7).

  The adder 143f adds the data length Length in the Length register and the value HDRP + 1 from the one adder 143b, and sets the obtained value HDRP + Length + 1 to RP (see step S23 in FIG. 6). The operation timing of the adder 143f is a timing at which CycleCT becomes the data length Length and resets (initializes) CycleCT (Step S22 in FIG. 6; see timing T34 in FIG. 7). At this timing, the selector 143g performs a switching operation to set the value HDRP + Length + 1 obtained by the adder 143f to RP (see (4) in FIGS. 5 to 7).

  The selector 143g performs a switching operation to set the value RP + 1 obtained by the one adder 143d to RP (see (2) in FIGS. 5 to 7). The timing for performing the switching operation is when the Opcode of the header is not a fetch response (see the NO route in step S15 in FIG. 6), or when the RP does not match HDRP + Length (NO route in step S19 in FIG. 6; FIG. 7). Timings T19 to T23 and T25 to T33).

  Further, the selector 143g performs a switching operation so that the value HDRP + 1 obtained by the one adder 143b is set to RP (see (3) in FIGS. 5 to 7). The timing at which the switching operation is performed is a timing at which RP matches HDRP + Length (YES route in step S19 in FIG. 6; see timing T24 in FIG. 7).

  The functions of the writing unit 142 and the reading unit 143 described above may be realized by being incorporated in the CPU 10A in hardware by a logic gate or the like, or may be implemented in the CPU 10A by software by executing a program. And may be realized.

  Next, operations of the writing unit 142 and the reading unit 143 configured as described above will be described with reference to FIGS. FIG. 6 is a flowchart illustrating the operation of the configuration (reading unit 143) related to the packet reading process shown in FIG. FIG. 7 is a time chart showing an operation when the configuration (reading unit 143) related to the packet reading process shown in FIGS. 4 and 5 first reads the tenth data (DTA) according to the flowchart shown in FIG.

  The packet write operation performed by the write unit 142 according to the first embodiment is the same as the operation of the related art described above with reference to FIG. On the other hand, the packet reading operation by the reading unit 143 of the first embodiment is different from the operation of the related art described above with reference to FIG.

  Here, the packet reading operation by the reading unit 143 according to the first embodiment will be described with reference to FIGS. 5 and 7 according to the flowchart (steps S11 to S24) shown in FIG.

  The router 14A determines whether the value of RP matches the value of HDWP (step S11). When the value of the RP matches the value of the HDWP (YES route in step S11), the router 14A determines that the packet to be written is being written, and returns to the process in step S11.

  If the value of RP does not match the value of HDWP (NO route in step S11), the router 14A determines that the writing of the packet to be written has been completed, and starts reading the packet from the reception buffer 141 (FIG. 7, timing T18). That is, the entry (one unit data) of the reception buffer 141 specified by the RP is read from the reception buffer 141 via the RDR (step S12). Then, it is determined whether the read entry is a header (HD) (step S13).

  At the start of packet reading, the header of the packet is first read, so that the read entry is determined to be the header (YES route in step S13). In this case, the read header Opcode is referred to, the data length Length of the packet being read from the reception buffer 141 is generated based on the Opcode (packet type), and the generated data length Length is read by the reading unit 143. This is set in the Length register (step S14).

  Thereafter, it is determined whether or not the Opcode is a fetch response (step S15). If the response is a fetch response (YES route in step S15), the selector 143g performs a switching operation to select (1) in FIG. Thus, the value RP + pa [6: 3] +1 obtained by the adder 143e is set to RP (step S16), and CycleCT is incremented by 1 (step S17). Then, the entry (data DTA) specified by the value (address) set in the RP is read (from the NO route of step S11 to step S12). That is, when the header of the packet is read, the address RP + pa [6: 3] +1 of the reception buffer 141 corresponding to the data requested by the core 11A is set to the RP based on the physical address pa [6: 3] of the header. Is set. In the example shown in FIG. 7, 11 indicating the address corresponding to the tenth data DTA is set in RP.

  Thereafter, in the next cycle, the entry to be read next to the header is data. In this case (NO route in step S13), it is determined whether the value of CycleCT has reached the data length (packet length) Length. (Step S18). That is, it is determined whether or not all the data of the read target packet has been read. FIG. 7 shows an example in which Length = 16.

  If CycleCT is not Length (NO route in step S18), it is determined whether the value of RP has reached the value HDRP + Length (value 16 in FIG. 7) (step S19). When RP is not HDRP + Length (NO route in step S19), or when the Opcode of the header is not a fetch response (NO route in step S15), the selector 143g performs a switching operation to select (2) in FIG. Thus, each time one unit of data is read (see timings T19 to T23 in FIG. 7) until the value of RP reaches the value HDRP + Length, the value of RP is incremented by 1 (step S20), and after CycleCT is incremented by 1 (Step S17), the process returns to step S11.

  When the value of RP reaches the value HDRP + Length (YES route in step S19), the selector 143g performs a switching operation to select (3) in FIG. As a result, the value HDRP + 1 obtained by the one adder 143b is set to RP (step S21), and CycleCT is incremented by one (step S17). For example, at timing T24 in FIG. 7, since HDRP = 0, 1 is set to RP. Thereafter, the process returns to step S11.

  In each cycle after setting the value HDRP + 1 in RP (see timings T25 to T33 in FIG. 7), the selector 143g continues until the value of CycleCT reaches the data length Length, that is, until all the data of the read target packet is read. Performs a switching operation to select (2) in FIG. Thus, each time one unit of data is read, the value of RP is incremented by 1 until the value of CycleCT reaches the data length Length (step S20), and after the CycleCT is incremented by 1 (step S17), the process proceeds to step S11. Return to

  When the value of CycleCT reaches the data length Length (YES route in step S18; see timing T34 in FIG. 7), the value of CycleCT is reset to 0 (step S22). Then, the selector 143g performs a switching operation so as to select (4) in FIG. Thus, the value HDRP + Length + 1 (value 17 in FIG. 7) obtained by the adder 143f is set in RP as the address of the data to be read next (step S23). The value HDRP + Length + 1 (value 17 in FIG. 7) obtained by the adder 143c is set in HDRP as the address of the header of the packet to be read next (step S24). Thereafter, the process returns to step S11.

  According to the above operation, in the first embodiment, the data DTA can be read ten cycles earlier than in the case of the related art shown in FIG. 22, and the latency is reduced.

  In the above-described operation, the order of data to be read is uniquely determined by the physical address pa [6: 3]. Therefore, the core 11A that has received the packet can easily determine which physical address is the data other than the data read first from the packet in the reception buffer 141.

[4] Information Processing Apparatus of Second Embodiment Next, an information processing apparatus (multiprocessor system) 1 ′ according to a second embodiment of the present invention will be described with reference to FIGS. 1 and 8 to 13. The second embodiment described here is a technique corresponding to a case where a plurality of processing target data exists at a predetermined interval Interval in one data block. That is, as described above, the second embodiment is a technique corresponding to a case where a plurality of necessary unit data (processing target data) exist in one packet with data in a stride access generated by a matrix calculation or the like. It is. For example, in the example illustrated in FIG. 13, a case is described in which four processing target data DT2, DT6, DTA, and DTE exist at a predetermined interval Interval = 4 in a packet including 16 8-byte data DT0 to DTF. explain.

  As shown in FIG. 1, the information processing apparatus 1 'of the second embodiment also has a plurality (two in FIG. 1) of CPUs 10A and 10B, similarly to the information processing apparatus 1 of the first embodiment. Also in the second embodiment, the CPU 10A and the CPU 10B are communicably connected to each other via the network 30 using high-speed serial transmission.

  The CPUs 10A and 10B in the information processing device 1 'have the same configuration as the CPUs 10A and 10B in the information processing device 1 described above with reference to FIGS. However, in the information processing apparatus 1 'of the second embodiment, as described below, the function of the CPU 10A as a first communication unit of the router 14A and the function of the CPU 10B as a second communication unit of the router 14B. Some changes are made to. Further, in the information processing apparatus 1 'of the second embodiment, as described below, the reading unit 143 in the CPU 10A (router 14A) is changed to a reading unit 143' (see FIGS. 1, 10, and 11). ing.

  Similarly to the first embodiment, the router (first communication unit) 14A in the CPU 10A of the second embodiment also transmits a fetch request generated by one core 11A to a fetch request packet (see FIGS. 9 and 17A). To the CPU 10B. Also, the router (first communication unit) 14A receives from the CPU 10B a fetch response packet (see FIGS. 9 and 17B) to which a data block including the processing target data corresponding to the fetch request is attached.

  However, the header of the fetch request packet transmitted from the router (first communication unit) 14A in the CPU 10A of the second embodiment to the CPU 10B has a format as shown in FIG. That is, in the header of the fetch request packet, in addition to the OPC, RQID, and physical address PA described above with reference to FIG. 18A, information on the predetermined interval (here, a value Interval indicating the predetermined interval) is included. It is.

  The router (second communication unit) 14B in the CPU 10B of the second embodiment reads a response header having a format as shown in FIG. 8B from a fetch response packet (DIMM 20B or the like) transmitted to the CPU 10A. Data block). As shown in FIG. 8B, the response header includes the address information pa [of the head processing target data extracted from the address information (see PA in FIG. 8A) included in the header of the fetch request packet. 6: 3] and a predetermined interval Interval are recorded. Then, the router (second communication unit) 14B transmits the data block to which the response header is added to the CPU 10A as a fetch response packet (see FIGS. 9 and 17B).

  Further, the router (first communication unit) 14A in the CPU 10A of the second embodiment has a reception buffer 141, a writing unit 142, and a reading unit 143 '. In the second embodiment, the receiving buffer 141, the writing unit 142, and the reading unit 143 'are provided in the router 14A of the CPU 10A, but may be provided in the CPU 10A. The reception buffer 141 and the writing unit 142 are configured in the same manner as the reception buffer 141 and the writing unit 142 of the first embodiment described above with reference to FIGS.

  The reading unit 143 'refers to the physical address pa [6: 3] and the predetermined interval Interval of the head processing target data recorded in the response header attached to the data block (fetch response packet). Then, the reading unit 143 'reads a plurality of processing target data requested by the core 11A from the reception buffer 141 based on the referred physical address pa [6: 3] and the predetermined interval Interval, and then reads the plurality of processing target data. The unit data other than the processing target data is sequentially read from the reception buffer 141. The reading unit 143 'in the second embodiment is configured as described below with reference to FIGS. 10 and 11, and operates as described below with reference to FIGS.

  In the second embodiment, the CPU 10A has a function as a first communication unit and a function as a reception buffer 141, a writing unit 142, and a reading unit 143 ', and the CPU 10B is a second communication unit. Is described. However, each of the plurality of CPUs 10A and 10B may have a function as the first and second communication units and a function as the reception buffer 141, the writing unit 142, and the reading unit 143 '.

  Here, with reference to FIG. 9, in the information processing apparatus 1 'of the second embodiment, a description will be given of packet routing when a fetch request for stride access is issued from the core 11A of one CPU 10A to the memory data of another CPU 10B. I do.

  In this case, as shown in FIG. 9, a fetch request packet (data-less packet) for reading necessary processing target data is issued and transmitted from the CPU 10A, and the memory 20B holding the processing target data via the network 30. Is routed to the CPU 10B having At this time, as shown in FIG. 8A, at least the address information PA of the processing target data and the predetermined interval Interval related to the stride access are included in the header of the fetch request packet.

  On the other hand, upon receiving the fetch request packet by the router 14B, the CPU 10B reads the data block including the requested processing target data from the memory 20B, generates a fetch response packet (packet with data), and transmits the fetch response packet to the CPU 10A. I do. At this time, as shown in FIG. 8B, the header (response header) of the fetch response packet generated by the CPU 10B includes a 4-bit data that can specify the head unit data (process target data) of the stride access target. The physical address pa [6: 3] is placed. Further, as shown in FIG. 8B, a predetermined interval Interval related to stride access is also carried in the header.

  When the CPU 10B generates the fetch response packet, the physical address PA (see FIG. 8A) described in the header of the fetch request packet indicates the 4-bit physical address pa [ 6: 3] is taken out. Also, a predetermined interval Interval related to the stride access is extracted from the header. By including the extracted physical address pa [6: 3] and the predetermined interval Interval in the response header, a response header having a format as shown in FIG. 8B is generated. The fetch response packet having the response header generated in this way is routed and transmitted to the CPU 10A that has issued the fetch request, as shown in FIG.

  As described above, in the second embodiment, the Interval indicating the address interval when the core 11A performs the stride access to the memory 20B is added to both the header of the fetch request packet and the header of the fetch response packet. Here, for example, when the number of unit data (8-byte data) included in the data block (128-byte data) is 16, the value of the predetermined interval Interval is an integer in the range of 0 <Interval <16. This is because when Interval = 0, the same unit data is selected, while when Interval = 16, the range exceeds the data block (16 unit data) included in the packet. .

  The fetch response packet received by the CPU 10A is first written into the reception buffer 141 provided in the router 14A by the writing unit 142 (see FIGS. 1 and 10) once for each unit data. Thereafter, by controlling the value of the RP (the address of the unit data to be read) in the reading unit 143 ′, of the packets written in the reception buffer 141, the processing target data requested by the core 11 A has priority over the reception buffer 141. Is read out.

  In particular, the reading unit 143 'in the second embodiment performs a plurality of processings requested by the core 11A based on the physical address pa [6: 3] of the first processing target data and the predetermined interval recorded in the response header. After the target data is read from the reception buffer 141, other data is sequentially read from the reception buffer 141.

  Hereinafter, a configuration of the second embodiment that realizes the above-described functions will be described with reference to FIGS. 10 and 11. FIG. 10 is a block diagram showing a reception buffer 141 included in the router 14A in the CPU 10A according to the second embodiment, and a configuration (a writing unit 142 and a reading unit 143 ') relating to packet writing / reading processing for the reception buffer 141. is there. FIG. 11 is a block diagram showing in detail the configuration (reading unit 143 ') relating to the packet reading process shown in FIG.

  As illustrated in FIG. 10, the writing unit 142 according to the second embodiment has the same WDR, HDWP, and WP as the writing unit 142 illustrated in FIG.

  The read unit 143 'of the second embodiment has an Interval register in addition to the same RDR, RP, HDRP, Length register and CycleCT as the read unit 143 shown in FIG. The WDR, HDWP, WP, RDR, RP, HDRP, Length register, and CycleCT are the same as those described above, and a description thereof will be omitted.

  In the Interval register added in the second embodiment, when the header (response header) of the fetch response packet is read from the reception buffer 141, a predetermined interval Interval recorded in the header is set. Note that for packets other than the fetch response packet, the packet type is set to 1 as the Interval value.

  Next, the configuration relating to the packet reading process shown in FIG. 10, that is, the reading unit 143 'will be described in more detail with reference to FIG. As shown in FIG. 11, the reading unit 143 'of the second embodiment includes a length generating unit 143a, one adders 143b and 143d, and adders 143c, 143e and 143f, and a selector similar to the reading unit 143 of the first embodiment. 143g and an adder 143h and a calculator 143i.

  As in the first embodiment, when reading the header from the reception buffer 141, the Length generation unit 143a generates the data length of the packet being read from the reception buffer 141 from the Opcode in the header and sets the data length in the Length register. I do.

  The 1 adder (+1) 143b adds 1 to the value indicated by HDRP, as in the first embodiment.

  As in the first embodiment, the adder 143c adds the data length Length in the Length register and the value HDRP + 1 from the one adder 143b, and sets the obtained value HDRP + Length + 1 to HDRP (see step S45 in FIG. 12). ). The operation timing of the adder 143c is the timing at which the value indicated by CycleCT becomes the data length Length and resets (initializes) CycleCT (see step S43 in FIG. 12 and timing T34 in FIG. 13).

  The 1 adder (+1) 143d adds 1 to the value indicated by RP, as in the first embodiment.

  As in the first embodiment, the adder 143e adds the physical address pa [6: 3] specifying the first processing target data requested by the core 11A and the value RP + 1 from the one adder 143d, and obtains the result. The value RP + pa [6: 3] +1 is set to RP (see step S37 in FIG. 12). The physical address pa [6: 3] is read from the header of the packet being read via the RD-BUS. The operation timing of the adder 143e is the timing of reading the header from the fetch response packet (YES route in step S36 in FIG. 12; see timing T18 in FIG. 13). At this timing, the selector 143g performs a switching operation so as to set the value RP + pa [6: 3] +1 obtained by the adder 143e to RP (see (1) in FIGS. 11 to 13).

  As in the first embodiment, the adder 143f adds the data length Length in the Length register and the value HDRP + 1 from the one adder 143b, and sets the obtained value HDRP + Length + 1 to RP (see step S44 in FIG. 12). ). The operation timing of the adder 143f is the timing at which the CycleCT becomes the data length Length and resets (initializes) the CycleCT (step S43 in FIG. 12; see timing T34 in FIG. 13). At this timing, the selector 143g performs a switching operation so as to set the value HDRP + Length + 1 obtained by the adder 143f to RP (see (4) in FIGS. 11 to 13).

  The adder 143h added in the second embodiment adds a predetermined interval Interval in the Interval register and the value of RP, and sets the obtained value RP + Interval to RP (see step S41 in FIG. 12). The operation timing of the adder 143h is when the Opcode of the header is not a fetch response (see NO route in step S36 in FIG. 12) or when RP + Interval is equal to or less than HDRP + Length (NO route in step S40 in FIG. 12; FIG. 13). Timings T19 to T21, T23 to T25, T27 to T29, and T31 to T32. At this timing, the selector 143g performs a switching operation to set the value RP + Interval obtained by the adder 143h to RP (see (2) in FIGS. 11 to 13).

  The arithmetic unit 143i added in the second embodiment is configured such that a value HDRP + [(RP−HDRP + 1)% Interval is obtained based on a predetermined interval Interval in the Interval register, the value HDRP + 1 from the one adder 143b, and the value of RP. ] Is calculated and the value is set to RP (see step S42 in FIG. 12). The operation timing of the arithmetic unit 143i is a timing when RP + Interval exceeds HDRP + Length (YES route in step S40 in FIG. 12; see timings T22, T26, and T30 in FIG. 13). At this timing, the selector 143g performs a switching operation so as to set the value obtained by the calculator 143i to RP (see (3) in FIGS. 11 to 13). Note that% in the above value is a symbol used in the operation for giving the remainder, and is defined as remainder = dividend% divisor. For example, 16% 4 = 4, 17% 4 = 1, and 14% 4 = 2.

  The functions of the writing unit 142 and the reading unit 143 'described above may be implemented by being incorporated in the CPU 10A in hardware by a logic gate or the like, or may be implemented in software by executing a program. It may be realized by being incorporated.

  Next, the operations of the writing unit 142 and the reading unit 143 'configured as described above will be described with reference to FIGS. FIG. 12 is a flowchart for explaining the operation of the configuration (reading unit 143 ') relating to the packet reading process shown in FIG. FIG. 13 shows that the configuration (reading unit 143 ') relating to the packet reading process shown in FIGS. 10 and 11 converts the second, sixth, tenth, and fourteenth data (DT2, DT6, DTA, DTE) according to the flowchart shown in FIG. 6 is a time chart showing an operation when reading is performed first.

  The packet writing operation performed by the writing unit 142 according to the second embodiment is the same as the operation of the related art described above with reference to FIG. On the other hand, the packet reading operation by the reading unit 143 'of the second embodiment is partially different from the operation of the reading unit 143 of the first embodiment described above with reference to FIG.

  The packet reading operation by the reading unit 143 'of the second embodiment will be described with reference to FIGS. 11 and 13 according to the flowchart (steps S31 to S45) shown in FIG.

  The router 14A determines whether the value of RP matches the value of HDWP (step S11). If the value of RP matches the value of HDWP (YES route in step S31), the router 14A determines that the packet to be written is being written, and returns to the process in step S31.

  If the value of RP does not match the value of HDWP (NO route in step S31), the router 14A determines that the writing of the packet to be written has been completed, and starts reading the packet from the reception buffer 141 (FIG. 13 timing T18). That is, the entry (one unit data) of the reception buffer 141 specified by the RP is read from the reception buffer 141 via the RDR (step S32). Then, it is determined whether the read entry is a header (HD) (step S33).

  At the start of packet reading, the header of the packet is first read, so that the read entry is determined to be the header (YES route in step S33). In this case, the predetermined interval Interval of the read header is referred to, and the value of the Interval is set in the Interval register of the reading unit 143 'from the header (step S34). In addition, the read header Opcode is referred to, the data length Length of the packet being read from the reception buffer 141 is generated based on the Opcode (packet type), and the generated data length Length is read by the reading unit 143 ′. It is set in the Length register (step S35).

  Thereafter, it is determined whether or not the Opcode is a fetch response (step S36). If the response is a fetch response (YES route in step S36), the selector 143g performs a switching operation to select (1) in FIG. Thereby, the value RP + pa [6: 3] +1 obtained by the adder 143e is set to RP (step S37), and CycleCT is incremented by 1 (step S38). Then, the entry (data DT2) specified by the value (address) set in the RP is read (from the NO route of step S31 to step S32). That is, when the header of the packet is read, the address RP + pa [6: 3 of the reception buffer 141 corresponding to the data (head unit data) requested by the core 11A based on the physical address pa [6: 3] of the header. ] +1 is set in the RP. In the example shown in FIG. 13, 3 indicating the address corresponding to the second data DT2 is set in RP.

  Thereafter, in the next cycle, the entry read out after the header is data. In this case (NO route in step S33), it is determined whether the value of CycleCT has reached the data length (packet length) Length. (Step S39). That is, it is determined whether or not all the data of the read target packet has been read. FIG. 13 shows an example in which Length = 16.

  If CycleCT = Length is not satisfied (NO route in step S39), it is determined whether the value RP + Interval exceeds the value HDRP + Length (value 16 in FIG. 13) (step S40). When RP + Interval is equal to or less than HDRP + Length (NO route in step S40), or when the Opcode of the header is not a fetch response (NO route in step S36), the selector 143g performs a switching operation to select (2) in FIG. Do.

  Thus, each time one unit of data is read, the value of the predetermined interval Interval (Interval = 4 in FIG. 13) is added to the value of RP until the value of RP + Interval exceeds the value HDRP + Length (step S41), and CycleCT is incremented by one. After that (Step S38), the process returns to Step S31. The execution timing of the process of step S41 corresponds to timings T19 to T21, T23 to T25, T27 to T29, and T31 to T33 in FIG.

  When the value of RP + Interval exceeds the value HDRP + Length (YES route in step S40), the selector 143g performs a switching operation to select (3) in FIG. As a result, the value HDRP + [(RP−HDRP + 1)% Interval] obtained by the arithmetic unit 143i is set to RP (step S42), and CycleCT is incremented by 1 (step S38).

  For example, at the timing T22 in FIG. 13, the value HDRP + [(RP−HDRP + 1)% Interval] = 0 + [(15-0 + 1)% 4] = 16% 4 = 4, so 4 is set to RP. At the timing T26 in FIG. 13, the value HDRP + [(RP−HDRP + 1)% Interval] = 0 + [(16-0 + 1)% 4] = 17% 4 = 1, so RP is set to 1. Similarly, at the timing T30 in FIG. 13, the value HDRP + [(RP−HDRP + 1)% Interval] = 0 + [(13−0 + 1)% 4] = 14% 4 = 2, so 2 is set in RP. . Thereafter, the process returns to step S31.

  Thereafter, when the value of CycleCT reaches the data length Length (YES route in step S39; see timing T34 in FIG. 13), the value of CycleCT is reset to 0 (step S43). Then, the selector 143g performs a switching operation so as to select (4) in FIG. Thus, the value HDRP + Length + 1 (value 17 in FIG. 13) obtained by the adder 143f is set in RP as the address of the data to be read next (step S44). Also, the value HDRP + Length + 1 (the value 17 in FIG. 7) obtained by the adder 143c is set in HDRP as the address of the header of the packet to be read next (step S45). Thereafter, the process returns to step S31.

  According to the above operation, in the second embodiment, the data DT2, DT6, DTA, and DTE are read before other data, and the latency is reduced.

  In the above-described operation, the order of data to be read is uniquely determined by the physical address pa [6: 3] of the first processing target data and the predetermined interval Interval. Accordingly, the core 11A that has received the packet can easily determine which physical address is the data other than the data group previously read from the packet in the reception buffer 141.

  Note that the first embodiment described above with reference to FIGS. 1 to 7 corresponds to the case where the value of the predetermined interval Interval is 1 in the second embodiment described above with reference to FIGS.

[5] Others Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and changes can be made without departing from the spirit of the present invention. It can be changed and implemented.

[6] Supplementary notes The following supplementary notes are further disclosed with respect to the embodiments including the above embodiments.

(Appendix 1)
An arithmetic processing device connected to another arithmetic processing device,
A processing unit that generates a read request for data to be processed;
A communication unit that transmits the read request generated by the processing unit to the other arithmetic processing device, and receives a data block including the processing target data corresponding to the transmitted read request from the other arithmetic processing device,
A buffer for storing the data block;
A writing unit for sequentially writing a plurality of unit data included in the data block received by the communication unit to the buffer,
A reading unit that preferentially reads out the processing target data, which is at least one of the plurality of unit data, from the buffer.

(Appendix 2)
The reading unit includes:
Referring to the address information of the processing target data recorded by the other arithmetic processing device in the response header attached to the data block,
After reading the processing target data corresponding to the address information from the buffer,
The arithmetic processing device according to claim 1, wherein the unit data other than the processing target data is sequentially read from the buffer.

(Appendix 3)
When the plurality of processing target data exists at predetermined intervals in the plurality of unit data,
The communication unit,
Transmitting the read request including the information on the predetermined interval to the other arithmetic processing device,
The reading unit includes:
Referring to the address information and the information on the predetermined interval of the head of the processing target data recorded by the other arithmetic processing device in the response header attached to the data block,
After reading the plurality of processing target data from the buffer based on the address information and the predetermined interval,
The arithmetic processing device according to claim 1, wherein the unit data other than the plurality of processing target data is sequentially read from the buffer.

(Appendix 4)
A first arithmetic processing unit;
A second processing unit connected to the first processing unit,
The first arithmetic processing unit includes:
A processing unit that generates a read request for data to be processed;
Transmitting a read request generated by the processing unit to the second arithmetic processing device, and receiving a data block including the processing target data corresponding to the transmitted read request from the second arithmetic processing device; Communication department,
A buffer for storing the data block;
A writing unit for sequentially writing a plurality of unit data included in the data block received by the first communication unit to the buffer;
A reading unit that preferentially reads the processing target data, which is at least one of the plurality of unit data, from the buffer,
The second arithmetic processing unit includes:
A second communication unit that receives the read request from the first arithmetic processing device and transmits the data block including the processing target data corresponding to the received read request to the first arithmetic processing device. Information processing device.

(Appendix 5)
The second communication unit in the second arithmetic processing device,
Attaching a response header recording the address information of the processing target data extracted from the address information included in the read request to the data block,
The information processing device according to claim 4, wherein the data block to which the response header is added is transmitted to the first arithmetic processing device.

(Appendix 6)
The reading unit in the first arithmetic processing device,
With reference to the address information of the processing target data recorded in the response header attached to the data block,
After reading the processing target data corresponding to the address information from the buffer,
The information processing apparatus according to claim 5, wherein the unit data other than the processing target data is sequentially read from the buffer.

(Appendix 7)
When the plurality of processing target data exists at predetermined intervals in the plurality of unit data,
The first communication unit in the first arithmetic processing device includes:
Transmitting the read request including the information on the predetermined interval to the second arithmetic processing unit;
The second communication unit in the second arithmetic processing device,
Attach to the data block a response header that records the address information of the first processing target data extracted from the address information included in the read request and the information related to the predetermined interval extracted from the read request,
5. The information processing device according to claim 4, wherein the data block to which the response header is added is transmitted to the first arithmetic processing device.

(Appendix 8)
The reading unit in the first arithmetic processing device,
With reference to the address information and the information on the predetermined interval of the head of the processing target data recorded in the response header attached to the data block,
Based on the address information and the predetermined interval, after reading the plurality of processing target data from the buffer,
8. The information processing apparatus according to claim 7, wherein the plurality of unit data other than the processing target data are sequentially read from the buffer.

(Appendix 9)
A control method of an information processing device, comprising: a first arithmetic processing device; and a second arithmetic processing device connected to the first arithmetic processing device,
The first arithmetic processing unit includes:
Transmitting a read request for data to be processed to the second arithmetic processing unit;
The second arithmetic processing unit includes:
When receiving the read request from said first processor, the processed data corresponding to said read request received transmitted-containing Mude Taburokku to the first processor,
The first arithmetic processing unit includes:
Receiving a data block including the processing target data corresponding to the read request from the second arithmetic processing unit;
A plurality of unit data included in the received data block are sequentially written to the buffer,
A control method for an information processing device, wherein the processing target data, which is at least one of the plurality of unit data, is preferentially read from the buffer.

(Appendix 10)
The second arithmetic processing unit includes:
Attaching a response header recording the address information of the processing target data extracted from the address information included in the read request to the data block,
The control method for an information processing device according to claim 9, wherein the data block to which the response header is added is transmitted to the first arithmetic processing device.

(Appendix 11)
The first arithmetic processing unit includes:
With reference to the address information of the processing target data recorded in the response header attached to the data block,
After reading the processing target data corresponding to the address information from the buffer,
11. The control method of an information processing device according to claim 10, wherein unit data other than the processing target data is sequentially read from the buffer.

(Appendix 12)
When the plurality of processing target data exists at predetermined intervals in the plurality of unit data,
The first arithmetic processing unit includes:
Transmitting the read request including the information on the predetermined interval to the second arithmetic processing unit;
The second arithmetic processing unit includes:
Attach to the data block a response header that records the address information of the first processing target data extracted from the address information included in the read request and the information related to the predetermined interval extracted from the read request,
The control method for an information processing device according to claim 9, wherein the data block to which the response header is added is transmitted to the first arithmetic processing device.

(Appendix 13)
The first arithmetic processing unit includes:
With reference to the address information and the information on the predetermined interval of the head of the processing target data recorded in the response header attached to the data block,
Based on the address information and the predetermined interval, after reading the plurality of processing target data from the buffer,
13. The control method for an information processing device according to claim 12, wherein the unit data other than the plurality of processing target data is sequentially read from the buffer.

1,1 'information processing device (multiprocessor system)
10, 10A, 10B CPU (arithmetic processing unit, multi-core processor)
11, 11A, 11B core (processing unit)
12,12A, 12B Shared cache (tertiary cache)
13, 13A, 13B MAC
14 router 14A router (first communication unit)
14B router (second communication unit)
141 Receive buffer (buffer)
142 Writer 143, 143 'Reader 143a Length generator 143b, 143d 1 adder (+1)
143c, 143e, 143f, 143h Adder 143g Selector 143i Arithmetic unit 20, 20A, 20B DIMM (Main memory)
30 Network

Claims (8)

An arithmetic processing device connected to another arithmetic processing device,
A processing unit that generates a read request for data to be processed;
A communication unit that transmits the read request generated by the processing unit to the other arithmetic processing device, and receives a data block including the processing target data corresponding to the transmitted read request from the other arithmetic processing device,
A buffer for storing the data block;
A writing unit sequentially writes a plurality of unit data included in the data block by the communication unit has received in the buffer,
A reading unit that preferentially reads the processing target data, which is at least one of the plurality of unit data, from the buffer,
The reading unit includes:
Address information of the processing target data recorded by the other processing unit in a response header attached to the data block, and information for specifying the processing target data from the plurality of unit data. See,
After reading the processing target data corresponding to the address information from the buffer,
An arithmetic processing device for sequentially reading unit data other than the processing target data from the buffer. An arithmetic processing device connected to another arithmetic processing device,
A processing unit that generates a read request for data to be processed;
A communication unit that transmits the read request generated by the processing unit to the other arithmetic processing device, and receives a data block including the processing target data corresponding to the transmitted read request from the other arithmetic processing device,
A buffer for storing the data block;
A writing unit sequentially writes a plurality of unit data included in the data block by the communication unit has received in the buffer,
A reading unit that preferentially reads the processing target data, which is at least one of the plurality of unit data, from the buffer,
When the plurality of processing target data exists at predetermined intervals in the plurality of unit data,
The communication unit,
Transmitting the read request including the information on the predetermined interval to the other arithmetic processing device,
The reading unit includes:
Referring to the address information and the predetermined interval of the head of the processing target data recorded by the other arithmetic processing device in the response header attached to the data block,
After reading the plurality of processing target data from the buffer based on the address information and the predetermined interval,
An arithmetic processing device for sequentially reading unit data other than the plurality of processing target data from the buffer. A first arithmetic processing unit;
A second processing unit connected to the first processing unit,
The first arithmetic processing unit includes:
A processing unit that generates a read request for data to be processed;
Transmitting a read request generated by the processing unit to the second arithmetic processing device and receiving a data block including the processing target data corresponding to the transmitted read request from the second arithmetic processing device; Communication department,
A buffer for storing the data block;
A writing unit sequentially writes a plurality of unit data of the first communication unit is included in the data block received in said buffer,
A reading unit that preferentially reads the processing target data, which is at least one of the plurality of unit data, from the buffer,
The second arithmetic processing unit includes:
A second communication unit that receives the read request from the first arithmetic processing device and transmits the data block including the processing target data corresponding to the received read request to the first arithmetic processing device. Have
The second communication unit in the second arithmetic processing device,
A response header, which is address information of the processing target data extracted from the address information included in the read request and records information for specifying the processing target data from the plurality of unit data, is stored in the data block. Attached to
An information processing device for transmitting the data block to which the response header is added to the first arithmetic processing device. A first arithmetic processing unit;
A second processing unit connected to the first processing unit,
The first arithmetic processing unit includes:
A processing unit that generates a read request for data to be processed;
Transmitting a read request generated by the processing unit to the second arithmetic processing device and receiving a data block including the processing target data corresponding to the transmitted read request from the second arithmetic processing device; Communication department,
A buffer for storing the data block;
A writing unit sequentially writes a plurality of unit data of the first communication unit is included in the data block received in said buffer,
A reading unit that preferentially reads the processing target data, which is at least one of the plurality of unit data, from the buffer,
The second arithmetic processing unit includes:
A second communication unit that receives the read request from the first arithmetic processing device and transmits the data block including the processing target data corresponding to the received read request to the first arithmetic processing device. Have
When the plurality of processing target data exists at predetermined intervals in the plurality of unit data,
The first communication unit in the first arithmetic processing device includes:
Transmitting the read request including the information on the predetermined interval to the second arithmetic processing unit;
The second communication unit in the second arithmetic processing device,
Address information of the first processing target data extracted from the address information included in the read request, wherein the information specifies the first processing target data from the plurality of unit data; Attaching a response header that records information on the predetermined interval extracted from the request to the data block,
An information processing device for transmitting the data block to which the response header is added to the first arithmetic processing device. The reading unit in the first arithmetic processing device,
With reference to the address information and the information on the predetermined interval of the head of the processing target data recorded in the response header attached to the data block,
Based on the address information and the predetermined interval, after reading the plurality of processing target data from the buffer,
The information processing apparatus according to claim 4, wherein unit data other than the plurality of processing target data is sequentially read from the buffer. A control method of an information processing device, comprising: a first arithmetic processing device; and a second arithmetic processing device connected to the first arithmetic processing device,
The first arithmetic processing unit includes:
Transmitting a read request for data to be processed to the second arithmetic processing unit;
The second arithmetic processing unit includes:
When receiving the read request from said first processor, said an address information of the processing target data retrieved from the address information included in the read request, for identifying a pre-Symbol processed data received A response header recording information is attached to a data block including the processing target data corresponding to the read request,
Transmitting the data block with the response header to the first arithmetic processing unit;
The first arithmetic processing unit includes:
Receiving the data block including the processing object data corresponding to said read request from said second processor,
Sequentially writes a plurality of unit data included in the received data blocks in the buffer,
A control method for an information processing device, wherein the processing target data, which is at least one of the plurality of unit data, is preferentially read from the buffer. In an information processing apparatus having a first arithmetic processing device and a second arithmetic processing device connected to the first arithmetic processing device,
The first arithmetic processing unit includes:
Transmitting a read request for data to be processed to the second arithmetic processing unit;
The second arithmetic processing unit includes:
Upon receiving the read request from the first processing unit, transmitting a data block including the processing target data corresponding to the received read request to the first processing unit;
The first arithmetic processing unit includes:
Receiving the data block including the processing object data corresponding to said read request from said second processor,
Sequentially writes a plurality of unit data included in the received data blocks in the buffer,
A control method of an information processing device, wherein the processing target data, which is at least one of the plurality of unit data, is read out preferentially from the buffer,
When the plurality of processing target data exists at predetermined intervals in the plurality of unit data,
The first arithmetic processing unit includes:
Transmitting the read request including the information on the predetermined interval to the second arithmetic processing unit;
The second arithmetic processing unit includes:
Address information of the first processing target data extracted from the address information included in the read request, wherein the information specifies the first processing target data from the plurality of unit data; Attaching a response header that records information on the predetermined interval extracted from the request to the data block,
A control method for an information processing device, wherein the data block to which the response header is added is transmitted to the first arithmetic processing device. The first arithmetic processing unit includes:
With reference to the address information and the information on the predetermined interval of the head of the processing target data recorded in the response header attached to the data block,
Based on the address information and the predetermined interval, after reading the plurality of processing target data from the buffer,
The method according to claim 7, wherein unit data other than the plurality of data to be processed is sequentially read from the buffer.

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