JP6654957B2 - Nitride semiconductor device - Google Patents

Description

  The present invention relates to a nitride semiconductor device.

  For example, Patent Document 1 discloses a HEMT. This HEMT has a heterojunction structure formed by stacking a low-temperature buffer layer made of GaN, a buffer layer made of GaN, an electron transit layer made of GaN, and an electron supply layer made of AlGaN on a substrate in this order. have. Further, the HEMT has a source electrode, a gate electrode, and a drain electrode on the electron supply layer.

  In the HEMT, the electron supply layer has a larger band gap energy than the electron transit layer, and a two-dimensional electron gas layer is formed below a heterojunction interface between the two layers. A two-dimensional electron gas layer is used as a carrier. That is, when the source electrode and the drain electrode are activated, the electrons supplied to the electron transit layer travel at high speed in the two-dimensional electron gas layer and move to the drain electrode. At this time, by controlling the voltage applied to the gate electrode to change the thickness of the depletion layer below the gate electrode, electrons moving from the source electrode to the drain electrode, that is, the drain current can be controlled.

Japanese Patent No. 5064824

  In the HEMT as described above, an improvement in switching speed is always required. Shortening the gate length contributes to high-speed switching. However, on the other hand, there is a problem that a leakage current easily flows under the gate, so that the breakdown voltage is reduced. Therefore, a field plate may be provided on the nitride semiconductor layer in order to suppress the concentration of the electric field, but it is difficult to obtain a sufficient breakdown voltage unless it is provided under appropriate conditions.

  One embodiment of the present invention provides a nitride semiconductor device that can achieve both improvement in switching speed and improvement in breakdown voltage.

One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, and a value of C _oss . Is V ₁ (V), the breakdown voltage of the device is V ₂ (V), the gate length is L _g (cm), and the field plate length is a value that decreases to half the value when the drain voltage is 0 V. _Is L _fp (cm), the shallow acceptor concentration is N _A (/ cm ³ ), the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum permittivity is ε ₀ , and the relative permittivity of the nitride semiconductor layer is ε. Then, a nitride semiconductor device satisfying the following equations (1) and (2) is provided.

V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
V ₂ <q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε (2)
In this case, the nitride semiconductor device may satisfy the following expressions (3) and (4).
q (N _A + N _DA ) · L _g ² / 2ε ₀ ε <1.2V ₁ (3)
q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε <1.2 V ₂ (4)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, and a value of C _oss . Is V ₁ (V), the breakdown voltage of the device is V ₂ (V), the gate length is L _g (cm), and the field plate length is a value that decreases to half the value when the drain voltage is 0 V. L _fp (cm), shallow donor concentration N _D (/ cm ³ ), deep donor concentration N _DD (/ cm ³ ) _, shallow acceptor concentration N _A (/ cm ³ ), and deep acceptor concentration N _DA ( / Cm ³ ), a vacuum dielectric constant being ε ₀ , and a relative dielectric constant of the nitride semiconductor layer being ε, providing a nitride semiconductor device satisfying the following expressions (5) and (6).

_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6)
In this case, the nitride semiconductor device may satisfy the following expressions (7) and (8).

_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, and a value of C _oss . Is V ₁ (V), the maximum rated voltage of the device is V ₂ (V), the gate length is L _g (cm), and the field plate length is a voltage that decreases to half the value when the drain voltage is 0 V. _Is L _fp (cm), the shallow acceptor concentration is N _A (/ cm ³ ), the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum permittivity is ε ₀ , and the relative permittivity of the nitride semiconductor layer is ε. Then, a nitride semiconductor device satisfying the following equations (1) and (2) is provided.

V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
V ₂ <q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε (2)
In this case, the nitride semiconductor device may satisfy the following expressions (3) and (4).
q (N _A + N _DA ) · L _g ² / 2ε ₀ ε <1.2V ₁ (3)
q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε <1.2 V ₂ (4)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, and a value of C _oss . Is V ₁ (V), the maximum rated voltage of the device is V ₂ (V), the gate length is L _g (cm), and the field plate length is a voltage that decreases to half the value when the drain voltage is 0 V. L _fp (cm), shallow donor concentration N _D (/ cm ³ ), deep donor concentration N _DD (/ cm ³ ) _, shallow acceptor concentration N _A (/ cm ³ ), and deep acceptor concentration N _DA ( / Cm ³ ), a vacuum dielectric constant being ε ₀ , and a relative dielectric constant of the nitride semiconductor layer being ε, providing a nitride semiconductor device satisfying the following expressions (5) and (6).

_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6)
In this case, the nitride semiconductor device may satisfy the following expressions (7) and (8).

_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, and a value of C _oss . Is V ₁ (V), the sheet carrier density of the two-dimensional electron gas is N _s (/ cm ² ), and the gate length is L _g (cm). ), Field plate length L _fp (cm), shallow donor concentration N _D (/ cm ³ ), deep donor concentration N _DD (/ cm ³ ) _, shallow acceptor concentration N _A (/ cm ³ ), deep acceptor Provided is a nitride semiconductor device that satisfies the following formulas (5) and (9) when the concentration is N _DA (/ cm ³ ), the vacuum dielectric constant is ε ₀ , and the relative dielectric constant of the nitride semiconductor layer is ε. I do.

_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
^{_{N s 2 / (N A +}} N DA -N D -N DD) <(N A + N DA -N D -N DD) · (L g + L fp) 2 ··· (9)
In this case, the nitride semiconductor device may satisfy the following expressions (7) and (10).

_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{(N A + N DA -N D} -N DD) · (L g + L fp) 2 <1.2N s 2 / (N A + N DA -N D -N DD) ··· (10)
One embodiment of the present invention includes a nitride semiconductor layer having a gate, a source, and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, and a value of C _oss . Is V ₁ (V), the sheet carrier density of the two-dimensional electron gas is N _s (/ cm ² ), and the gate length is L _g (cm). ), The field plate length is L _fp (cm), the shallow acceptor concentration is N _A (/ cm ³ ), the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum permittivity is ε ₀ , and the ratio of the nitride semiconductor layer. Provided is a nitride semiconductor device that satisfies the following expressions (1) and (11) when the dielectric constant is ε.

V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
^{_{N s 2 / (N A +}} N DA) <(N A + N DA) · (L g + L fp) 2 ··· (11)
In this case, the nitride semiconductor device may satisfy the following expressions (3) and (12).
q (N _A + N _DA ) · L _g ² / 2ε ₀ ε <1.2V ₁ (3)
(N _A + N _DA ) · (L _g + L _fp ) ² <1.2 N _s ² / (N _A + N _DA ) (12)
In one embodiment of the present invention, the gate length L _g is at 0.5μm or less, said field plate length L _fp is at 0.5μm or less, the maximum rated voltage of the device may be 50V or higher.

In one embodiment of the present invention, the nitride semiconductor layer includes C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, A deep acceptor level may be formed by doping at least one impurity selected from the group consisting of Mg, Ar, and He.
One embodiment of the present invention is an electron transit layer, a nitride semiconductor layer in contact with the electron transit layer, including an electron supply layer having a composition different from the electron transit layer, and a gate on the nitride semiconductor layer, A source and a drain, and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, wherein at least a part of the electron transit layer contains carbon, and a concentration of the carbon Is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

In one embodiment of the present invention, the electron transit layer includes a first region that forms an interface between the electron transit layer and the electron supply layer, and a second region that is formed at a distance of 50 nm or more from the interface. And the carbon concentration of the second region may be 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ , and the carbon concentration of the first region may be 1 × 10 ¹⁷ cm ⁻³ or less. .
In one embodiment of the present invention, the shallow donor concentration is N _D (/ cm ³ ), the deep donor concentration is N _DD (/ cm ³ ) _{, the} shallow acceptor concentration is N _A (/ cm ³ ), and the deep acceptor concentration is N _DA. (/ cm ³⁾ and the _{case, N a + N DA -N D} -N DD of the second region of the electron transit layer, even ^{4 × 10 16 cm -3 ~8 ×} 10 16 cm -3 Good.

One embodiment of the present invention is an electron transit layer, a nitride semiconductor layer in contact with the electron transit layer, including an electron supply layer having a composition different from the electron transit layer, and a gate on the nitride semiconductor layer, a source and a drain electrically connected to the gate or the source, through an insulating film and a field plate disposed on the nitride semiconductor layer, a gate length L _g is at 0.6μm or less, At least a part of the electron transit layer contains carbon, the concentration of the carbon is 1 × 10 ¹⁸ cm ⁻³ or more, the thickness of the insulating film below the field plate is d, and the thickness of the insulating film is Provided is a nitride semiconductor device that satisfies d / ε ≦ 14 when a relative dielectric constant is ε.

According to one embodiment of the present invention, when a voltage is applied between the source and the drain when the gate is off, as shown in the above formulas (1) and (5), The voltage when the region punches through (the right side of each equation) is higher than the voltage V ₁ (the left side of each equation) at which the two-dimensional electron gas disappears. Accordingly, punch-through under the gate can be prevented, so that generation of a leak current at the time of off can be suppressed.

Further, as shown in the above equations (2), (6), (9) and (11), the voltage (right side of each equation) when punching through the region of the nitride semiconductor layer under the field plate is determined by the device. because of greater than the breakdown voltage V ₂ or the maximum rated voltage V _2, it is possible to realize a highly reliable device.
Then, the breakdown voltage and the effect of improving the reliability as described above, as is apparent from the equation, even with a shorter gate length L _g, term calculated (shallow acceptors other than the gate length L _g of each formula Concentration N _A , deep acceptor concentration N _DA, etc.). Therefore, by designing the gate length _Lg to a desired length, the switching speed of the device can be improved while maintaining the breakdown voltage.

FIG. 1 is an external view of a semiconductor package including a nitride semiconductor device according to one embodiment of the present invention. FIG. 2 is a schematic sectional view of the nitride semiconductor device. Figure 3A _is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD. 3B _is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD. 3C _is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD. Figure 4A is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD of semi-insulating GaN layer. Figure 4B is a diagram for explaining a method of measuring the value of _{N A + N DA -N D -N} DD of semi-insulating GaN layer. FIG. 5 is a diagram showing the IV characteristics of FIGS. 4A and 4B. Figure 6 is a graph showing the relationship between the drain voltage _{V D} and the output capacitance _{C oss.} FIG. 7 is a diagram for explaining how to determine the depletion voltage of the two-dimensional electron gas below the field plate. FIG. 8 is a diagram for explaining how to obtain the depletion voltage of the two-dimensional electron gas in the region from the end of the field plate to the drain. FIG. 9 is a diagram for explaining the trap concentration dependency of the current. 10A to 10C are energy band diagrams showing the movement of electrons until the current starts flowing over time. FIG. 11 is a simulation result showing a potential distribution of the nitride semiconductor device according to the reference example. FIG. 12 is a simulation result showing the current density of the nitride semiconductor device according to the reference example. FIG. 13 is a simulation result showing the trap occupancy of the nitride semiconductor device according to the reference example. FIG. 14 is a simulation result showing a potential distribution of the nitride semiconductor device according to one embodiment of the present invention. FIG. 15 is a simulation result showing the current density of the nitride semiconductor device according to one embodiment of the present invention. FIG. 16 is a simulation result showing the trap occupancy of the nitride semiconductor device according to one embodiment of the present invention. FIG. 17 is a graph comparing the leak currents of the present embodiment and the reference example. Figure 18 is a diagram showing the relationship between the carbon concentration and the _{N A + N DA -N D -N} DD. FIG. 19A is a diagram showing a reference structure 1 set for simulation. FIG. 19B is a diagram showing the reference structure 2 set for the simulation. FIG. 20A is a diagram illustrating a relationship between the carbon concentration and the sheet resistance of the two-dimensional electron gas. FIG. 20B is a diagram illustrating a relationship between the carbon concentration and the mobility of the two-dimensional electron gas. FIG. 20C is a diagram illustrating a relationship between the carbon concentration and the sheet carrier density of the two-dimensional electron gas. Figure 21 is a diagram showing the relationship between sheet carrier density N _s and mobility of two-dimensional electron gas (2DEG mobility). FIG. 22A is a diagram showing the structure of AlGaN / GaN between the gate and the drain. FIG. 22B is a diagram showing the structure of AlGaN / GaN in the gate section. FIG. 23 is a diagram showing the relationship between the gate length and the gate breakdown voltage. Figure 24 _is a diagram showing the relationship between _{N A + N DA -N D -N} DD and depletion voltage under the field plate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is an external view of a semiconductor package 1 including a nitride semiconductor device 3 according to one embodiment of the present invention.
The semiconductor package 1 includes a terminal frame 2, a nitride semiconductor device 3 (chip), and a resin package 4.

  The terminal frame 2 is a metal plate. The terminal frame 2 includes a base 5 (island) that supports the nitride semiconductor device 3, a drain terminal 6, a source terminal 7, and a gate terminal 8. The drain terminal 6 is formed integrally with the base 5. The drain terminal 6, the source terminal 7, and the gate terminal 8 are electrically connected to the drain, source, and gate of the nitride semiconductor device 3 by bonding wires 9 to 11, respectively. The source terminal 7 and the gate terminal 8 are arranged so as to sandwich the central drain terminal 6.

The resin package 4 is made of, for example, a known mold resin such as an epoxy resin, and seals the nitride semiconductor device 3. The resin package 4 covers the base portion 5 of the terminal frame 2 and the bonding wires 9 to 11 together with the nitride semiconductor device 3. Some of the three terminals 6 to 8 are exposed from the resin package 4.
FIG. 2 is a schematic sectional view of the nitride semiconductor device 3. FIG. 2 does not show a cross section at a specific position in FIG. 1 but shows one cross section of an aggregate of elements considered to be necessary for the description of the present embodiment.

  The nitride semiconductor device 3 includes a substrate 12, a buffer layer 13 formed on the surface of the substrate 12, an electron transit layer 14 epitaxially grown on the buffer layer 13, and an electron supply layer epitaxially grown on the electron transit layer 14. 15 is included. Further, the nitride semiconductor device 3 is in ohmic contact with the electron supply layer 15 through the gate insulating film 16 covering the surface of the electron supply layer 15 and the contact holes 17 a and 18 a formed in the gate insulating film 16. It includes a source electrode 17 and a drain electrode 18 as ohmic electrodes. The source electrode 17 and the drain electrode 18 are arranged at intervals, and a gate electrode 19 is arranged between them. The gate electrode 19 faces the electron supply layer 15 via the gate insulating film 16.

Substrate 12 may be, for example, a conductive silicon substrate. The conductive silicon substrate may have, for example, an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ (more specifically, about 1 × 10 ¹⁸ cm ⁻³ ).
The buffer layer 13 may be a multilayer buffer layer in which a first buffer layer 131 and a second buffer layer 132 are stacked. The first buffer layer 131 is in contact with the surface of the substrate 12, and the second buffer layer 132 is stacked on the surface of the first buffer layer 131 (the surface opposite to the substrate 12). In the present embodiment, the first buffer layer 131 is formed of an AlN film, and its thickness may be, for example, about 0.2 μm. In the present embodiment, the second buffer layer 132 is made of an AlGaN film, and its thickness may be, for example, about 0.2 μm.

The gate insulating film 16 may be a multilayer gate insulating film in which a first insulating layer 161 and a second insulating layer 162 are stacked. The first insulating layer 161 is in contact with the surface of the electron supply layer 15, and the second insulating layer 162 is stacked on the surface of the first insulating layer 161 (the surface opposite to the electron supply layer 15). The first insulating layer 161 is formed of a SiN film in the present embodiment, and its thickness may be, for example, about 500 °. Such a first insulating layer 161 can be formed by a plasma CVD (chemical vapor deposition) method, a thermal CVD method, sputtering, or the like. An opening 161 a is formed in the first insulating layer 161 to allow the second insulating layer 162 to enter and come into contact with the electron supply layer 15. The second insulating layer 162, in this embodiment, is composed of alumina _(Al a _{O b),} the thickness thereof may be, for example, about 300 Å. The second insulating layer 162 has a concave portion 162a in a portion of the first insulating layer 161 that enters the opening 161a. Such a second insulating layer 162 can be formed by, for example, precisely controlling the film thickness by, for example, an ALD method.

When an alumina film is to be formed by the ALD method, in general, the composition ratio a: b of Al and O fluctuates, and the whole does not always become Al ₂ O ₃ . This is because the ALD method is a relatively low temperature process. However, an insulator made of Al and O can form an insulator layer having a large band gap and a high withstand voltage without strictly controlling the composition. In this specification, the term "alumina" is used including the case where the composition ratio a: b of Al and O is other than 2: 3.

The electron transit layer 14 and the electron supply layer 15 are made of a group III nitride semiconductor having a different Al composition (hereinafter, simply referred to as “nitride semiconductor”). For example, the electron transit layer 14 may be made of a GaN layer, and may have a thickness of about 0.5 μm. In the present embodiment, the electron supply layer 15 is composed of an Al _x Ga ₁ -xN layer (0 <x <1), and has a thickness of, for example, 5 nm to 30 nm (more specifically, about 20 nm). is there.

  As described above, the electron transit layer 14 and the electron supply layer 15 are made of nitride semiconductors having different Al compositions, form a heterojunction, and have lattice mismatch between them. Due to the polarization caused by the heterojunction and the lattice mismatch, the two-dimensional electron gas is placed at a position close to the interface between the electron transit layer 14 and the electron supply layer 15 (for example, at a distance of about several か ら from the interface). Twenty are spreading.

The electron transit layer 14 may have a shallow donor level E _D , a deep donor level E _DD , a shallow acceptor level E _A , and a deep acceptor level E _DA with respect to its energy band structure.
The shallow donor level E _D is, for example, an energy level at a distance of 0.025 eV or less from the energy level E _{C at} the lower end (bottom) of the conduction band of the electron transit layer 14, and is a deep donor level E _D. if you can distinguish it from the _DD, simply may be referred to as a "donor level E _D". Usually, the electrons of the donor doped at this position are excited in the conduction band and become free electrons even at room temperature (heat energy kT = about 0.025 eV). As an impurity to be doped into GaN channel layer 14 to form a shallow donor level E _D, for example, Si, at least one can be mentioned is selected from the group consisting of O. On the other hand, the deep donor level _{E DD} is, for example, the energy level at remote location over 0.025eV from energy level _{E C} of the conduction band bottom of the electron transit layer 14 (bottom). In other words, the deep donor level E _DD is formed by doping of a donor whose ionization energy required for excitation is larger than the thermal energy at room temperature. Therefore, usually, the electrons of the donor doped at this position are not excited to the conduction band at room temperature, but are trapped by the donor.

Shallow acceptor level E _A is, for example, energy level at a position below the distant 0.025eV from the energy level E _V of the valence of the upper end of the electron transit layer 14 (top), a deep acceptor level E if you can distinguish it from the _DA, it may simply be referred to as "acceptor level E _a". Normally, the holes of the acceptor doped at this position are excited into the valence band and become free holes even at room temperature (heat energy kT = about 0.025 eV). On the other hand, a deep acceptor level _{E DA} is, for example, the energy level at remote location over 0.025eV from energy level _{E V} of the valence of the upper end of the electron transit layer 14 (top). In other words, the deep acceptor level _EDA is formed by doping an acceptor whose ionization energy required for excitation is larger than thermal energy at room temperature. Therefore, usually, the holes of the acceptor doped at this position are not excited to the valence band at room temperature, and are in a state captured by the acceptor. At room temperature, Mg is known as an impurity that generates holes, but its activation rate (the ratio of holes generated to the amount of doping) is 1/10 or less. Although it can be interpreted as a deep acceptor, in the present invention, since N _A + N _DA is an important value, it can be interpreted as either. As an impurity to be doped in the electron transit layer 14 made of GaN in order to form a deep acceptor level _{E DA,} for example, C, Be, Cd, Ca , Cu, Ag, Au, Sr, Ba, Li, Na, K , Sc, Zr, Fe, Co, Ni, Mg, Ar, and He.

In the present embodiment, the description was shallow donor level E _D, deep donor level E _DD, the concentration of the shallow acceptor level E _A and the deep acceptor level impurities to form the E _DA (dopant), respectively, These shall be referred to as shallow donor concentration N _D , deep donor concentration N _DD, shallow acceptor concentration N _A , and deep acceptor concentration N _DA .
The impurity concentration of the whole electron transit layer 14 _is preferably _{N A + N DA -N D -N} DD> 0. This inequality is (a N D ₊ N _DD, hereinafter, this sum may be referred to as a donor concentration N _d.) Total impurity concentration of donor atoms capable of releasing electrons than capture the emitted electrons (a N a ₊ N _DA, hereinafter it may. call this sum the trap density N _t) the sum of the impurity concentration of the acceptor atom capable of means that large. That is, in the electron transit layer 14, almost all of the electrons emitted from the shallow donor atoms and the deep donor atoms are not excited by the conduction band but are captured by the shallow acceptor atoms or the deep acceptor atoms. It is a semi-insulating i-type GaN.

However, at least one selected from the group consisting of C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, Mg, Ar and He Doping does not necessarily function as a deep acceptor. For example, in the case of C (carbon), the impurity functions as a deep acceptor by being replaced with an N (nitrogen) site in a group III nitride semiconductor crystal. However, it can function as a shallow donor by replacing it with a group III element site. The proportion replaced at each site depends on the concentration of carbon doped. In addition, a crystal defect is generated by doping with an impurity, and it is unclear which crystal defect functions as a shallow donor, a deep donor, a shallow acceptor, or a deep acceptor. Therefore, SIMs (Secondary Ion Mass Spectrometry: secondary ion mass spectrometry) _N A _{+ N DA} is not possible to know the value of -N D _{-N DD} impurity concentration measurement by.

Measurement of the value of _{N A + N DA -N D -N} DD has been found that it is possible to carry out the measurement of the longitudinal leakage current of semi-insulating layer as shown in Figure 3A. As described above, the electron transit layer is a semi-insulating layer in which electrons emitted from a shallow donor and a deep donor are captured by a shallow acceptor and a deep acceptor. As shown in FIG. 10A, these layers are in a state where there is a deep acceptor level that does not capture electrons and a vacancy exists in the deep acceptor when no bias is applied. At this time, the GaN layer is electrically neutral. As shown in FIG. 10B, under an external voltage equal to or lower than a certain value, electrons are captured by a deep acceptor, which did not capture electrons when no bias is applied, and the positive bias side is negatively charged to cancel the electric field. It is minute. In this case, a partial area of the positive bias side of the semi-insulating layer is negatively charged, the charge density is _{N A + N DA -N D -N} DD. When a voltage higher than a certain level is applied, electrons are trapped in all deep acceptor levels, so that a further electric field cannot be canceled and the current starts to increase. At this time, the semi-insulating layer is negatively charged in all areas, the charge density is _{N A + N DA -N D -N} DD. Therefore, when the distribution of N _A + N _DA -N _D -N _DD in the semi-insulating layer is uniform, the elementary charge amount is defined as q, the thickness of the semi-insulating layer is defined as d, and the voltage at which the current starts increasing is defined as V _TH. , Using the Poisson equation,
_{N A + N DA -N D -N} DD = 2εε 0 V TH / qd 2
Can be obtained by

In this measurement, an electrode may be formed on the semi-insulating layer via a conductive layer and a conductive substrate as shown in FIGS. 3B and 3C.
When GaN is grown on a heterogeneous substrate, it is necessary to introduce a buffer layer between the GaN and the substrate. For example, in the case of semi-insulating GaN on a Si substrate, a semi-insulating buffer layer composed of a stack of AlN and AlGaN is included between the conductivity type substrate and the semi-insulating GaN layer to be measured. Since these buffer layers that are expected to have different _{N A + N DA -N D -N} DD is a semi-insulating GaN layer, to measure the _{N A + N DA -N D -N} DD of semi-insulating GaN layer Prepares a sample grown up to the buffer layer and a sample grown up to the semi-insulating GaN layer as shown in FIGS. 4A and 4B, and applies a positive bias to the substrate-side electrode. The difference of [Delta] V _TH of _{V TH} of each sample, the semi-insulating GaN layer thickness _{d GaN,} a buffer layer thickness and _{d buffer, N A + N DA} -N D -N DD of semi-insulating GaN layer,
_{N A + N DA -N D -N} DD = 2εε 0 ΔV TH / q (d GaN 2 + 2d GaN d buffer)
Can be obtained by

For example, when the thickness of the semi-insulating GaN layer grown under certain conditions is 1.5 μm and the thickness of the buffer layer is 0.2 μm, the IV characteristics shown in FIG. 5 are obtained. _a + _N DA _-N D _{-N DD} can be determined as 3.2 × ^{10 16} / cm ^3.
The electron supply layer 15 may have an AlN layer with a thickness of about several atoms (5 nm or less, preferably 1 nm to 5 nm, more preferably 1 nm to 3 nm) at the interface with the electron transit layer 14. Such an AlN layer suppresses electron scattering and contributes to an improvement in electron mobility.

  The gate electrode 19 may be composed of a laminated electrode film having a lower layer in contact with the gate insulating film 16 and an upper layer laminated on the lower layer. The lower layer may be made of Ni, Pt, Mo, W or TiN, and the upper layer may be made of Au or Al. The gate electrode 19 is arranged so as to be biased toward the source electrode 17, thereby having an asymmetric structure in which the distance between the gate and the drain is longer than the distance between the gate and the source. This asymmetric structure alleviates the high electric field generated between the gate and the drain and contributes to the improvement of the breakdown voltage.

The gate electrode 19 extends between the source electrode 17 and the drain electrode 18 into the recess 162a formed in the second insulating layer 162, and the gate body 191 is continuous with the gate body 191. The gate insulating film is formed outside the opening 161a. 16 and a field plate portion 192 extending toward the drain electrode 18. Distance L _fp between gate body portion 191 to the end portion of the drain electrode 18 side of the second insulating layer 162 drain end field plate portion 192 from 191a is an end of the drain electrode 18 side at the interface between the field plate length and Called. On the other hand, the distance _{L g} of the drain terminal 191a at the interface between the gate body portion 191 and the second insulating layer 162 to the source terminal 191b which is an end portion of the source electrode 17 side is referred to as the gate length. That is, the width of the effective gate area (the area within the recess 162a) Ga, which is the contact area between the gate electrode 19 and the bottom of the recess 162a of the second insulating layer 162, is called the gate length. Further, in this specification, the distance between the gate main body 191 and the drain electrode 18 is represented by L _gd .

It is preferable that the field plate length _Lfp is 1/10 or more and 1/2 or less of the gate-drain distance _Lgd . Specifically, it may be 0.1 μm or more and 0.5 μm or less. On the other hand, the gate length _{L g} is preferably 0.1μm or more 1.0μm or less. Specifically, it may be 0.2 μm or more and 0.5 μm or less.
The source electrode 17 and the drain electrode 18 are, for example, ohmic electrodes containing Ti and Al, and are electrically connected to the two-dimensional electron gas 20 via the electron supply layer 15.

  The bonding wires 9 to 11 shown in FIG. 1 are connected to the drain electrode 18, the source electrode 17, and the gate electrode 19, respectively. A back surface electrode 21 is formed on the back surface of the substrate 12, and the substrate 12 is connected to the base unit 5 via the back surface electrode 21. Therefore, in the present embodiment, the substrate 12 is electrically connected to the drain electrode 18 via the bonding wire 9 and has a drain potential.

  In the nitride semiconductor device 3, an electron supply layer 15 having a different Al composition is formed on the electron transit layer 14 to form a hetero junction. Thus, a two-dimensional electron gas 20 is formed in the electron transit layer 14 near the interface between the electron transit layer 14 and the electron supply layer 15, and a HEMT using the two-dimensional electron gas 20 as a channel is formed. The gate electrode 19 faces the electron supply layer 15 with the gate insulating film 16 interposed therebetween. When an appropriate negative voltage is applied to the gate electrode 19, the channel formed by the two-dimensional electron gas 20 can be cut off. Therefore, by applying a control voltage to the gate electrode 19, the source / drain can be turned on / off.

In use, for example, a predetermined voltage (for example, 200 V to 600 V) in which the drain electrode 18 side is positive is applied between the source electrode 17 and the drain electrode 18. In this state, an off voltage (for example, −5 V) or an on voltage (for example, 0 V) is applied to the gate electrode 19 with the source electrode 17 as the reference potential (0 V).
In the nitride semiconductor device 3 operating as described above, the nitride semiconductor device 3 satisfies the following expression (1) or (5) in order to improve the breakdown voltage.

V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
In the above equations (1) and (5), ε ₀ is a vacuum dielectric constant, and ε is a relative dielectric constant of the electron transit layer 14 (GaN). V ₁ of the respective left-hand side of formula (1) and (5), the field plate portion 192 electron transit layer 14 below is depleted, the two-dimensional electron gas 20 in the region indicates the voltage when depleted . On the other hand, each right side of the equations (1) and (5) indicates a voltage when a punch-through occurs under the gate and a leak current starts to flow. In other words, the inequalities expressed by the equations (1) and (5) indicate that the electron transit layer 14 does not punch-through under the gate until the electron transit layer 14 is depleted under the field plate portion 192. Can be reduced. Next, how to find the left and right sides of Equations (1) and (5) will be described.

First, the left side of the equation (1) and (5), _{V 1} indicates the drain voltage value the value of _{C oss} is reduced to 1/2 of the value when the drain voltage 0V, and the drain voltage _{V D} when showing the relationship between the output capacitance C _oss device graphically, the drain voltages V ₁ shown in FIG. The voltage V _1, the field plate portion 192 electron transit layer 14 below is depleted, defined as the voltage at which the two-dimensional electron gas 20 in the region disappears.

For example, as shown in the right diagram of FIG. 7, when an appropriate negative voltage is applied to the gate electrode, the two-dimensional electron gas is depleted under the field plate (FP) connected to the gate electrode. Polarization occurs between the GaN negatively charged layer (part of the electron transit layer 14 of the present embodiment) and the AlGaN layer thereon (the electron supply layer 15 of the present embodiment). At this time, an electric flux is generated upward from the AlGaN layer toward the field plate FP. The electric flux density D is based on Gauss's theorem (divD = ρ) and is equal to the sum of charges in the GaN negatively charged layer, which is a closed space facing the AlGaN layer. The thickness of the GaN negatively charged layer is W, the sheet carrier density of the two-dimensional electron gas in the GaN negatively charged layer to _{N s, D = q {N} s -W (N t -N d)} is derived. Then, D = from εE (ε is a relative dielectric constant of GaN) and _{V 1} = ∫Edz (z is the thickness direction of the GaN negatively charged layer) is established, as a _{result, V 1 = ∫q {N s} -W ( N _t -N _d)} / εdz is obtained. By calculating by substituting the designed values for each device in the _{V 1 = ∫q {N s -W} (N t -N d)} / εdz, depletion of the two-dimensional electron gas under the field plate FP it can be obtained a voltage _{V 1.} It is preferable that the depletion voltage V ₁ is smaller because it is more likely to be depleted. For this purpose, for example, the insulating film (the gate insulating film 16 in the present embodiment) under the field plate is made thinner or the insulating film becomes thinner. It may be made of a material having a high dielectric constant. The left diagram of FIG. 7 shows the distribution of the potential Φ and the distribution of the electric flux density D when the two-dimensional electron gas is depleted, respectively.

Further, reference, how to determine the depletion voltage V ₃ of the two-dimensional electron gas from the end portion of the drain electrode 18 side of the field plate portion 192 to the drain electrode 18 will be described with reference to FIG. Can be considered similarly to the case of FIG. 7, for example, GAN negatively charged layer is in the state where the depleted, the GaN negatively charged layer is enclosed space _{q {N s -W (N t} -N d)} of Although electric charges are present, no electric flux is generated upward from the AlGaN layer in the region, since the field plate FP is not provided above the GaN negatively charged layer. _{Thus, D = q {N s -W} (N t -N d)} = 0 _{becomes, W = N s / (N} t -N d) is derived from this equation. The depletion voltage _{V 3} in the region, derived from Poisson's _equation, and _{V 3 = q (N t -N} d) W 2 / 2ε. Since W ₌ a _{N s / (N t -N d} ), the depletion voltage _{V 3} does not depend on the thickness W of the GaN negatively charged layer can be defined by the trap density _{N t} and the donor concentration _{N d} .

Next, the right side of Expressions (1) and (5) will be described with reference to FIG. 9 and FIGS. 10A to 10C. As shown in FIG. 9, as a sample configuration for the simulation, a GaN layer having a thickness W = 5 μm, a shallow donor concentration N _D = 0.5 × 10 ¹⁶ cm ⁻³ , and a deep acceptor level E _DA = 0.7 eV Set. When the went increasing voltage (bias) between the electrodes of the front and back surfaces of the GaN layer was examined whether the rise of the current is how to vary with the deep acceptor concentration N _DA. Then, as is apparent from the graph of FIG. 9, a graph having substantially the same waveform was obtained, although the rising voltage was different. That is, from FIG. 9, it was found that the voltage at which the current started to flow in GaN depends on the trap concentration (in this simulation, the deep acceptor concentration N _DA ).

More specifically, as shown in FIG. 10A, when no voltage is applied between both electrodes (when no bias is applied), the acceptor and the deep acceptor generate the donor and the electrons emitted by the deep donor. Capture. At this time, since the number of positive charges due to the donors and deep donors that have emitted electrons is equal to the number of negative charges due to the acceptors and deep acceptors that have captured electrons, the GaN layer as a whole is electrically neutral. Next, when gradually applying a voltage as shown in FIG. 10B, the electron capture by positive bias side from the valence band (E _V) to deep acceptor occurs, negatively charged. Since the electric flux generated by the application of the voltage is canceled by the negatively charged region, the flowing current is extremely small. Then, as shown in FIG. 10C, when a certain voltage or more is applied, electron capture occurs in deep acceptors in all regions. Even if a voltage higher than this is applied, electron capture does not occur and the electric flux cannot be completely canceled out, so that a current flows. Expression containing the voltage V at this time is derived from Poisson's equation with _{N A + N DA -N D -N} DD = 2Vε 0 ε / qW 2, as a _{result, V = q (N A +} N DA -N D -N _DD ) .W ² / 2ε ₀ ε is obtained. When this is applied to the present embodiment, when a leak current flows under the gate, punch-through occurs laterally from the drain side to the source side in the region under the gate. L _g may be used. Thus, a right side of the equation _{(5) q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε is derived. On the other hand, the right side of the equation (1) is different from the formula (5) in that Equation (5) of the _{(N A + N DA -N D} -N DD) is in the _(N A _{+ N DA),} N _A + N _DA is the minimum amount necessary to cancel the electric flux, and it is sufficient to satisfy the right side of the equation (1). However, in consideration of the presence of the residual donor in GaN, the equation Moreover better satisfies the _{N a + N DA -N D -N} DD (5), a nitride semiconductor device 3, in order to further improve the reliability of the withstand voltage, satisfies the following formula (2) or (6) I have.

V ₂ <q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε (2)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6)
In the above formulas (2) and (6), V ₂ is the breakdown voltage or the maximum rated voltage of the device, ε ₀ is the vacuum permittivity, and ε is the relative permittivity of the electron transit layer 14 (GaN). . V ₂ of the left side of the equation (2) and (6), since a breakdown voltage or a maximum voltage rating of the device, is a value determined according to the individual devices. On the other hand, each right side of the equations (2) and (6) indicates a voltage at the time when a punch-through occurs under the field plate and the gate and a leak current starts to flow. In other words, the inequalities expressed by the equations (2) and (6) indicate that the dielectric breakdown voltage or the maximum of the nitride semiconductor device 3 is larger than the applied voltage at the time when the leak current starts to flow through by punching under the field plate and the gate. The rated voltage is exceeded, which indicates that the breakdown voltage and the maximum rated voltage specified for each device are highly reliable.

The dielectric breakdown voltage is a voltage at which the element itself is destroyed and cannot be used, or an off-leak current sharply increases. On the other hand, the maximum rated voltage is a voltage that must not be exceeded in order to maintain the reliability of the device.
The way to determine the right side of Expressions (2) and (6) can be considered in the same manner as the right side of Expressions (1) and (5). Because when the leakage current flows under the field plate and the gate punch through occurs in the transverse direction to the source side from the drain side area below the field plate and gate, the aforementioned _{V = q (N A + N} DA -N D −N _DD ) · W ² / 2ε ₀ ε The sum of the gate length and the field plate length (L _g + L _fp ) may be used instead of the thickness W of the GaN layer. Thus, equation (2) and a right-hand side _q of _{(6) (N A + N} DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε is derived.

The nitride semiconductor device 3 satisfies the above formulas (1), (2), (5) and (6), but more preferably the following formulas (3), (4), (7) or (8) Fulfill.
q (N _A + N _DA ) · L _g ² / 2ε ₀ ε <1.2V ₁ (3)
q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε <1.2 V ₂ (4)
_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8)
By satisfying the expressions (3), (4), (7) or (8), the parasitic capacitance can be extremely reduced while maintaining the breakdown voltage and the reliability, and the high-speed switching operation can be performed.

Next, the potential distribution, the current density, and the trap occupancy of the devices satisfying the above equations (1), (2), (5), and (6) and the devices not satisfying the above equations were simulated. The result was obtained.
FIGS. 11 to 13 show simulation results of the nitride semiconductor device according to the reference example (the above formulas (1), (2), (5) and (6) are not satisfied). FIG. 11 shows the potential distribution and FIG. Shows the current density, and FIG. 13 shows the trap occupancy. On the other hand, FIGS. 14 to 16 show simulation results of the nitride semiconductor device according to the present embodiment (satisfying the above formulas (1), (2), (5) and (6)), and FIG. FIG. 15 shows the current density, and FIG. 16 shows the trap occupancy.

First, the device according to the reference example is verified with reference to FIGS. Verification was performed using a drain voltage of 20 V, a GaN donor concentration of N _D = 1 × 10 ¹⁶ cm ⁻³ , a GaN deep acceptor concentration of N _DA = 0.5 × 10 ¹⁶ cm ⁻³ , and an insulating film below the field plate: SiO ₂ (Thickness: 100 nm). As a result of the verification, in the reference example, as shown in FIG. 11, no voltage drop was observed under the field plate, and a voltage drop occurred at the end of the gate. As a result, as shown in FIG. 12, a leak current is generated from the drain side to the source side across the gate. FIG. 13 shows that all traps (deep acceptors) under the gate are filled with electrons, which indicates that punch-through has occurred under the gate.

In contrast, except that in the thickness of the insulating film under the field plate to 10nm low depletion voltage V _1, the device of the present embodiment was verified under the same conditions as in Reference Example, as shown in FIG. 14 A voltage drop occurred at the end of the field plate, and as a result, almost no leak current flowed under the gate as shown in FIG. In addition, when the trap occupancy was confirmed in FIG. 16, it was found that the trap below the gate still has room for capturing electrons.

FIG. 17 shows a comparison of the leak current between the device of the present embodiment and the device of the reference example. As shown in FIG. 17, in a device that satisfies the above equations (1), (2), (5), and (6), almost no leak current flows when the gate is off, and the breakdown voltage is higher than that of a device that does not satisfy the above equation. It has been found that can be improved. Then, the breakdown voltage and the effect of improving the reliability as described above, as is apparent from the equation, even with a shorter gate length L _g, term calculated (shallow acceptors other than the gate length L _g of each formula Concentration N _A , deep acceptor concentration N _DA, etc.). Therefore, by designing the gate length _Lg to a desired length, the switching speed of the device can be improved while maintaining the breakdown voltage.

Then, C (carbon) is when it is doped, a description will be given of the relationship between the impurity concentration of the carbon and _{N A + N DA -N D -N} DD as impurities electron transit layer 14.
Figure 18 is a diagram showing the relationship between the carbon concentration and the _{N A + N DA -N D -N} DD. First, reference is made to the above inequality (5).
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
This equation (5) indicates that the electron transit layer 14 does not punch through under the gate until the electron transit layer 14 is depleted under the field plate portion 192, whereby the leakage current under the gate can be reduced. Accordingly, while satisfying the equation (5), the lower the on-resistance during operation of the nitride semiconductor device 3, to reduce the gate resistance component by shortening the gate length L _g, and, N A ₊ N _DA -N _D it is preferred to maximize the value of -N _DD.

In this regard, referring to Figure 18, even if a large amount of carbon doped as an impurity, at about 1 × ¹⁰ 19 ^{cm -3} carbon _{concentration,} the value of _{N A + N DA -N D -N} DD is saturated . On the other hand, if carbon is doped at a concentration of 1 × 10 ¹⁹ cm ⁻³ , the crystal quality of the electron transit layer 14 deteriorates, which is not preferable. In other words, it can be seen from FIG. 18 that the carbon concentration is preferably in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . In this range, even if small gate resistance component by shortening the gate length L _g, since the extent there is no influence such as degradation of crystal quality can increase the value of _{N A + N DA -N D -N} DD Equation (5) can be satisfied while lowering the on-resistance of the nitride semiconductor device 3.

Further, the carbon concentration in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ may be applied to the whole of the electron transit layer 14, but is preferably from the interface with the electron supply layer 15. It is preferably applied to a remote region, and it is preferable that a carbon concentration lower than the above range is applied to the interface with the electron supply layer 15. This is evidenced by FIGS. 19A, 19B, 20A, 20B and 20C.

FIGS. 19A and 19B are diagrams showing Reference Structure 1 and Reference Structure 2 set for simulation, respectively. In FIG. 19A and FIG. 19B, of the reference symbols shown in FIG. 2, only the symbols necessary for the following description are described, and other corresponding parts are omitted.
19A and 19B, the difference between Reference Structure 1 and Reference Structure 2 is that the electron transit layer 14 of Reference Structure 1 forms the first region where the interface between the electron transit layer 14 and the electron supply layer 15 is formed. 141 and a second region 142 formed at a portion (0.3 μm = 300 nm in this embodiment) away from the interface. For both structures, the pressure unit written on the left side of “GaN” of the electron transit layer 14 indicates a growth pressure when GaN is grown. When growing GaN using MOCVD, it is possible to increase the amount of carbon contained in TMG, which is a Ga (gallium) source, into the GaN crystal by lowering the growth pressure and the growth temperature when growing GaN. it can. Therefore, in the reference structure 1 of FIG. 19A, the carbon concentration of the second region 142 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ , while the carbon concentration of the first region 141 is 1 × 10 ¹⁷ cm ^{−3. −3} or less. In the reference structure 2 of FIG. 19B, the entire carbon concentration of the electron transit layer 14 is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

FIG. 20A shows the relationship between the carbon concentration and the sheet resistance of the two-dimensional electron gas for each structure, and FIG. 20B shows the relationship between the carbon concentration and the mobility of the two-dimensional electron gas. FIG. 20C shows the relationship between the carbon concentration and the sheet carrier density of the two-dimensional electron gas.
As shown in FIGS. 20A to 20C, in Reference Structure 2, as a result of uniformly increasing the carbon concentration of the electron transit layer 14, the sheet resistance of the two-dimensional electron gas increases and the mobility of the two-dimensional electron gas increases. And the sheet carrier density was reduced. On the other hand, in the reference structure 1, the sheet resistance, the mobility, and the sheet carrier of the two-dimensional electron gas were reduced because the carbon concentration at the interface with the electron supply layer 15 was suppressed to 1 × 10 ¹⁷ cm ⁻³ or less. Little change in density was seen.

On the other hand, as shown in FIG. 21, at the junction of AlGaN / GaN, mobility of two-dimensional electron gas is dependent on the sheet carrier density _{N s,} generally ^{_{N s = 8 × 10 12 cm}} -2 ~1 × It has been found that the maximum value is obtained in the range of 10 ¹³ cm ⁻² . Therefore, in the _following, on the assumption that it is ^{_{N s = 8 × 10 12 cm}} -2 ~1 × 10 13 cm -2, and calculates a preferred gate length _{L g,} and the thickness of the gate length _{L g} and the gate insulating film 16 Sought a relationship.

First, between the gate and the drain, as shown in FIG. 22A, a two-dimensional electron gas (2DEG) spreads at the AlGaN / GaN interface due to polarization caused by these heterojunctions and lattice mismatch. Here, when determining the mobility of two-dimensional electron gas based on _{^{N s = 8 × 10 12 cm}} -2 ~1 × 10 13 cm -2 , which is a prerequisite, the mobility mu = about 1500 cm ² / Vs . When the sheet resistance at the AlGaN / GaN interface is calculated from these, the sheet resistance Rs = 400Ω to 500Ω / sq.

On the other hand, as for the gate portion, as shown in FIG. 22B, a case where the gate insulating film has a single-layer structure of SiO ₂ (film thickness = 40 nm) and a gate voltage of 5 V is applied. Sheet carrier density _{N s} of the two-dimensional electron gas generated at the time of application of the gate voltage, becomes 6 × ¹⁰ 12 ^{cm -2} order, the mobility mu and the sheet resistance Rs is calculated therefrom, respectively, μ = 100~200cm ² / Vs and Rs = 5000Ω to 10000Ω / sq.

Here, in a device having a gate-drain breakdown voltage of 200 V, a distance of at least about 6 μm is required between the gate and the drain. In this case, the sheet resistance Rs of the gate portion as described above the gate - Considering that approximately 10 times the sheet resistance Rs of the drain, the gate length L _g is the gate - drain distance of (6 [mu] m) to about If it is not set to 1/10, the resistance cannot be equalized, and most of the ON resistance becomes the resistance of the gate portion. Accordingly, the gate length _{L g,} it is preferable that in the 0.6μm or less.

_{23, N A + N DA -N D} -N DD is, the lower limit of the preferred carbon concentration in the range ^{(1 × 10 18 cm -3 ~1} × 10 19 cm -3) of Figure 18 (about 4 × ^{10 16 3} shows the relationship between the gate length _Lg and the gate breakdown voltage when the voltage is in the range of cm ⁻³ ).
As shown in FIG. 23, when the gate length _{L g} is 0.6 .mu.m, the gate breakdown voltage of about 15V. That is, when a voltage of 15 V is applied to the gate, a leak current due to punch-through occurs below the gate, as shown in FIG. Therefore, in order to prevent such a leak current from occurring, it is necessary to deplete the area under the field plate portion 192 with a voltage lower than the voltage value of the gate breakdown voltage.

Figure 24 _is a diagram showing the relationship between _{N A + N DA -N D -N} DD and depletion voltage under the field plate. FIG. 24 shows the relationship when the thickness of the gate insulating film (SiN) is d = 100 nm, d = 200 nm, and d = 300 nm.
As shown in FIG. _24, the depletion voltage when _{N A + N DA -N D -N} DD = 4 × 10 16 cm -3 are respectively, when the case of d = 100 nm is 14 V, the d = 200 nm 26V , D = 300 nm is 34 V, and only when d = 100 nm, the depletion voltage <gate breakdown voltage (15 V) is satisfied. That is, assuming that the relative dielectric constant of SiN is ε = 7, when d / ε is 14 or less, before punch-through occurs under the gate, depletion is performed under the field plate portion 192 to suppress the leak current. Can be.

As described above, the embodiments of the present invention have been described, but the present invention can be further embodied in other forms.
For example, the field plate portion 192 does not need to be formed integrally with the gate main body portion 191, and may be formed as a field plate separated from the gate main body portion 191. In this case, the field plate may be electrically connected to the source electrode 17.

Further, in the nitride semiconductor device 3, even if the following expression (9) or (11), more preferably the following expression (10) or (12) is satisfied, the withstand voltage can be improved.
^{_{N s 2 / (N A +}} N DA -N D -N DD) <(N A + N DA -N D -N DD) · (L g + L fp) 2 ··· (9)
^{_{N s 2 / (N A +}} N DA) <(N A + N DA) · (L g + L fp) 2 ··· (11)
_{(N A + N DA -N D} -N DD) · (L g + L fp) 2 <1.2N s 2 / (N A + N DA -N D -N DD) ··· (10)
(N _A + N _DA ) · (L _g + L _fp ) ² <1.2 N _s ² / (N _A + N _DA ) (12)
Left side of the _N ^s 2 _/ of formula _{(9) (N A + N} DA -N D -N DD) , in FIG. 2, two-dimensional electrons from the edge of the drain electrode 18 side of the field plate portion 192 to the drain electrode 18 The voltage V _{3 at which the} gas is depleted (described with reference to FIG. 8) is shown. On the other hand, the right-hand side of _{(N A + N DA -N D} -N DD) · (L g + L fp) 2 of formula (9) shows the breakdown voltage can be held in the gate electrode 19 (gate body portion 191Tasu field plate portion 192) ing.

  Until the two-dimensional electron gas from the end on the drain electrode 18 side of the field plate portion 192 to the drain electrode 18 is depleted, a voltage drop occurs in the gate main body portion 191 and the field plate portion 192. Is depleted from the end to the drain electrode 18, a voltage drop occurs from the gate body 191 to the drain electrode 18. That is, the withstand voltage is maintained in the section A of FIG. 2 at a low drain voltage, but is maintained in the section B at a high drain voltage. Therefore, Expressions (9) and (11) indicate that at least the gate electrode 19 (the gate body portion 191+) is used until the two-dimensional electron gas from the end on the drain electrode 18 side of the field plate portion 192 to the drain electrode 18 is depleted. This means that the withstand voltage is maintained by the field plate portion 192).

  Further, in the above-described embodiment, an example has been described in which the electron transit layer 14 is made of a GaN layer and the electron supply layer 15 is made of AlGaN. However, if the electron transit layer 14 and the electron supply layer 15 have different Al compositions, Well, other combinations are possible. The combination of the electron supply layer / electron transit layer includes AlGaN layer / GaN layer, AlGaN layer / AlGaN layer (although having different Al composition), AlInN layer / AlGaN layer, AlInN layer / GaN layer, AlN layer / GaN layer, AlN layer. Layer / AlGaN layer. More generally, the electron supply layer contains Al and N in the composition. The electron transit layer contains Ga and N in the composition, and the Al composition is different from that of the electron supply layer. When the Al composition is different between the electron supply layer and the electron transit layer, lattice mismatch occurs between them, and carriers resulting from polarization contribute to the formation of a two-dimensional electron gas.

Further, in the above-described embodiment, silicon is exemplified as a material example of the substrate 12, but any other substrate material such as a sapphire substrate or a GaN substrate can be applied.
In addition, various design changes can be made within the scope of the matters described in the claims.

Reference Signs List 3 nitride semiconductor device 12 substrate 13 buffer layer 131 first buffer layer 132 second buffer layer 14 electron transit layer 141 first region 142 second region 15 electron supply layer 16 gate insulating film 161 first insulating layer 162 second insulating layer Reference Signs List 17 Source electrode 18 Drain electrode 19 Gate electrode 191 Gate body 191a Drain end of gate electrode 191b Source end of gate electrode 192 Field plate part 20 Two-dimensional electron gas L _g Gate length L _fp Field plate length L _gd Distance between gate and drain

Claims (16)

A gate, a nitride semiconductor layer having a source and a drain,
A field plate on the nitride semiconductor layer electrically connected to the gate or the source,
The drain voltage value at which the value of _Coss decreases to half the value when the drain voltage is 0 V is V ₁ (V), the breakdown voltage of the device is V ₂ (V), and the gate length is L _g (cm). The field plate length is L _fp (cm), the shallow acceptor concentration is N _A (/ cm ³ ), the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum permittivity is ε ₀ , and the relative permittivity of the nitride semiconductor layer is A nitride semiconductor device that satisfies the following equations (1) and (2) when the rate is ε.
V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
V ₂ <q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε (2) The nitride semiconductor device according to claim 1, wherein the following formulas (3) and (4) are satisfied.
q (N _A + N _DA ) · L _g ² / 2ε ₀ ε <1.2V ₁ (3)
q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε <1.2 V ₂ (4) A gate, a nitride semiconductor layer having a source and a drain,
A field plate on the nitride semiconductor layer electrically connected to the gate or the source,
The drain voltage value at which the value of _Coss decreases to half the value when the drain voltage is 0 V is V ₁ (V), the breakdown voltage of the device is V ₂ (V), and the gate length is L _g (cm). The field plate length is L _fp (cm), the shallow donor concentration is N _D (/ cm ³ ), the deep donor concentration is N _DD (/ cm ³ ) _{, the} shallow acceptor concentration is N _A (/ cm ³ ), and the deep acceptor concentration is _Is N _DA (/ cm ³ ), the vacuum dielectric constant is ε ₀ , and the relative dielectric constant of the nitride semiconductor layer is ε, a nitride semiconductor device satisfying the following formulas (5) and (6).
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6) The nitride semiconductor device according to claim 3, wherein the following formulas (7) and (8) are satisfied.
_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8) A gate, a nitride semiconductor layer having a source and a drain,
A field plate on the nitride semiconductor layer electrically connected to the gate or the source,
The drain voltage value at which the value of _Coss decreases to half the value when the drain voltage is 0 V is V ₁ (V), the maximum rated voltage of the device is V ₂ (V), and the gate length is L _g (cm). The field plate length is L _fp (cm), the shallow acceptor concentration is N _A (/ cm ³ ), the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum permittivity is ε ₀ , and the relative permittivity of the nitride semiconductor layer is A nitride semiconductor device that satisfies the following equations (1) and (2) when the rate is ε.
V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
V ₂ <q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε (2) The nitride semiconductor device according to claim 5, wherein the following formulas (3) and (4) are satisfied.
q (N _A + N _DA ) · L _g ² / 2ε ₀ ε <1.2V ₁ (3)
q (N _A + N _DA ) · (L _g + L _fp ) ² / 2ε ₀ ε <1.2 V ₂ (4) A gate, a nitride semiconductor layer having a source and a drain,
A field plate on the nitride semiconductor layer electrically connected to the gate or the source,
The drain voltage value at which the value of _Coss decreases to half the value when the drain voltage is 0 V is V ₁ (V), the maximum rated voltage of the device is V ₂ (V), and the gate length is L _g (cm). The field plate length is L _fp (cm), the shallow donor concentration is N _D (/ cm ³ ), the deep donor concentration is N _DD (/ cm ³ ) _{, the} shallow acceptor concentration is N _A (/ cm ³ ), and the deep acceptor concentration is _Is N _DA (/ cm ³ ), the vacuum dielectric constant is ε ₀ , and the relative dielectric constant of the nitride semiconductor layer is ε, a nitride semiconductor device satisfying the following formulas (5) and (6).
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
_{V 2 <q (N A +} N DA -N D -N DD) · (L g + L fp) 2 / 2ε 0 ε ··· (6) The nitride semiconductor device according to claim 7, wherein the following formulas (7) and (8) are satisfied.
_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{q (N A + N DA -N} D -N DD) · (L g + L fp) 2 / 2ε 0 ε <1.2V 2 ··· (8) A gate, a nitride semiconductor layer having a source and a drain,
A field plate on the nitride semiconductor layer electrically connected to the gate or the source,
_V 1 the drain voltage value the value of C _oss is reduced to 1/2 of the value when the drain voltage 0V (V), two-dimensional electron gas sheet carrier density _N s (/ ^cm 2), a gate length L _g (cm), field plate length L _fp (cm), shallow donor concentration N _D (/ cm ³ ), deep donor concentration N _DD (/ cm ³ ) _{, and} shallow acceptor concentration N _A (/ cm ^3). ), When the deep acceptor concentration is N _DA (/ cm ³ ), the vacuum permittivity is ε ₀ , and the relative permittivity of the nitride semiconductor layer is ε, the nitride satisfying the following formulas (5) and (9): Semiconductor device.
_{V 1 <q (N A +} N DA -N D -N DD) · L g 2 / 2ε 0 ε ··· (5)
^{_{N s 2 / (N A +}} N DA -N D -N DD) <(N A + N DA -N D -N DD) · (L g + L fp) 2 ··· (9) The nitride semiconductor device according to claim 9, wherein the following formulas (7) and (10) are satisfied.
_{q (N A + N DA -N} D -N DD) · L g 2 / 2ε 0 ε <1.2V 1 ··· (7)
_{(N A + N DA -N D} -N DD) · (L g + L fp) 2 <1.2N s 2 / (N A + N DA -N D -N DD) ··· (10) A gate, a nitride semiconductor layer having a source and a drain,
A field plate on the nitride semiconductor layer electrically connected to the gate or the source,
_V 1 the drain voltage value the value of C _oss is reduced to 1/2 of the value when the drain voltage 0V (V), two-dimensional electron gas sheet carrier density _N s (/ ^cm 2), a gate length L _g (cm), the field plate length L _fp (cm), the shallow acceptor concentration N _A (/ cm ³ ), the deep acceptor concentration N _DA (/ cm ³ ), the vacuum permittivity ε ₀ , and the nitride A nitride semiconductor device that satisfies the following expressions (1) and (11), where ε is the relative dielectric constant of the semiconductor layer.
V ₁ <q (N _A + N _DA ) · L _g ² / 2ε ₀ ε (1)
^{_{N s 2 / (N A +}} N DA) <(N A + N DA) · (L g + L fp) 2 ··· (11) The nitride semiconductor device according to claim 11, wherein the following formulas (3) and (12) are satisfied.
q (N _A + N _DA ) · L _g ² / 2ε ₀ ε <1.2V ₁ (3)
(N _A + N _DA ) · (L _g + L _fp ) ² <1.2 N _s ² / (N _A + N _DA ) (12) 13. The device according to claim 1, wherein the gate length L _g is 0.5 μm or less, the field plate length L _fp is 0.5 μm or less, and the maximum rated voltage of the device is 50 V or more. Nitride semiconductor devices.   The nitride semiconductor layer includes a group consisting of C, Be, Cd, Ca, Cu, Ag, Au, Sr, Ba, Li, Na, K, Sc, Zr, Fe, Co, Ni, Mg, Ar, and He. The nitride semiconductor device according to any one of claims 1 to 13, wherein a deep acceptor level is formed by doping at least one impurity selected from the group consisting of: An electron transit layer, and a nitride semiconductor layer including an electron supply layer in contact with the electron transit layer and having a composition different from that of the electron transit layer;
A gate, a source, and a drain on the nitride semiconductor layer;
A field plate on the nitride semiconductor layer electrically connected to the gate or the source,
Wherein at least a portion of the electron transit layer are contained in carbon, Ri concentration of the carbon ^{1 × 10 18 cm -3 ~1 ×} 10 19 cm -3 der,
The electron transit layer includes a first region forming an interface between the electron transit layer and the electron supply layer, and a second region formed at a portion separated from the interface by 50 nm or more.
The second region has a carbon concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ , the first region has a carbon concentration of 1 × 10 ¹⁷ cm ⁻³ or less,
When the shallow donor concentration is N _D (/ cm ³ ), the deep donor concentration is N _DD (/ cm ³ ) _{, the} shallow acceptor concentration is N _A (/ cm ³ ), and the deep acceptor concentration is N _DA (/ cm ³ ). ,
Wherein _{N A + N DA -N D -N} DD of the second region of the electron transit layer, Ru ^{4 × 10 16 cm -3 ~8 ×} 10 16 cm -3 der, nitride semiconductor devices. An electron transit layer, and a nitride semiconductor layer including an electron supply layer in contact with the electron transit layer and having a composition different from that of the electron transit layer;
A gate, a source, and a drain on the nitride semiconductor layer;
A field plate electrically connected to the gate or the source and disposed on the nitride semiconductor layer via an insulating film;
The gate length L _g is 0.6 μm or less;
At least a part of the electron transit layer contains carbon, and the concentration of the carbon is 1 × 10 ¹⁸ cm ⁻³ or more,
A nitride semiconductor device that satisfies d / ε ≦ 14, where d (nm) is the thickness of the insulating film below the field plate, and ε is the relative dielectric constant of the insulating film.

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