JP6596901B2 - Data transfer control device and electronic device using the same - Google Patents

Description

  The present invention relates to a data transfer control device that controls data transfer between a plurality of devices. Furthermore, the present invention relates to an electronic device using such a data transfer control device.

  In recent years, serial interfaces standardized by the USB (Universal Serial Bus) standard or the like have become widespread in order to connect various peripheral devices to a host device. Such a serial interface is widely used for connection between a personal computer and a printer, connection between a digital camera and a printer, or connection between a car navigation device and a portable audio device.

  For example, a personal computer has about 2 to 4 USB ports, but USB peripheral devices include a keyboard, mouse, printer, USB memory, external HDD (hard disk drive), etc. To do. Therefore, a USB hub is used to connect a personal computer with USB and many peripheral devices.

  In this case, a host device is connected to the upstream port circuit of the USB hub via USB, and a slave device is connected to the downstream port circuit of the USB hub via USB. Then, the USB hub controls data transfer between the host device and the slave device.

  However, in such a configuration, the connection target of the upstream port circuit is limited to the host device, and the connection target of the downstream port circuit is limited to the slave device. Therefore, it is not possible to control a system by connecting a dual role device having a host function in addition to a slave function to the downstream port circuit, or to control a host device connected to the upstream port circuit as a slave device. was there.

  As a related technique, Patent Document 1 discloses a data transfer control device capable of switching a port connection target. The data transfer control device includes an upstream port circuit, a plurality of downstream port circuits, and a hub logic circuit that performs data transfer control between the upstream port circuit and the plurality of downstream port circuits. An upstream / downstream port circuit is provided as at least one of the downstream port circuits.

  In the hub mode, the upstream port circuit performs an upstream port operation, and the upstream / downstream port circuit performs a downstream port operation. In the device mode, the upstream port circuit performs interface processing with the physical layer circuit of the upstream / downstream port circuit, and the upstream / downstream port circuit performs upstream port operation.

  Patent Document 2 discloses a USB host and a USB device when a USB device compliant with the OTG (On-The-Go) standard (a standard defined for connecting USB-compatible peripheral devices) is connected. There is disclosed a USB device control method capable of easily switching between and.

  In this USB device control method, when a plurality of USB devices including a dual role device functioning as a USB device or a USB host are connected via a hub, the function at the time of connecting the dual role device is determined, and the dual role device is determined. It is characterized by switching between a USB device and a USB host.

Japanese Patent Laying-Open No. 2010-93437 (paragraphs 0005 to 0006, FIG. 2) Japanese Patent Laying-Open No. 2004-157604 (paragraphs 0005 to 0006, FIG. 1)

  However, some dual-role devices cannot control a USB hub. Also, the inter-packet delay time is defined in the USB standard, but if a bit loss or dribble bit occurs due to a delay in detection of received data in the squelch detection circuit of the port circuit, the inter-packet delay time changes. The USB standard cannot be observed. Furthermore, some dual-role devices can be a host but do not have a protocol to return to a slave. A host device that has given the host right to such a device cannot acquire the host right again.

  Accordingly, a first object of the present invention is to enable such a device to perform a host operation when a device that has a host function but cannot control the hub is connected to the data transfer control device. That is. A second object of the present invention is to reduce bit loss or dribble bits when a device that cannot control a hub transfers data to other devices via a data transfer control device. Furthermore, a third object of the present invention is to enable a host device that has given a host right to a device that can become a host but does not have a protocol for returning to a slave, to acquire the host right again.

In order to solve at least a part of the above problems, a data transfer control device according to a first aspect of the present invention includes a first port circuit, a second port circuit, a first port circuit, and a second port circuit. In the first mode, the hub logic circuit that controls the transfer of data to and from the port circuit, the repeater circuit that reduces and outputs bit loss or dribble bits by at least shaping the input received data, and the first mode A first port circuit that performs a stream port operation is electrically connected to the hub logic circuit, and a first port circuit that performs a downstream port operation is electrically connected to the repeater circuit in the second mode. The selector circuit and the second port circuit that performs the downstream port operation in the first mode are electrically connected to the hub logic circuit. In the second mode, and a second selector circuit for electrically connecting the second port circuit that performs upstream port operation repeater circuit.

The data transfer control device according to the second aspect of the present invention includes a first port circuit, a second port circuit, a first port circuit that performs upstream port operation in the first mode, and a down port. By controlling the transfer of data to and from the second port circuit that performs the stream port operation, and at least shaping the received data that is input from the second port circuit that performs the upstream port operation in the second mode The bit loss or dribble bit is reduced and output to the first port circuit, and at least the received data input from the first port circuit performing the downstream port operation is shaped to reduce the bit loss or dribble bit. And a hub repeater logic circuit for outputting to the second port circuit.

According to the first or second aspect of the present invention, the data transfer control device at least shapes the reception data input from the second port circuit that performs the upstream port operation in the second mode , The bit loss or dribble bit is reduced and output to the first port circuit, and at least the received data input from the first port circuit performing the downstream port operation is shaped to reduce the bit loss or dribble bit. It operates as a repeater that outputs to the second port circuit. Accordingly, when a device that has a host function but cannot control the hub is connected to the second port circuit, such a device can perform a host operation. Here, the repeater circuit can reduce the bit loss or dribble bit by shaping the input received data, and can improve the dull waveform in the bus cable or the physical layer circuit.

In the first or second aspect of the present invention, the data transfer control device, in the second mode, device is disconnected from the second port circuit, or the device connected to the second port circuit when it stops communication is detected, or the connected bus to the first port circuit to suspend or supply bus supply potential to the power supply terminal of the bus connector connected to a first port circuit A control circuit for controlling the first port circuit so as to stop the operation may be further provided. Thus, even if the host device connected to the first port circuit gives the host right to the device connected to the second port circuit, the host device determines that the device does not already need the host right. be able to.

In this case, the control circuit, when the device connected to the first port circuit is detected that releases the pull-up of a predetermined terminal of the bus connector, the second mode of data transfer control device May be shifted to the first mode. Thus, the host device that has canceled the pull-up of the predetermined terminal can acquire the host right again.

In the above, the data transfer control device includes a plurality of second port circuits, and the control circuit selects the second code based on the identification code that identifies the port circuit selected from the plurality of second port circuits. in mode, and it outputs a signal for permitting data transmission operation definitive to the selected port circuit, and outputs a signal for prohibiting the data transmission operation definitive other port circuit of the plurality of second port circuits May be. As a result, other port circuits are set to a suspended state, a disconnected state, or the like, so that power consumption in unused port circuits can be reduced.

  An electronic device according to one aspect of the present invention includes any one of the data transfer control devices described above. Thus, when a device that has a host function but cannot control the hub is connected, an electronic device that enables such a device to perform a host operation can be provided.

The figure which shows the structure of the system containing the data transfer control apparatus which concerns on 1st Embodiment. The circuit diagram which shows the connection state in repeater mode of a data transfer control apparatus. FIG. 3 is a circuit diagram showing a configuration example of a squelch detection circuit shown in FIG. 2. FIG. 3 is a block diagram illustrating a configuration example of a sampling clock signal generation circuit illustrated in FIG. 2. The timing chart for demonstrating operation | movement of the repeater circuit shown in FIG. The timing chart for demonstrating the operation example of a data transfer control apparatus. The figure which shows the structural example of the data transfer control apparatus which concerns on 2nd Embodiment. 1 is a block diagram illustrating a configuration example of an electronic device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
<First Embodiment>
FIG. 1 is a block diagram showing a configuration example of a system including a data transfer control device according to the first embodiment of the present invention. As shown in FIG. 1, this system includes a main controller 10, a data transfer control device 20, and at least one device 30.

<Main controller>
The main controller 10 is, for example, a vehicle-mounted device such as a car navigation device or a personal computer, and has a slave function in addition to a host function. The main controller 10 includes a link controller 11 and an interface circuit (I / F) 12 that conforms to a USB standard including the UTMI standard or the ULPI standard.

  Here, the UTMI standard is an abbreviation for USB 2.0 Transceiver Macrocell Interface, and is an interface standard between a USB controller (logical layer circuit) and a transceiver (physical layer circuit). The ULPI standard is an abbreviation of UTMI + Low Pin Interface, and is a standard in which the number of wirings of the interface of the UTMI standard is reduced.

  Alternatively, the main controller 10 may include a root hub in addition to the interface circuit 12 or instead of the interface circuit 12. In addition to transmitting / receiving data to / from the data transfer control device 20, the root hub can also transmit / receive data to / from other devices.

<Device>
The device 30 is, for example, a keyboard, a mouse, a printer, a memory, an external HDD, or a portable audio device, and includes an interface circuit that conforms to the USB standard or the like. At least one of the devices 30 is a dual role device 30 a having a host function in addition to a slave function, and can control the main controller 10 via the data transfer control device 20. For example, a smart phone, a portable terminal, etc. correspond to the dual roll device 30a.

<Data transfer control device>
The data transfer control device 20 includes a port circuit 21, a port circuit 22, a hub logic circuit 23, a repeater circuit 24, selector circuits 25 and 26, a control circuit 27, and a storage unit 28.

  The port circuit 21 has an upstream port function and a downstream port function, and is connected to the main controller 10 via a bus. The port circuit 22 has a downstream port function, and is connected to the device 30 via a bus. At least one of the port circuits 22 has a downstream port function and an upstream port function, and is connected to the dual-role device 30a via a bus.

  The port circuit 21 includes an interface circuit 40 that conforms to the USB standard or the like. The interface circuit 40 performs interface processing with the main controller 10. The port circuit 21 performs data transfer and interface signal conversion processing between the main controller 10 and the hub logic circuit 23 or repeater circuit 24.

  For example, when the interface circuit 12 of the main controller 10 conforms to the UTMI standard, the interface circuit 40 is connected to the interface circuit 12 via a UTMI standard bus and performs interface processing of the UTMI standard with the interface circuit 12. You can go.

  Alternatively, when the link controller 11 of the main controller 10 conforms to the ULPI standard, the interface circuit 40 is connected to the link controller 11 via a ULPI standard bus, and performs interface processing of the ULPI standard with the link controller 11. Also good. In that case, the interface circuit 40 can directly perform interface processing with the link controller 11 without going through a transceiver (physical layer circuit).

  The port circuit 22 includes an interface circuit 50 that conforms to the USB standard or the like. The interface circuit 50 performs interface processing with the device 30. The port circuit 22 performs data transfer between the device 30 and the hub logic circuit 23 or the repeater circuit 24 and interface signal conversion processing.

  The hub logic circuit 23 is composed of, for example, a combinational logic circuit or a sequential circuit, and controls data transfer between the port circuit 21 and the port circuit 22, thereby allowing data between the main controller 10 and the device 30. Control the transfer of.

  Specifically, the hub logic circuit 23 controls data transfer of the port circuit 21 and transfers data to and from the main controller 10. Alternatively, the hub logic circuit 23 controls data transfer of the port circuit 22 and transfers data to and from the device 30. For example, the hub logic circuit 23 performs connection processing or disconnection processing between the port circuit 21 or 22 and the main controller 10 or the device 30, performs processing for detecting a bus error (fault), or recovers from a bus error. To control data transfer.

  The hub logic circuit 23 supports data transfer rates of HS mode (high speed mode: 480 Mbps), FS mode (full speed mode: 12 Mbps), and LS mode (low speed mode: 1.5 Mbps) compliant with the USB 2.0 standard. can do. For example, the hub logic circuit 23 translates an HS transaction transmitted from the main controller 10 into an FS transaction or an LS transaction, and transfers it to the port circuit 22.

<Switching between host operation and slave operation>
The main controller 10 and the dual role device 30a can be switched between a host operation and a slave operation, and can operate as both a host controller and a device.

  For example, the main controller 10 manages a control flow and a data transfer flow with the data transfer control device 20 as a host operation. The dual role device 30a transmits various requests to the main controller 10 as a host operation. On the other hand, the main controller 10 and the dual-role device 30a perform request processing and enumeration processing from the host controller as slave operations.

  However, some dual role devices having a host function in addition to a slave function include devices that cannot control the hub. Therefore, in the present embodiment, the repeater circuit 24, the selector circuits 25 and 26, the control circuit 27, and the storage unit are provided so that even if the dual roll device 30a is a device that cannot control the hub, other devices can be controlled. 28 are provided.

  The repeater circuit 24 shapes and retims the input received data and outputs it. The selector circuit 25, which is the first selector circuit, includes, for example, a plurality of transistors or a plurality of transmission gates, and electrically connects the port circuit 21 to a selected one of the hub logic circuit 23 and the repeater circuit 24. Connecting.

  The selector circuit 26, which is the second selector circuit, is composed of, for example, a plurality of transistors or a plurality of transmission gates, and electrically connects the port circuit 22a to a selected one of the hub logic circuit 23 and the repeater circuit 24. In addition to the connection, the other port circuit 22 is electrically connected to the hub logic circuit 23.

  The control circuit 27 is composed of, for example, a combinational logic circuit or a sequential circuit, and controls each unit of the data transfer control device 20. The storage unit 28 includes, for example, a register or a nonvolatile memory, and stores a register value or an identification code used for control of the data transfer control device 20. The storage unit 28 may store device information including an address of a device having a host function.

  In the first mode in which the main controller 10 performs the host operation, the control circuit 27 controls the port circuit 21 to perform the upstream port operation and also controls the port circuit 22a to perform the downstream port operation. In addition, the control circuit 27 controls the selector circuit 25 so that the port circuit 21 that performs the upstream port operation is electrically connected to the hub logic circuit 23, and the port circuit 22a that performs the downstream port operation is the hub logic circuit. The selector circuit 26 is controlled so as to be electrically connected to 23.

  In the second mode in which the dual role device 30a performs the host operation, the control circuit 27 controls the port circuit 21 to perform the downstream port operation and also controls the port circuit 22a to perform the upstream port operation. . Further, the control circuit 27 controls the selector circuit 25 so that the port circuit 21 that performs the downstream port operation is electrically connected to the repeater circuit 24, and the port circuit 22 a that performs the upstream port operation to the repeater circuit 24. The selector circuit 26 is controlled so as to be electrically connected.

  Hereinafter, the first mode in which the main controller 10 performs the host operation is also referred to as “hub mode”, and the second mode in which the dual roll device 30a performs the host operation is also referred to as “repeater mode”. The control circuit 27 sets the mode setting signal MOD to the first logic level when the data transfer control device 20 is set to the hub mode, and sets the mode setting signal MOD to the first logic level when the data transfer control device 20 is set to the repeater mode. 2 logic levels.

  For example, the main controller 10 and the dual-role device 30a may conform to the OTG (On-The-Go) standard, and may switch between the host operation and the slave operation according to the OTG standard. Alternatively, the main controller 10 and the dual-role device 30a may recognize the connection partner by negotiation at the time of connection with the data transfer control device 20, and switch between the host operation and the slave operation based on the recognition result. In those cases, the control circuit 27 may output the mode setting signal MOD based on the state of the bus set by the main controller 10 or the dual roll device 30a.

  Alternatively, based on a request transmitted from the main controller 10 to the hub logic circuit 23, the storage unit 28 may store a register value for setting a mode. In that case, the control circuit 27 may output the mode setting signal MOD based on the register value stored in the storage unit 28.

  Alternatively, a mode setting terminal or a mode setting switch is provided in the data transfer control device 20 or an electronic device using the same, and the main controller 10 and the dual roll device 30a receive a signal from the mode setting terminal or the mode setting switch. The host operation and the slave operation may be switched. In that case, a signal from the mode setting terminal or the mode setting switch may be used as the mode setting signal MOD.

  In the hub mode, the port circuits 21 and 22 are electrically connected to the hub logic circuit 23, the main controller 10 connected to the port circuit 21 performs a host operation, and the device 30 connected to the port circuit 22 is a slave. The data transfer control device 20 operates as a normal hub.

  On the other hand, in the repeater mode, the port circuits 21 and 22a are electrically connected to the repeater circuit 24, and the dual-role device 30a connected to the port circuit 22a performs the host operation and the main circuit connected to the port circuit 21. The controller 10 performs a slave operation, and the data transfer control device 20 operates as a repeater. Thus, when the dual role device 30a that has the host function but cannot control the hub is connected to the port circuit 22a, the dual role device 30a can perform the host operation.

  Also, in the USB standard, a time interval between packets (Inter Packet Delay) within one transaction is defined, but this is caused by a delay in detection of received data in the squelch detection circuit of the port circuit. If a bit loss or dribble bit occurs, the inter-packet delay time changes and the USB standard cannot be observed.

  For example, in the USB 2.0 standard HS mode, the time required to detect a squelch indicating that the USB is in an idle state may be a time corresponding to a 4-bit data length. For this reason, up to 4 bits of data that should not be originally received after receiving the original packet in the receiving device, so-called dribble bits, are allowed.

  However, in the case of the data transfer control device, it is not preferable to transmit the dribble bit even if the received dribble bit is within the standard. Even if the dribble bit transmitted to the subsequent device of the data transfer control device is 4 bits or less, it is possible that the excess data connected after the end code in the subsequent device exceeds 4 bits. This is because an undesirable operation may occur depending on the design contents.

  According to the present embodiment, since the repeater circuit 24 shapes and retimates the input received data, the bit loss or dribble bit is reduced, and the blunt waveform in the bus cable or physical layer circuit is improved. be able to. Next, the repeater circuit 24 will be described in detail with reference to FIG.

  FIG. 2 is a circuit diagram showing a connection state in the repeater mode of the data transfer control device shown in FIG. FIG. 2 shows the first port circuit 21, the second port circuit 22 a, the repeater circuit 24, and part of the selector circuits 25 and 26. In the following, as an example, a case where the first port circuit 21 and the second port circuit 22a include an interface circuit compliant with the USB standard will be described.

<First port circuit>
The first port circuit 21 includes a first USB connector including a data terminal D +, a data terminal D−, a power supply terminal VB, and a power supply terminal VG, an interface circuit 40, a sampling clock signal generation circuit 45, and a buffer circuit. (Elasticity buffer) 46 and a parallel / serial conversion circuit 47 are included. The interface circuit 40 includes a differential receiver 41, a differential driver 42, a connection state detection circuit 43, a squelch detection circuit 44, switch circuits SW1 to SW4, and resistors R1 to R3, R11, and R12. .

  The differential receiver 41 has a non-inverting input terminal connected to the data terminal D + of the first USB connector and an inverting input terminal connected to the data terminal D− of the first USB connector. The received data DIN is output by differentially amplifying the signal input to the input terminal.

  The differential driver 42 operates when the transmission enable signal EN1 is activated during data transmission, amplifies the transmission data DOUT input to the input terminal, and generates an output signal and an inverted output signal. The output terminal of the differential driver 42 is connected to the data terminal D + of the first USB connector via the resistor R11, and the inverted output terminal is connected to the data terminal D- of the first USB connector via the resistor R12. ing. When the transmission enable signal EN1 is inactivated, the output terminal and the inverted output terminal of the differential driver 42 are in an idle state (high impedance state).

  The switch circuits SW1 to SW4 are controlled to an on state or an off state in accordance with a control signal supplied from the control circuit 27 (FIG. 1). When the port circuit 21 performs the upstream port operation, the switches SW1 and SW2 are turned off and the switch circuit SW3 is turned on. As a result, the data terminal D + of the first USB connector is pulled up to the power supply potential VDD on the high potential side via the resistor R3. Further, the bus power supply potential VBUS is supplied from the power supply terminal VB of the first USB connector to the port circuit 21 via the switch circuit SW4.

  On the other hand, when the port circuit 21 performs the downstream port operation, the switch circuits SW1 and SW2 are turned on and the switch circuit SW3 is turned off. As a result, the data terminal D + of the first USB connector is pulled down to the power supply potential VSS on the low potential side via the resistor R1, and the data terminal D− is pulled down to the power supply potential VSS via the resistor R2. . Further, the bus power supply potential VBUS is supplied from the port circuit 21 to the power supply terminal VB of the first USB connector via the switch circuit SW4.

  When the port circuit 21 performs the downstream port operation, when a device in the HS mode or the FS mode is connected to the first USB connector via the USB bus, a high level signal is input to the data terminal D +, and the LS When a mode device is connected, a high level signal is input to the data terminal D-.

  The connection state detection circuit 43 includes, for example, a voltage dividing circuit that divides the power supply voltage (VDD−VSS), and a comparator that compares the levels of the data terminals D + and D− of the first USB connector with the divided voltage. The level of the data terminals D + and D− of the first USB connector is determined.

  Based on the determined level, the connection state detection circuit 43 detects that the device is connected to the first USB connector and that the device is disconnected from the first USB connector. Further, the connection state detection circuit 43 determines whether or not the data terminal D + or D− of the first USB connector is pulled up by a device connected to the first USB connector based on the determined level. Is detected. Based on the detection result, the connection state detection circuit 43 generates a connection state signal CS1 indicating the connection state of the device in the first USB connector, and the connection state signal CS1 is represented by the hub logic circuit 23 and the control circuit 27 shown in FIG. Output to.

  The squelch detection circuit 44 detects the presence / absence of a valid signal at the data terminals D + and D− of the first USB connector based on the bus activity or the current change amount, and generates a squelch signal SQ1 representing the detection result. The squelch detection circuit 44 outputs the squelch signal SQ1 to the buffer circuit 46, the packet detection correction circuit 61, and the hub logic circuit 23 and the control circuit 27 shown in FIG.

  FIG. 3 is a block diagram showing a configuration example of the squelch detection circuit shown in FIG. As shown in FIG. 3, the squelch detection circuit 44 includes a trigger circuit 71, an inverter 72, an AND circuit 73, a diode D0, a resistor R0, a capacitor C0, and a trigger circuit 74.

  The trigger circuit 71 differentially amplifies signals input to the data terminals D + and D− of the first USB connector to generate an output signal. The inverter 72 inverts the output signal of the trigger circuit 71. The AND circuit 73 generates a signal representing a logical product of the output signal of the trigger circuit 71 and the output signal of the inverter 72. The signal output from the AND circuit 73 is detected by the diode D0, the resistor R0, and the capacitor C0. The trigger circuit 74 has a hysteresis characteristic, determines the level of the detected signal, and generates the squelch signal SQ1.

  When the potential difference between the signals input to the data terminals D + and D− of the first USB connector becomes a predetermined value or more, the logical product of the output signal of the trigger circuit 71 and the output signal of the inverter 72 becomes a short pulse. The electric charge due to this short pulse is accumulated in the capacitor C0 via the diode D0. As a result, the input voltage of the trigger circuit 74 becomes a predetermined value or more, and the squelch signal SQ1 is activated to a high level. Further, when the potential difference between the signals input to the data terminals D + and D− of the first USB connector becomes a predetermined value or less, the input voltage of the trigger circuit 74 becomes a predetermined value or less and the squelch signal SQ1 becomes low level. Is deactivated.

  Referring to FIG. 2 again, the sampling clock signal generation circuit 45 is a sampling used to sample the reception data DIN based on a specific frequency component included in the reception data DIN output from the differential receiver 41. Generate a clock signal.

  FIG. 4 is a block diagram showing a configuration example of the sampling clock signal generation circuit shown in FIG. The sampling clock signal generation circuit 45 includes a PLL circuit 81 and a DLL circuit 82. The PLL circuit 81 includes, for example, a VCO (Voltage Controlled Oscillator) and generates multiphase clock signals CLK0 to CLK4 having the same frequency and different phases based on a specific frequency component included in the reception data DIN. .

  The DLL circuit 82 includes, for example, an edge detection circuit 83 and a clock signal selection circuit 84. The edge detection circuit 83 detects the edge of the reception data DIN. More specifically, the edge detection circuit 83 has an edge of the reception data DIN between any edges (rising edge or falling edge) of the multiphase clock signals CLK0 to CLK4 supplied from the PLL circuit 81. The edge detection information representing the detection result is output to the clock signal selection circuit 84. The clock signal selection circuit 84 selects one clock signal from the multiphase clock signals CLK0 to CLK4 based on the edge detection information, and outputs the selected clock signal to the buffer circuit 46 as the sampling clock signal SCLK.

  Referring to FIG. 2 again, the buffer circuit 46 includes, for example, a shift register or the like, and is serially input from the differential receiver 41 in synchronization with the sampling clock signal SCLK when the squelch signal SQ1 is activated. Stores received data DIN in the format. The reception data DIN stored in the buffer circuit 46 can be read as parallel data.

  In this way, by buffering the received data DIN, the difference between the frequency of the clock signal used in the device connected to the data transfer control device and the frequency of the internal clock signal of the data transfer control device is absorbed. Can do. The buffer circuit 46 fixes the input data at a low level or a high level when the squelch signal SQ1 is inactivated.

  The parallel / serial conversion circuit 47 includes, for example, a shift register and stores parallel data supplied from the repeater circuit 24 in synchronization with the internal clock signal ICLK1. The parallel / serial conversion circuit 47 reads the stored data in synchronization with the internal clock signal ICLK2, converts it into serial transmission data DOUT, and outputs it to the differential driver 42 of the interface circuit 40.

<Second port circuit>
The second port circuit 22a includes a second USB connector including a data terminal D +, a data terminal D−, a power supply terminal VB, and a power supply terminal VG, an interface circuit 50, a sampling clock signal generation circuit 55, and a buffer circuit. (Elasticity buffer) 56 and parallel / serial conversion circuit 57 are included. The interface circuit 50 includes a differential receiver 51, a differential driver 52, a connection state detection circuit 53, a squelch detection circuit 54, switch circuits SW5 to SW8, and resistors R5 to R7, R21, and R22. .

  The differential receiver 51 has a non-inverting input terminal connected to the data terminal D + of the second USB connector and an inverting input terminal connected to the data terminal D- of the second USB connector. The received data DIN is output by differentially amplifying the signal input to the input terminal.

  The differential driver 52 operates when the transmission enable signal EN2 is activated during data transmission, amplifies the transmission data DOUT input to the input terminal, and generates an output signal and an inverted output signal. The output terminal of the differential driver 52 is connected to the data terminal D + of the second USB connector via the resistor R21, and the inverted output terminal is connected to the data terminal D- of the second USB connector via the resistor R22. ing. When the transmission enable signal EN2 is inactivated, the output terminal and the inverted output terminal of the differential driver 52 are in an idle state (high impedance state).

  The switch circuits SW5 to SW8 are controlled to an on state or an off state in accordance with a control signal supplied from the control circuit 27 (FIG. 1). When the port circuit 22a performs the downstream port operation, the switches SW5 and SW6 are turned on and the switch circuit SW7 is turned off. As a result, the data terminal D + of the second USB connector is pulled down to the power supply potential VSS via the resistor R5, and the data terminal D- is pulled down to the power supply potential VSS via the resistor R6. Further, the bus power supply potential VBUS is supplied from the port circuit 22a to the power supply terminal VB of the second USB connector via the switch circuit SW8.

  On the other hand, when the port circuit 22a performs the upstream port operation, the switch circuits SW5 and SW6 are turned off and the switch circuit SW7 is turned on. As a result, the data terminal D + of the second USB connector is pulled up to the power supply potential VDD via the resistor R7. Further, the bus power supply potential VBUS is supplied from the power supply terminal VB of the second USB connector to the port circuit 22a via the switch circuit SW8.

  When the port circuit 22a performs the downstream port operation, if a device in the HS mode or the FS mode is connected to the second USB connector via the USB bus, a high level signal is input to the data terminal D +, and the LS When a mode device is connected, a high level signal is input to the data terminal D-.

  The connection state detection circuit 53 determines the level of the data terminals D + and D− of the second USB connector and, based on the determined level, that the device is connected to the second USB connector, Detects that the device is disconnected from the USB connector. Further, the connection state detection circuit 53 determines whether or not the data terminal D + or D− of the second USB connector is pulled up by a device connected to the second USB connector based on the determined level. Is detected. Based on the detection result, the connection state detection circuit 53 generates a connection state signal CS2 indicating the connection state of the device in the second USB connector, and the connection state signal CS2 is represented by the hub logic circuit 23 and the control circuit 27 shown in FIG. Output to.

  The squelch detection circuit 54 detects the presence / absence of a valid signal at the data terminals D + and D− of the second USB connector based on the bus activity or the current change amount, and generates a squelch signal SQ2 representing the detection result. The squelch detection circuit 54 outputs the squelch signal SQ2 to the buffer circuit 56, the packet detection correction circuit 62, and the hub logic circuit 23 and the control circuit 27 shown in FIG.

  The configuration and operation of the connection state detection circuit 53, squelch detection circuit 54, sampling clock signal generation circuit 55, buffer circuit 56, and parallel / serial conversion circuit 57 in the second port circuit 22a are the same as those in the first port circuit 21. This is the same as the connection state detection circuit 43, the squelch detection circuit 44, the sampling clock signal generation circuit 45, the buffer circuit 46, and the parallel / serial conversion circuit 47.

<Repeater circuit>
The repeater circuit 24 includes an internal clock signal generation circuit 60 and packet detection correction circuits 61 and 62. The internal clock signal generation circuit 60 includes, for example, an oscillation circuit that performs an oscillation operation using a crystal resonator or the like, and generates an internal clock signal ICLK1 for parallel data transfer and an internal clock signal ICLK2 for serial data transfer. . The internal clock signal generation circuit 60 may be provided outside the repeater circuit 24.

  For example, the transfer data received or transmitted by the data transfer control device is configured in units called frames, and one frame is a plurality of packets configured by a packet called SOF (Start Of Frame) followed by a packet. Including transactions. One transaction is a meaningful data transfer unit. As the packet type, a token packet, a data packet, a handshake packet, and the like are used in addition to the SOF packet.

  The SOF packet includes a synchronization code (SYNC: synchronization), a packet identification code (PID: Packet Identifier), a frame number, a CRC (cyclic redundancy check) code, and a packet end code (EOP: End Of Packet). It is out. The token packet includes a synchronization code, a packet identification code, an address code (ADDR: Device Address), an end point code (ENDP: End Point), a CRC code, and a packet end code. The data packet includes a synchronization code, a packet identification code, a data code (DATA), a CRC code, and a packet end code. The handshake packet includes a synchronization code, a packet identification code, and a packet end code.

  The packet detection / correction circuit 61 is composed of, for example, a combinational logic circuit or a sequential circuit, and receives from the buffer circuit 46 of the port circuit 21 in synchronization with the internal clock signal ICLK1 when the squelch signal SQ1 is activated. Read data. The packet detection / correction circuit 61 detects the start packet or the end packet of the received data based on the synchronization code, the packet identification code, the packet end code, or a part thereof.

  For example, when a missing bit (bit loss) occurs in the synchronization code in the start packet, the packet detection correction circuit 61 corrects the synchronization code by adding the missing bit to the synchronization code. Alternatively, the packet detection and correction circuit 61 corrects the packet end code by removing unnecessary bits when unnecessary bits (dribble bits) are added to the end packet.

  The packet detection and correction circuit 62 reads received data from the buffer circuit 56 of the port circuit 22a in synchronization with the internal clock signal ICLK1 when the squelch signal SQ2 is activated. The configuration and operation of the packet detection / correction circuit 62 are the same as those of the packet detection / correction circuit 61.

  Thereby, in the repeater mode, the repeater circuit 24 shapes and retims the reception data input from the port circuit 22a that performs the upstream port operation, and outputs it to the port circuit 21. The repeater circuit 24 shapes and retims the received data input from the port circuit 21 that performs the downstream port operation, and outputs the data to the port circuit 22a.

  In the repeater mode, the port circuit 22a that performs the upstream port operation may be selected from the plurality of port circuits 22. In this case, the storage unit 28 stores an identification code that identifies the port circuit 22 a selected from among the plurality of port circuits 22. For example, the identification code may be stored in the storage unit 28 from the main controller 10 in the hub mode, or may be stored in the nonvolatile memory of the storage unit 28 at the time of factory shipment.

  In the repeater mode, the control circuit 27 controls the selector circuit 25 to electrically connect the port circuit 21 to the repeater circuit 24 and electrically connects the port circuit 22a specified by the identification code to the repeater circuit 24. Thus, the selector circuit 26 is controlled.

  In addition, the control circuit 27 outputs an enable signal to the port circuit 22a selected from among the plurality of port circuits 22 in the repeater mode based on the identification code stored in the storage unit 28, and the plurality of ports. The disable signal may be output to another port circuit in the circuit 22. As a result, other port circuits are set to a suspended state, a disconnected state, or the like, so that power consumption in unused port circuits can be reduced.

  FIG. 5 is a timing chart for explaining the operation of the repeater circuit shown in FIG. FIG. 5 shows, as an example, a synchronization code (SYNC), a data code (DATA), and a packet end code (EOP) included in a data packet of received data.

  In the “up port side” of FIG. 5, a packet A transmitted from the dual roll device 30a (FIG. 1) to the port circuit 22a and a packet B transmitted from the port circuit 22a to the dual roll device 30a are shown. . Further, in the “down port side” of FIG. 5, a packet A transmitted from the port circuit 21 to the main controller 10 (FIG. 1) and a packet B transmitted from the main controller 10 to the port circuit 21 are shown. .

  FIG. 5A shows the operation when the repeater circuit 24 is not provided. When the packet A including the synchronization code (SYNC), the data code (DATA), and the packet end code (EOP) is transmitted from the dual roll device 30a to the port circuit 22a, the port circuit 22a stores the packet A. At that time, due to the delay in activation and deactivation of the squelch signal SQ2, a part of the leading end of the synchronization code (SYNC) is lost, bit loss occurs, and a dribble bit is added after the packet end code (EOP). The Thereafter, the packet A is transmitted from the port circuit 21 to the main controller 10.

  When the packet B including the synchronization code (SYNC), the data code (DATA), and the packet end code (EOP) is transmitted from the main controller 10 to the port circuit 21, the port circuit 21 stores the packet B. At that time, due to the delay in activation and deactivation of the squelch signal SQ1, a part of the leading end of the synchronization code (SYNC) is lost, bit loss occurs, and a dribble bit is added after the packet end code (EOP). The Thereafter, the packet B is transmitted from the port circuit 22a to the dual roll device 30a. As a result, as shown in FIG. 5A, the interval between the packets is widened, and synchronization is shifted in data transfer.

  FIG. 5B shows the operation when the repeater circuit 24 is provided. When the packet A is transmitted from the dual role device 30a to the port circuit 22a, the port circuit 22a stores the packet A. The packet detection correction circuit 62 adds the missing bit to the synchronization code (SYNC) and removes the dribble bit to correct the packet end code (EOP), thereby transmitting the packet from the dual roll device 30a to the port circuit 22a. The packet A is output to the port circuit 21 without being changed. Thereafter, the packet A is transmitted from the port circuit 21 to the main controller 10.

  When the packet B is transmitted from the main controller 10 to the port circuit 21, the port circuit 21 stores the packet B. The packet detection correction circuit 61 adds the missing bit to the synchronization code (SYNC) and removes the dribble bit to correct the packet end code (EOP), thereby inputting the port circuit 21 from the main controller 10. The packet B is output to the port circuit 22a without being changed. Thereafter, the packet B is transmitted from the port circuit 22a to the dual roll device 30a. Thereby, as shown in FIG. 5B, the influence on the data transfer between the dual-role device 30a and the main controller 10 can be reduced.

  By the way, among the devices used as the dual role device 30a, there are devices that can be a host but do not have a protocol for returning to a slave. If the main controller 10 gives the host right to such a device, the main controller 10 cannot acquire the host right again.

  Therefore, in the present embodiment, the control circuit 27 shown in FIG. 1 receives the device from the port circuit 22a in the repeater mode based on, for example, the connection state signal CS2 output from the connection state detection circuit 53 of the port circuit 22a. Detect disconnection. Alternatively, the control circuit 27 detects that the device connected to the port circuit 22a has stopped communication in the repeater mode based on the squelch signal SQ2 output from the squelch detection circuit 54 of the port circuit 22a.

  When the control circuit 27 detects in the repeater mode that the device has been disconnected from the port circuit 22a or the device connected to the port circuit 22a has stopped communicating, the bus connected to the port circuit 21 May be suspended, or the port circuit 21 may be controlled to stop the supply of the bus power supply potential VBUS to the power supply terminal VB of the first USB connector connected to the port circuit 21. Thereby, even if the main controller 10 connected to the port circuit 21 once gives the host right to the dual role device 30a connected to the port circuit 22a, the dual role device 30a does not already need the host right. Can be determined.

  In that case, when the control circuit 27 detects that the pull-up of the data terminal D + or D− of the first USB connector is canceled by the main controller 10 connected to the port circuit 21, the data transfer control device 20 may be shifted from the second mode to the first mode. As a result, the main controller 10 that has canceled the pull-up of the data terminal D + or D− of the first USB connector can acquire the host right again.

  As described above, according to the present embodiment, the dual-role device 30a performs the host operation when the dual-role device 30a that has the host function but cannot control the hub is connected to the port circuit 22a. Is possible. Further, since the repeater circuit 24 shapes and retimates the input received data and outputs it, it is possible to reduce bit loss or dribble bits and improve a waveform dull in the bus cable or physical layer circuit.

  FIG. 6 is a timing chart for explaining an operation example of the data transfer control device according to the first embodiment of the present invention. As shown in FIG. 1, the main controller 10 is connected to the port circuit 21 of the data transfer control device 20 via a bus, and the dual role device 30a is connected to the port circuit 22a of the data transfer control device 20 via the bus. It is connected to the. In this example, it is assumed that the main controller 10 and the dual roll device 30a conform to the OTG (On-The-Go) standard. The dual role device 30a stores a predetermined status requesting the host right in the OTG register.

  In step S1 shown in FIG. 6, the main controller 10 having the host right transmits / receives a transaction to / from the dual role device 30a via the data transfer control device 20 operating in the hub mode, and sets the OTG register of the dual role device 30a. Poll.

  In step S2, when the main controller 10 detects a predetermined status, the port circuit 22a is switched from the downstream port to the upstream port together with an identification code for identifying the port circuit 22a selected from among the plurality of port circuits 22. The request is transmitted to the data transfer control device 20. In addition, the main controller 10 transmits a notification of permission of the host right to the dual role device 30a via the data transfer control device 20.

  The hub logic circuit 23 of the data transfer control device 20 detects a request transmitted from the main controller 10 and sets an identification code and a mode for identifying the port circuit 22a selected from among the plurality of port circuits 22. A register value to be stored is stored in the storage unit 28. Thereby, the control circuit 27 shifts the data transfer control device 20 from the hub mode to the repeater mode, and controls the selector circuits 25 and 26 so as to electrically connect the port circuits 21 and 22a to the repeater circuit 24.

  In step S3, the dual-role device 30a releases the pull-up of the data terminal D + of the second USB connector to which the port circuit 22a is connected. For example, when the control circuit 27 of the data transfer control device 20 detects that the pull-up of the data terminal D + of the second USB connector is released based on the connection state signal CS2, the control circuit 27 to which the port circuit 21 is connected is connected. The pull-up of the data terminal D + of the USB connector 1 is canceled and the data terminals D + and D- are pulled down.

  In step S4, the main controller 10 pulls up the data terminal D + of the first USB connector. When the control circuit 27 of the data transfer control device 20 detects the pull-up of the data terminal D + of the first USB connector, it pulls up the data terminal D + of the second USB connector. In step S5, the bus is reset, and the data terminal D + of the first and second USB connectors once goes low.

  In step S6, the dual role device 30a that has acquired the host right performs a host operation. For example, the dual role device 30a transmits / receives a transaction to / from the main controller 10 via the data transfer control device 20 operating in the repeater mode, and polls the OTG register of the main controller 10.

  In step S7, the dual role device 30a is disconnected from the port circuit 22a of the data transfer control device 20, or communication is stopped. When the control circuit 27 of the data transfer control device 20 detects the disconnection or the communication stop of the dual role device 30a, the control circuit 27 suspends the bus connected to the port circuit 21 or the first connected to the port circuit 21. The supply of the bus power supply potential VBUS to the power supply terminal VB of the USB connector is stopped. Here, suspend is a state in which communication on the bus is suspended.

  In step S8, when the main controller 10 detects the suspension of the bus or the supply stop of the bus power supply potential VBUS, the main controller 10 pulls up the data terminal D + of the first USB connector at a desired timing in order to acquire the host right again. To release. When the control circuit 27 of the data transfer control device 20 detects that the pull-up of the data terminal D + of the first USB connector is released, the control circuit 27 releases the pull-up of the data terminal D + of the second USB connector. Pull down data terminals D + and D-. At that time, the control circuit 27 may cause the data transfer control device 20 to shift from the repeater mode to the hub mode.

  In step S9, the data transfer control device 20 pulls up the data terminal D + of the first USB connector within the time specified by the OGT standard, and starts the operation in the hub mode. Further, the dual-role device 30a pulls up the data terminal D + of the second USB connector when not disconnected from the port circuit 22a of the data transfer control device 20. In step S10, the bus is reset, and the data terminal D + of the first and second USB connectors once goes low.

<Second Embodiment>
Next, a data transfer control device according to a second embodiment of the present invention will be described.
FIG. 7 is a block diagram showing a configuration example of a data transfer control device according to the second embodiment of the present invention. In the second embodiment, the hub repeater logic circuit 210 of the hub logic circuit 23a has the function of the repeater circuit 24 in the first embodiment shown in FIG. In other respects, the second embodiment is the same as the first embodiment.

  As shown in FIG. 7, the data transfer control device 20 a includes a port circuit 21, a port circuit 22, a hub logic circuit 23 a, and a storage unit 28. The port circuit 21 has an upstream port function and a downstream port function, and is connected to the main controller 10 (FIG. 1). The port circuit 22 has a downstream port function and is connected to the device 30. At least one of the port circuits 22a has a downstream port function and an upstream port function, and is connected to the dual role device 30a (FIG. 1).

  The hub logic circuit 23 a includes a transaction translator 200, a hub repeater logic circuit 210, a hub state machine 220, a hub controller 230, a routing logic circuit 240, and a frame timer 250. The configuration of the hub logic circuit 23a is not limited to the configuration shown in FIG. 7, and various modifications such as omitting a part of the configuration or adding other components are possible.

  For example, the transaction translator 200 is updated when the main controller 10 that performs the host operation is connected to the port circuit 21 in the HS mode and the device 30 that performs the slave operation is connected to the port circuit 22 in the FS mode or the LS mode. Conversion processing is performed between the HS mode transaction on the stream side and the FS mode or LS mode transaction on the downstream side.

  The hub repeater logic circuit 210 is connected to the port circuit 21 and the port circuit in the hub mode when the data transfer speed mode between the main controller 10 connected to the port circuit 21 and the device 30 connected to the port circuit 22 is the same. The data transfer to and from 22 is controlled.

  The hub repeater logic circuit 210 is a repeater between the port circuit 22a connected to the dual-role device 30a that performs host operation and the port circuit 21 connected to the main controller 10 that performs slave operation in the repeater mode. Perform the action.

  For this purpose, the hub repeater logic circuit 210 includes an internal clock signal generation circuit 60 and packet detection correction circuits 61 and 62. The internal clock signal generation circuit 60 generates an internal clock signal ICLK1 for parallel data transfer and an internal clock signal ICLK2 for serial data transfer, and supplies the internal clock signal ICLK1 to the packet detection and correction circuits 61 and 62. Clock signals ICLK 1 and ICLK 2 are supplied to port circuits 21 and 22. The internal clock signal generation circuit 60 may be provided outside the hub repeater logic circuit 210.

  The packet detection and correction circuit 61 reads received data from the buffer circuit 46 of the port circuit 21 in synchronization with the internal clock signal ICLK1 when the squelch signal SQ1 shown in FIG. 2 is activated. The packet detection / correction circuit 61 detects the start packet or the end packet of the received data based on the synchronization code, the packet identification code, the packet end code, or a part thereof.

  For example, when a missing bit (bit loss) occurs in the synchronization code in the start packet, the packet detection correction circuit 61 corrects the synchronization code by adding the missing bit to the synchronization code. Alternatively, the packet detection and correction circuit 61 corrects the packet end code by removing unnecessary bits when unnecessary bits (dribble bits) are added to the end packet.

  The packet detection and correction circuit 62 reads received data from the buffer circuit 56 of the port circuit 22a in synchronization with the internal clock signal ICLK1 when the squelch signal SQ2 shown in FIG. 2 is activated. The configuration and operation of the packet detection / correction circuit 62 are the same as those of the packet detection / correction circuit 61.

  Thereby, in the repeater mode, the hub repeater logic circuit 210 shapes and retims the received data input from the port circuit 22a that performs the upstream port operation, and outputs the received data to the port circuit 21. The hub repeater logic circuit 210 shapes and retims the received data input from the port circuit 21 that performs the downstream port operation and outputs the data to the port circuit 22a.

  Further, in the hub mode, the hub repeater logic circuit 210 may reshape and retime the reception data input from the port circuit 21 that performs the upstream port operation and output the data to the port circuit 22. Further, the hub repeater logic circuit 210 may shape and retimate the reception data input from the port circuit 22 that performs the downstream port operation and output the data to the port circuit 21.

  The hub state machine 220 controls the state of the data transfer control device 20a. For example, the hub state machine 220 detects connection or disconnection between the port circuit 21 or 22 and the main controller 10 or the device 30, or performs connection processing or disconnection processing between the port circuit 21 or 22 and the main controller 10 or the device 30. Control the reset, stop, or return of the port circuit 21 or 22. The hub state machine 220 controls data transfer by performing processing for detecting a bus error (fault) and processing for recovering from a bus error.

  The hub controller 230 controls communication between the data transfer control device 20a and the main controller 10. For example, the hub controller 230 performs enumeration, exchanges resource information and settings of the data transfer control device 20a with the main controller 10, and processes a request from the main controller 10.

  The routing logic circuit 240 electrically connects the transaction translator 200 and the port circuit 22. Alternatively, the routing logic circuit 240 electrically connects the hub repeater logic circuit 210 and the port circuit 22. The frame timer 250 is used to synchronize the upstream frame and the downstream frame and control the frame interval.

  Here, the hub state machine 220 corresponds to the control circuit 27 in the first embodiment shown in FIG. The hub state machine 220 includes, for example, a combinational logic circuit or a sequential circuit, and controls each unit of the data transfer control device 20a.

  In the hub mode in which the main controller 10 performs the host operation, the hub state machine 220 controls the port circuit 21 so as to perform the upstream port operation and also controls the port circuit 22a so as to perform the downstream port operation. In the repeater mode in which the dual-role device 30a performs the host operation, the hub state machine 220 controls the port circuit 22a to perform the upstream port operation and also controls the port circuit 21 to perform the downstream port operation. To do.

  In the hub mode, the hub repeater logic circuit 210 controls data transfer between the port circuit 21 and the port circuit 22, and the data transfer control device 20a operates as a normal hub. On the other hand, in the repeater mode, the hub repeater logic circuit 210 operates as a repeater between the port circuit 21 and the port circuit 22a.

  Thus, when the dual role device 30a that has the host function but cannot control the hub is connected to the port circuit 22a, the dual role device 30a can perform the host operation. In addition, since the hub repeater logic circuit 210 shapes and retimates the input received data, the bit loss or dribble bit can be reduced and the blunt waveform in the bus cable or physical layer circuit can be improved. .

  In the repeater mode, the port circuit 22a that performs the upstream port operation may be selected from the plurality of port circuits 22. In this case, the storage unit 28 stores an identification code that identifies the port circuit 22 a selected from among the plurality of port circuits 22. For example, the identification code may be stored in the storage unit 28 from the main controller 10 in the hub mode, or may be stored in the nonvolatile memory of the storage unit 28 at the time of factory shipment.

  The hub state machine 220 controls the routing logic circuit 240 to electrically connect the port circuit 22a specified by the identification code to the hub repeater logic circuit 210 in the repeater mode.

  The hub state machine 220 outputs an enable signal to the port circuit 22a selected from the plurality of port circuits 22 in the repeater mode based on the identification code stored in the storage unit 28, and The disable signal may be output to another port circuit in the port circuit 22. As a result, other port circuits are set to a suspended state, a disconnected state, or the like, so that power consumption in unused port circuits can be reduced.

  By the way, among the devices used as the dual role device 30a, there are devices that can be a host but do not have a protocol for returning to a slave. If the main controller 10 gives the host right to such a device, the main controller 10 cannot acquire the host right again.

  Therefore, in the present embodiment, the hub state machine 220 is connected from the port circuit 22a to the device in the repeater mode, for example, based on the connection state signal CS2 output from the connection state detection circuit 53 (FIG. 2) of the port circuit 22a. Detect that is disconnected. Alternatively, the hub state machine 220 determines that the device connected to the port circuit 22a has stopped communicating in the repeater mode based on the squelch signal SQ2 output from the squelch detection circuit 54 (FIG. 2) of the port circuit 22a. Is detected.

  The hub state machine 220 is connected to the port circuit 21 when it is detected in the repeater mode that the device is disconnected from the port circuit 22a or the device connected to the port circuit 22a stops communication. The bus circuit may be suspended, or the port circuit 21 may be controlled to stop the supply of the bus power supply potential VBUS to the power supply terminal VB of the first USB connector connected to the port circuit 21. Thereby, even if the main controller 10 connected to the port circuit 21 once gives the host right to the dual role device 30a connected to the port circuit 22a, the dual role device 30a does not already need the host right. Can be determined.

  In this case, when the hub state machine 220 detects that the pull-up of the data terminal D + or D− of the first USB connector is released by the main controller 10 connected to the port circuit 21, the data transfer control is performed. The apparatus 20 may be shifted from the second mode to the first mode. As a result, the main controller 10 that has canceled the pull-up of the data terminal D + or D− of the first USB connector can acquire the host right again.

<Electronic equipment>
FIG. 8 is a block diagram illustrating a configuration example of an electronic device according to an embodiment of the present invention. For example, the data transfer control device according to the present invention includes an in-vehicle device such as a car navigation device, a personal computer, a home game machine, a printer, a television receiver, a digital camera, a digital photo frame, an AV recorder, or an AV player. It can be applied to other electronic devices.

  As shown in FIG. 8, the electronic device 300 includes a CPU 310, a data transfer control device 320, a device 330, a ROM (Read Only Memory) 340, a RAM (Random Access Memory) 350, a communication unit 360, a display A unit 370, an audio output unit 380, and an operation unit 390. Note that some of the components shown in FIG. 8 may be omitted or changed, or other components may be added to the components shown in FIG.

  Here, the CPU 310 corresponds to the main controller 10 shown in FIG. 1, the data transfer control device 320 corresponds to the data transfer control device 20 shown in FIG. 1 or the data transfer control device 20a shown in FIG. Corresponds to the device 30 shown in FIG. At least one of the devices 330 is a dual-role device 330a having a host function in addition to a slave function, and corresponds to the device 30a shown in FIG.

  The CPU 310 and the data transfer control device 320 communicate via a bus such as a USB. The data transfer control device 320 and the device 330 communicate via a bus such as a USB. The CPU 310 communicates with the ROM 340 to the operation unit 390 via the CPU bus.

  The CPU 310 performs various arithmetic processes and control processes using data supplied from the outside in accordance with programs stored in the ROM 340 and the like. For example, the CPU 310 performs various data processing according to an operation signal supplied from the operation unit 390, controls the communication unit 360 to perform data communication with the outside, and displays various data on the display unit 370. An image signal for displaying an image is generated, or an audio signal for causing the audio output unit 380 to output various sounds is generated.

  The ROM 340 stores programs, data, and the like for the CPU 310 to perform various arithmetic processes and control processes. The RAM 350 is used as a work area of the CPU 310, and temporarily stores programs and data read from the ROM 340, data input using the operation unit 390, calculation results executed by the CPU 310 according to the programs, and the like. To do.

  The communication unit 360 includes, for example, an analog circuit and a digital circuit, and performs data communication between the CPU 310 and an external device. The display unit 370 includes, for example, an LCD (Liquid Crystal Display) and the like, and displays various images based on image signals supplied from the CPU 310. The audio output unit 380 includes, for example, a speaker and outputs audio based on an audio signal supplied from the CPU 310. The operation unit 390 is an input device including, for example, operation keys, button switches, and the like, and outputs an operation signal corresponding to an operation by the user to the CPU 310.

  The case where the data transfer control device operates in the HS mode or the FS mode has been described above. When the data transfer control device operates in the LS mode, the data terminal D− of the first USB connector is pulled up via a resistor in the hub mode, and the data terminal D− of the second USB connector is in the repeater mode. Is pulled up through a resistor. Thus, the present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by those who have ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 10 ... Main controller, 11 ... Link controller, 12, 40, 50 ... Interface circuit, 20, 20a ... Data transfer control device, 21, 22, 22a ... Port circuit, 23, 23a ... Hub logic circuit, 24 ... Repeater circuit, 25, 26 ... selector circuit, 27 ... control circuit, 28 ... storage unit, 30 ... device, 30a ... dual roll device, 41, 51 ... differential receiver, 42, 52 ... differential driver, 43, 53 ... connection state detection Circuit, 44, 54 ... Squelch detection circuit, 45, 55 ... Sampling clock signal generation circuit, 46, 56 ... Buffer circuit, 47, 57 ... Parallel / serial conversion circuit, 60 ... Internal clock signal generation circuit, 61, 62 ... Packet Detection correction circuit, 71, 74 ... trigger circuit, 72 ... inverter, 7 ... AND circuit, 81 ... PLL circuit, 82 ... DLL circuit, 83 ... Edge detection circuit, 84 ... Clock signal selection circuit, 200 ... Transaction translator, 210 ... Hub repeater logic circuit, 220 ... Hub state machine, 230 ... Hub controller, 240 ... routing logic circuit, 250 ... frame timer, 300 ... electronic device, 310 ... CPU, 320 ... data transfer control device, 330 ... device, 330a ... dual roll device, 340 ... ROM, 350 ... RAM, 360 ... communication unit, 370 ... Display unit, 380 ... Audio output unit, 390 ... Operation unit, SW1-SW8 ... Switch circuit, R0-R22 ... Resistance, C0 ... Capacitor, D0 ... Diode

Claims (6)

A first port circuit;
A second port circuit;
A hub logic circuit for controlling transfer of data between the first port circuit and the second port circuit;
A repeater circuit that reduces bit loss or dribble bits and outputs by at least shaping received data to be input;
In the first mode, the first port circuit that performs upstream port operation is electrically connected to the hub logic circuit, and in the second mode, the first port circuit that performs downstream port operation is A first selector circuit electrically connected to the repeater circuit;
In the first mode, and electrically connecting the second port circuit that performs downstream port operations to the hub logic circuit, in said second mode, said second port circuit that performs upstream port operation A second selector circuit electrically connecting the repeater circuit to the repeater circuit;
A data transfer control device comprising: A first port circuit;
A second port circuit;
Controlling the transfer of data between the first port circuit performing upstream port operation and the second port circuit performing downstream port operation in the first mode, and upstream in the second mode; By at least shaping received data input from the second port circuit that performs the port operation, the bit loss or dribble bit is reduced and output to the first port circuit, and at the same time the downstream port operation is performed. A hub repeater logic circuit that reduces bit loss or dribble bits and outputs the data to the second port circuit by at least shaping received data input from one port circuit;
A data transfer control device comprising: In the second mode, device is disconnected from the second port circuit, or when the device connected to the second port circuit is detected that the stop communication, the first The bus connected to the port circuit is suspended, or the first port circuit is controlled to stop supplying the bus power supply potential to the power supply terminal of the bus connector connected to the first port circuit. The data transfer control device according to claim 1, further comprising a control circuit for performing the operation. Wherein the control circuit, when said first port circuit connected devices has canceled the pullup predetermined terminal of the bus connector is detected, the data transfer control device of the second The data transfer control device according to claim 3, wherein the mode is shifted from the mode to the first mode. A plurality of second port circuits;
Allow the control circuit, based on the port circuit selected from the plurality of second port circuits to the identification code for identifying, in said second mode, the data transmission operation definitive to the selected port circuit and outputs a signal to and outputs a signal for prohibiting the definitive data transmission operation to the other port circuit of the plurality of second port circuits, the data transfer control device according to claim 3 or 4, wherein.   An electronic device comprising the data transfer control device according to claim 1.

Images