JP6576128B2 - Capacitance measuring circuit, input device using the same, electronic device, and capacity measuring method - Google Patents

Description

  The present invention relates to a capacitance measuring device.

  Electronic devices such as computers, smart phones, tablet terminals, and portable audio devices in recent years are equipped with touch-type input devices as user interfaces. As touch-type input devices, a touch pad, a pointing device, and the like are known, and various inputs are possible by touching or bringing a finger or stylus into contact.

  Touch type input devices are broadly classified into a resistive film type and a capacitance type. The electrostatic capacity method detects presence / absence of user input and coordinates by converting changes in electrostatic capacity (hereinafter also simply referred to as “capacitance”) formed by a plurality of sensor electrodes into an electric signal in accordance with user input. .

The capacitance measurement includes a self-capacitance method and a mutual capacitance method. Patent Document 2 discloses a self-capacitance type capacitance measuring circuit. FIG. 1 is a circuit diagram showing a basic configuration of a conventional self-capacitance type capacitance measuring circuit 100r. The capacitance measuring circuit 100r is a C / V (capacitance / voltage) conversion circuit, and generates a detection voltage V _S corresponding to the capacitance C _S to be detected.

The capacitance measuring circuit 100r mainly includes a C / I (capacitance / current) conversion circuit 10r and an I / V (current / voltage conversion circuit) 20r. The C / I conversion circuit 10r generates a detection current I _S corresponding to the capacitance C _S. The C / I conversion circuit 10r includes a first transistor M1, a second transistor M2, a reset switch SW1, and a sense switch SW2. Reset switch SW1 initializes the electric charge of the electrostatic capacitance _{C S.} The first transistor M1 and the sense switches SW2 are provided in series between the power supply line _{V DD} and the electrostatic capacitance _{C S.} The first transistor M1 and the second transistor M2 form a current mirror circuit.

The I / V conversion circuit 20r converts the detection current I _S flowing through the second transistor M2 into a detection voltage V _S. For example, the I / V conversion circuit 20r includes an integration capacitor C _INT that is charged and discharged according to the detection current I _S.

The operation of capacitance measurement will be described. First, the reset switch SW1 is turned on, the charge of the capacitance C _S is reset to zero, then it turned off. Subsequently, the sense switch SW2 is turned on. For this time, the first transistor M1 capacitance _{C S} through the flow the charging current _{I CHG1,} until the first transistor M1 is saturated, the voltage of the capacitance _{C S} is increased. The charging current I _CHG1 flowing at this time is a current amount corresponding to the capacitance C _S. Charging current _{I CHG1} by the second transistor M2 is copied, the detected current _{I S} is generated. The output V _S of the I / V conversion circuit 20r is a voltage indicating the capacitance C _S.

JP 2001-325858 A JP 2012-182781 A

In many applications, between the capacitance measuring circuit 100r and the electrostatic capacitance C _S, there are wiring and pads, in their parasitic capacitance C _P is accompanied. Therefore, the combined capacitance of the capacitance C _S and the parasitic capacitance C _P becomes a detection target of the capacitance measurement circuit 100r.

In applications to detect the relative change amount of the electrostatic capacitance C _S of the plurality of channels as a touch panel, no input clogging capacitance variation is uniform measurement values of a plurality of the electrostatic capacitance C _S when the zero There is a need. However the variation of the parasitic capacitance C _P is contribute to prevent the uniformity of the measurements, reduce the detection sensitivity.

Therefore the capacitance measuring circuit 100r, it is required to reduce the effect of variations in the parasitic capacitance C _P for each channel, the offset cancel circuit 60r is provided for this purpose. Offset cancel circuit 60r charges the electrostatic capacitance _{C S} by a substantially constant amount of the offset current _{I OFS.}

FIG. 2 is an operation waveform diagram of the capacitance measuring circuit 100r of FIG. Beginning the reset switch SW1 is turned on, the electrostatic capacitance C _S is discharged. Subsequently, when the sense switch SW2 is turned on, the charging current I _CHG1 starts to flow. The electrostatic capacitance _{C S} is charged by the DC offset current _{I OFS.}

The detection voltage V _S in the capacitance measuring circuit 100r is represented by (iii), and is decomposed into a component (i) corresponding to the charging current I _CHG1 and a component (ii) corresponding to the offset current I _OFS . An ideal detection voltage V _{s_ref} when the influence of the variation of the parasitic capacitance C _P is completely canceled contrast represented by (iv).

In this circuit, by the offset current I _OFS is excessively flows into the electrostatic capacitance C _S, a factor to narrow the dynamic range. In the correction by the DC offset current I _OFS, it is impossible to completely correct the influence of the parasitic capacitance C _P.

  The present invention has been made in view of these problems, and one of exemplary purposes of an embodiment thereof is to provide a capacitance measuring circuit with improved dynamic range and / or sensitivity.

  One embodiment of the present invention relates to a capacitance measurement circuit that measures capacitance. The capacitance measuring circuit includes a first transistor provided between the capacitance and the fixed voltage terminal, a sense switch for switching on and off the capacitance charging operation by the first transistor, a correction capacitor, A correction charging circuit for charging the correction capacitor, a detection current corresponding to the first charging current flowing through the first transistor, and a correction current corresponding to the second charging current flowing from the correction charging circuit to the correction capacitor are synthesized. And a current synthesis circuit for generating a synthesized current, and detecting the capacitance based on the synthesized current.

  Since the correction current does not flow into the capacitance, the dynamic range can be improved as compared with the case where the offset current is supplied to the capacitance.

The second charging current may have substantially the same waveform as the first charging current.
By combining the correction current based on the second charging current with the detection current, it is possible to accurately correct the influence of the parasitic capacitance.

  The sense switch may be provided in series with the first transistor between the capacitance and the fixed voltage terminal. Thereby, on / off of the charging operation by the first transistor can be controlled according to on / off of the sense switch.

  The capacitance measuring circuit may further include a second transistor connected to the first transistor so as to form a first current mirror circuit having the first transistor as an input. The current flowing through the second transistor may be a detection current.

  The correction charging circuit includes a third transistor provided between the correction capacitor and the fixed voltage terminal, a correction switch for switching on and off the charging operation of the correction capacitor by the third transistor, and a third transistor comprising: A fourth transistor connected to the third transistor so as to form a second current mirror circuit serving as an input, and the current flowing through the fourth transistor may be a correction current.

The second current mirror circuit may be configured with a variable mirror ratio.
Thereby, the correction gain can be set according to the mirror ratio. Further, the circuit area can be reduced as compared with the case where the correcting capacitor is a variable capacitor.

  The correction switch may be synchronously controlled with the sense switch. Thereby, control can be simplified.

  The capacitance measuring circuit may further include an integrating capacitor that is charged and discharged by the combined current. The voltage of the integrating capacitor may be a detection voltage corresponding to the capacitance.

  The capacitance measurement circuit may further include a first reset switch that initializes the electric charge of the capacitance and a second reset switch that initializes the electric charge of the correction capacitor.

  In the capacitance measuring circuit, the correction capacitor may be a variable capacitor. By finely adjusting the capacitance of the correction capacitor according to the parasitic capacitance, the influence of the parasitic capacitance can be further reduced.

  Another aspect of the present invention relates to a capacitance measurement circuit that measures each of a plurality of capacitances. The capacitance measurement circuit is associated with a plurality of capacitances, each of which is associated with a plurality of capacitance-current conversion circuits that generate detection currents corresponding to the corresponding capacitances, and a plurality of capacitances, A plurality of correction current generation circuits that generate correction currents, a plurality of current synthesis circuits that are associated with a plurality of capacitances, each of which corresponds to a corresponding detection current and a corresponding correction current, and generates a combined current; Is provided. Each of the plurality of correction current generation circuits includes a correction capacitor and a correction charging circuit that charges the correction capacitor. The correction current corresponds to the second charging current flowing from the correction charging circuit to the correction capacitor.

  According to this aspect, it is possible to accurately correct the influence of the parasitic capacitance for each of the plurality of capacitances.

  Each of the plurality of capacitance-current conversion circuits includes a first transistor provided between the capacitance and the fixed voltage terminal, a sense switch for switching on / off of the charging operation of the capacitance by the first transistor, And a second transistor connected to the first transistor so as to form a first current mirror circuit having one transistor as an input, and the current flowing through the second transistor may be a detection current.

  The correction charging circuit includes a third transistor provided between the correction capacitor and the fixed voltage terminal, a correction switch for switching on and off the charging operation of the correction capacitor by the third transistor, and a third transistor comprising: A fourth transistor connected to the third transistor so as to form a second current mirror circuit serving as an input, and the current flowing through the fourth transistor may be a correction current.

  The second current mirror circuit may be configured with a variable mirror ratio. The correction switch may be synchronously controlled with the sense switch. The output node of each of the plurality of correction current generation circuits may be connected to the output node of the corresponding capacitance current conversion circuit.

  The capacitance measuring device may further include a current averaging circuit that generates an average current of a plurality of detection currents generated by a plurality of capacitance current conversion circuits or an average current of a plurality of combined currents. Each of the plurality of current combining circuits may combine an average current in addition to the corresponding detection current and the corresponding correction current.

  The current averaging circuit corresponds to a plurality of capacitances, each corresponding to a plurality of fifth transistors and a plurality of capacitances connected to generate a copy current proportional to the corresponding detected current. , Each of which corresponds to a plurality of sixth transistors and a plurality of capacitances, each of which is provided on a corresponding copy current path and whose control terminals are connected in common. A plurality of seventh transistors connected to a corresponding sixth transistor so as to form a third current mirror circuit to which the transistors are input, and even if the current flowing through the plurality of seventh transistors is an average current Good.

  An output node of each of the plurality of correction current generation circuits may be connected to a connection node of a corresponding fifth transistor and a corresponding sixth transistor.

  The capacitance measuring device further includes a plurality of integration capacitors that correspond to a plurality of capacitances, each of which is charged and discharged by a corresponding combined current, and the voltage of the integration capacitor is a detection voltage corresponding to the capacitance. There may be.

  The correction capacitor may be a variable capacitor.

The capacitance measuring device may be integrated on a single semiconductor integrated circuit.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.
By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

Another aspect of the present invention relates to an input device. The input device includes a plurality of sensor electrodes, and includes a touch panel in which the capacitance of sensor electrodes in the vicinity of coordinates touched by the user changes, and any one of the capacitance measurement circuits described above.
Since the sensitivity can be increased by using the above-described capacitance measuring circuit for a touch panel type input device, it is possible to detect an input accompanied by a minute capacitance change, for example, hovering.

  Another embodiment of the present invention relates to an electronic device. The electronic device includes the above-described input device. Since it is possible to detect an input with a minute capacity change such as hovering, a new user interface can be provided.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  The capacitance measuring circuit according to the present invention can improve sensitivity and / or dynamic range.

It is a circuit diagram which shows the basic composition of the conventional capacitance measuring circuit of a self-capacitance system. FIG. 2 is an operation waveform diagram of the capacitance measuring circuit in FIG. 1. It is a circuit diagram of the capacity | capacitance measuring circuit which concerns on embodiment. It is a circuit diagram which shows the structural example of the charging circuit for correction | amendment. FIG. 4 is an operation waveform diagram of the capacitance measuring circuit of FIG. 3. It is a circuit diagram of an input device provided with the capacity | capacitance measurement circuit of FIG. It is a circuit diagram of the input device concerning a modification. It is a circuit diagram which shows the specific example of control IC of FIG. It is a block diagram of an electronic device provided with an input device. It is a circuit diagram of the I / V conversion circuit which concerns on a 5th modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected to each other. Including the case of being indirectly connected through other members that do not substantially affect the state of connection, or do not impair the functions and effects achieved by the combination thereof.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

FIG. 3 is a circuit diagram of the capacitance measuring circuit 100 according to the embodiment. Capacitance measuring circuit 100 measures the capacitance _{C S,} and generates a detection voltage _{V S} that indicates an electrostatic capacitance _{C S.} The capacitance measuring circuit 100 includes a C / I (capacitance / current) conversion circuit 10, an I / V (current / voltage) conversion circuit 20, a correction capacitor C _COMP , a correction charging circuit 30, and a current synthesis circuit 40.

The C / I conversion circuit 10 generates a detection current I _S corresponding to the capacitance C _S. For example, the C / I conversion circuit 10 includes a reset switch SW1, a first transistor M1, a second transistor M2, and a sense switch SW2.

The reset switch SW1 is connected in parallel with the capacitance C _S and is provided to initialize the charge of the capacitance C _S. For example, the reset switch SW1 is a MOSFET and is controlled by a reset signal RST1 input to its gate.

The first transistor M1 is a MOSFET provided between the capacitance _CS and the fixed voltage terminal (power supply line 12). Sense switch SW2 is turned on charging of the capacitance C _S of the first transistor M1, it is provided in order to switch off. Between the sense switch SW2 supply line 12 and the capacitance _{C S} in FIG. 3, a MOSFET which is inserted in series with the first transistor M1, to the gate sense signal EVALB is input. The position of the sense switch SW2 is not limited to that in FIG. 3, and the first transistor M1 and the sense switch SW2 may be interchanged, or the sense switch SW2 may be provided between the gate and source of the first transistor M1. The current flowing through the capacitance _{C S} through the first transistor M1, referred to as a first charging current _{I CHG1.}

The second transistor M2 is connected to the first transistor M1 so as to form a first current mirror circuit 14 to which the first transistor M1 is input. The second transistors M2, the detected current _{I S} flows in proportion to the first charging current _{I CHG1.}

The correction charging circuit 30 charges the correction capacitor C _COMP according to the correction signal COMP. The correction charging circuit 30 outputs a correction current I _COMP corresponding to a current (referred to as a second charging current I _CHG2 ) flowing from the correction charging circuit 30 to the correction capacitor C _COMP . The correction charging circuit 30 is configured such that the waveform of the second charging current I _CHG2 is similar to the waveform of the first charging current I _CHG1 . Preferably, the correction capacitor C _COMP has a variable capacitance, and the capacitance value can be finely adjusted.

Current combining circuit 40, a detection current _{I S} in response to the first charging current _{I CHG1} flowing through the first transistor M1, correction according to the second charging current _{I CHG2} flowing from the correction charging circuit 30 to the correction capacitor _{C COMP} The current I _COMP is synthesized to generate a synthesized current _ID . Capacitance measuring circuit 100 detects the electrostatic capacitance _{C S} based on the combined current _{I D.} Current synthesis can include current addition, subtraction, averaging, weighted averaging, and the like.

The configuration of the current synthesis circuit 40 is not particularly limited. Most simply, regarding addition or subtraction, the current synthesis circuit 40 can be configured by wiring that connects a path through which the two currents I _S and I _COMP flow to one node. The current synthesis circuit 40 can also be configured by combining a current mirror circuit or the like.

The I / V conversion circuit 20 converts the combined current _ID into a detection voltage V _S. For example, the I / V conversion circuit 20 includes an integration capacitor C _INT that is charged by the combined current _ID . I / V conversion circuit 20, it is also possible to grasp an integrator for detecting the amount of charge flowing into the electrostatic capacitance C _S.

  FIG. 4 is a circuit diagram illustrating a configuration example of the correction charging circuit 30. It is desirable that the correction charging circuit 30 has substantially the same configuration as the C / I conversion circuit 10. The correction charging circuit 30 includes a third transistor M3, a fourth transistor M4, a reset switch SW3, and a correction switch SW4.

The third transistor M3 is a MOSFET provided between the correction capacitor C _COMP and the power supply line 12. The correction switch SW4 is provided to switch on / off the charging operation of the correction capacitor C _COMP by the third transistor M3. Here, the correction switch SW4 is a MOSFET inserted in series with the third transistor M3 between the correction capacitor C _COMP and the power supply line 12, and the correction signal COMP is input to the gate thereof. In the present embodiment, the correction signal COMP may be shared with the sense signal EVALB. In this case, the correction switch SW4 is synchronously controlled with the sense switch SW2.

  When the sense switch SW2 is provided in another location in the C / I conversion circuit 10, the correction switch SW4 is also provided in another location corresponding to the sense switch SW2.

The fourth transistor M4 is connected to the third transistor M3 so as to form a second current mirror circuit 34 to which the third transistor M3 is input. The current flowing through the fourth transistor M4 is the correction current I _COMP . The correction gain can be set according to the mirror ratio of the second current mirror circuit 34.

The reset switch SW3 is connected in parallel with the correction capacitor C _COMP and is provided to initialize the charge of the correction capacitor C _COMP . For example, the reset switch SW3 is a MOSFET and is controlled by a reset signal RST2 input to its gate. The reset signals RST2 and RST1 may be the same signal.

  The above is the configuration of the capacitance measuring circuit 100. Next, the operation will be described. FIG. 5 is an operation waveform diagram of the capacitance measuring circuit 100 of FIG.

First, the reset switches SW1 and SW2 are turned on, and the capacitance C _S and the correction capacitor C _COMP are discharged. During the subsequently Aru charge period (sensing period), the sense switch SW2 is turned on, starting the first charging current I _CHG1 flows to the electrostatic capacitance C _S, the electrostatic capacitance C _S is charged. The capacitance C _S is charged until the voltage V _CS reaches a predetermined voltage level V _TH .
V _TH = V _DD -2 × V _DS
V _DS is the drain-source voltage of the first transistor M1 and the sense switch SW2, and can be regarded as substantially zero when I _CHG1 = 0 when charging is completed.

In this charging period, the amount of charge Q ₁ flowing into the capacitance C _S is given by equation (1).
Q ₁ = V _TH × C _S = ∫I _CHG1 dt (1)

Correction switch SW4 are simultaneously turned on during the charging period, the second charging current _{I CHG2} flows in the correction capacitor _{C COMP,} the correction capacitor _{C COMP} is charged. The waveform of the second charging current I _CHG2 at this time can be said to be substantially the same (similar) as the waveform of the first charging current I _CHG1 , and the voltage V _{COMP of the} correction capacitor C _COMP is at the predetermined voltage level V _TH . It is charged until it reaches. The amount of charge Q ₂ flowing into the correction capacitor C _COMP is given by equation (2).
Q ₂ = V _TH × C _COMP = ∫I _CHG2 dt (2)

The charge amount Q ₃ supplied to the integrating capacitor C _INT is charged by the detection current I _S corresponding to the first charging current I _CHG1 and the correction current I _COMP corresponding to the second charging current I _CHG2 , and thus in the charging period. the total charge amount Q ₃ supplied is given by equation (3).
Q ₃ = k ₁ × Q ₁ + k ₂ × Q ₂ (3)
k ₁ is a constant corresponding to the mirror ratio of the first current mirror circuit 14. k ₂ is a correction gain and corresponds to the mirror ratio of the second current mirror circuit 34.

When Expressions (1) and (2) are substituted into Expression (3), Expression (4) is obtained.
Q ₃ = k ₁ × V _TH × C _S + k ₂ × V _TH × C _COMP
= V _TH × (k ₁ × C _S + k ₂ × C _COMP ) (4)

Therefore, the change amount ΔV _S of the detection voltage V _S of the integrating capacitor C _INT during the charging period is given by Expression (5).
ΔV _S = Q ₃ / C _INT = V _TH × (k ₁ × C _S + k ₂ × C _COMP ) / C _INT (5)
When the initial voltage of the detection voltage V _S is zero, ΔV _S = V _S.

As shown in FIG. 5, the detection voltage V _S in the capacitance measurement circuit 100 is represented by (iii), and the first charging current I _CHG1, that is, the component (i) corresponding to the detection current I _S , and the second charging current I _CHG2 , It is decomposed into the component (ii) corresponding to the correction current I _COMP . (Iv) shows an ideal detection voltage V _{S_REF} .

The first advantage of the capacitance measuring circuit 100 becomes clear by comparison with the capacitance measuring circuit 100r of FIG. In Figure 1, the offset current _{I OFS} is supplied to the electrostatic capacitance _{C S.} If the length and T of the charging period, the charge amount supplied to the electrostatic capacitance _{C S} by the offset current _{I OFS} is _{I OFS} × T. Therefore, in FIG. 1, the dynamic range is narrowed by the voltage width V = I _OFS × T / C _S. Correction current I _COMP does not flow to the electrostatic capacitance C _S according to the capacitance measuring circuit 100 according to the embodiment with respect to this. Thereby, the fall of a dynamic range can be suppressed.

In the capacitance measuring circuit 100 in addition, the correction current _{I COMP} is not constant current, having a detection current _{I S} and the same waveform. A detection voltage V _S based on equation (5) can be obtained. According to the capacitance measurement circuit 100 according to the embodiment, the detection voltage V _S can be brought close to the ideal detection voltage V _{S_REF} by optimizing the sizes of k ₁ , k ₂ , and C _COMP . This is equivalent to connecting a virtual capacitance of k ₂ / k ₁ × C _{COMP in} parallel with the capacitance C _S to be detected. This means that the influence of parasitic capacitance can be canceled, and therefore the sensitivity can be increased.

Next, the use of the capacitance measuring circuit 100 will be described. The capacitance measuring circuit 100 can be suitably used for the input device 2 having a touch panel. FIG. 6 is a circuit diagram of the input device 2 including the capacitance measuring circuit of FIG. The input device 2 includes a touch panel 3 and a control IC (Integrated Circuit) 4. The touch panel 3 includes a plurality of sensor electrodes, the electrostatic capacitance C _S of the contacted coordinates vicinity of the sensor electrode of the user is changed.

Control IC4 is provided with a plurality of capacitance measurement circuits ₁₀₀ 1 to 100 _N corresponding to a plurality of the electrostatic capacitance _{C S.} The multiplexer 50 selects a plurality of detection voltages V _{S1 to} V _SN from the plurality of capacitance measurement circuits 100 _{1 to} 100 _N in a time division manner. The A / D converter 52 converts the detection voltage V _S selected by the multiplexer 50 into a digital detection value D _S. The A / D converter 52 may be provided for each capacitance measuring circuit 100.

The above is the configuration of the input device 2. The input device 2 detects coordinates where a user's finger or stylus contacts (or approaches) based on a relative change amount of the plurality of capacitances C _{S1 to} C _SN .

The parasitic capacitances C _{P1 to} C _PN have variations, and the variations reduce detection sensitivity and deteriorate the dynamic range. In the control IC4 6, by optimizing the capacitance value of the plurality of correction capacitors _C COMP1 _{-C COMPN,} it is possible to cancel the variation in the parasitic capacitance _{C P} for each channel. As a result, the detection sensitivity is improved, and it is possible to detect an input accompanied by a minute capacitance change, such as hovering.

FIG. 7 is a circuit diagram of an input device 2a according to a modification. The control IC 4a in FIG. 7 further includes a current averaging circuit 54 in addition to the control IC 4 in FIG. The current averaging circuit 54 generates an average current I _AVE of the plurality of detection currents I _{S1 to} I _SN generated by the plurality of C / I conversion circuits 10. Then, the average currents I _{AVE1 to} I _AVEN are supplied to a plurality of current synthesis circuits 40 ₁ to 40 _{N. I AVE1 =} I AVE2 = a _{··· I} AVEN ₌ I _AVE.

The i-th (i = 1, 2,... N) current synthesis circuit 40 _i synthesizes the average current I _AVEi in addition to the corresponding detection current I _Si and the corresponding correction current I _COMPi . Specifically, the current synthesis circuit 40 _i synthesizes the correction current I _COMPi with the difference current I _y between the detection current I _Si and the average current I _AVE .

FIG. 8 is a circuit diagram showing a specific example of the control IC 4a of FIG. In this example, the current synthesis circuit 40 and the current averaging circuit 54 are integrally configured. The current averaging circuit 54 includes a plurality of fifth transistors M5, a plurality of sixth transistors M6, and a plurality of seventh transistors M7. A plurality of fifth transistor M5 corresponds to a plurality of the electrostatic capacitance C _S, respectively, are connected to generate a copy current I _C which is proportional to the corresponding detection current I _S.

A plurality of sixth transistor M6 may correspond to a plurality of the electrostatic capacitance C _S, respectively, provided in the path of the corresponding copy current I _C. Control terminals (gates) of the plurality of sixth transistors M6 are connected in common.

A plurality of seventh transistor M7 may correspond to a plurality of the electrostatic capacitance C _S, respectively, to correspond to the sixth transistor M6 forms a third current mirror circuit as an input, the corresponding sixth transistor M6 Connected. The current that flows through the seventh transistor M7 is the average current I _AVE . The second transistor M2 and the seventh transistor M7 are connected, whereby the current synthesis circuit 40 _generates a detection current I _D (= I _S −I _AVE ) corresponding to the difference between the detection current I _S and the average current I _AVE. Generate.

  The output node of the correction charging circuit 30 may be connected to the output node A of the C / I conversion circuit 10, that is, the connection node of the second transistor M2 and the seventh transistor M7. In this case, individual correction for each channel is possible. Alternatively, the output node of the correction charging circuit 30 may be connected to the connection node B of the fifth transistor M5 and the sixth transistor M6. The configuration example of the current synthesis circuit 40 has been described above.

  FIG. 9 is a block diagram of an electronic device 1 including the input device 2 of FIG. Examples of the electronic device 1 include a mobile phone terminal, a personal computer, a tablet terminal, a digital still camera, a portable music player, and a remote controller.

The electronic device 1 includes a DSP (Digital Signal Processor) 6 and an LCD (Liquid Crystal Display) 7 in addition to the input device 2. The input device 2 includes a touch panel 3 and a control IC 4. The touch panel 3 includes a plurality of sensor capacitors C _{S1 to} C _Sn arranged regularly. The plurality of sensor capacitors C _{S1 to} C _SN are substantially arranged in a matrix. The control IC 4 is connected to each of the plurality of sensor capacitors C _{S1 to} C _SN , detects each capacitance value, and outputs data indicating each capacitance value to the DSP 6.

The electronic device 1 of the user's finger 5 or pen (stylus) is in contact with the touch panel 3, or the proximity, the capacitance value of the sensor capacitance C _S of the contact coordinates is changed. DSP6, based on the capacitance value of the plurality of sensors capacitance C _S, it detects the coordinates touched by the user. For example, the touch panel 3 may be provided on the surface of the LCD 7 or may be provided at another location. By increasing the sensitivity of the control IC 4, a new user interface can be provided.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
In the correction charging circuit 30 of FIG. 4, the second current mirror circuit 34 may be configured such that its mirror ratio is variable. As a result, the correction gain can be adjusted with a smaller circuit area than when the correction capacitor C _COMP is made variable.

(Second modification)
In the embodiment, to generate the correction current _{I D} by adding synthesized correction current _{I COMP} on the detection current _{I S,} it may be corrected current _{I D} by subtracting the correction current _{I COMP} from the detected current _{I S.} In this case, the current synthesis circuit 40 may be configured to discharge the integrating capacitor C _INT with the correction current I _COMP . In this modification, the change width ΔV _S of the detection voltage V _S during the charging period is given by Expression (6).
ΔV _S = Q ₃ / C _INT = V _TH × (k ₁ × C _S −k ₂ × C _COMP ) / C _INT (6)

Prior to the charging period, an initializing circuit for initializing the integrating capacitor C _INT to a non-zero voltage is added, and the current synthesizing circuit 40 is configured to discharge the integrating capacitor C _INT by the synthesized current _ID . May be.

(Third Modification)
In FIG. 8, the current averaging circuit 54 may generate an average current I _AVE of a plurality of combined currents _ID .

(Fourth modification)
In the embodiment, the capacitance _CS is detected by integrating the composite current _ID using the integration capacitor C _INT of the I / V conversion circuit 20, but the present invention is not limited to this. The combined current I _D is converted into a digital value, may detect the electrostatic capacitance C _S by the digital signal processing.

(5th modification)
FIG. 10 is a circuit diagram of an I / V conversion circuit 20a according to a fifth modification. The I / V conversion circuit 20a is an integration circuit that further includes an operational amplifier 22, a feedback resistor _RFB , and a reset switch SW5 in addition to the integration capacitor _CINT . A reference voltage V _REF is input to the non-inverting input terminal of the operational amplifier 22. The integrating capacitor C _INT is provided between the output terminal and the inverting input terminal of the operational amplifier 22. The resistor R _FB and the reset switch SW5 are provided in parallel with the integrating capacitor C _INT .

When the reset switch SW5 is turned on, the detection voltage V _S is initialized to the reference voltage V _REF . In the reset switch SW5 is off, the combined current _{I D} is input, the capacitor _{C INT} is charged, the detected voltage _{V S} changes [Delta] V _S.
V _S = V _REF + ΔV _S

(Sixth Modification)
In the embodiment, the correction charging circuit 30 is synchronously controlled with the C / I conversion circuit 10, but the present invention is not limited to this. After the C / I conversion circuit 10 is operated to charge the integration capacitor C _INT of the I / V conversion circuit 20, the correction charging circuit 30 is operated to set the integration capacitor C _INT by the correction current I _COMP . It may be charged or discharged.

(Seventh Modification)
In the embodiment, the touch panel 3 in which the sensor capacitors _CS are substantially arranged in a matrix has been described as an example. However, the use of the capacitance measuring circuit 100 is not limited thereto. For example, the capacitance measuring circuit 100 can also be applied to an XY touch panel. In this case, the capacitance values of a plurality of row sensor electrodes and a plurality of column sensor electrodes can be detected simultaneously.

(Eighth modification)
The capacitance measuring circuit 100 shown in the embodiment may be inverted upside down. A person skilled in the art can understand that the P-channel MOSFET and the N-channel MOSFET may be appropriately replaced at this time. Charging and discharging at this time are reversed, but the essential operation is the same. Some transistors may be replaced with bipolar transistors.

(Ninth Modification)
In the embodiment, the case where the capacitance measuring circuit 100 is applied to an input device using a change in capacitance has been described, but the use of the capacitance measuring circuit 100 is not limited to this. For example, the present invention can be applied to a microphone in which a capacitor is formed by a diaphragm electrode and a back plate electrode, such as a capacitor type microphone, and the capacitance of the capacitor is changed by sound pressure.

(10th modification)
Further, since the capacitance measuring circuit 100 can amplify and detect a very small change in capacitance, it can be used for various other applications.

(Eleventh modification)
In the embodiment, the case where the capacitance measuring circuit 100 is integrated on one semiconductor integrated circuit has been described. However, the present invention is not limited to this, and each circuit block is configured by using chip parts or discrete elements. Also good. Which block is to be integrated may be determined according to the semiconductor manufacturing process to be employed, required cost, characteristics, and the like.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 2 ... Input device, 3 ... Touch panel, 4 ... Control IC, 5 ... Finger, 6 ... DSP, 7 ... LCD, 100 ... Capacity measurement circuit, 10 ... C / I conversion circuit, 12 ... Power supply line, DESCRIPTION OF SYMBOLS 14 ... 1st current mirror circuit, 20 ... I / V conversion circuit, 30 ... Correction circuit, 34 ... 2nd current mirror circuit, 40 ... Current composition circuit, 50 ... Multiplexer, 52 ... A / D converter, 54 ... Current averaging circuit, 60 ... offset cancel circuit, C _S ... capacitance, C _INT ... capacitor for integration, C _COMP ... capacitor for correction, M1 ... first transistor, M2 ... second transistor, M3 ... third transistor, M4 ... 4th transistor, M5 ... 5th transistor, M6 ... 6th transistor, M7 ... 7th transistor, SW1 ... Reset switch, SW2 ... Senses Pitch, SW3 ... reset switch, SW4 ... correction switch.

Claims (27)

A capacitance measuring circuit for measuring capacitance,
A first transistor provided between the capacitance and a fixed voltage terminal;
A sense switch for switching on and off the charging operation of the capacitance by the first transistor;
A correction capacitor;
A correction charging circuit for charging the correction capacitor;
A current combining circuit that generates a combined current by combining a detection current corresponding to the first charging current flowing through the first transistor and a correction current corresponding to a second charging current flowing from the correction charging circuit to the correction capacitor. When,
And a capacitance measuring circuit that detects the capacitance based on the combined current.   The first charging current is a current that flows when the voltage of the capacitance is changed by a predetermined voltage width,
  The capacitance measuring circuit according to claim 1, wherein the second charging current is a current that flows when the voltage of the correction capacitor is changed by the predetermined voltage width.   3. The capacitance measuring circuit according to claim 1, wherein the circuit including the first transistor and charging the capacitance and the correction charging circuit have the same configuration. The sense switch between the fixed voltage terminal and the electrostatic capacitance, the capacitance measuring circuit according to any one of claims 1 to 3, characterized in that provided on the first transistor in series. A second transistor connected to the first transistor so as to form a first current mirror circuit to which the first transistor is input;
Capacitance measuring circuit according to any one of claims 1 4, characterized in that the current flowing through the second transistor is the detection current. The correction charging circuit includes:
A third transistor provided between the correction capacitor and the fixed voltage terminal;
A correction switch for switching on and off the charging operation of the correction capacitor by the third transistor;
A fourth transistor connected to the third transistor so as to form a second current mirror circuit to which the third transistor is input;
The provided, capacitance measuring circuit according to any one of claims 1 to 5, current flowing in the fourth transistor is characterized in that said correction current. The capacitance measuring circuit according to claim 6 , wherein a mirror ratio of the second current mirror circuit is variable. The capacitance measuring circuit according to claim 7 , wherein the correction switch is synchronously controlled with the sense switch. Further comprising an integrating capacitor charged and discharged by the combined current,
The voltage of the integrating capacitor, the capacitance measuring circuit according to any one of claims 1 to 8, characterized in that a detected voltage corresponding to the electrostatic capacitance. A first reset switch for initializing the charge of the capacitance;
A second reset switch for initializing the charge of the correction capacitor;
Capacitance measuring circuit according to any one of claims 1 9, further comprising a. Capacitance measuring circuit according to any one of claims 1 to 10, characterized in that the correction capacitor is a variable capacitance. A capacitance measuring circuit for measuring each of a plurality of capacitances,
A plurality of capacitance-current conversion circuits which are associated with the plurality of capacitances and generate detection currents corresponding to the respective capacitances;
A plurality of correction current generating circuits which are associated with the plurality of capacitances, each generating a correction current;
A plurality of current combining circuits that are associated with the plurality of capacitances, combine a corresponding detection current and a corresponding correction current, and generate a combined current;
With
Each of the plurality of correction current generation circuits is
A correction capacitor;
A correction charging circuit for charging the correction capacitor;
And the correction current corresponds to a second charging current flowing from the correction charging circuit to the correction capacitor.   The capacity measurement circuit according to claim 12, wherein the capacity-current conversion circuit and the correction charging circuit have the same configuration. Each of the plurality of capacitance-current conversion circuits is
A first transistor provided between the capacitance and a fixed voltage terminal;
A sense switch for switching on and off the charging operation of the capacitance by the first transistor;
A second transistor connected to the first transistor so as to form a first current mirror circuit to which the first transistor is input;
The capacitance measuring circuit according to claim 12 , wherein a current flowing through the second transistor is the detection current. The correction charging circuit includes:
A third transistor provided between the correction capacitor and the fixed voltage terminal;
A correction switch for switching on and off the charging operation of the correction capacitor by the third transistor;
A fourth transistor connected to the third transistor so as to form a second current mirror circuit to which the third transistor is input;
The capacitance measuring circuit according to claim 14 , wherein a current flowing through the fourth transistor is the correction current. 16. The capacitance measuring circuit according to claim 15 , wherein a mirror ratio of the second current mirror circuit is variable. The capacitance measuring circuit according to claim 15 , wherein the correction switch is synchronously controlled with the sense switch. 18. The capacitance measuring circuit according to claim 12, wherein an output node of each of the plurality of correction current generation circuits is connected to an output node of a corresponding capacitance-current conversion circuit. A current averaging circuit that generates an average current of a plurality of detection currents generated by the plurality of capacitance current conversion circuits or an average current of a plurality of combined currents;
19. The capacitance measuring circuit according to claim 12, wherein each of the plurality of current combining circuits combines an average current in addition to a corresponding detection current and a corresponding correction current. The current averaging circuit is
A plurality of fifth transistors corresponding to the plurality of capacitances, each connected to generate a copy current proportional to a corresponding detected current;
A plurality of sixth transistors corresponding to the plurality of capacitances, each provided on a corresponding copy current path, and each control terminal connected in common;
A plurality of seventh transistors corresponding to the plurality of capacitances, each connected to a corresponding sixth transistor so as to form a third current mirror circuit to which the corresponding sixth transistor is input;
The capacitance measurement circuit according to claim 19 , wherein a current flowing through the plurality of seventh transistors is the average current. 21. The capacitance measuring circuit according to claim 20 , wherein an output node of each of the plurality of correction current generation circuits is connected to a connection node of a corresponding sixth transistor corresponding to the fifth transistor. A plurality of integrating capacitors corresponding to the plurality of capacitances, each of which is charged and discharged by a corresponding combined current, and the voltage of the integrating capacitor is a detection voltage corresponding to the capacitance The capacitance measuring circuit according to claim 12, wherein 23. The capacitance measuring circuit according to claim 12, wherein the correction capacitor is a variable capacitance. Capacitance measuring circuit according to any one of claims 1 to 23, on a single semiconductor integrated circuit, characterized in that it is monolithically integrated. A touch panel including a plurality of sensor electrodes, and the capacitance of the sensor electrodes in the vicinity of coordinates touched by the user is changed;
A capacitance measuring circuit according to any one of claims 12 to 23 ;
An input device comprising: An electronic apparatus comprising the input device according to claim 25 . A method for measuring capacitance,
Charging the capacitance while the sense switch is turned on by the sense switch and the first transistor, which are sequentially provided in series between the capacitance and the fixed voltage terminal;
Copying a charging current to the capacitance by a first current mirror circuit having the first transistor as an input;
Charging a correction capacitor in synchronization with the sense switch;
Combining the charging current to the capacitance and the charging current to the correction capacitor, and detecting the capacitance value of the capacitance based on the combined charging current;
A measurement method comprising:

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