JP6533434B2 - Station side optical terminator - Google Patents

Description

  The present invention relates to a station-side optical termination unit (OLT) of a passive optical network (PON).

  The present optical access system (see, for example, non-patent document 2) is a dedicated hardware Application Specific that has a cost advantage of chip unit cost in mass production in the processing unit in OLT on the premise that one type is introduced in large quantities. It incorporates an integrated circuit (ASIC) (see, for example, Non-Patent Document 1).

Ohmichi et al., "Development of communication LSI for 10G-EPON", SEI Technical Review No. 180, pp. 43-48 (2012) “40-Gigabit-capable passive optical networks (NG-PON 2): General requirements,” ITU-T, 2013. "Ultra-high capacity digital coherent optical transmission technology", http: // www. ntt. co. jp / journal / 1103 / files / jn201103013. pdf, (July 22, 2015 search) N. Iiyama et al. “Feasibility Study on a Scheme for Coexistence of DSP-based PON and 10-Gbps / λ PON Using Hierarchical Star QAM Format”, IEEE J. Lightwave Technol. , Vol. 31, no. 18, pp. 3085-3092, Sep. 2013. "Recommendation for Block Cipher Modes of Operation: Galois / Counter Mode (GCM) and GMAC", NIST, Nov. 2007.

  In general, since it is necessary to process frames of a plurality of users at high speed in an OLT, advanced devices are often used, so manufacturing costs remain high and development costs of several billion yen are required to introduce them into the market. It is said. In addition, since it is necessary to repeat the manufacturing of ASIC several times for debugging before the market introduction, the development period tends to be extended. Furthermore, because ASICs can not rewrite circuits, it is difficult to quickly update functionality in response to new user service requirements.

  Therefore, in order to solve the problems of the above ASIC, it is an object of the present invention to provide a low-cost station-side optical terminator with extensibility and flexibility.

  In order to solve the above problems, the station-side optical termination device according to the present invention has a configuration in which the function can be rewritten by software.

Specifically, the station-side optical termination device according to the present invention is connected to the subscriber-side optical termination device through an optical line, and converts the optical signal from the subscriber-side optical termination device into an electric signal to be a high-level device. A station-side optical termination apparatus which outputs to a network, converts an electric signal from the upper network into an optical signal, and outputs the optical signal to the subscriber-side optical termination apparatus,
An arithmetic unit that performs predetermined processing on the electrical signal;
A setting input unit configured to set the predetermined process performed by the arithmetic unit;
And the like.

  The station-side optical termination device has a structure in which an arithmetic unit is configured by a general purpose processor or the like, and software to be operated can be set from the outside. With this structure, the OLT can be configured without using an expensive ASIC, and further, the OLT function can be added or improved after the fact. Therefore, the present invention can provide a low-cost, station-side optical termination apparatus that is extensible and flexible.

  Here, a general-purpose processor has lower performance than an ASIC, and it is difficult to obtain desired throughput performance. That is, there is also a problem that it is difficult to satisfy contradictory requirements of the extensibility and flexibility of the OLT function and the throughput performance.

  Therefore, the computing unit of the station-side optical termination device according to the present invention converts the sequential electric signals into parallel electrical signals, performs the predetermined processing on the parallel electrical signals in parallel, and sequentially It is characterized by reconversion to an electrical signal.

  The central office side optical termination apparatus can obtain desired throughput performance with a general purpose processor by parallel processing of the OLT function. Therefore, the present invention can provide a station-side optical termination device that can meet the contradictory requirements of scalability, flexibility and throughput performance.

  The predetermined processing performed by the arithmetic unit of the station-side optical termination device according to the present invention is forward error correction according to a request from the subscriber-side optical termination device.

  The predetermined processing performed by the computing unit of the station-side optical termination device according to the present invention is encryption and decryption in response to a request from the subscriber-side optical termination device.

  The arithmetic unit of the station-side optical termination device according to the present invention is characterized in that the memory holds an expanded key for encryption, reads the expanded key from the memory for each of the electric signals, and performs encryption processing of the electric signals. I assume.

  The predetermined processing performed by the arithmetic unit of the station-side optical termination device according to the present invention is a modulation / demodulation signal processing according to a request from the subscriber-side optical termination device.

  The arithmetic unit of the station-side optical termination apparatus according to the present invention performs synchronous detection processing or asynchronous detection processing according to the conditions of the subscriber-side optical termination apparatus and the state of the optical signal from the subscriber-side optical termination apparatus. It is characterized by switching.

  The present invention can provide a low-cost station-side optical termination device that is extensible and flexible.

It is a figure explaining the structure (intensity modulation receiving structure) of the station side optical termination device which concerns on this invention. It is a figure explaining the composition (digital coherent composition) of the station side optical termination device concerning the present invention. It is a figure explaining the case where the arithmetic processing unit of the station side optical termination device concerning this invention is made to perform an encryption process. It is a figure explaining the case where forward error correction processing is made to the arithmetic unit of the station side optical termination device concerning the present invention. It is a figure explaining performing parallel calculation with the calculating | arithmetic unit of the station side optical termination device which concerns on this invention. It is a figure explaining that the arithmetic unit of the station side optical termination device which concerns on this invention has the expansion key for encryption previously. It is a figure explaining parallel processing of CTR encryption in a computing unit of a station-side optical termination device according to the present invention. It is a figure explaining parallel processing of GCM encryption in the arithmetic unit of the station side optical termination device concerning the present invention. It is a figure explaining the switching of the detection process in the modulation / demodulation signal process in the arithmetic unit of the station side optical termination device which concerns on this invention. It is a figure explaining the composition of the station side optical termination device concerning the present invention.

  Embodiments of the invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, components having the same reference numerals denote the same components.

[Task]
The problems of the prior art can be summarized as follows.
・ Diversification of user's demand advances small amount of dedicated hardware and increases chip price.
Most of the conventional communication devices are configured with dedicated hardware ASICs, and can not rewrite the processing after installation. A fixed encryption method, FEC, is used regardless of the request for each user.
-As the types of devices increase due to the diversification of user requirements, maintenance becomes difficult because the operator must learn how to use various devices.
-When implementing the OLT function by software, it is difficult to obtain desired throughput and delay performance because the general-purpose processor has lower performance compared to ASIC. Because data is processed sequentially, throughput does not increase.
The encryption process consists of expanded key generation and encoding process of encryption, and the amount of calculation is large, and it is difficult to obtain the throughput necessary for the communication device.

[Solution method]
The present invention adopts the following method for the above problems.
-Implement encryption processing and modulation / demodulation signal processing by a processor (GPU or CPU having a plurality of cores, etc.) for the communication apparatus.
Parallel implementation of function processing used in the PON system on a many core CPU. The input data sequence is divided into blocks, and multiple blocks are allocated to multiple cores for parallel processing.
Calculate the expanded key for each user in advance, and hold it in the memory for GPU or the memory for CPU.

[effect]
The following effects can be obtained by the present invention adopting the above method.
-In an access network where the type of equipment has increased with the increase in standards, there is a risk that chip prices will rise due to the diversification of small amounts of hardware, but by realizing it with software it is possible to use OLTs by using general-purpose products with fixed prices. realizable.
-Improved flexibility for diverse user requirements. It is possible to switch functions according to the user request. In particular, each user's request for throughput, distance, and delay is dealt with by rewriting the internal function. It utilizes programmable nature and responds flexibly to future diversified user demands.
A device of a plurality of standards can be made common to one hardware. Thereby, the maintainability is improved by reducing the types of devices to operate.
-It is possible to respond to future requests by rewriting the program.
-When operating with a general-purpose processor, the processing time can be shortened by sharing processing with a plurality of cores, and it becomes easy to obtain a desired throughput and delay.
Although pre-calculation of the expanded key increases memory usage, processing time can be shortened and desired throughput can be easily obtained.

Embodiment 1
FIG. 10 is a diagram for explaining the configuration of a station-side optical termination apparatus adopting the above method. In this specification, the station-side optical termination device is described as an OLT 301, and the subscriber-side optical termination device is described as an ONU.
The OLT 301 is connected to an ONU (not shown) through an optical line 51, converts an optical signal from the ONU into an electric signal and outputs the electric signal to the upper network 52, and converts the electric signal from the upper network 52 into an optical signal. A station-side optical termination unit that outputs data to the ONU,
A computing unit 14 that performs predetermined processing on the electrical signal;
A setting input unit (IF) 17 for setting the predetermined process performed by the arithmetic unit 14;
Equipped with

  Furthermore, the computing unit 14 converts the sequential electric signal into a parallel electric signal, performs the predetermined processing on the parallel electric signal in parallel, and reconverts the parallel electric signal into a sequential electric signal.

  The OLT 301 further includes a transmitter / receiver 11, an A / D converter 12A, a D / A converter 12B, a memory 13, an instruction memory 15, and an interface (IF) 16. The arithmetic unit 14 and the instruction memory 15 may be configured as a processor in one package.

  The upstream side will be described first. The input optical signal from the optical line 51 is converted into electricity by the transmitter / receiver 11. After being converted from analog to digital by the A / D converter 12 A, the data is sent to the memory 13, and the data is processed by the computing unit 14 and sent to the upper network 52 by the IF 16.

  Next, the downstream side will be described. The digital data input from the upper network 52 via the IF 16 is processed by the computing unit 14 and stored in the same memory 13 as the upstream data. The data is converted into an analog signal by the D / A converter 12 B and then transmitted from the transmitter / receiver 11 to the optical line 51.

  Also, the OLT 301 includes an IF 17 that can input a program for operating the computing unit 14 separately from the IF 16 of the main signal. By externally inputting the program into the instruction memory 15 by the IF 17, the program written in the instruction memory 15 can be rewritten. This program can be rewritten one or more times.

  Subsequently, the configuration of the computing unit 14 will be described. The computing unit 14 is composed of one CPU unit 21 and one GPU unit 22. The CPU unit 21 has a CPU 23 and a CPU memory 25, and the GPU unit 22 has a GPU 24 and a GPU memory 26. The GPU 24 has more cores than the CPU 23, and is a configuration suitable for parallel processing in which a plurality of calculations are simultaneously performed. The CPU 23 and the GPU 24 read the program of the instruction memory 15 and calculate data possessed by the CPU memory 25 and the GPU memory 26, respectively. Further, the CPU memory 25 and the GPU memory 26 are connected, and the CPU unit 21 moves data to be calculated by the GPU 24 to the GPU memory 26. For example, processing that should be performed by the CPU 23 is bandwidth control or transfer control. Processing that should be performed by the GPU 24 is modulation / demodulation signal processing, forward error correction, encryption and decryption.

  Note that FIG. 10 is an example in which the computing unit 14 includes the CPU unit 21 and the GPU unit 22. The computing unit 14 may not include the GPU unit 22 and may be configured of a CPU having a plurality of cores, and these CPUs may perform parallel processing of calculation.

  FIG. 1 is a diagram for explaining an OLT 301 in the case where an optical signal with an ONU is an intensity modulation scheme (binary (or multilevel) intensity shift keying (ASK) signal). At this time, the arithmetic unit 14 reads programs for bandwidth control, transfer control, modulation / demodulation signal processing, forward error correction, encryption and decryption from the instruction memory 15, and operates the CPU 23 and the GPU 24 according to the programs. The flow of processing content when the CPU 23 and the GPU 24 operate according to the program is described in the computing unit 14 of FIG. 1.

  In the upward direction, the A / D converter 12A simply performs threshold determination on the input signal by the A / D converter 12A to convert the signal received by the transmitter / receiver 11 into a single sequence (or multiple sequence) digital signal, and inputs it to the memory 13. The arithmetic unit 14 performs modulation / demodulation signal processing, forward error correction processing, and encryption processing on the digital signal, performs band control and transfer control, and causes the IF 16 to output a digital signal.

  In the downlink direction, the arithmetic unit 14 performs decoding processing, forward error correction processing, and modulation / demodulation signal processing on the signal input from the upper network 52 and inputs the signal to the memory 13. If the optical signal to the optical line 51 is an ASK signal, the D / A converter 12 B takes out as a series of data from the memory 13, converts it into an analog signal, and delivers it to the transmitter / receiver 11.

  FIG. 2 is a diagram for explaining the OLT 301 when the optical signal with the ONU is a high-order modulation scheme (such as OFDM or quadrature amplitude modulation). Also in this case, the arithmetic unit 14 reads the program from the instruction memory 15 and operates the CPU 23 and the GPU 24 according to the program.

  In the upward direction, the transceiver 11 outputs the received signal to the A / D converter 12A. In particular, when the optical signal is an optical IQ modulation signal such as optical quaternary phase shift keying (QPSK) or optical 16-level quadrature amplitude modulation (16 QAM), the transmitter / receiver 11 is an optical coherent receiver and A / A. A two-sequence signal of I and Q is output to D converter 12A (four sequences in the polarization diversity configuration). The A / D converter 12A digitally samples the waveform of the signal and outputs it. The operation after the A / D converter 12A is the same as in FIG.

  In the downward direction, the operation up to the memory 13 is the same as in FIG. If the optical signal to the optical line 51 is an optical coherent signal, the D / A converter 12 B takes out two series of data from the memory 13, converts it into an analog signal, and delivers it to the transmitter / receiver 11.

Second Embodiment
In the present embodiment, an example will be described in which the arithmetic unit 14 performs the encryption process with the program input to the instruction memory 15. This encryption process is encryption according to the user's request. The computing unit 14 switches and operates the encryption program according to the user request.

  FIG. 3 is a diagram for explaining an example in which a program that switches the type of encryption in response to a user request is input to the instruction memory 15, and the arithmetic unit 14 operates according to the program. Arithmetic unit 14 forms MAC frame processing unit 31 and processing allocation unit 32 according to the program. The program describes an encryption type for each user and a program of each encryption. Then, the MAC frame processing unit 31 looks at the frame stored in the memory 13 (a digital signal converted to an electrical signal by the transmitter / receiver 11 and converted from analog to analog by the A / D converter 12A) to see LLID (Logical Link. ID) is sent to the processing allocation unit 32. The processing allocation unit 32 accesses the instruction memory 15, and obtains a user request (encryption type for each user) and its encryption program according to the LLID. Then, the process allocation unit 32 performs the encryption process according to the user request on the frame.

(Embodiment 3)
In the present embodiment, an example in which the arithmetic unit 14 performs the FEC process with the program input to the instruction memory 15 will be described. This FEC process is a redundant process according to the user's request. The computing unit 14 switches and operates the program of the FEC processing according to the user request.

  FIG. 4 is a diagram for explaining an example in which a program for switching the redundancy of the FEC processing is input to the instruction memory 15 in response to a user request, and the operation unit 14 operates according to the program. The arithmetic unit 14 forms the redundancy setting unit 41 and the FEC unit 42 according to the program. The program describes a program for switching the redundancy of the FEC processing according to the user request and the distance to the ONU. Then, the redundancy setting unit 41 sees a frame stored in the memory 13 (a digital signal converted to an electrical signal by the transmitter / receiver 11 and converted from analog to analog by the A / D converter 12A) and user information (for example, digital information) Check LLID). The redundancy setting unit 41 can acquire the user request (distance from the ONU) from the instruction memory 15 based on the LLID, so determines the redundancy parameter based on the distance from the ONU and sends this to the FEC unit 42. The FEC unit 42 performs an FEC process according to the user request on the frame according to the redundant parameter.

(Embodiment 4)
In this embodiment, parallel processing of encryption by the GPU will be described with reference to FIG.
The frame from the memory 13 arrives at the CPU memory 25. The CPU unit 21 transfers this frame to the GPU memory 26. The GPU 24 divides a frame (plaintext) of the GPU memory 26 into a plurality of blocks, and assigns these to each core of the GPU. The results calculated by each core are combined again to form an encrypted frame. The encrypted frame is stored in the CPU memory 25 via the GPU memory 26 and output to the upper network 52.

Embodiment 5
In the present embodiment, the encryption processing will be described in more detail using FIGS. 6 to 8.
The expanded key for each user used for the encryption process is pre-computed by the CPU 23 or GPU 24 using software, or pre-computed externally before performing real-time processing of the OLT. Then, the expanded key is held in the GPU memory 26. The GPU 24 reads out and uses the expanded key from the GPU memory 26 when encoding encoding. When the CPU 23 is used as the main process of encryption, the CPU memory 25 holds the expanded key. When the key is updated, the expanded key calculation is performed each time, and the expanded key of the GPU memory 26 is updated.

FIG. 7 and FIG. 8 are diagrams for explaining the operation when the CTR and GCM encryption methods standardized in PON are realized in the computing unit 14, respectively. The symbols used in the figure are as follows.
P: Plain text (Plain Text)
C: Ciphertext A: Data not to be encrypted (Associated data)
T: Authenticator E: Block Cipher

  The CTR is as follows. The plaintext data stream is divided into a plurality of blocks. In each core of the CPU 23 or GPU 24, the encryption of the counter and the exclusive OR calculation of the data stream are operated in parallel for each block. As described in FIG. 6, the expanded key is pre-computed, stored in the CPU memory 25 or GPU memory 26, and used in real time operation.

  The GCM is as follows. The plaintext data stream is divided into a plurality of blocks. In each core of the CPU 23 or GPU 24, the encryption of the counter, the exclusive OR with the block, the GHASH function, the exclusive OR with the E value, and the MSB calculation are operated in parallel. The expanded key and the E value are pre-computed and stored in the CPU memory 25 or the GPU memory 26 as described in FIG.

Embodiment 6
In the present embodiment, an example will be described in which the arithmetic unit 14 switches modulation / demodulation signal processing by a program input to the instruction memory 15. This modulation / demodulation signal processing is modulation / demodulation signal processing according to the user's request. Arithmetic unit 14 switches and operates a program of modulation / demodulation signal processing according to a user request.

  FIG. 9 is a diagram for explaining an example of switching between synchronous detection processing and asynchronous detection processing in digital coherent in modulation and demodulation signal processing. The arithmetic unit 14 forms a processing allocation unit 91 by the program input to the instruction memory 15. The program describes a user request and a program for switching the detection method.

  The processing allocation unit 91 looks at the reception IQ signal stored in the memory 13 (a digital signal converted to an electrical signal by the transmitter / receiver 11 and converted from analog to analog signal by the A / D converter 12A) to view user information (for example, LLID) Examine). The processing allocation unit 91 can acquire a user request (whether synchronous detection or asynchronous detection) from the instruction memory 15 based on user information, and therefore performs modulation / demodulation signal processing according to the user request.

  In synchronous detection, the IQ signal is raised to the power of M, the average value is calculated for a plurality of symbols, and after the sum is taken, identification is performed. On the other hand, in asynchronous detection, identification processing is performed after multiplication with a complex conjugate of a signal obtained by delaying an IQ signal by one symbol. Synchronous detection processing improves reception sensitivity as compared to asynchronous detection processing, but the amount of calculation increases and utilization of processor resources increases (calculation time in a CPU or GPU increases).

  For example, the processing allocation unit 91 uses synchronous detection processing for a user who has a long request for extension, and uses asynchronous detection processing for a user whose request is not so high. This determination can suppress the use of processor resources and improve the throughput. Also, only asynchronous detection processing can be used for detection processing to suppress processor resources and improve throughput.

  Further, the processing allocation unit 91 may read the uplink signal reception timing for each user by the MPCP unit, read a request according to the user of the reception signal from the memory, and may allocate synchronous detection or asynchronous detection. Alternatively, it is also possible to identify the user by correlating at the time of OLT reception by the ONU adding a preamble to the upstream signal for each user.

(Other embodiments)
Although it has been described in the second and fifth embodiments that the arithmetic unit 14 performs the encryption process on the upstream signal, the program can be input to the instruction memory 15 so that the arithmetic unit 14 can perform the decryption process on the downstream signal.

[Supplementary note]
The following describes the OLT of the present embodiment.
An object of the present invention is to provide an OLT capable of meeting the contradictory requirements of scalability, flexibility and throughput performance.

(1) An OLT having an input unit connected to an ONU through an optical circuit and inputting an input signal from the ONU, and an output unit outputting a processing result after the data conversion as an output signal,
A processing unit configured to record a predetermined data conversion process by software for the input signal and to perform the data conversion process by a processor;
An OLT characterized by having:

(2): In the OLT of (1) above,
The OLT performs predetermined modulation / demodulation signal processing, forward error correction, and encryption according to a request from the ONU.

(3): In the OLT of (1) above,
An OLT that has the function of dividing a data string into a plurality of blocks on a GPU or CPU, allocating divided data to each core, and operating processing in parallel.

(4): In the OLT of (1) above,
An OLT that has an expanded key according to the user of encryption stored in a memory on the GPU or CPU, reads the expanded key from the memory during real-time operation, and performs encryption processing.

(5): In the OLT of (1) to (4) above,
An OLT that switches synchronous detection processing or asynchronous detection processing according to the user's conditions and conditions as a modulation / demodulation signal processing function.

11: transceiver 12A: A / D converter 12B: D / A converter 13: memory 14: arithmetic unit 15: instruction memory 16: interface (IF)
17: Interface (IF)
21: CPU unit 22: GPU unit 23: CPU
24: GPU
25: CPU memory 26: GPU memory 31: MAC frame processing unit 32: processing allocation unit 41: redundancy setting unit 42: FEC processing unit 51: optical line 52: upper network 91: processing allocation unit 301: OLT (station side light Termination device)

Claims (7)

It is connected to the subscriber-side optical termination unit through an optical line, converts the optical signal from the subscriber-side optical termination unit into an electrical signal and outputs it to the upper network, and the electrical signal from the upper-level network to the optical signal A station-side optical termination unit that converts and outputs the converted signal to the subscriber-side optical termination unit;
An arithmetic unit that performs predetermined processing on the electrical signal;
A setting input unit that sets a program of the predetermined process performed by the arithmetic unit in an instruction memory;
Equipped with
The computing unit includes a CPU , a CPU memory, a GPU , and a GPU memory connected to the CPU memory .
The CPU moves data from the CPU memory to the GPU memory which is better to be processed by the GPU among data indicated by the electric signal input to the CPU memory, and sets the program set in the instruction memory Reading and performing the first processing of the predetermined processing on data held by the CPU memory ;
The GPU reads a program set in the instruction memory, and performs a second process different from the first process among the predetermined processes on data included in the GPU memory. Optical termination device. The station-side optical termination device according to claim 1, wherein the first process is band control or transfer control . 3. The station-side optical termination device according to claim 1, wherein the second process is forward error correction according to a request from the subscriber-side optical termination device. The station-side optical termination device according to any one of claims 1 to 3, wherein the second process is encryption and decryption in response to a request from the subscriber-side optical termination device. 5. The station-side light according to claim 4, wherein the GPU holds an expanded key for encryption in a memory, reads the expanded key from the memory for each of the electric signals, and performs an encryption process of the electric signal. Termination device. The station-side optical termination device according to any one of claims 1 to 5, wherein the second processing is modulation / demodulation signal processing according to a request from the subscriber-side optical termination device. The GPU according to claim 6, wherein the GPU switches between synchronous detection processing and asynchronous detection processing according to the condition of the subscriber-side optical termination device and the state of the optical signal from the subscriber-side optical termination device. Station-side optical termination unit.

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