JP6516097B2 - Arithmetic device, IC card, arithmetic method, and arithmetic processing program - Google Patents

Description

  The present invention relates to the technical field of an arithmetic device that includes multiple cores and can perform parallel processing.

  For control devices that may lose safety if they fail, measures have been taken to monitor the main core by a monitoring unit such as a sub core and detect an abnormality in the main core to guarantee the safe operation of the control device. . As one example, as disclosed in Patent Document 1, a technique called lock step is in widespread use. The lock step is a technology in which a plurality of cores execute the same processing in parallel and compare the execution results to determine that each core is operating normally. For example, as disclosed in Patent Document 2, there is known a technology that guarantees safe operation by authenticating an opposite device using encryption technology while lock step aims to detect a failure. .

JP, 2010-128627, A JP, 2013-138304, A

  However, side channel attacks are known in fields such as smart cards and TPMs (Trusted Platform Module) known as authentication devices. Side channel attack is a threat that has existed for a long time in the controller for cryptographic computation, and the content of computation using power consumed during computation and secondary information (side channel information) represented by generated electromagnetic waves Attack method to estimate For example, in an IC card provided with a plurality of cores and capable of performing parallel processing, when the plurality of cores simultaneously execute the same processing, power consumption and electromagnetic waves are increased and are likely to be targets for side channel attacks. Becoming a problem.

  Therefore, the present invention has been made in view of the above problems and the like, and side channel information is not increased even if a plurality of cores execute the same processing, and it is possible to realize high tamper resistance. An object is to provide a device, an IC card, an arithmetic method, and an arithmetic processing program.

In order to solve the above problem, the invention according to claim 1 is an operation including a first operation unit and a second operation unit that execute the same process in parallel according to a command received from an external terminal. The apparatus includes clock signal delay means for delaying the clock signal generated by the clock signal generation means for a predetermined time, and the first operation unit receives the clock signal generated by the clock signal generation means. The processing is performed in synchronization with the clock signal, and the second arithmetic unit inputs a clock signal delayed by a predetermined time by the clock signal delay unit when the command is a command requesting security processing , There line said security processing in synchronization with a clock signal, a command which said command requests a security process There case, input the clock signal generated by said clock signal generating means, characterized in that in synchronization with the clock signal performs processing other than the security processing.

  The invention according to claim 2 is characterized in that, in the arithmetic device according to claim 1, the clock signal delaying unit delays the clock signal by a half cycle as the predetermined time.

The invention according to claim 3 is an IC card including a first operation unit and a second operation unit that execute the same process in parallel according to a command received from an external terminal , wherein the clock signal is generated. A clock signal delay unit for delaying the clock signal generated by the unit for a predetermined time, and the first arithmetic unit receives the clock signal generated by the clock signal generation unit, and synchronizes with the clock signal. When the processing is performed and the command is a command requiring security processing , the second arithmetic unit receives a clock signal delayed by a predetermined time by the clock signal delay unit, and synchronizes the security signal in synchronization with the clock signal. There line processing, if the command is not a command for requesting the security process, said clock signal Receives a clock signal generated by the generating means and processing the rows Ukoto other than the security processing in synchronization with the clock signal.

The invention according to claim 4 is an arithmetic method in an arithmetic device provided with a first arithmetic unit and a second arithmetic unit which execute the same process in parallel according to a command received from an external terminal , The clock signal delaying step for delaying the clock signal generated by the clock signal generation means for a predetermined time is included, and the first arithmetic unit receives the clock signal generated by the clock signal generation means and is synchronized with the clock signal. And the second operation unit inputs a clock signal delayed for a predetermined time by the clock signal delay step when the command is a command requesting security processing, and synchronizes with the clock signal. There line said security processing Te, ne command said command requests the security process When the input the clock signal the clock signal generated by the generating means, in synchronism with the clock signal and wherein the processing line Ukoto other than the security processing.

The invention according to claim 5 is a computer having a first arithmetic unit and a second arithmetic unit that executes the same process in parallel according to a command received from an external terminal , generated by clock signal generation means. Performing a clock signal delay step of delaying the clock signal for a predetermined time, and the first arithmetic unit inputs the clock signal generated by the clock signal generation unit, and performs the processing in synchronization with the clock signal. performed, the second operation unit, when the command is a command for requesting the security process receives a clock signal delayed a predetermined time by the clock signal delaying step, the security processing in synchronization with the clock signal There line, if the command is not a command for requesting the security process, the click Tsu receives a clock signal generated by the click signal generating means, in synchronism with the clock signal and said row Ukoto processing other than the security processing.

  According to the present invention, even when a plurality of cores execute the same processing, side channel information is not increased, and high tamper resistance can be realized.

FIG. 6 is a diagram showing an example of a schematic configuration of an IC chip C. It is a figure which shows an example of power consumption when the core 1 and the core 2 perform the same process synchronizing with the same clock signal. FIG. 7 is a diagram showing an example of power consumption when core 1 performs authentication processing in synchronization with a clock signal and core 2 performs the same authentication processing in synchronization with a clock signal delayed by a half cycle from the clock signal. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiment described below is an embodiment in the case where the present invention is applied to an IC chip.

  First, with reference to FIG. 1, a schematic configuration of an IC chip according to the present embodiment will be described. FIG. 1 is a view showing a schematic configuration example of an IC chip C. As shown in FIG. The IC chip C is an example of the arithmetic device of the present invention. The IC chip C is mounted on a cash card, a credit card, an electronic money card, an employee card or the like and used. Alternatively, the IC chip C is incorporated in a communication device such as a smartphone or a mobile phone. The IC chip C may be built directly on the circuit board of the communication device.

  As shown in FIG. 1, the IC chip C includes a core 1, a core 2, a clock generation circuit 3, a clock switching circuit 4, a switching control register 5, a random access memory (RAM) 6, a flash memory 7, and a read only memory (ROM). And 8) and an I / O circuit 9. The core 1 is an example of a first arithmetic unit. The core 2 is an example of a second arithmetic unit. The cores 1 and 2 are configured to be capable of parallel processing. The core 1, the core 2, the switching control register 5, the RAM 6, the flash memory 7, the ROM 8, and the I / O circuit 9 are connected to the bus 10. The bus 10 comprises an address bus and a data bus. The clock generation circuit 3 may not be provided in the IC chip C. In this case, the IC chip C receives a clock signal from the clock generation circuit provided in the external terminal via the I / O circuit 9.

  The cores 1 and 2 respectively include an arithmetic unit, an internal memory, a program counter, an interrupt controller, and the like, and execute the same processing in parallel. The computing units each include an instruction register and a decoder. Each internal memory comprises a data register. The program counter holds an address on the flash memory 7 or the ROM 8 in which an instruction code to be executed next is stored. The interrupt controller is for the core 1 and the core 2 to give an interrupt command to each other without passing through the bus 10.

  The clock generation circuit 3 includes a variable frequency generation circuit (PLL (Phase Locked Loop)) or the like. The clock generation circuit 3 is an example of a clock signal generation unit. The clock generation circuit 3 is, for example, a variable frequency generation circuit from a clock CLK input from an external terminal through the I / O circuit 9 or a clock CLK input from an internal oscillator (not shown) provided in the IC chip C. , And generates clock signals for the core 1, core 2, switch control register 5, RAM 6, flash memory 7, ROM 8 and I / O circuit 9. For example, the clock generation circuit 3 generates a clock signal (system clock) having a clock frequency of 60 MHz based on the input clock CLK, and outputs the generated clock signal to the core 1 and the clock switching circuit 4. The clock generation circuit 3 also outputs the input clock CLK to the switching control register 5, the RAM 6, the flash memory 7, the ROM 8, and the I / O circuit 9.

  The clock switching circuit 4 includes an inverter (logic inversion circuit), a selector, and the like. The inverter is an example of clock signal delay means. The inverter has a half cycle delay of the clock signal input from the clock generation circuit 3 (for example, when the clock frequency is 60 MHz, a delay of 1/2 of the time (17 ns) corresponding to one clock (one cycle) ). In other words, the inverter inverts the logic level (high level and low level) of the input clock signal. The selector selects one of the clock signal input from the clock generation circuit 3 and the clock signal delayed by a half cycle by the inverter according to the logic level of the signal output from the switching control register 5 It is possible. For example, when a high level signal is input, a clock signal delayed by a half cycle is selected by the inverter. The clock signal thus selected is output to the core 2. The example of FIG. 1 shows an example in which a clock signal delayed by a half cycle by an inverter is output. As a result, the clock signal input to the core 2 is delayed by a half cycle (in other words, the logic level of the clock signal is inverted) than the clock signal input to the core 1.

  The switching control register 5 is, for example, an 8-bit register, and outputs a signal of a logic level according to the binary state (0 or 1) of a specific bit (for example, the most significant bit) to the selector of the clock switching circuit 4. For example, although the above-mentioned specific bit is initially maintained at "0", under a predetermined condition, it is changed to "1" representing the use state of the inverter.

  The RAM 6 is a work memory, and temporarily stores processing results of the cores 1 and 2. The flash memory 7 is a non-volatile memory, and stores programs such as an OS and an application to be executed by the core 1 and the core 2. Further, the flash memory 7 is provided with a secure storage area, in which an encryption key (which may be a combination of a secret key and a public key) is stored. Note that instead of the flash memory 7, "Electrically Erasable Programmable Read-Only Memory" may be applied. The ROM 8 also stores part of the program stored in the flash memory 7.

  The I / O circuit 9 takes on an interface with an external terminal. In the case of the contact type IC chip C, the I / O circuit 9 is provided with, for example, eight terminals C1 to C8. For example, terminal C1 is a power supply terminal, terminal C2 is a reset terminal, terminal C3 is a clock terminal, terminal C5 is a ground terminal, and terminal C7 is a terminal for communication with an external terminal. On the other hand, in the case of the non-contact type IC chip C, the I / O circuit 9 is provided with, for example, an antenna and a modulation / demodulation circuit. In addition, as an example of an external terminal, an IC card issuing machine, an ATM, a ticket gate, an authentication gate, etc. may be mentioned. Alternatively, when the IC card 1 is incorporated into a communication device, the external terminal corresponds to a control unit that takes on the function of the communication device.

  In the above configuration, the core 1 receives the clock signal generated by the clock generation circuit 3 and performs processing in synchronization with the clock signal. On the other hand, the core 2 receives the clock signal generated by the clock generation circuit 3 or a clock signal generated by the clock generation circuit 3 and delayed by a half cycle by the inverter of the switching control register 5, and synchronizes with the clock signal. Perform the same process as step 1. Such processing is repeatedly performed in the following flow (1) to (4), for example, when a command from an external terminal is received.

(1) The instruction code stored at the address pointed to by the program counter is fetched from the flash memory 7 into the instruction register (instruction read).

(2) The fetched instruction code is interpreted (decoded) by the decoder (instruction interpretation). The instruction code is described in the application or the OS. For example, an instruction code for encryption used by a plurality of applications is described in the OS.

(3) The interpreted instruction is executed (instruction execution). Note that, for example, normal arithmetic operation, logical operation, encryption operation, decryption operation, and the like are performed by instruction execution.

(4) The operation result is written to the RAM 6 (writing). After writing, the value of the program counter is advanced to fetch the next instruction code.

  For example, when the command received from the external terminal is not a command (authentication command) for requesting an authentication process (an example of a security process) including an encryption operation or a decryption operation, the core 1 is a specific bit of the switching control register 5 The core 2 is requested to perform an authentication process without changing the setting of ("0" representing the initial state). In this case, the same clock signal generated by the clock generation circuit 3 is input to the cores 1 and 2. Thus, the cores 1 and 2 receive the clock signal generated by the clock generation circuit 3 and perform the same processing in synchronization with the clock signal. For example, when it is determined that authentication processing is performed, if it is determined at the application level (for example, when an authentication command is received), it may be determined at the OS level (encryption operation) At runtime etc).

  On the other hand, when the command received from the external terminal is a command for requesting an authentication process (an example of a security process) involving an encryption operation or a decryption operation, the core 1 initially sets a specific bit of the switching control register 5 The setting is changed from “0” representing the state to “1” representing the usage state of the inverter. Thereby, the selector of the clock switching circuit 4 switches so as to select a clock signal delayed by a half cycle by the inverter according to the logic level (for example, high level) of the signal output from the switching control register 5. Then, the core 1 requests the core 2 to perform an authentication process. In this case, while the clock signal generated by the clock generation circuit 3 is input to the core 1, a clock signal delayed by a half cycle from the clock signal is input to the core 2.

  Thus, while the core 1 receives the clock signal generated by the clock generation circuit 3 and performs processing in synchronization with the clock signal, the core 2 is generated by the clock generation circuit 3 and the inverter of the switching control register 5 A clock signal delayed by a half cycle is input, and the same processing as that of the core 1 is performed in synchronization with the clock signal.

  FIG. 2 is a diagram showing an example of power consumption when the core 1 and the core 2 perform the same processing in synchronization with the same clock signal. In the case of FIG. 2, the power consumption is the highest at the time of instruction execution, and since the instruction execution of the core 1 and the instruction execution of the core 2 are at the same timing, the total power consumption is doubled. On the other hand, in FIG. 3, the core 1 performs authentication processing in synchronization with a clock signal, and the core 2 performs the same authentication processing in synchronization with a clock signal delayed by a half cycle from the clock signal. It is a figure which shows an example. In the case of FIG. 3, since the instruction execution of the core 1 and the instruction execution of the core 2 are shifted by a half cycle, the total power consumption is flattened as compared with the case of FIG.

  As described above, according to the above embodiment, the IC chip C includes an inverter that delays the clock signal generated by the clock generation circuit 3 by a half cycle, and the core 1 generates the clock generated by the clock generation circuit 3 A signal is input and processing is performed in synchronization with the clock signal. The core 2 receives a clock signal delayed by a half cycle by the clock generation circuit 3 and performs the same processing as the core 1 in synchronization with the clock signal. With such a configuration, even if the cores 1 and 2 execute the same processing, the side channel information is not increased, and high tamper resistance can be realized. When the core 2 performs processing other than security processing such as authentication processing, the same clock signal as that of the core 1 is input, and the processing is performed in synchronization with the clock signal, so the delay of the clock signal is delayed. It is possible to minimize the processing time delay due to

  In the above embodiment, although the case where the inverter is applied as the clock signal delay means has been described, the clock signal is delayed by a half cycle using a clock detection circuit that detects the rising edge and the falling edge of the clock signal. You may configure it. In this case, the IC chip C is provided with a clock detection circuit instead of the clock switching circuit 4, and the clock detection circuit is connected to each of the core 1 and the core 2. Here, a common clock detection circuit of the core 1 and the core 2 may be provided, or clock detection circuits separate from the core 1 and the core 2 may be provided. The clock detection circuit connected to the core 1 detects the rising edge of the clock signal and sets it as the start position of the clock, and the clock detection circuit connected to the core 2 detects the falling edge of the clock signal and starts the clock Position. Thus, the core 2 can input a clock signal delayed by a half cycle with respect to the clock signal input to the core 1 and perform the processing in synchronization with the clock signal. In the above embodiment, an inverter is taken as an example of the clock signal delay means, and the input clock signal is delayed by a half cycle (0.5 cycle) (an example of a predetermined time delay). In this case, although it is preferable from the balance between the processing speed and the effect of the present invention (side channel information is not increased), the clock signal delaying means changes the input clock signal by 1 instead of delaying by a half cycle. . 5 cycles or 2 cycles (or 0.5 cycles, 1.5 cycles, and times other than 2 cycles) may be configured to be delayed, and even with this configuration, the effects of the present invention can be exhibited. it can. Further, in the above embodiment, an IC chip having two cores has been described as an example, but the present invention is also applicable to a multi-core processor having three or more cores.

1, 2 Core 3 clock generation circuit 4 clock switching circuit 5 switching control register 6 RAM
7 Flash memory 8 ROM
9 I / O circuit 10 bus C IC chip

Claims (5)

An arithmetic apparatus comprising a first arithmetic unit and a second arithmetic unit that execute the same process in parallel according to a command received from an external terminal ,
Clock signal delaying means for delaying the clock signal generated by the clock signal generating means for a predetermined time;
The first operation unit receives the clock signal generated by the clock signal generation unit, and performs the processing in synchronization with the clock signal.
The second arithmetic unit, when the command is a command for requesting the security process receives a clock signal delayed a predetermined time by said clock signal delay means, line physician the security processing in synchronization with the clock signal An arithmetic device characterized in that if the command is not a command requiring security processing, a clock signal generated by the clock signal generation means is input and processing other than the security processing is performed in synchronization with the clock signal; .   The arithmetic device according to claim 1, wherein the clock signal delay unit delays the clock signal by a half cycle as the predetermined time. An IC card comprising a first arithmetic unit and a second arithmetic unit that execute the same process in parallel according to a command received from an external terminal ,
The clock signal generated by the clock signal generating means comprises a clock signal delay means for a predetermined time late cast,
The first operation unit receives the clock signal generated by the clock signal generation unit, and performs the processing in synchronization with the clock signal.
The second arithmetic unit, when the command is a command for requesting the security process receives a clock signal delayed a predetermined time by said clock signal delay means, line physician the security processing in synchronization with the clock signal If the command is not a command for requesting the security process, IC to said clock signal generating means receives a clock signal generated by, said line Ukoto processing other than the security processing in synchronization with the clock signal card. An arithmetic method in an arithmetic device provided with a first arithmetic unit and a second arithmetic unit that executes the same process in parallel according to a command received from an external terminal ,
Including a clock signal delay step of delaying the clock signal generated by the clock signal generation means for a predetermined time period;
The first operation unit receives the clock signal generated by the clock signal generation unit, and performs the processing in synchronization with the clock signal.
The second arithmetic unit, when the command is a command for requesting the security process by the clock signal delaying step receives a clock signal delayed a predetermined time, the row physician the security processing in synchronization with the clock signal If the command is not a command for requesting the security process, calculation the inputs a clock signal the clock signal generated by the generation means and row Ukoto processing other than the security processing in synchronization with the clock signal Method. A computer comprising a first arithmetic unit and a second arithmetic unit that execute the same process in parallel according to a command received from an external terminal ,
Performing a clock signal delay step of delaying the clock signal generated by the clock signal generation means for a predetermined time;
The first operation unit receives the clock signal generated by the clock signal generation unit, and performs the processing in synchronization with the clock signal.
The second arithmetic unit, when the command is a command for requesting the security process by the clock signal delaying step receives a clock signal delayed a predetermined time, the row physician the security processing in synchronization with the clock signal If the command is not a command for requesting the security process, calculation the inputs a clock signal the clock signal generated by the generation means and row Ukoto processing other than the security processing in synchronization with the clock signal Processing program.

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