JP6506010B2 - Power consumption estimation technology for semiconductor integrated circuits - Google Patents

Description

  The present invention relates to a technique for estimating power consumption of a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit capable of measuring the power consumption, a method of measuring the power consumption of the semiconductor integrated circuit, a device for estimating the power consumption of the semiconductor integrated circuit, The present invention relates to a design apparatus for designing a semiconductor integrated circuit that enables measurement of power consumption.

  For semiconductor integrated circuits, it is important to estimate the power consumption at the design stage of the semiconductor integrated circuit because the power consumption affects the chip area and the energy saving performance. As a method of estimating the power consumption of a semiconductor integrated circuit at the design stage, a method using simulation is known.

  In the method using simulation, a simulation program for executing simulation of the actual operation of the semiconductor integrated circuit, circuit information describing information on the circuit configuration of the semiconductor integrated circuit, and an input for actually operating the semiconductor integrated circuit A simulation pattern describing the pattern of the signal is used. In such simulation, the apparatus that executes the simulation records the number of transitions of the state of the observation node determined in advance in the semiconductor integrated circuit on the storage medium as a simulation result. The apparatus that executes the simulation estimates the power consumption of the semiconductor integrated circuit to be designed based on the number of transitions of the recorded state of the node (ie, the number of toggles).

  In the method using simulation, in order to estimate the power consumption, information of the transition of the state of the observation node of the semiconductor integrated circuit is required. However, in the conventional simulation result, in general, in addition to the information on the transition of the state of the observation node, information not necessary for the estimation of power consumption, such as the analog value of the potential of the observation node, skew and through information, etc. have. In the conventional method using simulation, the device that executes the simulation increases its execution time in order to calculate unnecessary information for the estimation of the power consumption. Since the execution time of simulation is proportional to the number of observation nodes, an increase in the execution time of simulation is a problem that can not be ignored when estimating the power consumption of a semiconductor integrated circuit with a large number of observation nodes.

  On the other hand, it is important for product evaluation to actually measure the power consumption of a semiconductor integrated circuit. Semiconductor integrated circuits have components (i.e., modules) for realizing various functions, and it is required to measure the power consumption of each module. The number of toggles of the output of the circuit to be measured in order to actually measure the power consumption of the semiconductor integrated circuit for each module while suppressing an increase in the execution time of the simulation for estimating the power consumption of such a semiconductor integrated circuit. There is a power consumption evaluation method that records

  For example, Patent Document 1 below discloses a power consumption evaluation method of a power consumption measurement target circuit. The power consumption evaluation method disclosed in Patent Document 1 below simulates a power consumption measurement target circuit and a field programmable array in which a toggle detection circuit for detecting the number of toggles of circuit elements of the power consumption measurement target circuit is configured. A pattern is input, and power consumption of the power consumption measurement target circuit is obtained based on the number of toggles detected by the toggle detection circuit after completion of the simulation.

JP 2002-288257 A

  The conventional circuit disclosed in the above-mentioned Patent Document 1 records the number of toggles of the circuit to be measured, but it is necessary to record the number of toggles of all nodes of the circuit to be measured. Still had challenges. In addition, the conventional circuit disclosed in Patent Document 1 efficiently controls power consumption by controlling a semiconductor integrated circuit incorporating a toggle detection circuit or a field programmable array including a toggle detection circuit. In order to calculate the number of toggles to be measured, no consideration has been made. In addition, since the conventional circuit disclosed in Patent Document 1 requires a toggle detection circuit for each node of the measurement target circuit, when the toggle detection circuit is incorporated in a semiconductor integrated circuit, the chip area increases. Had.

  Therefore, an object of the present invention is to provide a semiconductor integrated circuit capable of efficiently estimating power consumption while suppressing an increase in chip area.

  Another object of the present invention is to provide a semiconductor integrated circuit capable of efficiently measuring the power consumption for each module.

  Another object of the present invention is to provide an estimation device capable of efficiently estimating the power consumption of a semiconductor integrated circuit.

  Another object of the present invention is to provide a semiconductor design device capable of designing a semiconductor integrated circuit that efficiently measures power consumption for each module.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  That is, the present invention according to one aspect includes at least one shift circuit that receives a first signal from a first combinational circuit and outputs a second signal based on the first signal to a second combinational circuit; A clock generation circuit which generates a predetermined enable signal and a predetermined shift clock based on a predetermined system clock and outputs the generated predetermined enable signal and the predetermined shift clock to the shift circuit; One shift circuit has a plurality of output control circuits each comprising a pair of selection circuits and a sequential circuit, and the plurality of output control circuits are configured such that the output from the sequential circuit of one of the output control circuits is the other output The clock generation circuit is connected in a ring shape so as to be input to the selection circuit of the control circuit, and the clock generation circuit A first state for a first period of time during which the predetermined system clock alternates a number of times corresponding to a multiplication of the number of second, and a second state necessary to capture the second signal after the first period of time A third enable signal is generated so as to be in the second state over a period and output to the corresponding selection circuit, and the predetermined system clock is alternated once in addition to the first period. The semiconductor integrated circuit generates the predetermined shift clock so as to alternate over a period and outputs the shift clock to the corresponding sequential circuit.

  Here, the selection circuit in each of the plurality of output control circuits may output the first signal or the sequential circuit in the output control circuit in the previous stage of the one output control circuit according to the predetermined enable signal. One of the two signals is output as a selection signal to the corresponding sequential circuit, and the sequential circuit in each of the plurality of output control circuits is configured to output the second corresponding selection signal in accordance with the predetermined shift clock. It may be output as a signal of

  The semiconductor integrated circuit may include a plurality of shift circuits, and each of the plurality of shift circuits may be configured to have the same number of sequential circuits.

  Furthermore, according to another aspect of the present invention, there is provided a measuring method for measuring the power consumption of a semiconductor integrated circuit under the control of a controller, the method comprising at least one shift having a plurality of sequential circuits connected in a ring. Providing a semiconductor integrated circuit including a circuit, inputting a test pattern to the semiconductor integrated circuit, acquiring an output state of each of the sequential circuits corresponding to a plurality of states of the test pattern, and acquiring Calculating the power consumption of the semiconductor integrated circuit based on the state of the output of each sequential circuit, and acquiring the state of the output of each sequential circuit, the operating frequency of the semiconductor integrated circuit To a first frequency, capturing an output of each sequential circuit in the at least one shift circuit, and an operating frequency of the semiconductor integrated circuit Setting a second frequency higher than the first frequency, acquiring the state of the output of one of the sequential circuits in the at least one shift circuit, and further setting each of the sequential circuits in the at least one shift circuit It is a measuring method including repeating the number of times corresponding to the multiplication of the number of sequential circuits in the shift circuit to repeat the shift of the state of the output to the sequential circuit of the next stage.

  Furthermore, according to another aspect of the present invention, there is provided a measuring device for measuring the power consumption of a semiconductor integrated circuit, comprising: a control device having at least a memory and a processor, the control device comprising a plurality of annularly connected devices. A semiconductor integrated circuit including at least one shift circuit having a sequential circuit is disposed at a predetermined position, a test pattern is input to the semiconductor integrated circuit, and the operation of the semiconductor integrated circuit with respect to a plurality of states of the test pattern. The frequency is set to a first frequency, the output of each sequential circuit in the at least one shift circuit is captured, the operating frequency of the semiconductor integrated circuit is set to a second frequency higher than the first frequency, Obtaining the state of the output of one of said sequential circuits in one shift circuit, and The output of the sequential circuit is repeated by shifting the state of the output of each sequential circuit to the sequential circuit of the next stage by the number of times corresponding to the multiplication of the number of sequential circuits in the shift circuit by one. The measurement device is configured to calculate the power consumption of the semiconductor integrated circuit based on the state of

  Furthermore, according to another aspect of the present invention, there is provided a semiconductor design apparatus for designing a semiconductor integrated circuit model, comprising: a processor; and a memory capable of storing a predetermined design program, and executing the predetermined program Under the control of the processor, based on the attributes assigned to each module, it is determined whether there is a module for which the power consumption should be separately estimated, and the module which should individually perform the power consumption estimation If it is determined that there is, the sequential circuit model for the module is extracted, a shift circuit model corresponding to the extracted sequential circuit model is generated, and the number of sequential circuit models corresponding to each of the generated shift circuit models Generating a sequential circuit model in at least one of the shift circuit models such that If it is determined that there is no module that individually estimates the shift circuit model, a shift circuit corresponding to the sequential circuit model is generated, and the number of sequential circuit models corresponding to each of the generated shift circuit models matches. The semiconductor design apparatus generates a sequential circuit model in at least one of the shift circuit models.

  Furthermore, according to another aspect of the present invention, there is provided a semiconductor design method implemented by a semiconductor design apparatus for designing a semiconductor integrated circuit model, wherein power consumption is estimated separately based on the attributes assigned to each module. If it is determined that there is a module to be performed, and if it is determined that there is a module to separately estimate the power consumption, a sequential circuit model for the module is extracted, and the extracted sequential circuit model is corresponded Generating a shift circuit model, generating a sequential circuit model in at least one of the shift circuit models such that the number of sequential circuit models corresponding to each of the generated shift circuit models matches; If it is determined that there is no module to estimate power consumption separately, Generating a corresponding shift circuit model, and further generating a sequential circuit model in at least one of the shift circuit models such that the number of sequential circuit models corresponding to each of the generated shift circuit models matches. , And a semiconductor design method.

  Further, according to another aspect of the present invention, there is provided a program for estimating the power consumption of a semiconductor integrated circuit, the program receiving a first signal from a first combinational circuit model in a processor of an estimation device, A function of forming at least one shift circuit model for outputting a second signal based on the first signal to a second combinational circuit model, and a predetermined enable signal and a predetermined shift clock based on a predetermined system clock And at least one shift circuit model is configured to implement a function of generating and generating a clock generation circuit model that generates the predetermined enable signal and the predetermined shift clock thus generated to the shift circuit model. A plurality of output control circuit models each comprising a pair of selection circuit models and a sequential circuit model; An output control circuit model of the clock generation circuit is connected in a ring so that an output from the sequential circuit model of one of the output control circuit models is input to the selection circuit model of the other output control circuit model, The function of forming a model is in a first state for a first period during which the predetermined system clock alternates a number of times corresponding to the multiplication of the number of sequential circuit models in the at least one shift circuit model. A function of generating the predetermined enable signal to be in a second state for a second period necessary to capture the second signal after a period of time, and outputting to the corresponding selection circuit model And the predetermined period is to alternate during a third period in which the predetermined system clock alternates once in addition to the first period. Generating a shift clock, it includes a function of outputting to a corresponding said sequential circuit model, and a program.

  Furthermore, according to another aspect of the present invention, there is provided an estimation method for estimating power consumption of a semiconductor integrated circuit model, the estimation method comprising: at least one shift circuit model having a plurality of sequential circuit models connected in a ring. Acquiring a semiconductor integrated circuit model, inputting a simulation pattern to the semiconductor integrated circuit model, acquiring an output state of a sequential circuit model corresponding to a plurality of states of the simulation pattern, and acquiring Calculating the power consumption of the semiconductor integrated circuit model based on the state of the output of the sequential circuit model, and obtaining the state comprises setting the operating frequency of the semiconductor integrated circuit model to a first frequency. Setting each of the sequential circuit models in the at least one shift circuit model. Capturing, setting the operating frequency of the semiconductor integrated circuit model to a second frequency higher than the first frequency, and the state of the output of one of the sequential circuit models in the at least one shift circuit model. And shifting the state of the output of each sequential circuit model in the at least one shift circuit model to the sequential circuit model of the next stage corresponds to the multiplication of the number of sequential circuit models in the shift circuit model. It is an estimation method including repeating only the number of times added by one to.

  Furthermore, the present invention according to another aspect is an estimation device for estimating the power consumption of a semiconductor integrated circuit model, comprising: an execution device including at least a memory and a processor; and a storage device storing a simulation pattern. The execution device acquires at least one shift circuit model having a plurality of sequential circuit models connected in a ring, inputs a simulation pattern to the semiconductor integrated circuit model, and performs the plurality of states of the simulation pattern. The operating frequency of the semiconductor integrated circuit model is set to a first frequency, the output of each sequential circuit model in the at least one shift circuit model is captured, and the operating frequency of the semiconductor integrated circuit model is higher than the first frequency Setting the second frequency to the at least one shift circuit In the shift circuit model, obtaining the state of the output of one of the sequential circuit models in the loop and shifting the state of the output of each sequential circuit model in the at least one shift circuit model to the sequential circuit in the next stage It is configured to calculate the power consumption of the semiconductor integrated circuit model based on the acquired output state of the sequential circuit model by repeating the number of times corresponding to the multiplication of the number of the sequential circuit model and adding it by one. Is an estimate device.

  According to the present invention, the semiconductor integrated circuit can efficiently estimate the power consumption while suppressing an increase in the chip area.

  Further, according to the present invention, the semiconductor integrated circuit can efficiently measure the power consumption for each module.

  Also, according to the present invention, the estimation device can estimate the power consumption of the semiconductor integrated circuit efficiently.

  Further, according to the present invention, the semiconductor design device can design a semiconductor integrated circuit capable of efficiently measuring the power consumption for each module.

  Other technical features, objects, effects, and advantages of the present invention will be made clear by the following embodiments described with reference to the attached drawings.

FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention. It is a figure showing an example of composition of a clock generation circuit of a semiconductor integrated circuit concerning one embodiment of the present invention. It is a figure showing an example of composition of a shift circuit of a semiconductor integrated circuit concerning one embodiment of the present invention. It is a figure which shows the other example of a structure of the shift circuit of the semiconductor integrated circuit which concerns on one Embodiment of this invention. It is a figure which shows the other example of a structure of the shift circuit of the semiconductor integrated circuit which concerns on one Embodiment of this invention. 5 is a timing chart of various signals in a test mode of the semiconductor integrated circuit according to an embodiment of the present invention. FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor measurement system according to an embodiment of the present invention. It is a flowchart which shows roughly the operation | movement which the semiconductor measuring device which concerns on one Embodiment of this invention measures the power consumption of a semiconductor integrated circuit. It is a figure showing an example of the schematic structure of the semiconductor design device concerning one embodiment of the present invention. It is a conceptual diagram for demonstrating an example of the memory content of the memory module of the semiconductor design apparatus which concerns on one Embodiment of this invention. It is a flowchart which shows roughly the operation | movement at the time of the semiconductor design apparatus which concerns on one Embodiment of this invention designing a semiconductor integrated circuit. It is a flowchart which shows roughly operation | movement of the simulation which the semiconductor design apparatus which concerns on one Embodiment of this invention estimates the power consumption of a virtual semiconductor integrated circuit.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a view showing an example of a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit 10 according to the present embodiment includes, for example, a combination circuit 11, a control circuit 12, a clock generation circuit 13, a plurality of shift circuits 14, and a plurality of selection circuits 15. It comprises.

  The combinational circuit 11 is a logic circuit that does not include a sequential circuit such as a flip flop. The combinational circuit 11 (1) is provided on the input side of the semiconductor integrated circuit 10, performs a logical operation on the input signal IN input from the outside, and outputs the signal to the plurality of shift circuits 14 as the data input signal DIN. Do. Specifically, the combinational circuit 11 (1) performs a logical operation on the input signals IN (1) to IN (m) input from the outside, and shifts the signals as the data input signals DIN1 to DINn. 1) to the data terminal d of 14 (n). Here, the value n indicates the number of shift circuits 14 provided in the semiconductor integrated circuit 10, and the value m indicates the number of signals of the input signal IN.

  Further, the combinational circuit 11 (2) is provided on the output side of the semiconductor integrated circuit 10, performs a logical operation on the data output signal DOUT output from the plurality of shift circuits 14, and generates a plurality of such signals as the user signal USR. To the selection circuit 15 of FIG. Specifically, combinational circuit 11 (2) performs a logic operation on data output signals DOUT1 to DOUTn outputted from shift circuits 14 (1) to 14 (n) and outputs user signals USR (1) to USR ( The signal is output to the input terminals A0 of the selection circuits 15 (1) to 15 (n) as n). In this example, the user signal USR is output from the combinational circuit 11 (2), but is not limited to this. The user signal USR may be output from the combinational circuit 11 (1). It may be output from the circuit.

  Control circuit 12 controls on / off of the test mode of semiconductor integrated circuit 10 in accordance with mode signal MODE externally inputted through mode terminal mode, and generates system clock CLK, and the clock is generated by each component. Output to Specifically, the control circuit 12 sets the state of the test control signal CT_TST to the "test mode" when the mode signal MODE received from the outside via the mode terminal Mode indicates the "test mode". On the other hand, when the mode signal MODE received from the outside via the mode terminal Mode indicates the "normal mode", the control circuit 12 sets the state of the test control signal CT_TST to the "normal mode". Further, the control circuit 12 generates a system clock CLK, outputs the clock to the clock generation circuit 13, and outputs the test control signal CT_TST to the clock generation circuit 13 and the selection terminal SL of the selection circuit 15.

  The clock generation circuit 13 generates and outputs the shift clock SF_CLK and the enable signal ENA according to the system clock CLK output from the control circuit 12 and the state “test mode” or “normal mode” of the test control signal CT_TST. Specifically, the clock generation circuit 13 determines the state of the test control signal CT_TST output from the control circuit 12. When the clock generation circuit 13 determines that the test control signal CT_TST is in the “test mode”, the enable signal ENA takes the “capture mode” or the “shift mode” according to the count count of the system clock CLK, and the enable signal. And a shift clock SF_CLK according to ENA. On the other hand, when the clock generation circuit 13 determines that the test control signal CT_TST is in the “normal mode”, the clock generation circuit 13 generates the enable signal ENA always in the “0” state and the shift clock SF_CLK equal to the system clock CLK. Do. Then, the clock generation circuit 13 outputs the shift clock SF_CLK to the clock terminal ck of the shift circuit 14 and the enable signal ENA to the enable terminal ena of the shift circuit 14 and the input terminal A1 of the selection circuit 15 (n + 1).

  A plurality (n) of shift circuits 14 are provided between combinational circuit 11 (1) and combinational circuit 11 (2) of semiconductor integrated circuit 10, and shift circuit 14 is based on shift clock SF_CLK output from clock generation circuit 13. A signal according to the state of the enable signal ENA output from the clock generation circuit 13 is output. Specifically, shift circuit 14 determines the state of enable signal ENA output from clock generation circuit 13 respectively. When shift circuit 14 determines that the state of enable signal ENA is "capture mode", data input signal DIN output from combinational circuit 11 (1) is output as data output signal DOUT based on shift clock SF_CLK. , And output to the combinational circuit 11 (2). On the other hand, shift circuit 14 selects shift signal SFT from shift terminal sfo based on shift clock SF_CLK output from clock generation circuit 13 when judging that the state of enable signal ENA is “shift mode”. It outputs to the circuit 15.

  Although shift circuit 14 is provided to connect combinational circuits 11 (1) and 11 (2) in semiconductor integrated circuit 10 in the same figure, at least one of combinational circuits 11 (1) and 11 (2) is provided. The shift circuit 14 may be provided for each module provided with one or more and at least one or more sequential circuits. In such a case, the outputs of the shift circuit 14 indicate the states of the outputs of the modules, respectively.

  The plurality of selection circuits 15 (1) to 15 (n + 1) are, for example, multiplexers. The plurality of selection circuits 15 (1) to 15 (n + 1) receive user signals USR (1) to (n + 1) or a plurality of user signals output from combination circuit 11 (2) according to test control signal CT_TST output from control circuit 12. The shift signal SFT output from the shift circuits 14 (1) to 14 (n) is selected, and the selection result is output as the output signal OUT.

  Specifically, when selection circuit 15 (i) determines that the state of test control signal CT_TST output from control circuit 12 is "normal mode", the user signal output from combinational circuit 11 (2) The USR (i) is selected, and the selection result is output as an output signal OUT (i). On the other hand, when the selection circuit 15 (i) determines that the state of the test control signal CT_TST output from the control circuit 12 is in the "test mode", the shift signal SFT (i) output from the shift circuit 14 (i) And the selection result is output as an output signal OUT (i). Here, i is a positive integer of 1 or more and n or less.

  Further, when it is determined that the state of the test control signal CT_TST output from the control circuit 12 is in the “normal mode”, the selection circuit 15 (n + 1) at the last stage outputs the user signal output from the combinational circuit 11 (2) USR (n + 1) is selected, and the selection result is output as an output signal OUT (i). On the other hand, when it is determined that the state of test control signal CT_TST output from control circuit 12 is in the “test mode”, selection circuit 15 (n + 1) at the final stage outputs enable signal ENA output from clock generation circuit 13 The selected result is output as an output signal OUT (i). In the test mode, the output signal OUT (n + 1) output from the selection circuit 15 (n + 1) of the last stage indicates that the semiconductor integrated circuit 10 is in the test mode.

  The semiconductor integrated circuit 10 configured as described above receives the input signal IN input from the outside according to the test control signal CT_TST output from the control circuit 12 into the combination circuit 11 (1), the plurality of shift circuits 14 (1 ) Through 14 (n) and the combinational circuit 11 (2), or output the state of the outputs of the plurality of shift circuits 14 (1) through 14 (n) as the output signal OUT. Do.

  FIG. 2 is a diagram showing an example of the configuration of a clock generation circuit of a semiconductor integrated circuit according to an embodiment of the present invention. As shown in the figure, the clock generation circuit 13 is configured to include a counter 131, AND circuits 132 and 133, and a selection circuit 134.

  The counter 131 generates an output control signal CNT_O and a clock generation signal CKG_O from the system clock CLK output from the control circuit 12, outputs the output control signal CNT_O to the AND circuit 132, and outputs the clock generation signal CKG_O to the AND circuit 133. Output each.

  Specifically, the counter 131 becomes "1" while the system clock CLK alternates by the number of times (for example, 1) of the number of sequential circuits 142 described later included in the shift circuit 14 and the semiconductor integrated circuit 10 An output control signal CNT_O which is “0” during a period necessary to capture the state of the output of the shift circuit 14 is generated, and the signal is output to the AND circuit 132. Furthermore, the counter 131 becomes “1” while the system clock CLK alternates once in addition to the period when the output control signal CNT_O is “1”, and is necessary for capturing the state of the output of the shift circuit 14 thereafter. A clock generation signal CKG_O which is “0” which is a short period only during a period when the system clock CLK alternates once more than the period is generated, and the signal is output to the AND circuit 133.

  In this example, the counter 131 is “1” while the system clock CLK alternates by the number of times (for example, 1) of the number of sequential circuits 142 included in the shift circuit 14; Instead, the counter 131 may be "1" while the system clock CLK alternates by an arbitrary multiple such as twice or three times the number of sequential circuits 142 included in the shift circuit 14.

  The AND circuit 132 is, for example, an AND gate. The AND circuit 132 performs an AND operation on the output control signal CNT_O and the test control signal CT_TST, and outputs the operation result as an enable signal ENA. Specifically, the AND circuit 132 performs an AND operation on the output control signal CNT_O output from the counter 131 and the test control signal CT_TST output from the control circuit 12, and the operation result is an enable signal. As ENA, it outputs to the enable terminal ena of the shift circuit 14 and the input terminal A1 of the selection circuit 15 (n + 1). The enable signal ENA indicates the "capture mode" when the state is "0" and indicates the "shift mode" when the state is "1".

  The AND circuit 133 is, for example, an AND gate. The AND circuit 133 performs an AND operation on the clock generation signal CKG_O and the system clock CLK, and outputs the operation result to the input terminal A1 of the selection circuit 134. Specifically, the AND circuit 133 performs an AND operation on the clock generation signal CKG_O output from the counter 131 and the system clock CLK output from the control circuit 12, and selects the operation result from the selection circuit 134. Output to the input terminal A1.

  The selection circuit 134 is, for example, a multiplexer. The selection circuit 134 selects the output from the AND circuit 133 or the system clock CLK according to the state of the test control signal CT_TST, and outputs the selection result as the shift clock SF_CLK. Specifically, selection circuit 134 determines the state of test control signal CT_TST output from control circuit 12. If the selection circuit 134 determines that the state of the control signal CT_TST is in the “normal mode”, the selection circuit 134 selects the system clock CLK output from the control circuit 12 and uses the selection result as the shift clock SF_CLK. Output to ck. On the other hand, when the selection circuit 134 determines that the state of the control signal CT_TST is in the “test mode”, the selection circuit 134 selects the output from the AND circuit 133 and uses the selection result as the shift clock SF_CLK. Output to

  While the test control signal CT_TST indicates the “test mode”, the clock generation circuit 13 configured as described above “1” while the system clock CLK alternates by the number of times of multiplication of the number of sequential circuits 142 included in the shift circuit 14. And during a period necessary to capture the state of the output of the shift circuit 14, the enable signal ENA that is “0” and the period when the enable signal ENA is “1”, for one system clock CLK Generating an alternating shift clock SF_CLK and outputting the two signals;

  FIG. 3A is a view showing an example of the configuration of a shift circuit of a semiconductor integrated circuit according to an embodiment of the present invention. As shown in the drawing, the shift circuit 14 (i) is configured to include selection circuits 141 (1) to 141 (x) and sequential circuits 142 (1) to 142 (x). Here, the value x indicates the number of selection circuits 141 and sequential circuits 142 provided in the shift circuit 14. The selection circuit 141 and the sequential circuit 142 form a pair to form the output control circuit 140 (for example, a broken line in the figure). Each of the plurality of output control circuits 140 is connected in a ring so that a signal output from its own sequential circuit 142 is input to the selection circuit 141 of the output control circuit 140 of the next stage.

  The selection circuit 141 is, for example, a multiplexer. Selection circuit 141 outputs a data input signal DINi output from combinational circuit 11 (1) or a data output signal output from sequential circuit 142 at the front stage of corresponding sequential circuit 142 in accordance with enable signal ENA output from clock generation circuit 13. DOUTi is selected, and the selection result is output to the sequential circuit 142.

  Specifically, the selection circuit 141 (s) determines the state of the enable signal ENA output from the clock generation circuit 13. If selection circuit 141 (s) determines that the state of enable signal ENA is in the “capture mode”, selection circuit 141 (s) selects data input signal DINi (s) output from combinational circuit 11 (1), and selects the selected result. It outputs to the data input terminal D of the sequential circuit 142 (s). On the other hand, when it is determined that the state of the enable signal ENA is in the “shift mode”, the selection circuit 141 (s) selects the data output signal DOUTi (s−1) output from the sequential circuit 142 (s−1). And outputs the selection result to the data input terminal D of the sequential circuit 142 (s). In addition, when it is determined that the state of the enable signal ENA is in the “shift mode”, the selection circuit 141 (1) at the first stage determines the data output signal DOUTi (x) output from the sequential circuit 142 (x) at the last stage. Are selected, and the selection result is output to the data input terminal D of the sequential circuit 142 (1). Here, s is a positive integer of 1 or more and x or less.

  The sequential circuit 142 is, for example, a D-type flip flop. The sequential circuit 142 sets the selection result output from the selection circuit 141 as the data output signal DOUTi based on the shift clock SF_CLK output from the clock generation circuit 13 and the combination circuit 11 (2) and the selection circuit 141 of the next stage. Output to input terminal A1.

  Specifically, sequential circuit 142 (s) combines the selection result output from selection circuit 141 (s) as data output signal DOUTi (s) based on shift clock SF_CLK output from clock generation circuit 13. It outputs to the circuit 11 (2) and the input terminal A1 of the selection circuit 141 (s + 1). Further, sequential circuit 142 (x) at the final stage combines the selection result output from selection circuit 141 (s) as data output signal DOUTi (s) based on shift clock SF_CLK output from clock generation circuit 13. The selection result is output to the input terminal A1 of the selection circuit 15 (i) as the shift signal SFT, which is output to the circuit 11 (2) and the input terminal A1 of the selection circuit 141 (1).

  FIG. 3B is a view showing another example of the configuration of the shift circuit of the semiconductor integrated circuit according to the embodiment of the present invention. As shown in the figure, the shift circuit 14 'is configured to further include an AND circuit 143 and a dummy sequential circuit 144 in the shift circuit 14 of FIG. 3A. Since the selection circuit 141 and the sequential circuit 142 in the figure are the same as those described in FIG. 3A, the description thereof is omitted.

  The AND circuit 143 is, for example, an AND gate. The AND circuit 143 performs an AND operation on the output from the preceding sequential circuit 142 or 144 and the enable signal ENA, and outputs the operation result to the corresponding sequential circuit 144. Specifically, AND circuit 143 (s) has a logic with respect to data output signal DOUTi (s + 1) output from sequential circuit 142 or 144 in the previous stage and enable signal ENA output from clock generation circuit 13. A product operation is performed, and the operation result is output to the data input terminal D of the corresponding sequential circuit 144 (s). As described above, the “capture mode” indicates the state “0” in the logical operation, and the “shift mode” indicates the state “1” in the logical operation.

  The sequential circuit 144 is, for example, a D-type flip flop. The sequential circuit 144 outputs the output from the corresponding AND circuit 143 as the data output signal DOUTi to the combination circuit 11 (2) and the AND circuit 143 of the next stage based on the shift clock SF_CLK. Specifically, sequential circuit 144 (s) combines the output from corresponding AND circuit 143 (s) as data output signal DOUTi (s + 2) based on shift clock SF_CLK output from clock generation circuit 13. It outputs to the circuit 11 (2) and the AND circuit 143 (s + 1) of the next stage.

  FIG. 3C is a diagram showing another example of the configuration of the shift circuit of the semiconductor integrated circuit according to one embodiment of the present invention. As shown in the figure, the shift circuit 14 ′ ′ is configured to further include an AND circuit 145 in the shift circuit 14 ′ of FIG. 3B. Further, the shift circuit 14 ′ ′ includes a sequential circuit 144 ′ in place of the sequential circuit 144 in the shift circuit 14 ′ of FIG. 3B. Since the selection circuit 141, the sequential circuit 142, and the AND circuit 143 in the same figure are the same as those described in FIG. 3B, the description thereof is omitted.

  The AND circuit 145 is, for example, an AND gate. The AND circuit 145 performs an AND operation on the shift clock SF_CLK output from the clock generation circuit 13 and the test control signal CT_TST output from the control circuit 12, and outputs the operation result to the clock of the sequential circuit 144 '. Output to the terminal CK.

  The sequential circuit 144 'is, for example, a D-type flip flop. Based on the output from the AND circuit 145, the sequential circuit 144 'outputs the output from the corresponding AND circuit 143 as the data output signal DOUTi to the combination circuit 11 (2) and the AND circuit 143 at the next stage. Specifically, based on the output from AND circuit 145, sequential circuit 144 ′ (s) sets the output from corresponding AND circuit 143 (s) as data output signal DOUTi (s + 2). 2) and the next stage AND circuit 143 (s + 1).

  Shift circuit 14 configured as described above receives data input signal DINi output from combinational circuit 11 (1) according to the state "capture mode" or "shift mode" of enable signal ENA output from clock generation circuit 13. Is output to the combinational circuit 11 (2) through the selection circuit 141 and the sequential circuit 142, or the selection circuit 141 and the AND circuit 143 which are connected in a chain state of the state of the outputs of the sequential circuits 142 and 144; Output from the final stage sequential circuit 144 via the sequential circuits 142 and 144.

  FIG. 4 is a timing chart of various signals in a test mode of the semiconductor integrated circuit according to the embodiment of the present invention. In the same figure, timings at which the system clock CLK alternates are defined as times t501 to t513. Further, it is assumed that the control circuit 12 outputs the control signal CT_TST indicating the “test mode”. Further, it is assumed that the shift circuit 14 of the semiconductor integrated circuit 10 has three sequential circuits 142. Further, it is assumed that a period necessary to capture the state of the output of the shift circuit 14 is four clocks of the system clock CLK.

  The clock generation circuit 13 of the semiconductor integrated circuit 10 generates and outputs a clock generation signal CKG_O and an output control signal CNT_O based on the system clock CLK output from the control circuit 12. The clock generation circuit 13 becomes “0” during a period required to capture the state of the output of the shift circuit 14 (that is, during a period from time t501 to t505), and multiplies the number of sequential circuits 142 included in the shift circuit 14. An output control signal CNT_O which is "1" in a period in which the system clock CLK alternates (that is, a period from time t505 to t508) the number of times (in this example, 1) is generated, and the logical product with the test control signal CT_TST And output as an enable signal ENA. The clock generation circuit 13 generates the output control signal CNT_O in the same manner as at times t501 to t507 after time t508.

  In addition, the clock generation circuit 13 performs a period (that is, a period from time t502 to t505) shorter by one clock of the system clock CLK than a period necessary for capturing the state of the output of the shift circuit 14 of the semiconductor integrated circuit 10. The clock generation signal CKG_O is generated to be “0” and to be “1” for a period (that is, a period from time t505 to t509) longer by one clock of the system clock CLK than the period “1” of the output control signal CNT_O. The clock generation circuit 13 generates the clock generation signal CKG_O after time t510 in the same manner as at times t502 to t509.

  Also, the clock generation circuit 13 generates the shift clock SF_CLK alternating while the clock generation signal CKG_O is “1” based on the clock generation signal CKG_O generated by itself. The clock generation circuit 13 stops the alternation of the shift clock SF_CLK at time t502, starts the alternation of the clock at time t505, and stops the alternation of the clock at time t509. After time t510, the clock generation circuit 13 repeats the stop of the alternation of the shift clock SF_CLK and the start of the alternation in the same manner as the operation from time t502 to t509.

  Shift circuit 14 is in the state of data input signal DIN output from combinational circuit 11 (1) according to enable signal ENA (the same as output control signal CNT_O in this example) output from clock generation circuit 13, or a sequential circuit The state 142 is output as the data output signal DOUTi. Specifically, shift circuit 14 outputs the state of data input signal DIN output from combinational circuit 11 (1) at times t501 to t505, and outputs the state of sequential circuit 142 at times t506 to t508, At t509 to t512, the state of the data input signal DIN output from the combinational circuit 11 (1) is output.

  Sequential circuits 142 (1) to 142 (3) are output from sequential circuit 142 at the previous or last stage according to state “1” of output control signal CNT_O at time t 501 based on shift clock SF_CLK. Output DA1, DB1 and DC1. Subsequently, at time t505, sequential circuits 142 (1) to 142 (3) are output from combinational circuit 11 (1) based on shift clock SF_CLK in accordance with state "0" of output control signal CNT_O. Capture states DA2, DB2 and DC2.

  Next, at time t506, sequential circuits 142 (1) to 142 (3) output from sequential circuit 142 of the previous or last stage based on shift clock SF_CLK according to the state "1" of output control signal CNT_O. Output states DC2, DA2 and DB2. Subsequently, at time t507, sequential circuits 142 (1) to 142 (3) output from sequential circuit 142 at the previous or last stage based on shift clock SF_CLK according to state "1" of output control signal CNT_O. State DB2, DC2 and DA2 are output. Further, sequential circuits 142 (1) to 142 (3) are output from sequential circuit 142 at the previous or last stage based on shift clock SF_CLK at time t508 according to the state "1" of output control signal CNT_O. Output state DA2, DB2 and DC2. Then, sequential circuits 142 (1) to 142 (3) are output from combinational circuit 11 (1) at time t 512 based on shift clock SF_CLK according to the state “0” of output control signal CNT_O. Capture DA3, DB3 and DC3.

  As described above, the semiconductor integrated circuit 10 captures data output from the combinational circuit 11 (1) at the actual operating frequency, and multiplies the number of sequential circuits 142 included in the shift circuit 14 by the frequency of the system clock CLK + 1 The states of sequential circuits 142 (1) through 142 (3) are shifted. Thus, semiconductor integrated circuit 10 makes the state after shifting the outputs of sequential circuits 142 (1) to 142 (3) equal to the state before shifting the outputs of sequential circuits 142 (1) to 142 (3). Output of the sequential circuits 142 (1) to 142 (3) to the outside because the data output from the combinational circuit 11 (1) can be captured next without additional processing. can do.

  In the semiconductor integrated circuit 10, the clock generation circuit 13, the selection circuit 141 of the shift circuit 14 and the selection circuit 15 are added to the existing semiconductor integrated circuit in the estimation of the power consumption. On the other hand, it is possible to estimate the power consumption by suppressing the increase of the chip area.

  FIG. 5 is a view showing an example of a schematic configuration of a semiconductor measurement system according to an embodiment of the present invention. As shown in the figure, a semiconductor measurement system 1 according to the present embodiment is configured to include a semiconductor integrated circuit 10 and a semiconductor measurement device 20. Here, since the semiconductor integrated circuit 10 is the same as that described in FIG. 1, the description of the details of the configuration will be omitted.

  The semiconductor integrated circuit 10 performs the processing described with reference to FIGS. 1 to 4 on input signals IN (1) to IN (m) input from the outside, and outputs semiconductors as output signals OUT (1) to OUT (n). Output to the measuring device 20. The semiconductor integrated circuit 10 receives the input signal IN and the mode signal MODE from the semiconductor measurement device 20 and operates under the control of the semiconductor measurement device 20. In addition, semiconductor integrated circuit 10 has its own operation mode (for example, “test mode” and “in accordance with mode signal MODE indicating operation mode (for example,“ test mode ”and“ normal mode ”) input from semiconductor measurement device 20. Determine the "normal mode", "capture mode" and "shift mode").

  The semiconductor measuring device 20 is, for example, an LSI tester or an evaluation board. The semiconductor measurement device 20 controls the operation of the semiconductor integrated circuit 10 and controls the operation mode of the semiconductor integrated circuit 10. The semiconductor measurement device 20 includes, for example, a control device 21, a comparator 22, a toggle number calculation device 23, and a storage device 24. The storage device 24 stores, for example, a test program and test data.

  Control device 21 has a memory and a processor (not shown), determines an operation and an operation mode of semiconductor integrated circuit 10 in accordance with a test program read from storage device 24, and controls the operation and the operation mode. The input signal IN to be performed and the mode signal MODE are output to the semiconductor integrated circuit 10. Next, the control device 21 outputs the determination reference of each comparator 22 to each comparator 22 as an evaluation signal VAL. Then, the control device 21 measures the power consumption of the semiconductor integrated circuit 10 based on the number of toggles of the sequential circuit 142 of the semiconductor integrated circuit 10 calculated by the toggle number calculating device 23, and stores the measured power consumption value. Output to 24.

  The comparator 22 outputs the state of the output signal OUT output from the semiconductor integrated circuit 10 as the test signal TST to the toggle number calculating device 23 in accordance with the evaluation signal VAL output from the control device 21.

  The number of toggles calculation device 23 calculates the number of toggles of the sequential circuit 142 of each module of the semiconductor integrated circuit 10 based on the test signal TST output from the comparator 22 and the enable signal ENA output from the semiconductor integrated circuit 10. , The calculated result is output to the control device 21. Specifically, the toggle number calculating device 23 changes the state indicated by the test signals TST (1) to TST (n) output from the comparators 22 (1) to 22 (n) from "1" to "0", Or count the number of transitions from “0” to “1”. Next, the number-of-toggles calculating device 23 calculates the number of toggles of each module of the semiconductor integrated circuit 10 by totaling the counted number of times for each comparator 22, and sums the number of toggles of each module and the number of toggles ( That is, the toggle number of the entire semiconductor integrated circuit 10 is output to the control device 21 as the test signal TST.

  Semiconductor measurement system 1 configured as described above has “test mode” and “normal mode” which are operation modes of semiconductor integrated circuit 10, and a test pattern for controlling the operation of semiconductor integrated circuit 10 as input signal IN ( The states 1) to IN (m) are output to the semiconductor integrated circuit 10, and the states of the output signals OUT (1) to OUT (n + 1) output from the semiconductor integrated circuit 10 are determined. Thus, the semiconductor measurement system 1 calculates the number of toggles of the sequential circuit 142 of each module of the semiconductor integrated circuit 10, and based on the number of toggles, the power consumption of each module and the entire consumption of the semiconductor integrated circuit 10. Power can be measured efficiently.

  FIG. 6 is a flowchart schematically showing an operation of the semiconductor measurement device according to an embodiment of the present invention to measure the power consumption of the semiconductor integrated circuit. In the figure, first, the semiconductor measurement apparatus 20 arranges the semiconductor integrated circuit 10 whose power consumption is to be measured at a place where the measurement object of the semiconductor measurement system 1 is to be arranged (S601). Next, the semiconductor measurement device 20 acquires a test pattern from the storage device 24, and inputs the acquired test pattern to the semiconductor integrated circuit 10 in which the test pattern is arranged (S602). Subsequently, the semiconductor measurement device 20 sets the semiconductor integrated circuit 10 in the test mode (S603).

  The semiconductor integrated circuit 10 sets itself in the capture mode under the control of the semiconductor measurement device 20 (S604). Specifically, under the control of the semiconductor measurement device 20, the semiconductor integrated circuit 10 generates an enable signal ENA indicating a capture mode and a shift clock SF_CLK according to the enable signal ENA. While the semiconductor integrated circuit 10 is in the "capture mode", the semiconductor integrated circuit 10 operates at the actual operating frequency.

  The semiconductor measurement device 20 causes the shift circuit 14 of the semiconductor integrated circuit 10 to capture the data input signal DIN output from the combinational circuit 11 (1) of the semiconductor integrated circuit 10 (S605). Then, the semiconductor measurement device 20 sets the semiconductor integrated circuit 10 in the “shift mode” (S606). Specifically, semiconductor measuring device 20 transmits mode signal MODE. The semiconductor integrated circuit 10 generates an enable signal ENA indicating a shift mode and a shift clock SF_CLK according to the enable signal ENA under the control of the semiconductor measurement device 20. While the semiconductor integrated circuit 10 is in the "shift mode", the semiconductor integrated circuit 10 operates at the frequency of the system clock CLK.

  The semiconductor integrated circuit 10 shifts the state of the output of the sequential circuit 142 of the shift circuit 14 to the sequential circuit 142 of the next stage under the control of the semiconductor measuring device 20 and stores the state of the sequential circuit 142. The processing is repeated by the number of sequential circuits 142 included in the shift circuit 14 plus one (loop A: S607 to S609).

  More specifically, under the control of the semiconductor measurement device 20, the semiconductor integrated circuit 10 shifts the state of the output of the sequential circuit 142 of the shift circuit 14 to the sequential circuit 142 of the next stage once (S608). Next, the semiconductor measuring device 20 determines the state of the output output from the sequential circuit 142 at the last stage by the comparator 22 and outputs the determination result to the toggle number calculating device 23. The toggle number calculating device 23 records the state of the output output from the comparator 22 (S609).

  The semiconductor measurement device 20 determines whether the state of the sequential circuit 142 of the shift circuit 14 of the semiconductor integrated circuit 10 is stored with respect to the desired state of the test pattern (S610). If the semiconductor measurement device 20 determines that the state of the sequential circuit 142 of the shift circuit 14 of the semiconductor integrated circuit 10 is not stored with respect to the desired state of the test pattern (No in S610), the process returns to the process of step S604. . On the other hand, when the semiconductor measuring device 20 determines that the state of the sequential circuit 142 of the shift circuit 14 of the semiconductor integrated circuit 10 is stored with respect to the desired state of the test pattern (Yes in S610), the process proceeds to step S611. .

  The semiconductor measurement device 20 calculates the number of toggles of the semiconductor integrated circuit 10 by the toggle number calculation device 23 based on the result of the comparator 22 stored in the toggle number calculation device 23 (S611). Then, the semiconductor measuring device 20 calculates the power consumption by the control device 21 based on the number of toggles, stores the calculated value of the power consumption as the measurement result in the storage device 24 (S612), and the semiconductor integration is performed. The measurement of the power consumption of the circuit 10 is ended.

  As described above, the semiconductor integrated circuit 10 first operates in the capture mode under the control of the semiconductor measurement device 20, and captures data output from the combinational circuit 11 (1). Next, the semiconductor integrated circuit 10 operates in the shift mode under the control of the semiconductor measurement device 20 and shifts the state of the sequential circuit 142 by the number of the sequential circuits 142 included in the shift circuit 14 of the semiconductor integrated circuit 10. Thereby, the semiconductor integrated circuit 10 makes the state after the shift circuit 14 shifts the output of the sequential circuit 142 equal to the state before shifting the output of the sequential circuit 142 under the control of the semiconductor measuring device 20. The semiconductor integrated circuit 10 can capture data to be output next from the combinational circuit 11 (1) without performing additional processing under the control of the semiconductor measuring device 20, so the state of the sequential circuit 142 can be efficiently compared It can be output to 22.

  In addition, the semiconductor measuring device 20 processes the result for each comparator 22 to calculate the number of toggles for each module of the semiconductor integrated circuit 10 corresponding to each comparator 22, and based on the calculation result, the semiconductor integrated circuit 10 is Power consumption can be measured for each module.

  FIG. 7 is a diagram showing an example of a schematic configuration of a semiconductor design device according to an embodiment of the present invention. As shown in the figure, a semiconductor design device 700 according to the present embodiment is configured to include a processor module 702, a chipset 703, a memory module 704, a storage device 705, and an input / output device 706.

  Processor module 702 may include, but is not limited to, for example, a processor core, a microcontroller, a digital signal processor, and / or a combination thereof. Here, the term "processor core" is treated as having the same meaning as a processor (that is, a processing device) meaning a main processor, a CPU, an MPU or the like. Processor module 702 may include one or more levels of caching mechanisms.

  The chipset 703 includes a bridge with a bus connecting the processor module 702, the memory module 704, the storage device 705, the input / output device 706, and the like, and a circuit in which other components necessary to configure the computing device are integrated. . The chipset 703 is controlled by, for example, the processor module 702.

  Memory module 704 is typically a primary storage device comprised of volatile memory (eg, RAM), non-volatile memory (eg, ROM, flash memory, etc.) and / or combinations thereof. The memory module 704 typically holds all or part of a device driver, an operating system (OS) program, one or more programs and information necessary to execute various programs, and the like, and uses the processor module 702. To be served. The processor module 702, the chipset 703, and the memory module 704 constitute an execution device 701.

  The storage device 705 typically comprises a hard disk drive (HDD), an optical disk drive, a solid state device (SSD), or the like. The storage device 705 functions as a secondary storage device of the processor module 702, and stores an OS, various programs, execution results of various programs, and information necessary for executing various programs.

  The input / output device 706 is various peripheral interfaces, and is, for example, a keyboard, a mouse, a display, a printing device, a communication device, and the like. The input / output device 706 receives an input of information necessary for the semiconductor design device 700 to design the semiconductor integrated circuit 10, and outputs information of the semiconductor integrated circuit 10 designed by the semiconductor design device 700.

  In the semiconductor design apparatus 700 configured as described above, the processor module 702 designs the semiconductor integrated circuit 10 in accordance with the program stored in the memory module 704. The semiconductor design device 700 also functions as a device for estimating the power consumption of the semiconductor integrated circuit 10 in the design process or the semiconductor integrated circuit 10 which has already been designed. That is, according to the program stored in the memory module 704, the semiconductor design device 700 calculates the number of toggles of the design process or the already designed semiconductor integrated circuit 10 by the processor module 702, and based on the calculated number of toggles. The power consumption of the semiconductor integrated circuit 10 is estimated.

  FIG. 8 is a conceptual diagram for explaining an example of the storage content of the memory module of the semiconductor design device according to the embodiment of the present invention. In the figure, a circuit information generation program 7041 is a program for designing the semiconductor integrated circuit 10 on the semiconductor design device 700. The circuit configuration of the semiconductor integrated circuit 10 generated by the circuit information generation program 7041 is stored in the memory module 704 as circuit information 7043. The circuit information generation program 7041 may use the existing circuit information 7043 as a base for designing the semiconductor integrated circuit 10.

  The circuit information 7043 is data including part or all of the information on the circuit configuration of the semiconductor integrated circuit 10 generated by the circuit information generation program 7041. The circuit information 7043 is further updated in the process of designing the semiconductor integrated circuit 10 by the circuit information generation program 7041. The circuit information 7043 finally includes almost all of the circuit information 7043 of the semiconductor integrated circuit 10 described above according to the design of the semiconductor integrated circuit 10 by the circuit information generation program 7041. As described above, the circuit information 7043 including substantially all of the circuit information of the semiconductor integrated circuit 10 is stored in the storage medium (the memory module 704 in this example).

  The simulation pattern information 7044 is information of a virtual input signal used when performing simulation on the virtual semiconductor integrated circuit 10 indicated by the circuit information 7043 described above by the power consumption estimation program 7042. The simulation pattern information 7044 has information of a signal substantially equal to the input signal IN output to the virtual semiconductor integrated circuit 10 by the semiconductor design device 700 described above.

  The power consumption estimation program 7042 is a program for the semiconductor design device 700 to estimate the power consumption of the semiconductor integrated circuit 10 in the design process or in the design. The power consumption estimation program 7042 is executed by the processor module 702, calculates the number of toggles of the semiconductor integrated circuit 10 shown in the circuit information 7043 according to the circuit information 7043 and the simulation pattern information 7044, and based on the calculated number of toggles. The power consumption of the semiconductor integrated circuit 10 is estimated. Specifically, the power consumption estimation program 7042 is executed by the processor module 702, and inputs simulation pattern information 7044 which is a virtual input signal to the virtual semiconductor integrated circuit 10 shown in the circuit information 7043. Run simulations to estimate power consumption. The power consumption estimation program 7042 is executed by the processor module 702 to calculate the number of toggles of the virtual semiconductor integrated circuit 10 based on the state of the output of the sequential circuit 142 of the shift circuit 14 of the virtual semiconductor integrated circuit 10. The power consumption is estimated based on the calculated number of toggles, and the value of the power consumption is stored as a simulation result 7045.

  FIG. 9 is a flow chart schematically showing an operation when a semiconductor design device according to an embodiment of the present invention designs a semiconductor integrated circuit. In the figure, the semiconductor design device 700 first determines whether there is a module for which power consumption should be estimated separately (that is, the shift circuit 14 should be provided separately) in the semiconductor integrated circuit 10 (S901). More specifically, an attribute is assigned in advance to each module as to whether or not power consumption should be estimated separately, and the semiconductor design device 700 refers to the semiconductor integrated circuit by referring to the attribute of each module. It is determined whether or not there is a module in the circuit 10 whose power consumption should be individually estimated. When the semiconductor design device 700 determines that there is no module for which the power consumption should be estimated individually in the semiconductor integrated circuit 10 (No in S901), the virtual semiconductor integrated circuit 10 has a predetermined number of shift circuits 14. The virtual semiconductor integrated circuit 10 is divided, the shift circuit 14 is configured for all sequential circuits 142 (for example, D-type flip flops) of the virtual semiconductor integrated circuit 10 (S902), and the process proceeds to step S907. .

  On the other hand, when determining that there is a module for which power consumption should be estimated individually in the semiconductor integrated circuit 10 (Yes in S901), the semiconductor design device 700 determines modules to be separately provided (S903). Then, the sequential circuit 142 is extracted from a designated one of the determined modules (S904), and the shift circuit 14 is configured for the extracted sequential circuit 142 (S905).

  The semiconductor design device 700 determines whether or not the shift circuit 14 is configured for all of the modules to be separately provided with the shift circuit 14 determined in step S903 (S906). If the semiconductor design device 700 determines that the shift circuit 14 is not configured for all the modules for which the shift circuit 14 is to be separately provided (No in S906), the process proceeds to step S904. On the other hand, if the semiconductor design device 700 determines that the shift circuit 14 has been configured for all of the modules for which the shift circuit 14 should be provided separately (Yes in S906), the process proceeds to step S907.

  The semiconductor design device 700 adds dummy sequential circuits 144 to each shift circuit 14 so that the number of sequential circuits 142 included in each shift circuit 14 corresponds to all the shift circuits 14 of the virtual semiconductor integrated circuit 10. Insert it (S907). Then, the semiconductor design device 700 adds the clock generation circuit 13, the selection circuit 15, the shift circuit 14 and the signal line connecting the selection circuit 15 to the virtual semiconductor integrated circuit 10 (S908). The design of the semiconductor integrated circuit 10 is finished.

  FIG. 10 is a flow chart schematically showing the operation of simulation in which the semiconductor design device according to an embodiment of the present invention estimates the power consumption of a virtual semiconductor integrated circuit. In the figure, first, the semiconductor design device 700 acquires circuit information 7043 having information of the virtual semiconductor integrated circuit 10 whose power consumption is to be measured from the memory module 704 (S1001). Next, the semiconductor design device 700 starts the power consumption estimation program 7042 from the memory module 704, and selects circuit information 7043 and simulation pattern information 7044 according to the program. Then, the semiconductor design device 700 inputs simulation pattern information 7044 to the virtual semiconductor integrated circuit 10 shown in the circuit information 7043 to start simulation (S1002), and places the virtual semiconductor integrated circuit 10 in the test mode. It sets (S1003).

  The semiconductor design device 700 sets the virtual semiconductor integrated circuit 10 in the capture mode (S1004). Specifically, the semiconductor design device 700 causes the virtual semiconductor integrated circuit 10 to generate the enable signal ENA indicating the capture mode and the shift clock SF_CLK according to the enable signal ENA. While the virtual semiconductor integrated circuit 10 is in the "capture mode", the virtual semiconductor integrated circuit 10 operates at the actual operating frequency.

  The semiconductor design device 700 causes the shift circuit 14 of the virtual semiconductor integrated circuit 10 to capture the data input signal DIN output by the combinational circuit 11 (1) of the semiconductor integrated circuit 10 (S1005). Then, the semiconductor design device 700 sets the virtual semiconductor integrated circuit 10 in the “shift mode” (S1006). Specifically, the semiconductor design device 700 causes the virtual semiconductor integrated circuit 10 to generate an enable signal ENA indicating the shift mode and a shift clock SF_CLK according to the enable signal ENA. While virtual semiconductor integrated circuit 10 is in the “shift mode”, semiconductor integrated circuit 10 operates at the frequency of system clock CLK.

  The semiconductor design device 700 shifts the state of the output of the sequential circuit 142 of the shift circuit 14 of the virtual semiconductor integrated circuit 10 to the sequential circuit 142 of the next stage, and stores the state of the sequential circuit 142. Are repeated the number of sequential circuits 142 included in the shift circuit + 1 (loop B: S1007 to S1009).

  More specifically, the semiconductor design device 700 shifts the state of the output of the sequential circuit 142 of the shift circuit 14 of the virtual semiconductor integrated circuit 10 once to the sequential circuit 142 of the next stage (S1008). The design apparatus 700 stores the state of the output output from the final stage sequential circuit 142 as a simulation result 7045 (S1009).

  The semiconductor design device 700 determines whether the state of the sequential circuit 142 of the shift circuit 14 of the virtual semiconductor integrated circuit 10 has been stored with respect to the desired state of the simulation pattern (S1010). When the semiconductor design device 700 determines that the state of the sequential circuit 142 of the shift circuit 14 of the virtual semiconductor integrated circuit 10 is not stored with respect to the desired state of the simulation pattern (No in S1010), the process of step S1004. Return to On the other hand, when the semiconductor design device 700 determines that the state of the sequential circuit 142 of the shift circuit 14 of the virtual semiconductor integrated circuit 10 is stored with respect to the desired state of the simulation pattern (Yes in S1010), the process of step S1011 Go to

  The semiconductor design device 700 calculates the number of toggles of the virtual semiconductor integrated circuit 10 based on the simulation result 7045 (that is, the stored state of the output of the sequential circuit 142) (S1011). Then, the semiconductor design device 700 estimates the power consumption of the virtual semiconductor integrated circuit 10 based on the number of toggles (S1012), and ends the estimation of the power consumption of the virtual semiconductor integrated circuit 10.

  As described above, the semiconductor design device 700 first operates the virtual semiconductor integrated circuit 10 in the capture mode to capture data output from the combinational circuit 11 (1). Next, the semiconductor design device 700 operates the virtual semiconductor integrated circuit 10 in the shift mode to shift the state of the sequential circuit 142 by the number of the sequential circuits 142 of the shift circuit 14 of the semiconductor integrated circuit 10 + 1. Thus, the semiconductor design device 700 causes the semiconductor integrated circuit 10 to make the state after the shift circuit 14 shifts the output of the sequential circuit 142 equal to the state before shifting the output of the sequential circuit 142. Since the semiconductor design device 700 can capture data output from the combinational circuit 11 (1) next to the semiconductor integrated circuit 10 without performing additional processing, the state of the sequential circuit 142 can be efficiently stored. Power consumption can be estimated.

  In addition, the semiconductor design device 700 can efficiently estimate the power consumption of each module of the virtual semiconductor integrated circuit 10 corresponding to each output by processing the determination result for each output of the virtual semiconductor integrated circuit 10 it can.

  Each of the above-described embodiments is an example for describing the present invention, and the present invention is not limited to the embodiments. The present invention can be practiced in various forms without departing from the scope of the invention.

  For example, in the method disclosed herein, the steps, operations or functions may be performed in parallel or in different orders, as long as the results are not inconsistent. The steps, operations and functions described are merely provided as examples, and some of the steps, operations and functions may be omitted without departing from the scope of the invention, and may be combined with one another. One or more steps, operations or functions may be added.

  In addition, although various embodiments are disclosed herein, the specific features (technical matters) in one embodiment may be added to the other embodiments or modified while appropriately improving the technical features. Specific features in the form can be substituted, and such form is also included in the scope of the present invention.

  The present invention can be widely used in the field of semiconductor integrated circuits.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor measurement system 10 ... Semiconductor integrated circuit 11 ... Combination circuit 12 ... Control circuit 13 ... Clock generation circuit 131 ... Counter 132, 133 ... AND circuit 134 ... Selection circuit 14 ... Shift circuit 140 ... Output control circuit 141 ... Selection circuit 142, 144 Sequential circuit 143, 145 AND circuit 15 Selection circuit 20 Semiconductor measurement device 21 Control device 22 Comparator 23 Toggle count calculation device 24 Storage device 700 Semiconductor design device 701 Execution device 702 Processor module 703: Chip set 704: Memory module 7041: Circuit information generation program 7042: Power consumption estimation program 7043: Circuit information 7044: Simulation pattern information 7045: Simulation result 705: Storage device 7 6 ... input and output device

Claims (10)

At least one shift circuit receiving a first signal from the first combinational circuit and outputting a second signal based on the first signal to the second combinational circuit;
A clock generation circuit which generates a predetermined enable signal and a predetermined shift clock based on a predetermined system clock, and outputs the generated predetermined enable signal and the predetermined shift clock to the shift circuit;
The at least one shift circuit is
A plurality of output control circuits each comprising a pair of selection circuits and a sequential circuit,
The plurality of output control circuits are connected in a ring so that an output from the sequential circuit of one of the output control circuits is input to the selection circuit of another of the output control circuits.
The clock generation circuit is in a first state for a first period during which the predetermined system clock alternates a number of times corresponding to multiplication of the number of the sequential circuits in the at least one shift circuit. The predetermined enable signal is generated to be in the second state for a second period necessary for capturing the second signal later, and is output to the corresponding selection circuit, and the first period And generating the predetermined shift clock so as to alternate for a third period in which the predetermined system clock alternates once, and outputting the shift clock to the corresponding sequential circuit .
The selection circuit of each of the plurality of output control circuits selects an output from a sequential circuit of another output control circuit connected in a ring shape, when the predetermined enable signal is in the first state. To select and output the first signal when the predetermined enable signal is in the second state.
Semiconductor integrated circuit. The selection circuit in each of the plurality of output control circuits is a first signal or a second signal output from a sequential circuit in an output control circuit in a stage preceding the one output control circuit according to the predetermined enable signal. Output any one of the above as a selection signal to the corresponding sequential circuit,
The sequential circuit in each of the plurality of output control circuits outputs the corresponding selection signal as the second signal according to the predetermined shift clock.
The semiconductor integrated circuit according to claim 1 . A plurality of the shift circuits,
Each of the plurality of shift circuits is configured to have the same number of sequential circuits,
The semiconductor integrated circuit according to claim 1. A measuring method for measuring power consumption of a semiconductor integrated circuit under control of a controller,
Have a plurality of sequential circuits connected in a ring, the first combining circuit receives the first signal, at least capable of outputting a second signal based on the first signal to the second combinational circuit 1 Preparing a semiconductor integrated circuit comprising three shift circuits,
Inputting a test pattern to the semiconductor integrated circuit;
Obtaining a state of an output of each of the sequential circuits corresponding to a plurality of states of the test pattern;
Calculating the power consumption of the semiconductor integrated circuit based on the acquired state of the output of each sequential circuit;
Including
To obtain the state of the output of each sequential circuit,
Setting the operating frequency of the semiconductor integrated circuit to a first frequency in a first mode ;
Receiving the input through the first combinational circuit in the first mode to capture the output of each sequential circuit in the at least one shift circuit;
Setting the operating frequency of the semiconductor integrated circuit to a second frequency higher than the first frequency in a second mode ;
In the second mode, a state of an output of the one sequential circuit connected in a ring in the at least one shift circuit is obtained, and each of the order in the circular connection in the at least one shift circuit. Repeating the shift of the state of the output of the circuit to the sequential circuit in the next stage is repeated a number of times corresponding to the multiplication of the number of sequential circuits in the at least one shift circuit.
Measuring method, including. A measuring device for measuring the power consumption of a semiconductor integrated circuit, comprising:
A control device having at least a memory and a processor;
The controller is
Have a plurality of sequential circuits connected in a ring, the first combining circuit receives the first signal, at least capable of outputting a second signal based on the first signal to the second combinational circuit 1 Placing a semiconductor integrated circuit with three shift circuits in place,
Input a test pattern to the semiconductor integrated circuit;
For multiple states of the test pattern,
In the first mode, the operating frequency of the semiconductor integrated circuit is set to the first frequency,
Receiving an input through the first combinational circuit in the first mode to capture an output of each sequential circuit in the at least one shift circuit;
In the second mode, the operating frequency of the semiconductor integrated circuit is set to a second frequency higher than the first frequency,
In the second mode, a state of an output of the one sequential circuit connected in a ring in the at least one shift circuit is obtained, and each of the order in the circular connection in the at least one shift circuit. Shifting the state of the output of the circuit to the sequential circuit in the next stage is repeated the number of times corresponding to the multiplication of the number of sequential circuits in the at least one shift circuit by one addition;
The power consumption of the semiconductor integrated circuit is calculated based on the acquired state of the output of the sequential circuit.
measuring device. A semiconductor design apparatus for designing a semiconductor integrated circuit model,
A processor,
A memory capable of storing a predetermined design program;
Under control of the processor executing the predetermined program,
Based on the attributes assigned to each module, determine whether there is a module for which power consumption should be estimated separately,
If it is determined that there is a module for which the power consumption should be estimated separately, all sequential circuit models for each of the modules are extracted, and shift circuit models corresponding to all the extracted sequential circuit models are respectively generated. further, as the number of sequential circuit models, each with the generated said shift circuit model matches, inserting a dummy sequence circuit model in each of the shift circuit model,
When it is determined that there is no module for individually estimating the power consumption, all sequential circuit models are extracted from the semiconductor integrated circuit model, and the plurality of corresponding shifts are divided by dividing all the extracted sequential circuit models. generating circuit, further, as the number of sequential circuit models, each with the generated plurality of shift circuits model matches, inserting a dummy sequence circuit model to each of the plurality of shift circuit model,
Semiconductor design equipment. A semiconductor design method implemented by a semiconductor design apparatus for designing a semiconductor integrated circuit model, comprising:
Determining whether there is a module to which power consumption should be individually estimated based on the attributes assigned to each module;
If it is determined that there is a module for which the power consumption should be estimated separately, all sequential circuit models for each of the modules are extracted, and shift circuit models corresponding to all the extracted sequential circuit models are respectively generated. further, as the number of sequential circuit models, each with the generated said shift circuit model matches, and inserting a dummy sequence circuit model in each of the shift circuit model,
When it is determined that there is no module to estimate the power consumption individually, all sequential circuit models are extracted from the semiconductor integrated circuit model, and the plurality of corresponding shifts are divided by dividing all the extracted sequential circuit models and it produces a circuit, further, as the number of sequential circuit models, each with the generated plurality of shift circuits model matches, inserting a dummy sequence circuit model to each of the plurality of shift circuit model,
Semiconductor design methods, including: A program for estimating the power consumption of a semiconductor integrated circuit,
The program is executed by the processor of the estimation device
Forming at least one shift circuit model that receives a first signal from the first combinational circuit model and outputs a second signal based on the first signal to the second combinational circuit model;
A function of forming a clock generation circuit model that generates a predetermined enable signal and a predetermined shift clock based on a predetermined system clock and outputs the generated predetermined enable signal and the predetermined shift clock to the shift circuit model; Configured to achieve
The at least one shift circuit model is
A plurality of output control circuit models each comprising a pair of selection circuit models and a sequential circuit model,
The plurality of output control circuit models are cyclically connected such that an output from the sequential circuit model of one of the output control circuit models is input to the selection circuit model of another of the output control circuit models.
The function of forming the clock generation circuit model is
The first state is established for a first period during which the predetermined system clock alternates a number of times corresponding to multiplication of the number of sequential circuit models in the at least one shift circuit model, and the second state is selected after the first period. Generating the predetermined enable signal to be in a second state for a second period necessary to capture the signal of
The predetermined shift clock is generated so as to be output to the corresponding selection circuit model and to be alternated over a third period in which the predetermined system clock alternates once in addition to the first period. and the ability to output in order circuit model, only including,
The selection circuit model of each of the plurality of output control circuit models is an output from a sequential circuit of another output control circuit model connected in a ring when the predetermined enable signal is in the first state. Are selected and output, and when the predetermined enable signal is in the second state, the first signal is selected and output.
program. An estimation method for estimating power consumption of a semiconductor integrated circuit model, the estimation method comprising:
Have a plurality of sequential circuit model which is connected to the annular, the first combining circuit receives the first signal, at least a second signal based on a first signal that can be output to the second combinational circuit Obtaining a semiconductor integrated circuit model comprising one shift circuit model;
Inputting a simulation pattern into the semiconductor integrated circuit model;
Obtaining an output state of a sequential circuit model corresponding to a plurality of states of the simulation pattern;
Calculating the power consumption of the semiconductor integrated circuit model based on the acquired state of the output of the sequential circuit model.
To get the status is
Setting the operating frequency of the semiconductor integrated circuit model to a first frequency in a first mode ;
Receiving an input through the first combinational circuit in the first mode to capture an output of each sequential circuit model in the at least one shift circuit model;
Setting the operating frequency of the semiconductor integrated circuit model to a second frequency higher than the first frequency in a second mode ;
In the second mode, a state of an output of the one sequential circuit model connected in a ring in the at least one shift circuit model is obtained, and further, the ring is connected in the at least one shift circuit model be repeated as many times plus only one time to the number of times corresponding to be shifted to the next stage of the sequential circuit model the state of the output to the multiplication of the number of sequential circuit model in the at least one shift circuit model of the sequential circuit model When,
Estimated method, including An estimation apparatus for estimating the power consumption of a semiconductor integrated circuit model,
An execution device comprising at least a memory and a processor;
A storage device for storing a simulation pattern;
The execution device is
Have a plurality of sequential circuit model which is connected to the annular, the first combining circuit receives the first signal, at least a second signal based on a first signal that can be output to the second combinational circuit Get one shift circuit model,
Input a simulation pattern to the semiconductor integrated circuit model,
For multiple states of the simulation pattern,
In the first mode, the operating frequency of the semiconductor integrated circuit model is set to the first frequency,
Receiving an input through the first combinational circuit in the first mode to capture an output of each sequential circuit model in the at least one shift circuit model;
In the second mode, the operating frequency of the semiconductor integrated circuit model is set to a second frequency higher than the first frequency,
In the second mode, a state of an output of the one sequential circuit model connected in a ring in the at least one shift circuit model is obtained, and further, the ring is connected in the at least one shift circuit model repeated the number of times the state of the output is added by one time to be shifted to the next stage of the sequential circuit on the number of times corresponding to the multiplication of the number of sequential circuit model in the at least one shift circuit model of the sequential circuit model,
The power consumption of the semiconductor integrated circuit model is calculated based on the acquired state of the output of the sequential circuit model.
Quotation device.