JP6476500B2 - Image processing system, gaming machine - Google Patents

Description

  The present invention relates to an image processing system for displaying an image drawn using data on a plurality of display means, and a gaming machine using such an image processing system.

  Along with the development of image display technology, an image processing system for forming an image to be displayed on this image display device is used in various fields and various devices together with an image display device such as a display. 2. Description of the Related Art Conventionally, many image processing systems have been proposed that store compressed and encoded data of a moving image obtained by a compression algorithm such as MPEG, decode it, and display it on an image display device such as a liquid crystal display. In recent years, for example, in game machines such as game machines and pachinko machines, a plurality of displays (display means) are used in one device, and the effect of presentation is enhanced by displaying moving images or still images on each display. There are many things.

  In recent years, the volume of image information has increased with the increase in image resolution, and the necessity of processing a large amount of compressed and encoded data during image processing and image formation has increased. Conventionally, as a means for meeting such a need, image processing is performed using an inexpensive and large-capacity memory such as a NAND flash memory outside an integrated circuit for image processing, and a formed image is displayed on a display device. A technique for displaying an image is known (for example, see Patent Document 1). In addition, in a conventional image processing processor having an external memory and an on-chip memory, whether the determination unit should write a series of data read from a predetermined address range of the external storage device by the data processing unit to the internal storage unit. If the data processing means reads the data in the same address range of the external storage device again, the data is read from the internal storage instead. There is known an invention for performing image processing in (see Patent Document 2, for example).

JP 2011-147815 A JP-A-2005-18428

  Here, in order to process a large amount of compressed and encoded data, it is necessary to increase the capacity of the memory and increase the reading / writing speed of the memory. On the other hand, if the memory capacity is increased and the speed is increased, the manufacturing cost of the image processing system will increase. This problem becomes more prominent in an environment where a plurality of displays are provided in one device and more image information should be processed.

  However, in Patent Document 1, the number of displays increases because the number of external memories and the number of wirings connected to the external memories must be increased as the number of parallel processes and parallel processes in image processing increases. If the amount of data to be processed in parallel or parallel increases, the manufacturing cost of the image processing system increases, and there is a problem that a practical limit is imposed on a large amount of data and high-speed processing.

  In Patent Document 2, although specific data can be stored in the internal storage means based on the address from which data is read, the processing procedure itself in image processing is based on the use of a memory similar to the conventional one. Therefore, there is a problem that large-scale processing and high-speed processing of data used in a plurality of displays cannot be performed.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an image processing system capable of performing image formation and image display at a high speed and suppressing an increase in manufacturing cost when images are simultaneously displayed on a plurality of screens. It is an object of the present invention to provide a gaming machine using such an image processing system.

In order to achieve the object, the invention described in claim 1 is an image processing system for displaying an image on a plurality of display means, and an image forming means for forming an image to be displayed on the display means; A first storage unit used as a drawing area for generating an image data by drawing an image displayed on at least one of the plurality of display units by the image forming unit; and the image forming unit A plurality of second storage means for storing the image data generated in the first storage means formed in a quantity corresponding to the quantity of the display means, and the image data from the second storage means A plurality of image display circuits provided corresponding to the respective display means, acquired and displayed on the respective display means, the first storage means and the second storage Reception of the image data between the unit and a transmitting and receiving means for transmitting and receiving the image data between the second memory means and the image display circuit, the first memory And the plurality of image display circuits are provided in an image processing apparatus main body for generating and displaying the image data, respectively, and the second storage means is detachable from the image processing apparatus main body. is configured, the first storage means is a said second access speed to the recorded data than the storage means fast, the second storage means, said data than said first storage means The image forming unit moves the image data generated in the first storage unit from the main body of the image processing apparatus to the second storage unit, and thereby stores the second storage unit. Memorize in means And moving the image data stored in the second storage means to the image processing apparatus main body, supplying the moved image data to the image display circuit, and generating an image based on the image data. It is displayed on the display means .

  According to a second aspect of the present invention, in addition to the configuration of the first aspect, the drawing area of the first storage unit is a frame displayed on the display unit having the maximum total number of pixels. The second storage means has a data amount of one frame displayed on all of the display means. It is characterized by being formed in the capacity more than the sum total.

  According to a third aspect of the present invention, in addition to the configuration according to the first or second aspect, the second storage unit is more than twice the total amount of data of one frame displayed on all the display units. In addition to being formed in a capacity, it is configured to perform temporary storage by storing the generated image and transmission of the stored image to the image display circuit by two or more buffer configurations. It is a feature.

According to a fourth aspect of the present invention, in addition to the configuration according to any one of the first to third aspects, a first bandwidth of data transmission between the image forming unit and the first storage unit is The second bandwidth of data transmission between the image display circuit and the second storage means has a relationship represented by the following formula (1).
Number of layers + 1.5 ≦ first bandwidth / second bandwidth ≦ number of layers × 2 + 2.5 (1)
According to a fifth aspect of the present invention, in addition to the configuration according to any one of the first to fourth aspects, the first storage unit and the second storage unit are each formed by a RAM. It is characterized by.

  A sixth aspect of the present invention is a gaming machine, comprising a plurality of display means, and using the image processing system according to any one of the first to fifth aspects.

  According to the first aspect of the present invention, the first storage means includes a drawing area in which the drawing means draws an image displayed on at least one of the plurality of display means and generates image data. And the second storage means is configured such that the drawing means stores the image data generated in the first storage means. Temporary storage of the generated image data can be performed simultaneously in parallel in the first storage unit and the second storage unit. Further, the first storage means has a higher access speed to the recorded data than the second storage means, and the second storage means has a larger data storage capacity than the first storage means. As a result, the image data of the images displayed on all the display means is generated at high speed by the first storage means and sent to the second storage means, and each display means is provided in the second storage means. Image data to be displayed can be stored and temporarily stored. In addition, it is possible to suppress the capacity of the first storage unit from being excessively limited to only the minimum processing that requires high-speed processing in the generation of image data. Further, by temporarily storing the image data to be displayed on the display means by the second storage means having a larger capacity than the first storage means, still images and moving images that are not visually uncomfortable are displayed on the respective display means. Can be displayed. Thereby, when displaying an image on a plurality of screens simultaneously, it is possible to provide an image processing system that can perform image formation and image display at a high speed and suppress an increase in manufacturing cost.

  According to the second aspect of the present invention, the drawing area of the first storage means is displayed on all display means with a data amount of one frame or more displayed on the display means having the maximum total number of pixels. In order to generate the image data to be displayed on all the display means at high speed and send it to the second storage means by forming the capacity to be equal to or less than the total amount of data of one frame to be processed Can be configured as required capacity. Further, since the second storage means is formed with a capacity that is equal to or larger than the total amount of data of one frame displayed on all the display means, the second storage means is displayed on each display means. The image data can be configured as a capacity necessary for temporarily storing each image data. Thereby, when displaying an image on a plurality of screens simultaneously, it is possible to provide an image processing system that can perform image formation and image display at a high speed and suppress an increase in manufacturing cost.

  According to the invention described in claim 3, in the second storage means, the temporary storage of the image by the two or more buffer configurations and the transmission of the formed image to the image display circuit are performed continuously and at high speed. It becomes possible to do. Thereby, when displaying an image on a plurality of screens simultaneously, it is possible to provide an image processing system that can perform image formation and image display at a high speed and suppress an increase in manufacturing cost.

  According to the invention described in claim 4, the value obtained as a result of performing the predetermined calculation with the first bandwidth and the second bandwidth is defined by the relationship with the predetermined value based on the number of layers. Thus, the first storage means is used when the image data is configured using the first storage means and the image data is temporarily stored and transmitted to the image display circuit using the second storage means. Data transmission from the second storage means to the second storage means and data transmission from the second storage means to the image display circuit can be performed continuously and simultaneously in parallel. Thereby, when displaying an image on a plurality of screens simultaneously, it is possible to provide an image processing system that can perform image formation and image display at a high speed and suppress an increase in manufacturing cost.

  According to the fifth aspect of the present invention, a plurality of screens are provided by using the RAM capable of reading and writing data and randomly accessing the recorded data for the first storage means and the second storage means, respectively. When displaying images simultaneously, it is possible to configure an image processing system that can perform image formation and image display at high speed and can suppress an increase in manufacturing cost.

  According to the sixth aspect of the present invention, when images are simultaneously displayed on a plurality of screens using the image processing system of the present invention, image formation and image display can be performed at a high speed and the manufacturing cost can be reduced. It is possible to provide a gaming machine that can prevent a surge.

1 is a diagram showing an overall configuration of an image processing system and a gaming machine according to an embodiment of the present invention. It is a figure which shows typically the processing content in the internal memory and external memory of an image processing system same as the above. It is the figure which showed the relationship of the read / write speed of the external memory and internal memory for performing a process appropriately for every layer of image data of the image processing system same as the above. It is a flowchart which shows the process sequence of an image processing system same as the above. It is a figure which shows typically the process sequence of an image processing system same as the above.

  1 to 5 show an embodiment of the present invention.

[Basic configuration]
FIG. 1 is a block diagram showing the overall configuration of an image processing system and a gaming machine according to this embodiment.

The image processing system 1A shown in FIG. 1, a pachinko machine, built into the gaming machine 100 Pachi like, a plurality of display portions ₆ 0 of the gaming machine _100, 6 1, to form an image displayed on · · · _{6 n} Used for. The image processing system 1 </ b> A is disposed in the housing of the gaming machine 100.

An image processing system 1A according to this embodiment shown in FIG. 1 includes an image processing device 1, a first auxiliary storage device 2, a second auxiliary storage device 3, and an external device as "second storage means". A memory 4 and a plurality of display units 6 ₀ , 6 ₁ ,... 6 _n are provided. The first auxiliary storage device 2, the second auxiliary storage device 3, and the external memory 4 are connected to an external data bus 5 as “transmission / reception means”, and image processing is performed via the external data bus 5. It is connected to the device 1.

The image processing apparatus 1 of the image processing system 1A is, for example, a GPU (Graphics Processing Unit), and is a unit having various configurations for performing image processing and image drawing in a computer apparatus or a computer unit. In this embodiment, the image processing apparatus 1 forms a plurality of images (including both still images and moving images) based on various programs and data, and displays the formed images on the display units 6 ₀ , 6. ₁ ,... 6 _n are displayed.

The image processing apparatus 1 includes a control unit 7, a drawing unit 8, a transfer unit 9, an internal memory 10 as a “first storage unit”, a display circuit unit 11, and a communication interface (I / F) unit 12. The configuration is bus-connected to an internal data bus 13 as “transmission / reception means”. Then, the display circuit unit 11, a display unit _{6 0, 6 1, ··· 6} n as many of the plurality of image display circuit _{14 0, 14 1, ··· 14} n are provided.

  The control unit 7 is, for example, a CPU (Central Processing Unit), and comprehensively controls transmission / reception of signals and data of the entire image processing apparatus 1 and signal processing and data processing. Specifically, for example, a control information program is read from the first auxiliary storage device 2, and each component such as the drawing unit 8 and the transfer unit 9 of the image processing system 1A is controlled based on this program. A command is generated to form image data requested by the host controller of the machine 100 in the image processing system 1A.

The drawing unit 8 performs various processes necessary for image processing and image drawing. In this embodiment, the drawing unit 8 is supplied from the control unit 7 (based on a display list (not shown) for the control unit 7 to form an image requested by the host control unit of the gaming machine 100). Te, by performing the graphic drawing, etc., each layer constituting each of the display section 6 _0, 6 _1, one frame of the predetermined unit (e.g., video constituting the image displayed on · · · 6 _n (hierarchy) ) On the basis of processing for generating rendering data (hereinafter simply referred to as “layer data”, which is the same in this specification) that constitutes the image data for each image, and the respective display units 6 ₀ , 6 ₁ , ... 6 A process for generating image data (hereinafter simply referred to as “image data”; the same applies in this specification) as an image displayed on _n is performed.

  Specifically, for example, the drawing unit 8 uses the internal memory 10 as a work area and the image content data (for example, compressed by compression CODEC such as MPEG) necessary for image formation read from the second auxiliary storage device 3. Data) is used to perform a predetermined drawing process, and individual layer data and image data are generated as a result of the drawing process (see FIG. 2, which will be described in detail later).

The transfer unit 9 transfers the image data recorded in the frame buffer 110 of the internal memory 10 to the external memory 4 and temporarily stores it under the control of the control unit 7. Specifically, for example, the transfer unit 9 reads out and captures image data stored in the frame buffer 110 of the internal memory 10 under the control of the control unit 7, and stores the captured image data in any of the external memories 4. stored is written in the area (for example, ₀ the first region 161 of the storage areas 16 _0). As a result, the image data is temporarily stored in the external memory 4 (details will be described later).

  The internal memory 10 is a storage means capable of high-speed access to recorded data, such as eDRAM (embedded DRAM) and SRAM (Static Random Access Memory). The internal memory 10 is used as a drawing processing work area in the drawing unit 8 (see FIG. 2, will be described in detail later), and stores a frame buffer 110 as a “drawing area” for storing image data, and layer data. And a layer data storage unit 120.

Capacity of the frame buffer 110 in the internal memory 10, and the capacity of the external memory 4, a plurality of display portions 6 _0, 6 _1, is set based on the data amount of an image to be displayed at a time · · · 6 _n ( See Fig. 3. Details will be described later).

Display circuit unit 11, and an image display circuit _{14 0, 14 1, ··· 14} n acquires the image data stored in the external memory 4, a display section _{6 0,} 6 1, the · · · _{6 n} converted into displayable data format, ₀ display unit 6 various _images, 6 _1, performs various processes for displaying and transmitted to · · · 6 _n. Specifically, the display circuit unit 11 reads the image data recorded in the external memory 4 and sends it to the image display circuits 14 ₀ , 14 ₁ ,... 14 _n . Each of the image display circuit _{14 0, 14 1, ··· 14} n converts the image data acquired display unit _{6 0,} 6 1, into a displayable data · · · _{6 n,} the data transmission unit 15 ₀ , ₁₅ 1, ... 15 display unit ₆ through the _{n 0,} 6 1, and sent to ... _{6 n,} the display section _{6 0,} 6 1, is an image displayed on ... _{6 n.}

  The communication interface unit 12 performs various types of processing (for example, conversion of data itself, conversion of address information for transmission / reception, etc.) necessary for transmission / reception of data inside and outside the image processing apparatus 1.

  The internal data bus 13 constitutes a data and signal transmission / reception path between the respective components inside the image processing apparatus 1. The internal data bus 13 is preferably configured so that a plurality of data and signals can be transmitted and received simultaneously in parallel.

  The first auxiliary storage device 2 is, for example, various ROMs, and is connected to the image processing device 1 by an external data bus 5 and an internal data bus 13. The first auxiliary storage device 2 stores a program for controlling each component such as the drawing unit 8 and the transfer unit 9 of the image processing system 1A.

The second auxiliary storage device 3 is also a variety of storage devices, for example, and is connected to the image processing device 1 by an external data bus 5 and an internal data bus 13. In the second auxiliary storage device 3, various content data used for rendering an image and forming an image on the display units 6 ₀ , 6 ₁ ,... 6 _n are recorded. Specifically, the second auxiliary storage device 3 is an SSD (Solid State Device), in which compressed data for generating image data is recorded by the processing of the drawing unit 8 compressed by a compression CODEC such as MPEG. ing.

  The external memory 4 is a variety of RAMs, and image data that has been subjected to drawing processing in the frame buffer 110 of the internal memory 10 is transferred and recorded. The external memory 4 can use SDRAM (Synchronous DRAM), GDDR (Graphics DDR), or the like that can be formed with a larger storage capacity than the internal memory 10 but has a lower access speed to recorded data than the internal memory 10.

As described above, in the external memory 4, the display unit _{6 0,} 6 1, image data of each frame to be displayed respectively · · · _{6 n} are stored. Specifically, the external memory 4, a plurality, for example, the display unit _{6 0,} 6 1, storage area _{16 0,} 16 1 of the same number as the number of · · · _{6 n} (i.e. the n + 1), is · · · 16 _n Is formed. Further, first region ₁₆₁ is divided respective storage areas in the two _0, 161 1, · · · 161 _n and the second region _{162 0, 162 1, ··· 162} n are formed, double buffering ( in the two storage areas, it is temporarily stored in the image data generated in the internal memory 10 in one storage area for example the first region 161 ₀ is stored, is stored from the other storage areas for example second regions 162 ₀ The process of alternately repeating the state in which the image data is transferred is performed). In this embodiment, the storage area is double buffering using two of the first and second areas. However, the present invention is not limited to this, and a multiple buffer configuration comprising two or more areas. If it is good.

The storage capacity of the external memory 4 is set based on the data amount of the image to be displayed on the plurality of display units 6 ₀ , 6 ₁ ,... 6 _n at a time (see FIG. 3 and will be described in detail later). .

  The external data bus 5 connects the external components of the image processing apparatus 1 to a state in which data and signals can be transmitted and received with each other to form a data and signal transmission and reception path. It is desirable to configure so that a plurality of data and signals can be transmitted and received simultaneously in parallel.

The bus width of the internal data bus can be set to several thousand bits, whereas the bus width used as a connection interface of an external device such as PCI is 64 bits, and when driven at the same frequency, In general, the transmission speed is about 1 to several hundredths to several tens of minutes. The bandwidths (communication speed) of the internal data bus 13 and the external data bus 5 are the capacity of the frame buffer 110 of the internal memory 10 and the capacity of the external memory 4, that is, a plurality of display units 6 ₀ , 6 ₁ ,. 6 _n is set based on the data amount of the image to be displayed at once (details will be described later).

[Processing in internal memory and transfer to external memory by drawing unit]
FIG. 2 schematically shows processing in the internal memory 10 and transfer processing to the external memory 4 by the drawing unit 8 of the image processing system 1A of this embodiment.

As shown in FIG. 2, in this embodiment, the drawing unit 8 uses the layer data storage unit 120 and the frame buffer 110 of the internal memory 10 as work areas, and displays the individual display units 6 ₀ , 6 ₁ ,. · in 6 _n to generate the image data of each frame to be displayed.

  Specifically, the drawing unit 8 uses image content data (for example, data compressed by compression CODEC such as MPEG) necessary for image formation read from the second auxiliary storage device 3 (see FIG. 1). A predetermined drawing process is performed.

  For example, as shown in FIG. 2, in the case of an image having background, person, and smoke effects, first, data related to the background layer is read from the second auxiliary storage device 3 and decoded by the drawing unit 8. Certain background layer data is stored in the layer data storage unit 120 of the internal memory 10. Thereafter, the drawing unit 8 stores the background layer data stored in the layer data storage unit 120 of the internal memory 10 and the image data stored in the frame buffer 110 (when the background layer is created, the data in the frame buffer is empty, Alternatively, the background layer image is superimposed on the image data in the frame buffer 110 and rendered, and the image data (A) as a rendering result is stored in the frame buffer 110 of the internal memory 10.

  Next, data relating to the symbol layer is read from the second auxiliary storage device 3, decoded by the drawing unit 8, and the resulting symbol layer data is stored in the layer data storage unit 120 of the internal memory 10. Thereafter, the design layer data stored in the layer data storage unit 120 and the image data (A) stored in the frame buffer 110 are read, and the image data (A) and the design layer data are overlaid and drawn. The resulting image (B) is stored in the frame buffer 110 of the internal memory 10.

  Further, the data related to the effect layer is read from the second auxiliary storage device 3, decoded by the drawing unit 8, and the effect layer data as a result thereof is stored in the layer data storage unit 120 of the internal memory 10. Thereafter, the effect layer data stored in the layer data storage unit 120 and the image data (B) stored in the frame buffer 110 are read, and the image data (B) and the effect layer data are overlaid and drawn. The resulting image (C) is stored in the frame buffer 110 of the internal memory 10.

When the image of all the layers are combined with the image data of the frame buffer 110, image data is first region e.g. a first storage area for example storage region 16 ₀ of the external memory 4 via the communication interface unit 12 from the frame buffer 110 It is transferred to and stored in either the area 161 ₀ or the second area, for example, the second area 162 ₀ (for example, the first area 161 ₀ ) (see FIG. 2). At that time, the image data drawn in the previous frame is stored in the other area (for example, the second area 162 ₀ ) of the external memory 4 (see FIG. 2). The display circuit unit 11 reads the image data from the other side of the area, and displays the corresponding specific display example, the display unit 6 _0.

In FIG. 2, but describes only the processing of the first region 161 ₀ of the one storage area 16 ₀ of the external memory 4 and the second region 162 _0, other storage area ₁₆ 1, ... 16 first region ₁₆₁ 1 of _n, · · · 161 _n and the second region ₁₆₂ 1, the same processing even in a · · · 162 _n is performed. As a result of the processing, the image data is displayed on the corresponding display units 6 ₁ ,... 6 _n .

Generates individual image data performs a drawing process in a high-speed internal memory 10 of the reading, the display section _{6 0,} 6 1, the number of storage areas ₁₆ corresponding to the · · · _{6 n 0,} 16 1, · · · 16 By storing the image data for each frame in the external memory 4 having _n , the individual display units 6 ₀ , 6 ₁ ,... are generated using the image data while generating each image data at high speed. 6 _n can be displayed. That is, the generation of individual image data by drawing processing and the generation of image data for each frame using the image data are performed as a continuous process, and the processing for generating the image data is speeded up. Smooth video playback can be realized.

[Prerequisites for setting memory capacity and transfer speed]
For example, the gaming machine 100 five display section _{6 0,} 6 1, ... _{6 4} are provided, each of the display section _{6 0,} 6 1, ... _{6 4} below <Table 1> Consider the case of specs.

この場合、従来技術においては、全ての表示部６_０，６_１，・・・６_４における処理を高速化するためには、内部メモリ１０のフレームバッファ１１０の容量は、表示部６_０，６_１，・・・６_４の必要メモリ容量の合計以上の大きさ、例えば５５０Ｍｂが必要とされる。すなわち、描画部が描画する全ての画像データをフレームバッファ１１０に記憶しておき、それを表示回路で表示するためである。 <Table 1>

In this case, in the prior art, in order to speed up the processing in all the display units 6 ₀ , 6 ₁ ,... 6 ₄ , the capacity of the frame buffer 110 of the internal memory 10 is set to the display units 6 ₀ , 6. _1, greater than or equal to the sum of the size of the required memory capacity.. _{6 4,} for example, 550Mb are required. That is, all the image data drawn by the drawing unit is stored in the frame buffer 110 and displayed on the display circuit.

  However, as described above, the internal memory 10 is expensive, and an increase in the memory capacity of the internal memory 10 leads to an increase in cost.

On the other hand, in view of displaying an image on the plurality of display units 6 ₀ , 6 ₁ ,... 6 ₄ , the image is drawn with the minimum internal memory using the external memory 4 having a low access speed. it is desired, a plurality of display portions 6 _0, 6 _1, assuming the display to ... 6 _4, to ensure the external memory capacity of extent, also the line drawing processing at any level of the internal memory capacity Conventionally, no consideration has been given to whether or not it should be.

Therefore, in this embodiment, as described above, when generating image data using the internal memory 10 having a higher data reading speed than the external memory 4 and the external memory 4 having a larger capacity than the internal memory 10, a plurality of display portions 6 _0, 6 _1, found relationship from ... 6 ₄ resolutions and internal memory capacity and transfer rate and external memory transfer rate relationships and internal memory and external memory, the internal minimum It is an object of the present invention to provide an image processing apparatus that supports a plurality of display units with reduced memory costs.

Hereinafter, it displays a smooth moving motion respective display portion 6 _0, 6 _1, in ... 6 ₄ without excessive memory capacity, the memory capacity of the internal memory 10 and external memory 4, the internal data bus 13 An example of a setting mode of the bandwidth of the external data bus 5 (of which the bandwidth is smaller) and the access speed to the data recorded in the internal memory 10 will be described.

[Internal memory capacity setting]
In the image processing system 1A of this embodiment, the memory capacity of the internal memory 10, specifically, the capacity of the frame buffer 110 formed in the internal memory 10 when processing is performed is all the display units 6 ₀ , 6 _1, greater than the capacity that can store image data for one frame to be displayed on the full resolution things in ... _{6 4,} and all the display section _{6 0,} 6 1, in ... _{6 4} It is set smaller than the capacity that can store one frame of the maximum resolution image.

For example, when the display units 6 ₀ , 6 ₁ ,... 6 _{4 of} the image processing system 1A have the specifications described in <Table 1>, the capacity of the frame buffer 110 is expressed by the following formula (1). Set as follows.

About 283Mb (display section _{6 0} (i.e., all the display section _{6 0,} 6 1, substantially the same memory capacity capable of storing image data of one frame of full resolution ones) in ... _{6 4)} <Internal capacity of the frame buffer 110 of the memory 10 <about 548Mb (all display portion _{6 0,} 6 1, substantially the same in the memory capacity to store all the image data of one frame of ... _{6 4)} (1)

[External memory capacity setting]
In the image processing system 1A of this embodiment, as described above, each of the display section ₆ 0 in the external memory _4, 6 1, ... _{6 4} same number of storage areas ₁₆ and _0, 16 1, ... 16 _n is provided, and the drawing unit 8 performs processing by double buffering in each storage area. That is, divides each of the storage areas into two, divided one region (e.g., 0 first region 161 of the storage areas 16 ₀₎ and stores the image data generated in the internal memory 10 temporarily storing region, the other region (e.g., 0 second region 162 of the storage areas 16 ₀₎ is used as an area for sending the stored image data to the display circuit unit 11.

In order to realize such processing, in this embodiment, the storage areas 16 ₀ , 16 ₁ ,... 16 _n of the external memory 4 are all displayed in the display units 6 ₀ , 6 ₁ ,. ₄ is set to have a memory capacity that is at least twice as large as the memory capacity for storing one frame of image data of the maximum resolution (display unit 6 ₀ in Table 1).

For example, when the display units 6 ₀ , 6 ₁ ,... 6 _{4 of} the image processing system 1A have the specifications described in <Table 1>, the capacity of the external memory 4 is expressed by the following formula (2). Set as follows.

Capacity of external memory 4 ≧ 1096 Mb (about 548 Mb × 2) (2)

[Relationship between transfer rate of external memory and internal memory]
For example, the specifications of five display units 6 ₀ , 6 ₁ ,... 6 ₄ are as shown in <Table 1> (4K2K: 1 unit, Full HD: 4 units), and each display unit 6 ₀ , 6 _1, when an image displayed by ... _{6 4} (motion picture) was 30fps, all the display section _{6 0,} 6 1, the amount of data to be transmitted to.. _{6 4,} following values (3 ) Based on (4), the following formula (5) is obtained.

Display units 6 ₀ , 6 ₁ ,... 6 ₄ Capacity for all screens: 548 Mb (3)
Number of display frames per second: 30 fps (4)
Data amount to be transmitted to the display units 6 ₀ , 6 ₁ ,... 6 ₄ per second = (3) × (4) = 548 (Mb) × 30 (fps) = 16.461 Gb (5)

This transfer speed is a speed required for the image display circuits 14 ₀ , 14 ₁ ,... 14 _n to read data from the external memory 4, and drawing data from the frame buffer 110 of the internal memory 10 by the transfer unit 9. Are simultaneously performed, so that the transfer rate of the external memory 4 is at least a value represented by the following formula (6), which is twice the 16.461 Gbps of the above (5).

Transfer rate of the external memory 4 ≧ 32.922 Gbps (6)

The value of the transfer rate varies with specification of the display unit _{6 0,} 6 1, ... _{6 4.} For example, five of the display section _{6 0,} 6 1, if all of the ... _{6 4} also having a resolution of 4K2K display section _{6 0,} the capacity of the external memory 4 becomes as shown in the following equation (7), The operating frequency of the external memory 4 is as shown in the following formula (8).

Capacity of external memory 4 = 283.1 (Mb) × 5 (unit) × 2 (times) = about 2.8 Gb (7)
Transfer rate of external memory 4 = 1415.5 (Mbit) x 30 (fps) x 2 (times) = 84.930 Gbps (8)

When the above formulas (3) to (8) are combined, the transfer rate of the external memory 4 is as shown in the following formula (9).

Transfer rate of external memory 4 ≧ display units 6 ₀ , 6 ₁ ,... 64 The total required memory capacity corresponding to the resolution of ₄ × number of display frames per second × 2 (9)

[Transfer speed of internal memory 10]
In the internal memory 10, writing / reading of the decoding result of the compression encoded data in the drawing unit 8, writing / reading of drawing data in the drawing unit 8, reading out to the transfer unit 9 and the like are performed simultaneously. Therefore, those processes need to be performed without delay.

  Here, the speed required for writing to and reading from the internal memory 10 will be examined on the basis of the layer of image data.

<When the number of image layers is 1>
In this example, the following processing is performed.
[Procedure A]
(Procedure 01) The encoded data stored in the second auxiliary storage device 3 is decoded by the drawing unit 8, and the layer data as the decoding result is written in the layer data storage unit 120 of the internal memory 10 (procedure 02). The drawing unit 8 reads the layer data stored in the layer data storage unit 120 of the memory 10 (step 03), and the drawing unit 8 reads the image data stored in the frame buffer 110 (step 04). , And the combined image data is written to the frame buffer 110 (step 05). The image data stored in the frame buffer 110 is read, transferred to the external memory 4 through the transfer unit 9, and written to the external memory 4. If the total processing speed of the two processes that are read is “1”, the process of [Procedure A] is performed. Since the access to the internal memory 10 occurs five times in total as described in the above steps 01 to 05, the writing and reading speed is 2.5 times that of the external memory 4 (= 5 access / 2 access). This is necessary (see arrow 200 in FIG. 3).

<When the number of image layers is 2>
In this case, since decoding of the encoded data is performed for each layer, writing of the decoding result and reading of the decoding result are performed twice, and one frame of image data for which drawing has been completed is transferred via the transfer unit 9. Reading for storing in the external memory 4 is also performed once. On the other hand, the combination of the layer data stored in the layer data storage unit 120 of the internal memory 10 and the image data in the frame buffer may be performed for each layer or may not be performed for each layer. In some cases, the image data is stored in the data storage unit 120 and combined with the image data in the frame buffer 110 after all layer data is stored.

Therefore, a procedure when the drawing unit 8 combines all layers at once is described as [Procedure B], and a procedure when combining for each layer is described as [Procedure C].
[Procedure B]
(Procedure 11) The encoded data stored in the second auxiliary storage device 3 is decoded by the drawing unit 8, and the first layer data as the decoding result is written in the layer data storage unit 120 of the internal memory 10 (procedure 12). ) The encoded data stored in the second auxiliary storage device 3 is decoded by the drawing unit 8, and the second layer data as the decoding result is written in the layer data storage unit 120 of the internal memory 10 (in this case, (The layer data storage unit 120 needs a capacity for storing the first layer data and the second layer data.)
(Procedure 13) The drawing unit 8 reads the image data stored in the frame buffer 110 (Procedure 14) and reads the first layer data stored in the layer data storage unit 120 of the internal memory 10 (Procedure 15). The second layer data stored in the layer data storage unit 120 is read (step 16), the image data read in steps 23 to 24, the first and second layer data are combined, and the combined image data is combined with the frame buffer 110. (Procedure 17) The image data stored in the frame buffer 110 is read and transferred to the external memory 4 via the transfer unit 9. And in this case, the total of the two processes of writing to and reading from the external memory 4 If the processing speed is set to “1”, access to the internal memory 10 is increased in order to perform the processing of [Procedure B]. Since a total of seven times occurs as described in steps 11 to 17, the writing / reading speed is required to be 3.5 times that of the external memory 4 (= 7 access / 2 access) (arrow 300 in FIG. 3). reference).
[Procedure C]
(Procedure 21) The encoded data stored in the second auxiliary storage device 3 is decoded by the drawing unit 8, and the first layer data as the decoding result is written in the layer data storage unit 120 of the internal memory 10 (procedure 22). The drawing unit 8 reads the first layer data stored in the layer data storage unit 120 of the internal memory 10 (procedure 23). The drawing unit 8 reads the image data stored in the frame buffer 110 (procedure 24). The layer data and the image data are combined, and the combined first image data is written into the frame buffer 110 (procedure 25). The encoded data stored in the second auxiliary storage device 3 is decoded by the drawing unit 8, and the decoding is performed. The second layer data as a result is written into the layer data storage unit 120 of the internal memory 10 (the first layer data can be overwritten).
(Procedure 26) The drawing unit 8 reads the second layer data stored in the layer data storage unit 120 of the internal memory 10 (procedure 27). The drawing unit 8 reads the first image data stored in the frame buffer 110 ( Step 28) The first layer data and the first image data are combined, the combined second image data is written to the frame buffer 110 (Step 29), the second image data stored in the frame buffer 110 is read, and the transfer unit Then, when the total processing speed of the two processes of writing and reading to the external memory 4 is “1”, the process of [Procedure C] is performed to the internal memory 10. As described in Procedure 21 to Procedure 29 above, a total of 9 accesses occur, so the writing and reading speed is 4.5 times that of the external memory 4 ( = 9 access / 2 access) (see arrow 400 in FIG. 3).

FIG. 3 shows the relationship between the read / write speeds of the external memory 4 and the internal memory 10 for performing processing appropriately calculated for each layer of the image data, calculated based on operations such as the procedure A to the procedure C. FIG. In summary, the magnification of the writing / reading speed (first bandwidth) of the internal memory 10 with respect to the writing / reading speed (second bandwidth) of the external memory 4 is expressed by the following equation (10). Calculated.

Number of layers + 1.5 ≦ rate of speed (first bandwidth / second bandwidth) ≦ number of layers × 2 + 2.5 (10)

As described above, when the layers are combined for each layer, the capacity of the layer data storage unit is sufficient to store the layer data of the maximum resolution image, and a plurality of layer data is handled. However, layer data may be overwritten in order, but when combining layers, it is necessary to keep storing each layer data in the layer data storage until the combining process is performed. A capacity capable of storing all the layer data is required.

  The number of layers in the above embodiment refers to the number of layers having the same amount of data as the size of the frame buffer in the frame in which the number of drawn pixels is the maximum among the contents displayed on the plurality of display devices by the image processing system. The number of drawings is assumed. Therefore, when one layer is divided into a plurality of small layers, the above formula (10) is not satisfied. In such a case, a plurality of divided small layers having the same size as the capacity of the frame buffer are set to 1 The above condition is satisfied by considering it as a layer.

[Processing procedure]
FIG. 4 is a flowchart showing a processing procedure of the image processing system 1A according to this embodiment. FIG. 5 schematically shows the procedure on a functional block diagram. The processing procedure of the image processing system 1A according to this embodiment will be described below with reference to FIG. For simplicity of explanation, creation order of the image data display section _{6 0,} 6 1, the order of ... _{6 4,} also, each of the display section _{6 0,} 6 1, displayed ... _{6 4} A case where the image to be processed is one layer will be described below.

First, the control unit 7 reads a program for controlling the image processing system 1 </ b> A from the first auxiliary storage device 2. Based on this program, the control unit 7 causes the drawing unit 8 and the transfer unit 9 to generate image data as described below and display units 6 ₀ , 6 ₁ ,... 6 based on the generated image data. ₄ is controlled to display an image (step S1).

When image data is requested from the upper control unit of the gaming machine 100, the control unit 7 outputs a display list for drawing the image data to the drawing unit 8, and the drawing unit 8 stores the display list in the internal memory 10. to ensure the capacity required for the image data processing to be output to the display section 6 ₀ as the frame buffer 110 (step S1). For example, if an image of 4K2K displayed on the display unit _{6 0,} to ensure more capacitance 283.1Mb as a frame buffer 110.

Next, the drawing unit 8 reads the encoded image content data from the second auxiliary storage device 3, decodes and stores the data as layer data in the layer data storage unit 120 of the internal memory 10, and further stores the layer data The layer data of the unit 120 and the image data of the frame buffer 110 are read and combined, and the image data is written to the frame buffer 110 (step S2).
Then, the transfer unit 9, and transfers the image data stored in the frame buffer 110 of one frame of the internal memory 10 storage areas of the external memory 4, for example, the first region 161 0 storage area 16 _0, to (step S3).

  Next, the drawing unit 8 releases the area of the internal memory 10 used as the frame buffer 110 (step S4).

The rendering unit 8 ensures the capacity necessary for image data processing to be output to the display unit ₆₁ as a frame buffer 110, the number of images to generate the step S4 from the same step S1, i.e., the display unit step S1~S4 repeated only a few ( "No" in step S5), and the display unit ₆₁ to generate image data for constituting the image to be displayed respectively on ... _{6 4.}

At this time, in the process corresponding to step S1, in the case shown in the <Table 1>, the drawing unit 8, the image data constituting an image of a Full HD to be displayed on the display unit 6 _1, ... 6 ₄ In order to generate the drawing data, a capacity of about 70 Mb is secured as the frame buffer 110 in the internal memory 10 and drawing data is generated. And the process corresponding to step S2-S4 is repeated.

By repeating 4 more times the processing in step S1 to S4, all the display section ₆ 0, one of the storage areas of the drawing data displayed in ... _{6 4} external memory 4, for example, the first region ₁₆₁ 0, 161 _1, is stored in the ... 161 _4, a state in which image data is generated, all the display section ₆ 0,... _{6 4} of the image data generation is completed (step S5 "Yes").

Step S5 is a "Yes", after all of the display section ₆ 0, the image data to be displayed on ... _{6 4} is stored in the external memory 4, the display unit _{6 0,} 6 1, ... 6 the image display circuit ₁₄ 0 ₄ display _timing, 14 1, 14 ₄ reads the image data from the external memory 4, the image display circuit _{14 0,} 14 1, ... 14 _4, the data transmission unit image data acquired 15 _{0, 15} 1, ... 15 ₄ display section ₆ 0 through ₆ 1, and sent to ... _{6 4,} the display unit _{6 0,} 6 1, is an image displayed on ... _{6 4} (step S6). When each display unit 6 ₀ , 6 ₁ ,... 6 ₄ displays one frame at 30 fps, each image display circuit reads necessary image data from the external memory 4 every 33.3 msec.

As described above, the capacity of the internal memory 10, the capacity of the external memory 4, the transfer speed of the internal data bus 13 and the external data bus 5, the control of the drawing unit 8, the display circuit unit 11 and the image display circuits 14 ₀ , 14 ₁ , · · · 14 _n control, etc. by performing the, while suppressing the capacity of the frame buffer 110 for expensive internal memory 10 in one screen of any one of the display unit for example, the display section 6 _0, a plurality of display portions 6 ₀ , 6 ₁ ,... 6 _n can be drawn and displayed at a high speed.

Above, in this embodiment, the internal memory 10, the drawing unit 8, a plurality of display portions 6 _0, 6 _1, by drawing the image displayed in at least one of · · · 6 _n image configured to use as a drawing area for generating data, the external memory 4, the display unit 6 _0, 6 _1, configured as used as a storage area for image data of an image displayed on · · · 6 _n As a result, a plurality of image data necessary for display is generated using the high access speed of the internal memory 10, and the generated plurality of image data is stored in the external memory 4. Since the image data is supplied to the units 6 ₀ , 6 ₁ ,... 6 _n , it is possible to prevent the capacity of the internal memory 10 from becoming excessive.

In In this embodiment, the frame buffer 110 in the internal memory 10, the display section 6 _0, 6 _1, the total number of pixels among the · · · 6 _n or more data volume per frame displayed largest of Since the internal memory 10 is formed to have a capacity equal to or less than the sum of the data amount of one frame displayed on all the display units (for example, the display unit 6 ₀ ), all the display units 6 ₀ , 6 ₁ ,. - image data to be displayed in 6 _n may be configured as a space required to send to the external memory 4 to generate a high speed. Further, the external memory 4, by being formed to a total capacity of more than the data volume per frame displayed by all of the display unit _{6 0, 6 1, ··· 6} n, the external memory 4, respectively of the display unit _{6 0,} 6 1, the image data to be displayed on · · · _{6 n,} the display section _{6 0,} 6 1, as the capacity required to form concurrently every · · · _{6 n} Can be configured. Thereby, when displaying an image on a plurality of screens simultaneously, it is possible to provide an image processing system 1A that can perform image formation and image display at a high speed and suppress an increase in manufacturing cost.

  In this embodiment, the external memory 4 can perform temporary storage of image data by double buffering and transmission of temporarily stored image data. Transmission can be performed continuously and at high speed. Thereby, when displaying an image on a plurality of screens simultaneously, it is possible to provide an image processing system 1A that can perform image formation and image display at a high speed and suppress an increase in manufacturing cost.

In this embodiment, the internal data bus 13, and / or, the bandwidth of the external data bus 5, the generation of the image data and the display section 6 _0, 6 _1, the display of an image in · · · 6 _n consecutive When the configuration of drawing data using the internal memory 10 and the generation of image data using the external memory 4 are performed, the data transmission from the internal memory 10 to the external memory 4 and the external memory 4 are performed. ₁₄ 0 of the display circuit 11 _from, 14 1, continuously sending data to · · · 14 _n, and it is possible to perform simultaneously in parallel. Thereby, when displaying an image on a plurality of screens simultaneously, it is possible to provide an image processing system 1A that can perform image formation and image display at a high speed and suppress an increase in manufacturing cost.

  In this embodiment, when RAMs capable of reading and writing data and random access to recorded data are used for the internal memory 10 and the external memory 4 respectively, and images are displayed simultaneously on a plurality of screens. Thus, it is possible to configure the image processing system 1A that can perform image formation and image display at a high speed and suppress an increase in manufacturing cost.

  In this embodiment, when images are simultaneously displayed on a plurality of screens using the image processing system 1A of the present invention, image formation and image display can be performed at a high speed and an increase in manufacturing cost is suppressed. A gaming machine 100 that can be provided can be provided.

  In this embodiment, the image processing system 1A of the present invention is used for the gaming machine 100, but the present invention can also be applied to an image processing system 1A used for other than the gaming machine 100.

  In this embodiment, the “drawing area” of the internal memory 10 is the frame buffer 110. However, the present invention is not limited to this, and the area that combines the frame buffer 110 in the internal memory 10 and other configurations is “ It may be a “drawing area”. Specifically, for example, an area obtained by combining the frame buffer 110 and the layer data storage unit 120 may be a “drawing area”. Alternatively, an area other than the frame buffer 110 in the internal memory 10, for example, a layer data storage unit 120 or an area (not shown) other than the layer data storage unit 120 may be used as a “drawing area”.

  The above embodiment is an exemplification of the present invention, and it is needless to say that the present invention is not limited to the above embodiment.

DESCRIPTION OF SYMBOLS 1A ... Image processing system 4 ... External memory 5 ... External data bus (transmission / reception means)
6 ₀ , 6 ₁ ,..., 6 ₄ , 6 _n ... Display unit (display means)
8: Drawing section (image forming means)
10: Internal memory (first storage means)
13 ... Internal data bus (transmission / reception means)
14 ₀ , 14 ₁ ,... 14 _n, image display circuit 100, gaming machine 110, frame buffer (drawing area)

Claims (6)

An image processing system for displaying an image on a plurality of display means,
Image forming means for forming an image to be displayed on the display means;
A first storage means used as a drawing area for drawing an image displayed on at least one of the plurality of display means and generating image data by the image forming means;
A plurality of second storage means for storing the image data generated in the first storage means , wherein a quantity corresponding to the quantity of the display means is formed by the image forming means;
A plurality of image display circuits provided corresponding to the respective display means for acquiring the image data from the second storage means and displaying the image data on the respective display means;
For transmitting / receiving the image data between the first storage means and the second storage means, and for transmitting / receiving the image data between the second storage means and the image display circuit. Transmission / reception means,
The first storage means and the plurality of image display circuits are respectively provided in an image processing apparatus main body for generating and displaying the image data, and the second storage means is provided for the image processing apparatus main body. It is configured to be able to contact and separate,
The first storage means has a higher access speed to recorded data than the second storage means,
The second storage means is configured to have a larger storage capacity of the data than the first storage means ,
The image forming unit moves the image data generated in the first storage unit from the main body of the image processing apparatus to the second storage unit and stores the image data in the second storage unit. The image data stored in the second storage means is moved to the image processing apparatus main body, the moved image data is supplied to the image display circuit, and an image based on the image data is displayed on the display means. an image processing system, characterized in that letting. The drawing area of the first storage means has a data amount of one frame displayed on all of the display means that is greater than or equal to a data amount of one frame displayed on the display means having the maximum total number of pixels. Formed to a capacity less than the sum of
The image processing system according to claim 1, wherein the second storage unit is formed with a capacity that is equal to or greater than a total amount of data of one frame displayed on all the display units. The second storage means is formed in a capacity that is at least twice the total amount of data of one frame displayed on all the display means,
The two or more plural buffer configurations are configured to perform temporary storage by storing the generated image and transmission of the stored image to the image display circuit. Or the image processing system of 2. The first bandwidth for data transmission between the image forming means and the first storage means is relative to the second bandwidth for data transmission between the image display circuit and the second storage means. The following formula (1)
4. The image processing system according to claim 1, wherein the image processing system is configured to have the following relationship.
Number of layers + 1.5 ≦ first bandwidth / second bandwidth ≦ number of layers × 2 + 2.5 (1)   The image processing system according to claim 1, wherein the first storage unit and the second storage unit are each formed by a RAM.   A gaming machine comprising a plurality of display means and using the image processing system according to any one of claims 1 to 5.

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