JP6415479B2 - Exposure apparatus, exposure method, and semiconductor package manufacturing method - Google Patents

Exposure apparatus, exposure method, and semiconductor package manufacturing method Download PDF

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JP6415479B2
JP6415479B2 JP2016109640A JP2016109640A JP6415479B2 JP 6415479 B2 JP6415479 B2 JP 6415479B2 JP 2016109640 A JP2016109640 A JP 2016109640A JP 2016109640 A JP2016109640 A JP 2016109640A JP 6415479 B2 JP6415479 B2 JP 6415479B2
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substrate
semiconductor chip
measurement
height
exposure
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JP2017215484A5 (en
JP2017215484A (en
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真一郎 平井
真一郎 平井
順一 本島
順一 本島
大川　直人
直人 大川
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Canon Inc
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Canon Inc
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Priority to KR1020170067383A priority patent/KR102175554B1/en
Priority to CN201710405957.8A priority patent/CN107450279B/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70358—Scanning exposure, i.e. relative movement of patterned beam and workpiece during imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70608—Monitoring the unpatterned workpiece, e.g. measuring thickness, reflectivity or effects of immersion liquid on resist
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • G03F7/70716—Stages
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • G03F7/70716—Stages
    • G03F7/70725—Stages control
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • G03F7/70733—Handling masks and workpieces, e.g. exchange of workpiece or mask, transport of workpiece or mask
    • G03F7/7075—Handling workpieces outside exposure position, e.g. SMIF box

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

本発明は、露光装置、露光方法、及び物品製造方法に関する。   The present invention relates to an exposure apparatus, an exposure method, and an article manufacturing method.

近年、ＦＯＷＬＰ（Fan Out Wafer Level Packaging）と呼ばれる半導体デバイスのパッケージング方法が、半導体デバイス製造工程に取り入れられてきている。ＦＯＷＬＰにおいては、図１に示すような、前工程処理が終わりダイシングされた複数の半導体チップ１０１を並べてモールド材１０２で固めた基板１００が構成される。このような基板１００は再構成基板ともよばれる。そして、この基板１００に対して、露光装置などによるマイクロリソグラフィ技術を用いて、図２に示すような配線層１０３、電極パッド１０４などが形成される。ＦＯＷＬＰにおいては、図２から分かるように、配線層１０３、電極パッド１０４は、半導体チップ１０１上のみならず、モールド材１０２上にも形成される。   In recent years, a semiconductor device packaging method called FOWLP (Fan Out Wafer Level Packaging) has been incorporated into a semiconductor device manufacturing process. In FOWLP, as shown in FIG. 1, a substrate 100 in which a plurality of diced semiconductor chips 101 are arranged and hardened with a molding material 102 is configured after the pre-process treatment. Such a substrate 100 is also called a reconstructed substrate. Then, a wiring layer 103, an electrode pad 104, and the like as shown in FIG. 2 are formed on the substrate 100 using a microlithography technique using an exposure apparatus or the like. In FOWLP, as can be seen from FIG. 2, the wiring layer 103 and the electrode pad 104 are formed not only on the semiconductor chip 101 but also on the molding material 102.

パッケージングの高密度化のため、特に配線層１０３は微細なものが多く、線幅は数μm程度となる。このため、露光装置を用いてこれらのパターニングを行う場合、基板の高さ方向の位置合わせが重要となる。この高さ方向の位置合わせにおいては、基板の高さをあらかじめ計測し、基板を保持するステージの高さを調整することが一般的である。   In order to increase the packaging density, the wiring layer 103 is particularly fine and the line width is about several μm. For this reason, when performing these patterning using an exposure apparatus, alignment in the height direction of the substrate is important. In this alignment in the height direction, it is common to measure the height of the substrate in advance and adjust the height of the stage that holds the substrate.

しかし、モールド材１０２の平坦化は難しく、図３に示すように、モールド材１０２には、表面の粗さ３ａ、凹み３ｂ、あるいは凸部３ｃなどが存在するため、高精度な基板の高さ計測が難しい。このような課題に対しては、従来、基板の高さ計測により得られた計測値が異常であると判断される場合、基板の高さ方向の位置合わせ制御においてはその計測値を除外するといった対策が行われる。例えば特許文献１は、基板の高さを計測するための複数のセンサで露光領域内の段差形状を計測し、その計測結果に基づき、複数のセンサのうち基板の高さ方向の位置合わせ制御に用いるセンサを選択する技術を開示している。   However, it is difficult to flatten the molding material 102. As shown in FIG. 3, the molding material 102 has a surface roughness 3a, a dent 3b, or a projection 3c. Measurement is difficult. For such problems, conventionally, when it is determined that the measurement value obtained by measuring the height of the substrate is abnormal, the measurement value is excluded in the alignment control in the height direction of the substrate. Measures are taken. For example, Patent Document 1 measures a step shape in an exposure region with a plurality of sensors for measuring the height of a substrate, and performs alignment control in the height direction of the substrate among the plurality of sensors based on the measurement result. A technique for selecting a sensor to be used is disclosed.

特開２００２‐１００５５２号公報JP 2002-100552 A

しかし、従来技術によれば、基板の状態によっては、基板の高さ計測の結果の正常、異常の判断が正しく行われず、不適切な基板の高さ位置合わせが行われ、微細なパターニングができない場合があった。   However, according to the prior art, depending on the state of the substrate, whether the substrate height measurement result is normal or abnormal cannot be determined correctly, improper substrate height alignment is performed, and fine patterning cannot be performed. There was a case.

本発明は、半導体チップとモールド材とを含む基板に形成される配線層の高精度化に有利な技術を提供することを目的とする。   An object of the present invention is to provide a technique advantageous for increasing the accuracy of a wiring layer formed on a substrate including a semiconductor chip and a molding material.

本発明の一側面によれば、切り出されて基板上に配置された半導体チップと、該半導体チップの周囲に配置され、前記基板に対する前記半導体チップの位置を固定する固定材とを有する基板の露光領域を露光する露光装置であって、前記基板を保持して移動するステージと、前記ステージに保持された前記基板の露光領域の複数の計測点であって、前記半導体チップの上に位置する計測点と前記固定材の上に位置する計測点とを含む複数の計測点において前記基板の高さを計測する計測部と、制御部とを有し、前記制御部は、前記基板における前記半導体チップの配置に基づいて、前記複数の計測点のうち前記半導体チップの上に位置する計測点の重みよりも、前記固定材の上に位置する計測点における重みが小さくなるように、前記複数の計測点におけるそれぞれの計測結果に重み付けを行い、該重み付けがされた計測結果に基づいて、前記ステージの高さ及び傾きの少なくともいずれかを制御し、前記ステージの高さ及び傾きの少なくともいずれかが制御された状態で前記半導体チップからの配線を構成するために前記基板の露光領域を露光することを特徴とする露光装置が提供される。 According to an aspect of the present invention, there is provided a substrate having a semiconductor chip cut out and disposed on the substrate, and a fixing member disposed around the semiconductor chip and fixing the position of the semiconductor chip with respect to the substrate. An exposure apparatus that exposes an exposure area, the stage holding and moving the substrate, and a plurality of measurement points of the exposure area of the substrate held on the stage, and positioned on the semiconductor chip A measurement unit that measures the height of the substrate at a plurality of measurement points including a measurement point and a measurement point located on the fixing material; and a control unit, wherein the control unit includes the semiconductor on the substrate. based on the placement of the chip, the plurality of than the weight of the measurement points located on the semiconductor chip of the measuring points, as the weight at the measurement point located on the fixed member is reduced, the plurality of It performs weighting to each of the measurement result in the measurement point, based on the weighted metrology results, control at least one of the height and tilt of the stage, at least one of the height and tilt of the stage An exposure apparatus is provided that exposes an exposure region of the substrate in order to configure wiring from the semiconductor chip in a controlled state .

本発明によれば、半導体チップとモールド材とを含む基板に形成される配線層の高精度化に有利な技術を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the technique advantageous for the precision improvement of the wiring layer formed in the board | substrate containing a semiconductor chip and a mold material can be provided.

再構成基板を説明する図。The figure explaining a reconfiguration | reconstruction board | substrate. 再構成基板を説明する図。The figure explaining a reconfiguration | reconstruction board | substrate. 再構成基板におけるモールド材の表面の粗さ、凹凸の例を示す図。The figure which shows the example of the roughness of the surface of the molding material in a reconstitution board | substrate, and an unevenness | corrugation. 実施形態における露光装置の構成を示す図。1 is a diagram showing a configuration of an exposure apparatus in an embodiment. 露光領域内のフォーカス計測点の例を示す図。The figure which shows the example of the focus measurement point in an exposure area | region. 半導体チップとフォーカス計測点の配置例を示す図。The figure which shows the example of arrangement | positioning of a semiconductor chip and a focus measurement point. 半導体チップとフォーカス計測点の配置例を示す図。The figure which shows the example of arrangement | positioning of a semiconductor chip and a focus measurement point.

以下、図面を参照して本発明の好適な実施形態について詳細に説明する。なお、本発明は以下の実施形態に限定されるものではなく、本発明の実施に有利な具体例を示すにすぎない。また、以下の実施形態の中で説明されている特徴の組み合わせの全てが本発明の課題解決のために必須のものであるとは限らない。   DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment, It shows only the specific example advantageous for implementation of this invention. Moreover, not all combinations of features described in the following embodiments are indispensable for solving the problems of the present invention.

図４は、実施形態における露光方法を実施する露光装置の構成を示す図である。露光装置は、光源４０１を有する。光源４０１は、i線水銀ランプやエキシマレーザなどで構成されうる。照明光学系４０２は、光源４０１からの光を導光してマスク４０３を照明する。マスク４０３には投影されるべきパターンが描かれている。マスク４０３を通過した光は、投影光学系４０４を通して、基板１００に達する。本実施形態において、基板１００は、ＦＯＷＬＰにより得られた、いわゆる再構成基板である。この再構成基板は、図１に示されるように、前工程処理が終わりダイシングされた１つ以上の半導体チップ１０１を配置し、半導体チップ１０１の周囲にモールド材１０２（例えば、エポキシ樹脂）を配置することにより構成される。そして、この基板１００に対して、露光装置を用いて、図２に示すような配線層１０３、電極パッド１０４などが形成される。ＦＯＷＬＰにおいては、図２から分かるように、配線層１０３、電極パッド１０４は、半導体チップ１０１上のみならず、モールド材１０２上にも形成される。図１では半導体チップ１０１間は配線層１０３で接続されていないが、場合によっては、異なる特性の複数の半導体チップが配線層により接続されるものもある。   FIG. 4 is a view showing the arrangement of an exposure apparatus that performs the exposure method according to the embodiment. The exposure apparatus has a light source 401. The light source 401 can be composed of an i-line mercury lamp, an excimer laser, or the like. The illumination optical system 402 guides the light from the light source 401 and illuminates the mask 403. A pattern to be projected is drawn on the mask 403. The light that has passed through the mask 403 reaches the substrate 100 through the projection optical system 404. In the present embodiment, the substrate 100 is a so-called reconstructed substrate obtained by FOWLP. As shown in FIG. 1, one or more semiconductor chips 101 that have been diced after the pre-process treatment are disposed on the reconstructed substrate, and a molding material 102 (for example, epoxy resin) is disposed around the semiconductor chip 101. It is constituted by doing. Then, a wiring layer 103, an electrode pad 104, and the like as shown in FIG. 2 are formed on the substrate 100 using an exposure apparatus. In FOWLP, as can be seen from FIG. 2, the wiring layer 103 and the electrode pad 104 are formed not only on the semiconductor chip 101 but also on the molding material 102. In FIG. 1, the semiconductor chips 101 are not connected by the wiring layer 103, but in some cases, a plurality of semiconductor chips having different characteristics are connected by the wiring layer.

マスク４０３に描かれたパターンが投影光学系４０４を介して基板１００の表面に投影される。投影されたマスクパターンの像は、あらかじめ基板１００の表面に塗布されていたレジストやポリイミドなどの感光性の材料を反応させる。それを現像することにより、基板１００の表面にパターンが形成される。   A pattern drawn on the mask 403 is projected onto the surface of the substrate 100 via the projection optical system 404. The projected image of the mask pattern is reacted with a photosensitive material such as resist or polyimide previously applied to the surface of the substrate 100. By developing it, a pattern is formed on the surface of the substrate 100.

基板１００は、基板を保持して移動する基板ステージ４０５に保持されており、基板ステージ４０５をステップ移動させて所定の露光領域を露光することを繰り返して基板１００の表面全体にわたって露光を行うことができる。基板ステージ４０５は、不図示の干渉計やエンコーダなどの位置計測装置を通じて、その位置や姿勢が高精度に管理されており、それによって高精度な重ね合わせ露光を実現している。   The substrate 100 is held by a substrate stage 405 that holds and moves the substrate, and the entire surface of the substrate 100 can be exposed by repeatedly moving the substrate stage 405 to expose a predetermined exposure region. it can. The position and orientation of the substrate stage 405 are managed with high accuracy through a position measuring device such as an interferometer and an encoder (not shown), thereby realizing high-precision overlay exposure.

露光の際は、マスクパターンの像の位置に基板の高さ及び傾きを合わせるため、計測部４０６（例えばフォーカスセンサ）で基板の高さを計測し、その計測結果に基づき、基板ステージ４０５の高さ及び傾きの少なくともいずれかが制御される。なお、以下では、基板ステージ４０５の高さ及び傾きの少なくともいずれかを制御することを、単に「基板の高さ位置合わせ」という場合もある。   At the time of exposure, in order to match the height and tilt of the substrate to the position of the image of the mask pattern, the height of the substrate stage 405 is measured based on the measurement result by measuring the height of the substrate with a measurement unit 406 (for example, a focus sensor). At least one of the height and the inclination is controlled. In the following description, controlling at least one of the height and inclination of the substrate stage 405 may be simply referred to as “substrate height alignment”.

なお、図４において、計測部４０６は光学的な検出を行うフォーカスセンサとして描かれているが、これに限らず、静電容量センサや圧力センサ等を用いた他の検出方式でもよい。基板の高さ及び傾きを計測するため、図５に示すように、露光領域５０１内には計測部４０６によってフォーカス状態が計測される複数の計測点５０２が含まれる。図５では９つの計測点５０２が格子状に配置されているが、配置数、配置位置はこれに限定されない。   In FIG. 4, the measurement unit 406 is depicted as a focus sensor that performs optical detection. However, the measurement unit 406 is not limited thereto, and may be another detection method using a capacitance sensor, a pressure sensor, or the like. In order to measure the height and inclination of the substrate, a plurality of measurement points 502 at which the focus state is measured by the measurement unit 406 are included in the exposure region 501 as shown in FIG. In FIG. 5, nine measurement points 502 are arranged in a grid pattern, but the number of arrangements and the arrangement positions are not limited to this.

また、計測部４０６、基板ステージ４０５、投影光学系４０４などは、制御部４０７に接続されている。制御部４０７は、不図示の記憶部を含み、計測部４０６で計測された基板の高さや傾きの情報など種々の情報を記憶するとともに、基板ステージ４０５などに駆動指令を出して制御する。制御部４０７は、例えば、基板ステージ４０５をステップ移動させて露光領域５０１を露光することを繰り返して基板全体を露光する、いわゆるステップアンドリピート方式で露光を行うよう制御することができる。   In addition, the measurement unit 406, the substrate stage 405, the projection optical system 404, and the like are connected to the control unit 407. The control unit 407 includes a storage unit (not shown), stores various information such as information on the height and tilt of the substrate measured by the measurement unit 406, and controls the substrate stage 405 and the like by issuing a drive command. For example, the control unit 407 can control to perform exposure by a so-called step-and-repeat method in which the entire substrate is exposed by repeatedly moving the substrate stage 405 to expose the exposure region 501.

本実施形態における露光装置の構成は概ね以上のとおりである。以下、この露光装置による露光方法を説明する。   The configuration of the exposure apparatus in the present embodiment is generally as described above. Hereinafter, an exposure method using this exposure apparatus will be described.

制御部４０７は、露光領域５０１の大きさ及び位置の情報、及び、露光領域５０１における計測点５０２の位置の情報を、あらかじめ保持している。通常、図６に示すように、半導体チップ１０１に対し露光領域５０１の方が大きく、１つの露光領域５０１に半導体チップ１０１が複数含まれる。つまりこの場合には、１回の露光で複数の半導体チップが同時に露光されうる。   The control unit 407 holds in advance information on the size and position of the exposure area 501 and information on the position of the measurement point 502 in the exposure area 501. Normally, as shown in FIG. 6, the exposure region 501 is larger than the semiconductor chip 101, and a plurality of semiconductor chips 101 are included in one exposure region 501. That is, in this case, a plurality of semiconductor chips can be exposed simultaneously by one exposure.

制御部４０７には、基板１００における半導体チップ１０１の配置に関する設計データが入力される。設計データは例えば、不図示の操作画面を介してユーザにより入力され、制御部４０７の記憶部に記憶される。設計データは、例えば、個々の半導体チップ１０１のサイズ及び基板１００における配置位置の情報、または、半導体チップ１０１の外形形状の情報を含む。制御部４０７は、複数の計測点のそれぞれが、半導体チップ１０１の上に位置するかモールド材１０２の上に位置するかを判定する。これは、例えば、露光領域５０１の大きさ及び位置、露光領域５０１における計測点５０２の位置等の既知の情報と、入力された設計データに含まれる半導体チップ１０１のサイズ及び配置位置の情報とに基づいて判定される。図６においては、半導体チップ１０１上に位置する計測点が６０１で、モールド材１０２上に位置する計測点が６０２で示されている。例えば、９個の計測点５０２が図５に示されるように配置されている場合、図６に示されるように、それらのうち４個の計測点６０１が半導体チップ１０１上に位置し、５個の計測点６０２がモールド材１０２上に位置する。   Design data relating to the arrangement of the semiconductor chip 101 on the substrate 100 is input to the control unit 407. For example, the design data is input by the user via an operation screen (not shown) and stored in the storage unit of the control unit 407. The design data includes, for example, information on the size of each semiconductor chip 101 and the arrangement position on the substrate 100, or information on the outer shape of the semiconductor chip 101. The control unit 407 determines whether each of the plurality of measurement points is located on the semiconductor chip 101 or the mold material 102. This includes, for example, known information such as the size and position of the exposure area 501 and the position of the measurement point 502 in the exposure area 501, and information on the size and arrangement position of the semiconductor chip 101 included in the input design data. Based on the determination. In FIG. 6, the measurement point located on the semiconductor chip 101 is indicated by 601, and the measurement point located on the molding material 102 is indicated by 602. For example, when nine measurement points 502 are arranged as shown in FIG. 5, four measurement points 601 are located on the semiconductor chip 101 as shown in FIG. The measurement point 602 is located on the mold material 102.

前述の通り、モールド材１０２の平坦化は難しく、半導体チップ１０１に比べて、表面が粗い、凹凸があるため、高精度な基板の高さ計測が難しいという課題がある。そこで本実施形態の露光方法においては、制御部４０７が半導体チップ１０１上に位置する計測点での計測結果のみに基づいて、露光時の基板の高さ位置合わせを実施する。半導体チップ１０１に比べて平坦ではないモールド材１０２上の計測点６０２の計測結果を露光時の基板の高さ位置合わせに用いないことで、高精度なフォーカス制御が可能であり、微細な配線層の形成を実現することができる。   As described above, it is difficult to planarize the molding material 102, and there is a problem that it is difficult to measure the height of the substrate with high accuracy because the surface is rough and uneven as compared with the semiconductor chip 101. Therefore, in the exposure method of the present embodiment, the control unit 407 performs the height alignment of the substrate at the time of exposure based only on the measurement result at the measurement point located on the semiconductor chip 101. By not using the measurement result of the measurement point 602 on the mold material 102 that is not flat compared to the semiconductor chip 101 for the height alignment of the substrate at the time of exposure, high-precision focus control is possible, and a fine wiring layer Can be realized.

図６では、１つの露光領域５０１に半導体チップ１０１が複数含まれる例を示したが、図７のように、１つの露光領域５０１に含まれる半導体チップ１０１が１つだけの場合でも、上記と同様の方法を適用することができる。図７の例においても、制御部４０７は、複数の計測点のそれぞれについて、半導体チップ１０１上に位置するかモールド材１０２上に位置するかを判定する。   FIG. 6 shows an example in which a plurality of semiconductor chips 101 are included in one exposure region 501, but even when only one semiconductor chip 101 is included in one exposure region 501 as shown in FIG. Similar methods can be applied. Also in the example of FIG. 7, the control unit 407 determines whether each of the plurality of measurement points is located on the semiconductor chip 101 or the mold material 102.

上述の説明では、制御部４０７が半導体チップ１０１上に位置する計測点の計測結果のみに基づき、露光時の基板の高さ位置合わせを実施するようにした。しかし、モールド材１０２上に位置する計測点の計測結果を完全に無効とはせず、複数の計測点におけるそれぞれの計測結果に重み付けを行い、該重み付けがされた計測結果に基づいて、前記基板の高さ及び傾きの少なくともいずれかを制御するようにしてもよい。例えば、半導体チップ１０１上に位置する計測点よりも、モールド材１０２上に位置する計測点の計測結果に対する重みを小さくする。こうすることで、例えば半導体チップ１０１上に位置する計測点の数が十分に確保できない場合に、モールド材１０２上に位置する計測点が重みを小さくした上で利用され、基板の高さ位置合わせの精度を維持することができる。なお、上述の説明のようにモールド材１０２上に位置する計測点の計測結果を完全に無効とする場合には、モールド材１０２上に位置する計測点の計測結果に対する重みを０にすればよい。これにより、該計測点の計測結果が除外される。また、半導体チップ１０１の配置に関する設計データに基づいて、計測部４０６による複数の計測点５０２が半導体チップ１０１上にのみ配置されるように計測部４０６を調整してもよい。また、半導体チップ１０１の配置に関する設計データに基づいて、半導体チップ１０１上の計測点５０２を追加して、計測点の数を増やして、計測してもよい。   In the above description, the control unit 407 performs the height alignment of the substrate at the time of exposure based only on the measurement result of the measurement points located on the semiconductor chip 101. However, the measurement results at the measurement points located on the mold material 102 are not completely invalidated, and the measurement results at the plurality of measurement points are weighted, and the substrate is based on the weighted measurement results. It is also possible to control at least one of the height and the inclination. For example, the weight for the measurement result of the measurement point located on the mold material 102 is made smaller than the measurement point located on the semiconductor chip 101. By doing so, for example, when the number of measurement points located on the semiconductor chip 101 cannot be sufficiently secured, the measurement points located on the mold material 102 are used with a reduced weight, and the height alignment of the substrate is performed. Accuracy can be maintained. When the measurement result of the measurement point located on the molding material 102 is completely invalidated as described above, the weight for the measurement result of the measurement point located on the molding material 102 may be set to 0. . Thereby, the measurement result of the measurement point is excluded. The measurement unit 406 may be adjusted so that a plurality of measurement points 502 by the measurement unit 406 are arranged only on the semiconductor chip 101 based on design data regarding the arrangement of the semiconductor chip 101. Further, measurement may be performed by adding measurement points 502 on the semiconductor chip 101 and increasing the number of measurement points based on design data related to the arrangement of the semiconductor chip 101.

＜物品製造方法の実施形態＞
本発明の実施形態に係る物品製造方法は、例えば、半導体デバイス等のマイクロデバイスや微細構造を有する素子等の物品を製造するのに好適である。本実施形態の物品製造方法は、基板に塗布された感光剤に上記の露光装置を用いて潜像パターンを形成する工程（基板を露光する工程）と、かかる工程で潜像パターンが形成された基板を現像する工程とを含む。更に、かかる製造方法は、他の周知の工程（酸化、成膜、蒸着、ドーピング、平坦化、エッチング、レジスト剥離、ダイシング、ボンディング、パッケージング等）を含む。本実施形態の物品製造方法は、従来の方法に比べて、物品の性能・品質・生産性・生産コストの少なくとも１つにおいて有利である。 <Embodiment of article manufacturing method>
The article manufacturing method according to the embodiment of the present invention is suitable for manufacturing an article such as a micro device such as a semiconductor device or an element having a fine structure. In the article manufacturing method of the present embodiment, a latent image pattern is formed on the photosensitive agent applied to the substrate using the above-described exposure apparatus (a step of exposing the substrate), and the latent image pattern is formed in this step. Developing the substrate. Further, the manufacturing method includes other well-known steps (oxidation, film formation, vapor deposition, doping, planarization, etching, resist stripping, dicing, bonding, packaging, and the like). The article manufacturing method of this embodiment is advantageous in at least one of the performance, quality, productivity, and production cost of the article as compared with the conventional method.

１００：基板、４０１：光源、４０２：照明光学系、４０３：マスク、４０４：投影光学系、４０５：基板ステージ、４０６：計測部、４０７：制御部 100: substrate, 401: light source, 402: illumination optical system, 403: mask, 404: projection optical system, 405: substrate stage, 406: measurement unit, 407: control unit

Claims (14)

切り出されて基板上に配置された半導体チップと、該半導体チップの周囲に配置され、前記基板に対する前記半導体チップの位置を固定する固定材とを有する基板の露光領域を露光する露光装置であって、
前記基板を保持して移動するステージと、
前記ステージに保持された前記基板の露光領域の複数の計測点であって、前記半導体チップの上に位置する計測点と前記固定材の上に位置する計測点とを含む複数の計測点において前記基板の高さを計測する計測部と、
制御部と、
を有し、
前記制御部は、前記基板における前記半導体チップの配置に基づいて、前記複数の計測点のうち前記半導体チップの上に位置する計測点の重みよりも、前記固定材の上に位置する計測点における重みが小さくなるように、前記複数の計測点におけるそれぞれの計測結果に重み付けを行い、該重み付けがされた計測結果に基づいて、前記ステージの高さ及び傾きの少なくともいずれかを制御し、
前記ステージの高さ及び傾きの少なくともいずれかが制御された状態で前記半導体チップからの配線を構成するために前記基板の露光領域を露光することを特徴とする露光装置。 An exposure apparatus that exposes an exposure region of a substrate having a semiconductor chip cut out and disposed on the substrate, and a fixing material disposed around the semiconductor chip and fixing the position of the semiconductor chip with respect to the substrate. And
A stage for holding and moving the substrate;
A plurality of measurement points in the exposure area of the substrate held on the stage, wherein the measurement points include a measurement point located on the semiconductor chip and a measurement point located on the fixing material. A measurement unit for measuring the height of the substrate;
A control unit;
Have
The control unit, based on the arrangement of the semiconductor chip on the substrate, in a measurement point located on the fixing material rather than a weight of the measurement point located on the semiconductor chip among the plurality of measurement points. Weighting each measurement result at the plurality of measurement points so as to reduce the weight , and controlling at least one of the height and inclination of the stage based on the weighted measurement result,
An exposure apparatus that exposes an exposure area of the substrate in order to form a wiring from the semiconductor chip in a state in which at least one of a height and an inclination of the stage is controlled . 前記制御部は、前記固定材の上に位置する計測点の計測結果に対する重みを０にすることにより該計測点の計測結果を除外して前記ステージの高さ及び傾きの少なくともいずれかを制御することを特徴とする請求項１に記載の露光装置。   The control unit controls at least one of the height and the tilt of the stage by excluding the measurement result of the measurement point by setting the weight to the measurement result of the measurement point located on the fixed material to 0. The exposure apparatus according to claim 1, wherein: 前記制御部は、前記半導体チップのサイズ及び前記基板における前記半導体チップの位置の少なくとも一方を示す情報に基づいて、前記重み付けを行うことを特徴とする請求項１または２に記載の露光装置。 The control unit, on the basis of the semiconductor chip size and information indicating at least one of the position of said semiconductor chip in said substrate, the exposure apparatus according to claim 1 or 2, characterized in that the weighting. 前記制御部は、
前記露光領域における前記複数の計測点の位置と、前記半導体チップのサイズ及び前記基板における前記半導体チップの位置の少なくとも一方を示す情報とに基づいて、前記複数の計測点のそれぞれが、前記半導体チップの上に位置するか前記固定材の上に位置するかを判定することを特徴とする請求項３に記載の露光装置。 The controller is
And positions of the plurality of measurement points in the exposure area, on the basis of the information indicating at least one of the position of the semiconductor chip in size and the substrate of the semiconductor chip, each of said plurality of measurement points, the semiconductor an apparatus according to either positioned on the fixed member or located on the chip to claim 3, wherein the stamp Teisu Rukoto. 前記露光領域に、前記半導体チップが複数含まれることを特徴とする請求項１乃至４のいずれか１項に記載の露光装置。   The exposure apparatus according to claim 1, wherein the exposure region includes a plurality of the semiconductor chips. 前記露光領域に含まれる前記半導体チップは１つであることを特徴とする請求項１乃至４のいずれか１項に記載の露光装置。   The exposure apparatus according to claim 1, wherein the number of the semiconductor chips included in the exposure region is one. 前記固定材はモールド材であることを特徴とする請求項１乃至６のいずれか１項に記載の露光装置。   The exposure apparatus according to claim 1, wherein the fixing material is a mold material. 切り出されて基板上に配置された半導体チップと、該半導体チップの周囲に配置され、前記基板に対する前記半導体チップの位置を固定する固定材とを有する基板の露光領域を露光する露光装置であって、
前記基板を保持して移動するステージと、
前記ステージに保持された前記基板の露光領域の複数の計測点であって、前記半導体チップの上に位置する計測点と前記固定材の上に位置する計測点とを含む複数の計測点において前記基板の高さを計測可能な計測部と、
制御部と、
を有し、
前記計測部は、前記複数の計測点のうち、前記半導体チップの上に位置する計測点のみにおいて前記基板の高さを計測し、
前記制御部は、前記計測部によって計測された計測結果に基づいて、前記ステージの高さ及び傾きの少なくともいずれかを制御し、前記ステージの高さ及び傾きの少なくともいずれかが制御された状態で前記半導体チップからの配線を構成するために前記基板の露光領域を露光することを特徴とする露光装置。 An exposure apparatus that exposes an exposure region of a substrate having a semiconductor chip cut out and disposed on the substrate, and a fixing material disposed around the semiconductor chip and fixing the position of the semiconductor chip with respect to the substrate. And
A stage for holding and moving the substrate;
A plurality of measurement points in the exposure area of the substrate held on the stage, wherein the measurement points include a measurement point located on the semiconductor chip and a measurement point located on the fixing material. A measurement unit capable of measuring the height of the substrate;
A control unit;
Have
The measurement unit measures the height of the substrate only at the measurement points located on the semiconductor chip among the plurality of measurement points,
The control unit controls at least one of the height and inclination of the stage based on the measurement result measured by the measurement unit, and is in a state in which at least one of the height and inclination of the stage is controlled. An exposure apparatus that exposes an exposure area of the substrate in order to form wiring from the semiconductor chip . 前記制御部は、前記半導体チップのサイズ及び前記基板における前記半導体チップの位置の少なくとも一方を示す情報に基づいて、前記複数の計測点のうちの着目する計測点が前記半導体チップの上に位置するか否かを判定することを特徴とする請求項８に記載の露光装置。 The control unit, on the basis of the semiconductor chip size and information indicating at least one of the position of said semiconductor chip in said substrate, located on the focus measuring points of the plurality of measurement points of the semiconductor chip The exposure apparatus according to claim 8, wherein it is determined whether or not to perform. 前記固定材はモールド材であることを特徴とする請求項８または９に記載の露光装置。   The exposure apparatus according to claim 8, wherein the fixing material is a mold material. 切り出されて基板上に配置された半導体チップと、該半導体チップの周囲に配置され、前記基板に対する前記半導体チップの位置を固定する固定材とを有する基板の露光領域を露光する露光方法であって、
ステージに保持された前記基板の露光領域の複数の計測点であって、前記半導体チップの上に位置する計測点と前記固定材の上に位置する計測点とを含む複数の計測点において前記基板の高さを計測する工程と、
前記基板における前記半導体チップの配置に基づいて、前記複数の計測点のうち前記半導体チップの上に位置する計測点における計測結果の重みよりも、前記固定材の上に位置する計測点における計測結果の重みが小さくなるように、前記複数の計測点におけるそれぞれの計測結果に重み付けを行う工程と、
前記重み付けがされた計測結果に基づいて、前記ステージの高さ及び傾きの少なくともいずれかを制御する工程と、
前記ステージの高さ及び傾きの少なくともいずれかが制御された状態で前記半導体チップからの配線を構成するために前記基板の露光領域を露光する工程と、
を有することを特徴とする露光方法。 An exposure method for exposing an exposure region of a substrate having a semiconductor chip cut out and disposed on the substrate, and a fixing material disposed around the semiconductor chip and fixing the position of the semiconductor chip with respect to the substrate. And
The substrate at a plurality of measurement points which are a plurality of measurement points in the exposure area of the substrate held on a stage, including measurement points located on the semiconductor chip and measurement points located on the fixing material. The process of measuring the height of
Based on the arrangement of the semiconductor chip on the substrate, the measurement result at the measurement point located on the fixing material rather than the weight of the measurement result at the measurement point located on the semiconductor chip among the plurality of measurement points. Weighting each measurement result at the plurality of measurement points so that the weight of
Controlling at least one of the height and inclination of the stage based on the weighted measurement result;
Exposing an exposure area of the substrate to configure wiring from the semiconductor chip in a state in which at least one of the height and inclination of the stage is controlled;
An exposure method comprising: 切り出されて基板上に配置された半導体チップと、該半導体チップの周囲に配置され、前記基板に対する前記半導体チップの位置を固定する固定材とを有する基板の露光領域を露光する露光方法であって、
ステージに保持された前記基板の露光領域の複数の計測点のうち、前記半導体チップの上に位置する計測点のみにおいて前記基板の高さを計測する工程と、
前記計測された計測結果に基づいて、前記ステージの高さ及び傾きの少なくともいずれかを制御する工程と、
前記ステージの高さ及び傾きの少なくともいずれかが制御された状態で前記半導体チップからの配線を構成するために前記基板の露光領域を露光する工程と、
を有することを特徴とする露光方法。 An exposure method for exposing an exposure region of a substrate having a semiconductor chip cut out and disposed on the substrate, and a fixing material disposed around the semiconductor chip and fixing the position of the semiconductor chip with respect to the substrate. And
Of the plurality of measurement points of the exposure area of the substrate held on the stage, the step of measuring the height of the substrate only at the measurement points located on the semiconductor chip;
Controlling at least one of the height and inclination of the stage based on the measured measurement result;
Exposing an exposure area of the substrate to configure wiring from the semiconductor chip in a state in which at least one of the height and inclination of the stage is controlled;
An exposure method comprising: 切り出されて基板上に配置された半導体チップと、前記半導体チップの周囲に配置され、前記基板に対する前記半導体チップの位置を固定する固定材とを有する基板に対して、前記半導体チップからの配線を構成することで半導体パッケージを製造する方法であって、
ステージに保持された前記基板の露光領域の複数の計測点であって、前記半導体チップの上に位置する計測点と前記固定材の上に位置する計測点とを含む複数の計測点において前記基板の高さを計測する工程と、
前記基板における半導体チップの配置に基づいて、前記複数の計測点のうち前記半導体チップの上に位置する計測点における計測結果の重みよりも、前記固定材の上に位置する計測点における計測結果の重みが小さくなるように、前記複数の計測点におけるそれぞれの計測結果に重み付けを行う工程と、
前記重み付けがされた計測結果に基づいて、前記ステージの高さ及び傾きの少なくともいずれかを制御する工程と、
前記ステージの高さ及び傾きの少なくともいずれかが制御された状態で前記半導体チップからの配線を構成するために前記基板の露光領域を露光する工程と、
を有することを特徴とする半導体パッケージの製造方法。 Cut out a semiconductor chip disposed on the substrate, disposed around the semiconductor chip to the substrate and a fixing member for fixing the position of said semiconductor chip to said substrate, wiring from the semiconductor chip a method of manufacturing a semi-conductor package by configuring,
The substrate at a plurality of measurement points which are a plurality of measurement points in the exposure area of the substrate held on a stage, including measurement points located on the semiconductor chip and measurement points located on the fixing material. The process of measuring the height of
Based on the arrangement of the semiconductor chip on the substrate, the measurement result at the measurement point located on the fixing material is more than the weight of the measurement result at the measurement point located on the semiconductor chip among the plurality of measurement points. Weighting each measurement result at the plurality of measurement points so as to reduce the weight ; and
Controlling at least one of the height and inclination of the stage based on the weighted measurement result;
Exposing an exposure area of the substrate to configure wiring from the semiconductor chip in a state in which at least one of the height and inclination of the stage is controlled;
A method for manufacturing a semiconductor package, comprising: 切り出されて基板上に配置された半導体チップと、前記半導体チップの周囲に配置され、前記基板に対する前記半導体チップの位置を固定する固定材とを有する基板に対して、前記半導体チップからの配線を構成することで半導体パッケージを製造する方法であって、
ステージに保持された前記基板の露光領域の複数の計測点のうち、前記半導体チップの上に位置する計測点のみにおいて前記基板の高さを計測する工程と、
前記計測された計測結果に基づいて、前記ステージの高さ及び傾きの少なくともいずれかを制御する工程と、
前記ステージの高さ及び傾きの少なくともいずれかが制御された状態で前記半導体チップからの配線を構成するために前記基板の露光領域を露光する工程と、
を有することを特徴とする半導体パッケージの製造方法。 Cut out a semiconductor chip disposed on the substrate, disposed around the semiconductor chip to the substrate and a fixing member for fixing the position of said semiconductor chip to said substrate, wiring from the semiconductor chip a method of manufacturing a semi-conductor package by configuring,
Among the plurality of measurement points in the exposure area of the substrate held on the stage, a step of measuring the height of the substrate at only the measurement point located on the front Symbol semiconductors chips,
Controlling at least one of the height and inclination of the stage based on the measured measurement result;
Exposing an exposure area of the substrate to configure wiring from the semiconductor chip in a state in which at least one of the height and inclination of the stage is controlled;
A method for manufacturing a semiconductor package, comprising:
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