JP6390840B2 - Semiconductor device and electronic equipment - Google Patents

Description

  The present invention relates to a semiconductor device and an electronic apparatus.

  In a semiconductor device such as an MCU (Micro Controller Unit) (for example, an IC (Integrated Circuit)), a processor executes a program stored in a memory to realize a desired function. In such a semiconductor device, it is a problem to protect the program from unauthorized use. In Patent Document 1, the debug circuit is disabled during power-on reset to prevent access to security resources (registers, firmware, I / O devices), and is selected during system initialization from the boot memory. When the security code that reads the security procedure is executed and the called security procedure is valid, the system is operated in a secure environment according to the called security procedure, and the called security procedure is not valid. Has proposed a method to enable debugging functions and hide all security functions.

Japanese translation of PCT publication No. 2003-521776

  If the method of Patent Document 1 is applied, the debug circuit that can access the program (firmware) is disabled at the time of power-on reset, so that the program may be protected from unauthorized use. unknown. However, the technique disclosed in Patent Document 1 disables the debug circuit itself, which complicates the circuit for realizing this and increases the size of the semiconductor device. Further, in the technique of Patent Document 1, when the called security procedure is valid, the system is operated in a secure environment (the debug function cannot be used), so that the security procedure is disabled and the program is debugged. There is also a problem that it is difficult to perform sufficient debugging when the security procedure is effective. Note that there is a similar problem not only with protection against unauthorized use of programs, but also with respect to protection against unauthorized use (including unintended use) of an inspection circuit built in a semiconductor device.

  The present invention has been made in view of the above problems, and according to some aspects of the present invention, it is possible to reduce the risk of unauthorized use of a program while reducing an increase in cost. A semiconductor device and an electronic device can be provided. In addition, according to some aspects of the present invention, it is possible to provide a semiconductor device and an electronic device that can be easily debugged while reducing the possibility of unauthorized use of a program. In addition, according to some aspects of the present invention, it is possible to provide a semiconductor device and an electronic device that can reduce the risk of unauthorized use of the inspection circuit while reducing an increase in cost. In addition, according to some aspects of the present invention, it is possible to provide a semiconductor device and an electronic device that can be easily inspected while reducing the possibility of unauthorized use of the inspection circuit.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following aspects or application examples.

[Application Example 1]
A semiconductor device according to this application example is used for non-volatile memory, a processor that executes a program stored in the non-volatile memory, a debug circuit having a debug function of the program, and debugging of the program A first external terminal, a mask circuit for disconnecting electrical connection between the first external terminal and the debug circuit for a predetermined period after reset release, and the predetermined period, and the first circuit after the predetermined period has elapsed. And a control circuit for controlling whether or not to disconnect the electrical connection between the external terminal and the debug circuit.

  According to the semiconductor device of this application example, the electrical connection between the first external terminal and the debug circuit is disconnected by the mask circuit for a predetermined period after the reset is released, and the first external terminal and the debug circuit are disconnected. In the predetermined period in which the electrical connection is disconnected, the control circuit can control the disconnection even after the elapse of the predetermined period, so that the program is illegally used from the first external terminal via the debug circuit. Can reduce the risk. Further, the semiconductor device according to this application example can be realized with a simple configuration in which the electrical connection between the first external terminal and the debug circuit is disconnected by the mask circuit and the control circuit. Therefore, according to the semiconductor device of this application example, it is possible to reduce the risk of unauthorized use of the program while reducing the increase in cost.

  Further, according to the semiconductor device according to this application example, the first circuit after the predetermined period elapses by the control circuit in the predetermined period in which the electrical connection between the first external terminal and the debug circuit is disconnected. Since control is possible so that the external terminal and the debug circuit are electrically connected, the program can be easily debugged from the first external terminal via the debug circuit.

[Application Example 2]
In the semiconductor device according to the application example, when the processor executes a first instruction included in the program in the predetermined period, the control circuit includes the first external terminal even after the predetermined period elapses. And the debug circuit may be disconnected from the electrical connection.

  According to the semiconductor device of this application example, in the program, when the first instruction is incorporated at a position to be executed by the processor in a predetermined period from the reset release, the first instruction is passed even after the predetermined period has elapsed. The electrical connection between the external terminal and the debug circuit is disconnected. Therefore, for example, by incorporating the first instruction at a desired position in the program, the possibility of unauthorized use of the program can be reduced.

[Application Example 3]
The semiconductor device according to the application example further includes an input / output interface circuit for a signal between the first external terminal and the processor, and the control circuit is configured so that the processor executes the first command in the predetermined period. When the above is executed, the first external terminal and the input / output interface circuit may be electrically connected.

  According to the semiconductor device of this application example, in the program, when the first instruction is incorporated at a position to be executed by the processor during a predetermined period after reset release, after the elapse of the predetermined period, The first external terminal and the input / output interface circuit are electrically connected while the electrical connection between the first external terminal and the debug circuit is disconnected. Therefore, the first external terminal can be used both as an external terminal for debugging and an external terminal for input / output interface.

[Application Example 4]
The semiconductor device according to the application example further includes a second external terminal, and the nonvolatile memory erases stored information when a predetermined signal is input to the second external terminal. Also good.

  In the semiconductor device according to this application example, when a predetermined signal is input to the second external terminal, the processor may perform control to erase information stored in the nonvolatile memory.

  According to the semiconductor device of this application example, information stored in the nonvolatile memory can be erased by inputting a predetermined signal to the second external terminal. Therefore, when the first instruction is incorporated at a desired position in the program, the first instruction is erased. Thereafter, after the predetermined period after the reset is released, the first external terminal and the debug are deleted. Since the circuit is electrically connected, it is possible to access information in the nonvolatile memory from the first external terminal. However, since the program is erased, there is no possibility of unauthorized use.

  Further, according to the semiconductor device according to this application example, after the program in which the first instruction is incorporated at a desired position is erased, the first external terminal and the debug circuit are passed after a predetermined period after the reset is released. Are electrically connected to each other, so that information can be written to the nonvolatile memory from the first external terminal. Therefore, for example, the erased program can be rewritten to a non-volatile memory or rewritten with a new program.

[Application Example 5]
In the semiconductor device according to the application example described above, the nonvolatile memory has a plurality of storage areas, and when a predetermined signal is input to the second external terminal, the information is erased for each storage area. The information in the storage area in which the first instruction is stored may be erased last.

  According to the semiconductor device of this application example, if the information stored in the nonvolatile memory is not completely erased, the probability that the first instruction remains without being erased increases. The risk of unauthorized use of information that has not been made can be reduced.

[Application Example 6]
In the semiconductor device according to the application example, the predetermined period may be longer than a time required for the processor to execute the first instruction.

  According to the semiconductor device according to this application example, the processor can execute the first instruction during a predetermined period in which the electrical connection between the first external terminal and the debug circuit is disconnected. Even after the predetermined period has elapsed, the first external terminal and the debug circuit remain disconnected. Therefore, the risk of unauthorized use of the program can be reduced.

[Application Example 7]
In the semiconductor device according to the application example described above, the control circuit may electrically connect the first external terminal and the debug circuit when the processor executes a second instruction.

  According to the semiconductor device of this application example, for example, even when the electrical connection between the first external terminal and the debug circuit is disconnected even after a predetermined period has elapsed since the reset release, the processor outputs the second instruction. By executing, the first external terminal and the debug circuit can be electrically connected. This makes it possible to debug the program from the first external terminal.

In order to reduce the possibility of unauthorized use of the program, for example, when a predetermined signal is input to a predetermined external terminal, the processor executes the second instruction,
Information about the second command, the predetermined external terminal, and the predetermined signal may be disclosed only to authorized users who have the authority to use the program.

[Application Example 8]
The semiconductor device according to this application example disconnects an electrical connection between the inspection circuit, the first external terminal used for the inspection, and the first external terminal and the inspection circuit for a predetermined period after the reset is released. A mask circuit; and a control circuit that controls whether or not to disconnect the electrical connection between the first external terminal and the inspection circuit even after the predetermined period has elapsed in the predetermined period.

  According to the semiconductor device of this application example, the electrical connection between the first external terminal and the inspection circuit is disconnected by the mask circuit for a predetermined period after the reset is released, and the first external terminal and the inspection circuit are disconnected. Since the control circuit can be controlled to disconnect after the lapse of the predetermined period in the predetermined period in which the electrical connection is disconnected, the possibility that the inspection circuit is illegally used from the first external terminal is reduced. Can be made. In addition, the semiconductor device according to this application example can be realized with a simple configuration in which the electrical connection between the first external terminal and the inspection circuit is disconnected by the mask circuit and the control circuit. Therefore, according to the semiconductor device of this application example, it is possible to reduce the risk of unauthorized use of the inspection circuit while reducing the increase in cost.

  Further, according to the semiconductor device according to this application example, the first circuit is disconnected from the first external terminal by the control circuit in the predetermined period after the predetermined period has elapsed. Since the external terminal and the inspection circuit can be controlled to be electrically connected, the semiconductor device can be easily inspected from the first external terminal via the inspection circuit.

[Application Example 9]
The semiconductor device according to the application example further includes a non-volatile memory and a processor that executes a program stored in the non-volatile memory, and the control circuit is configured so that the processor stores the program in the predetermined period. When the included first instruction is executed, the electrical connection between the first external terminal and the inspection circuit may be disconnected even after the predetermined period has elapsed.

  According to the semiconductor device of this application example, in the program, when the first instruction is incorporated at a position to be executed by the processor in a predetermined period from the reset release, the first instruction is passed even after the predetermined period has elapsed. The electrical connection between the external terminal and the inspection circuit is cut off. Therefore, for example, by incorporating the first instruction at a desired position in the program, the possibility of unauthorized use of the inspection circuit can be reduced.

  The semiconductor device according to the application example further includes an input / output interface circuit for a signal between the first external terminal and the processor, and the control circuit is configured such that the processor has the first circuit in the predetermined period. When the above command is executed, the first external terminal and the input / output interface circuit may be electrically connected.

  According to this semiconductor device, in the program, when the first instruction is incorporated at a position to be executed by the processor during a predetermined period from the reset cancellation, the first external terminal after the predetermined period elapses The first external terminal and the input / output interface circuit are electrically connected while disconnecting the electrical connection between the first external terminal and the inspection circuit. Therefore, the first external terminal can be used as an external terminal for inspection and an external terminal for input / output interface.

  In the semiconductor device according to the application example, the predetermined period may be longer than a time required for the processor to execute the first instruction.

  According to the semiconductor device according to this application example, the processor can execute the first instruction during a predetermined period in which the electrical connection between the first external terminal and the inspection circuit is disconnected. Even after the predetermined period has elapsed, the first external terminal and the inspection circuit remain disconnected. Therefore, the risk of unauthorized use of the inspection circuit can be reduced.

  In the semiconductor device according to the application example described above, the control circuit may electrically connect the first external terminal and the inspection circuit when the processor executes a second instruction.

  According to this semiconductor device, for example, even when the electrical connection between the first external terminal and the inspection circuit is disconnected even after a predetermined period has elapsed since reset release, the processor executes the second instruction. The first external terminal and the inspection circuit can be electrically connected. As a result, the semiconductor device can be inspected from the first external terminal.

  In order to reduce the possibility that the inspection circuit is illegally used, for example, when a predetermined signal is input to a predetermined external terminal, the processor executes the second instruction, and the second instruction The information about the predetermined external terminal and the predetermined signal may be disclosed only to an authorized user who has the authority to use the program.

[Application Example 10]
An electronic apparatus according to this application example includes any one of the semiconductor devices described above.

  According to this application example, the semiconductor device can reduce the risk of unauthorized use of the program or the inspection circuit while reducing the increase in cost, so that a highly reliable electronic device can be realized at low cost. .

1 is a diagram illustrating a configuration example of a semiconductor device according to a first embodiment. The figure which shows an example of the program memorize | stored in a non-volatile memory. The figure which shows an example of the timing chart in case a processor runs the program of FIG. The figure which shows an example of the program memorize | stored in a non-volatile memory. The figure which shows an example of the timing chart in case a processor runs the program of FIG. The figure which shows an example of the timing chart in case the information of a non-volatile memory is erased entirely. The figure which shows the structural example of a non-volatile memory. The figure which shows an example of the timing chart in case a debug terminal effective instruction is performed. The figure which shows the structural example of the semiconductor device of 2nd Embodiment. The figure which shows the structural example of the semiconductor device of 3rd Embodiment. 1 is a functional block diagram of an electronic apparatus according to an embodiment. 1 is a diagram illustrating an example of an appearance of an electronic apparatus according to an embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. 1. Semiconductor device 1-1. First Embodiment [Configuration of Semiconductor Device]
FIG. 1 is a diagram illustrating a configuration example of the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a processor 10, a nonvolatile memory 20, a RAM (Random
(Access Memory) 30, reset circuit 40, oscillation circuit 50, GPIO (General Purpose Input Output) circuit 60, debug circuit 70, mask circuit 80, control circuit 90, and bus 100 to which these elements are connected. Yes. Note that the semiconductor device 1 of the present embodiment may have a configuration in which some of these elements are omitted or changed, or other elements are added.

  The semiconductor device 1 may be composed of, for example, a one-chip IC or may be composed of a plurality of chips. The semiconductor device 1 may be, for example, an MCU or an SOC (System On a Chip).

  The semiconductor device 1 is configured to be able to communicate with the host CPU 3 via an external terminal P01 and an external terminal (not shown) for a communication interface (such as a clock terminal and a data terminal). The semiconductor device 1 is configured to be able to communicate with the debug device 2 (device that executes a debugger) via the external terminal DBG.

  The processor 10 executes a program stored in the nonvolatile memory 20 and performs processing according to the program. For example, when the semiconductor device 1 is used for an electronic timepiece, the processor 10 may perform various processes for realizing a time calculation function, a stopwatch function, an alarm function, and the like by executing a program. Good.

  The nonvolatile memory 20 stores a program executed by the processor 10, data used by the program, and the like. The nonvolatile memory 20 can be realized by, for example, a flash memory or an EEPROM.

  The RAM 30 is a volatile memory for temporarily storing necessary information, and temporarily stores data obtained as a result of the processor 10 performing an operation according to a program stored in the nonvolatile memory 20. For example, it is used as a work area of the processor 10.

  The reset circuit 40 generates a low-level reset signal rst_n when the semiconductor device 1 is powered on or when the processor 10 executes a reset command, and removes the nonvolatile memory 20 and the oscillation circuit 50. Initialize the circuit.

  When the semiconductor device 1 is powered on, the oscillation circuit 50 starts an oscillation operation and outputs a clock signal clk based on the oscillation signal. In the present embodiment, when power is supplied to the semiconductor device 1, the reset is released after the oscillation of the oscillation circuit 50 is stabilized (the reset signal rst_n becomes high level), and the processor 10, the debug circuit 70, and the mask circuit 80. The control circuit 90 operates in synchronization with the clock signal clk.

  For example, the reset circuit 40 may be realized by a time constant circuit using resistors and capacitors, or a circuit that sets the reset signal rst_n to a high level when a predetermined number of clock pulses such as the clock signal clk are counted.

The GPIO circuit 60 is a signal input / output interface circuit between the external terminal P01 and the processor 10, and propagates a signal input from the external terminal P01 to the processor 10 or outputs a desired signal output from the processor 10. Propagate to the external terminal P01. For example, when the external terminal P01 is pulled up to a high level and the host CPU 3 supplies a low level signal to the external terminal P01, the processor 10 causes the external terminal P01 to change from the high level via the GPIO circuit 60. A predetermined interrupt process may be executed by recognizing the change to the low level.

  The debug circuit 70 is a circuit having a debugging function for programs and data stored in the nonvolatile memory 20 (functions such as setting breakpoints and step execution). The external terminal DBG (an example of a first external terminal) is an external terminal used for debugging the program and data. The debug device 2 accesses the debug circuit 70 via the external terminal DBG to Data debugging can be performed. Specifically, the debug device 2 transmits the debug request signal dbgreq to the debug circuit 70 via the external terminal DBG. When the debug circuit 70 receives the debug request signal dbgreq, the debug device 2 transmits the debug request signal dbgreq via the external terminal DBG. A debug response signal dbback is transmitted to After receiving the debug response signal dbback, the debug device 2 transmits a debug command (a command for setting a breakpoint or executing a step) to the debug circuit 70 via the external terminal DBG, and the debug circuit 70 responds to the debug command. Process.

  The mask circuit 80 is a circuit that disconnects the electrical connection between the external terminal DBG and the debug circuit 70 for a predetermined period from the reset release. In the present embodiment, the mask circuit 80 sets an unillustrated mask period signal mask, which is an internal signal, to a high level only during this predetermined period. The mask circuit 80 does not propagate the debug request signal dbgreq or the debug command input from the external terminal DBG while the mask period signal mask is at the high level, and after a predetermined period has elapsed since the reset release (the mask period signal mask is After the low level, the debug request signal dbgreq and the debug command are propagated. As a result, in this embodiment, at least during a predetermined period from reset cancellation, all signals input to the external terminal DBG are invalid, and the debug circuit 70 cannot be accessed from the external terminal DBG.

  The control circuit 90 determines whether or not to disconnect the electrical connection between the external terminal DBG and the debug circuit 70 even after the lapse of the predetermined period in a predetermined period (period in which the mask period signal mask is at a high level) after reset is released. It is a circuit to control. For example, when the processor 10 executes a debug terminal invalid instruction (an example of a first instruction) included in a program in a predetermined period (a period in which the mask period signal mask is high), the predetermined period After the elapse of time, the electrical connection between the external terminal DBG and the debug circuit 70 may be disconnected. In addition, when the processor 10 does not execute the debug terminal invalid instruction in the predetermined period, the control circuit 90 electrically connects the external terminal DBG and the debug circuit 70 after the predetermined period has elapsed. It may be. A predetermined period after the reset is released (a period in which the mask period signal mask is at a high level) is set to be longer than the time required for the processor 10 to execute the debug terminal invalid instruction.

  In the present embodiment, the control circuit 90 includes a switch circuit 92 and a terminal control circuit 94.

  When the debug enable signal dbgen from the terminal control circuit 94 is at a high level, the switch circuit 92 propagates the output signal of the mask circuit 80 (for example, the debug request signal dbgreq or the debug command) to the debug circuit 70, or debugs The output signal of the circuit 70 (for example, the debug response signal dbback) is propagated to the mask circuit 80. Further, the switch circuit 92 does not propagate the output signal of the mask circuit 80 to the debug circuit 70 and does not propagate the output signal of the debug circuit 70 to the mask circuit 80 when the debug enable signal dbgen is at a low level.

  The terminal control circuit 94 sets the debug enable signal dbgen to a high level after reset release, and the processor 10 executes a debug terminal invalid instruction in a predetermined period after the reset is released (a period in which the mask period signal mask is high level). Thereafter, the debug enable signal dbgen is fixed at a low level. For example, the terminal control circuit 94 includes a register (not shown) including a debug enable bit (initial value is 1) corresponding to the debug enable signal dbgen. The debug terminal invalid instruction is a load that sets this debug enable bit to 0. It may be an instruction.

  According to the semiconductor device 1 of the first embodiment configured as described above, if the processor 10 does not execute the debug terminal invalid instruction in a predetermined period after the reset is released, the debugging is started from the external terminal DBG after the predetermined period has elapsed. Access to the circuit 70 becomes possible. Therefore, it is possible to debug programs and data stored in the nonvolatile memory 20.

  On the other hand, when the processor 10 executes the debug terminal invalid instruction during a predetermined period after the reset is released, the debug circuit 70 cannot be accessed from the external terminal DBG even after the predetermined period has elapsed. Therefore, after the debugging of the program and data stored in the nonvolatile memory 20 is completed, for example, by adding or replacing the debug terminal invalid instruction near the head of the program, the external terminal DBG can be used for the debug circuit 70. Access becomes impossible, and the possibility of unauthorized use of programs and data via the debug circuit 70 can be reduced.

[Operation Example 1 of Semiconductor Device]
FIG. 2 is a diagram illustrating an example of a debug target program stored in the nonvolatile memory 20. In the present embodiment, the processor 10 first executes the instruction arranged at the 0x0000 address of the nonvolatile memory 20 after the reset is released. In the example of FIG. 2, a vector fetch instruction is arranged at the address 0x0000, and the processor 10 first executes this vector fetch instruction after reset release. The vector fetch instruction is a jump instruction to a predetermined reset vector (x0100 address in the example of FIG. 2). Next, the processor 10 sequentially executes each instruction stored after the 0x0100 address. In the example of FIG. 2, after the address 0x0100, a NOP instruction (nop), a NOP instruction (nop), a load instruction (ld), a load instruction (ld), an addition instruction (add), a load instruction (ld), and a subtraction instruction (Sub), load instruction (ld), jump instruction (jp), logical left shift instruction (sll), load instruction (ld), load instruction (ld),... Are arranged in this order. The instruction sequence stored after the 0x0100 address is a program to be debugged.

FIG. 3 is a diagram showing an example of a timing chart when the processor 10 executes the program of the example of FIG. In the example of FIG. 3, at time _{t 0,} debug unit 2 is entering a debug request signal dbgreq through the external terminals DBG.

Next, when the reset is released at time t ₁ (when the reset signal rst_n changes from the low level to the high level), both the mask period signal mask and the debug enable signal dbgen are at the high level. Also, after the reset is released at time t _1, processor 10 reads in synchronism with the rising edge of the clock signal clk, the vector fetch is disposed 0x0000 address of the nonvolatile memory 20 instructions (see Figure 2) And execute.

Then, the processor 10 at time _{t 2} later, reads and executes the instruction sequence is arranged after 0x0100 address of the nonvolatile memory 20 (debug target program) (see Figure 2).

After that, at time t ₃ , the mask period signal mask changes to low level, and the debug enable signal dbgen is high level. Therefore, the debug circuit 70 receives the debug request signal dbgreq, and receives the debug response signal dbback through the external terminal DBG. Is output.

Debugger 2 receives the debug response signal DBGACK, at time _{t 4,} to stop the debug request signal Dbgreq, since, through the external terminals DBG, allows the input debug command to the debug circuitry 70.

  In the example of FIG. 3, the mask period signal mask is at a high level during a period of eight clock pulses of the clock signal clk after the reset is released, and the debug device 2 from the external terminal DBG to the debug circuit 70 during this period. Cannot be accessed, but will be accessible after the period.

[Operation Example 2 of Semiconductor Device]
FIG. 4 is a diagram showing an example of a program stored in the nonvolatile memory 20 after debugging of the program of FIG. 2 is completed. FIG. 5 is a timing when the processor 10 executes the program of the example of FIG. It is a figure which shows an example of a chart. In the example of FIG. 4, in the example of FIG. 2, the two NOP instructions (nop) arranged at the top 0x0100 address and 0x0102 address of the program to be debugged are replaced with the debug terminal invalid instruction, and the others are shown in FIG. This is the same as the example.

Also in the example of FIG. 5, the debug request signal dbgreq is input via the external terminal DBG at time t ₀ as in the example of FIG. 3. When the reset at time t ₁ is released, the mask period signal mask and debug enable signal dbgen has become both a high level, the processor 10, the vector fetch instruction in synchronization with the rising edge of the clock signal clk (Fig. 4) is read and executed.

Then, the processor 10 at time t ₂ later, reads and executes the instruction sequence is arranged after 0x0100 address of the nonvolatile memory 20 (program debugging is completed) (see Fig. 4). Here, the processor 10 reads and executes the debug terminal invalid instruction from time t ₂ to time t ₃ , whereby the debug enable signal dbgen changes from high level to low level.

Then, at time _{t 4,} but the mask period signal mask is changed to the low level, since the debug enable signal dbgen is at a low level, it is not possible to debug circuitry 70 receives a debug request signal Dbgreq, debug from the external terminal DBG The response signal dbback is not output.

  In the example of FIG. 5, after the reset is released, the mask period signal mask is at a high level during a period of 8 clock pulses of the clock signal clk, and the debug circuit 70 cannot be accessed from the external terminal DBG during this period. Even after the lapse of the period, the debug enable signal dbgen is at a low level, so that the debug circuit 70 cannot be accessed from the external terminal DBG. Therefore, it is possible to reduce the possibility that the program stored in the nonvolatile memory from the external terminal DBG via the debug circuit 70 is illegally used.

[Operation Example 3 of Semiconductor Device]
In the present embodiment, the nonvolatile memory 20 erases stored information when a predetermined signal (for example, a low level signal) is input to the external terminal P01 (an example of a second external terminal). . The non-volatile memory 20 may erase only the programs and data that are not desired to be used illegally from the stored information, or may erase all the stored information. For example, when a predetermined signal is input to the external terminal P01, the processor 10 may perform control to erase information stored in the nonvolatile memory 20 by interrupt processing.

  For example, when the user changes the input signal gpio_n from the external terminal P01 from a high level to a low level for the purpose of rewriting a program stored in the nonvolatile memory 20, it is stored in the nonvolatile memory 20 accordingly. The existing information may be deleted.

  In addition, any one or a plurality of predetermined external terminals (an example of the second external terminal) to be fixed to the high level or the low level of the semiconductor device 1 changes from the high level to the low level, or from the low level. When the level is changed to a high level, it may be regarded as an unauthorized access, and the processor 10 may perform control to erase information stored in the nonvolatile memory 20.

  For example, the nonvolatile memory 20 may be erased by setting all bits of the information to be erased to 1, and a code having all the bits 1 may be assigned to the NOP instruction. That is, all erased information may be NOP instructions.

FIG. 6 is a diagram illustrating an example of a timing chart when information in the nonvolatile memory 20 is completely erased. Also in FIG. 6, the debug request signal dbgreq is input via the external terminal DBG at time t ₀ as in the example of FIG. When reset is at time _{t 1} is released, the mask period signal mask and debug enable signal dbgen has become both a high level, the processor 10, after time _{t 1,} in synchronization with the rising edge of the clock signal clk 4 Run the example program. Here, the processor 10 reads and executes the debug terminal invalid instruction from time t ₂ to time t ₃ , whereby the debug enable signal dbgen changes from high level to low level.

Then, at time _{t 4,} but the mask period signal mask is changed to the low level, since the debug enable signal dbgen is at a low level, it is not possible to debug circuitry 70 receives a debug request signal Dbgreq, debug from the external terminal DBG The response signal dbback is not output.

Then, at time _{t 5,} when the input signal gpio_n from the external terminal P01 is changed from the high level to the low level, the processor 10 at time _{t 5} ~ time _{t 6,} the interrupt processing, and stored in the nonvolatile memory 20 Delete all information.

Then, at time _{t 7,} again is reset to the semiconductor device 1 changes from the reset signal rst_n the high level to the low level at time _{t 8,} the debug request signal dbgreq via the external terminals DBG is entered again . When at time _{t 9} the reset is released, the mask period signal mask and debug enable signal dbgen are both high level, the processor 10, 0x0000 address of the nonvolatile memory 20 in synchronization with the rising edge of the clock signal clk And the NOP instruction (nop) changed by erasing the vector fetch instruction is read and executed. Since the nonvolatile memory 20 has been completely erased, the NOP instruction (nop) is placed at all addresses, and the processor 10 then repeatedly executes the NOP instruction (nop).

Then, at time _{t 10,} the mask period signal mask is changed to the low level, since the debug enable signal dbgen is at a high level, the debug circuit 70 receives the debug request signal Dbgreq, debugging response signal dbgack through the external terminals DBG Is output.

  As described above, after the information in the nonvolatile memory 20 is completely erased (or after the program or data that is not to be illegally used is erased), the debug terminal invalid instruction is not executed while the mask period signal mask is at the low level. Therefore, after the period has elapsed, the debug circuit 70 can be accessed from the external terminal DBG. However, since the nonvolatile memory 20 does not contain useful information, the risk of unauthorized use can be reduced.

  Furthermore, since the debug circuit 70 can be accessed from the external terminal DBG after the period has elapsed, a vector fetch instruction is written from the external terminal DBG to the 0x0000 address of the nonvolatile memory 20, and after the reset vector address, It becomes possible to write a new program in which a debug terminal invalid instruction is arranged near the head. This makes it possible to rewrite the program while reducing the risk of unauthorized use.

  The nonvolatile memory 20 is configured to have a plurality of storage areas (for example, sectors and blocks), and stores a predetermined signal when input to the external terminal P01 or other predetermined external terminal. Preferably, the stored information is erased for each storage area, and the information in the storage area in which the debug terminal invalid instruction is stored is erased last. For example, as shown in FIG. 7, when the nonvolatile memory 20 has 16 sectors and erases information on a sector basis, when a debug terminal invalid instruction is stored in the sector 1, After erasing all the information in the sectors 2 to 16, the information in the sector 1 is finally erased. In this way, even if the information stored in the nonvolatile memory 20 is not completely erased and the program or part of the data is not erased, the debug terminal invalid instruction is not erased. Therefore, it is possible to reduce the risk of unauthorized use of programs and data that have not been erased.

[Operation Example 4 of Semiconductor Device]
In the present embodiment, the control circuit 90 may electrically connect the external terminal DBG and the debug circuit 70 when the processor 10 executes a debug terminal valid instruction (second instruction). For example, when a predetermined signal is input to a predetermined external terminal, the processor 10 may execute a debug terminal valid instruction by interrupt processing. For example, when the input signal gpio_n from the external terminal P01 changes from the high level to the low level, the processor 10 may execute the debug terminal valid instruction.

FIG. 8 is a diagram illustrating an example of a timing chart when the debug terminal valid instruction is executed. Also in FIG. 8, as in the example of FIG. 5, at time _{t 0,} the debug request signal dbgreq via the external terminals DBG is input. When reset is at time _{t 1} is released, the mask period signal mask and debug enable signal dbgen has become both a high level, the processor 10, after time _{t 1,} in synchronization with the rising edge of the clock signal clk 4 Run the example program. Here, the processor 10 reads and executes the debug terminal invalid instruction from time t ₂ to time t ₃ , whereby the debug enable signal dbgen changes from high level to low level.

Then, at time _{t 4,} but the mask period signal mask is changed to the low level, since the debug enable signal dbgen is at a low level, it is not possible to debug circuitry 70 receives a debug request signal Dbgreq, debug from the external terminal DBG The response signal dbback is not output.

Then, at time _{t 5,} when the input signal gpio_n from the external terminal P01 is changed from the high level to the low level, the processor 10 At time _{t 5,} the interrupt processing and executes the debug terminal valid instruction. Thus, at time _{t 6,} the debug enable signal dbgen is changed from low level to high level, the debug circuit 70 receives the debug request signal Dbgreq, outputs a debug response signal dbgack through the external terminals DBG.

Then, the debugging apparatus 2 receives the debug response signal DBGACK, at time _{t 7,} to stop the debug request signal Dbgreq, since, through the external terminals DBG, allows the input debug command to the debug circuitry 70.

  For example, if information that the debug circuit 70 can be accessed from the external terminal DBG when a predetermined signal is input to a predetermined external terminal is disclosed to only an authorized user, the information is stored in the nonvolatile memory 20. The risk of unauthorized use of existing programs and data can be reduced. In addition, the authorized user can debug the program even after the debug terminal invalid instruction is installed in the program.

[effect]
As described above, according to the semiconductor device 1 of the first embodiment, the electrical connection between the external terminal DBG and the debug circuit 70 is disconnected by the mask circuit 80 during a predetermined period after the reset is released, and the external terminal In the predetermined period in which the electrical connection between the DBG and the debug circuit 70 is disconnected, the processor 10 executes the debug terminal invalid instruction, so that the control circuit 90 can debug the external terminal DBG and the debug even after the predetermined period has elapsed. Control is performed so that the circuit 70 is electrically disconnected. Therefore, it is possible to reduce the possibility that the program stored in the nonvolatile memory 20 from the external terminal DBG via the debug circuit 70 is illegally used.

  The semiconductor device 1 according to the first embodiment can be realized with a simple configuration in which the electrical connection between the external terminal DBG and the debug circuit 70 is disconnected by the mask circuit 80 and the control circuit 90. Therefore, according to the semiconductor device 1 of the first embodiment, it is possible to reduce the risk of unauthorized use of the program while reducing the increase in cost.

  Further, according to the semiconductor device 1 of the first embodiment, the processor 10 does not execute the debug terminal invalid instruction in the predetermined period in which the electrical connection between the external terminal DBG and the debug circuit 70 is disconnected. The control circuit 90 controls the external terminal DBG and the debug circuit 70 to be electrically connected after the predetermined period has elapsed. Accordingly, the program stored in the nonvolatile memory 20 can be easily debugged from the external terminal DBG via the debug circuit 70.

  Further, according to the semiconductor device 1 of the first embodiment, whether or not the external terminal DBG and the debug circuit 70 are electrically connected is controlled depending on whether or not the debug terminal invalid instruction is arranged near the head of the program. can do. Therefore, a user (for example, a program developer) can arbitrarily set validity / invalidity of the external terminal DBG. For example, the external terminal DBG becomes valid after a lapse of a predetermined period from the reset release of the semiconductor device 1, the debug device 2 writes a debug terminal invalid instruction from the external terminal DBG near the beginning of the program, and then resets the semiconductor device 1. Then, the external terminal DBG can be invalidated.

1-2. Second Embodiment FIG. 9 is a diagram illustrating a configuration example of a semiconductor device according to a second embodiment. In FIG. 9, the same components as those in FIG. As shown in FIG. 9, the semiconductor device 1 according to the second embodiment includes a processor 10, a nonvolatile memory 20, a RAM 30, a reset circuit 40, an oscillation circuit 50, a GPIO circuit 60, a GPIO circuit 62, a debug circuit 70, and a mask circuit 80. The control circuit 90 and the bus 100 to which these elements are connected are configured. Note that the semiconductor device 1 of the present embodiment may have a configuration in which some of these elements are omitted or changed, or other elements are added. Hereinafter, the semiconductor device 1 of the second embodiment will be described focusing on the differences from the semiconductor device 1 of the first embodiment, and overlapping descriptions will be omitted or simplified as appropriate.

  The semiconductor device 1 of the second embodiment differs from the semiconductor device 1 of the first embodiment (FIG. 1) in terms of the function of the control circuit 90 and the connection relationship between the mask circuit 80 and the control circuit 90, and the GPIO circuit. 62 is added. Furthermore, the external terminal DBG for debugging in the first embodiment is replaced with an external terminal DBG / P00 that is also used as an external terminal DBG for debugging and an external terminal P00 for general purpose input / output.

  Similar to the semiconductor device 1 of the first embodiment, the semiconductor device 1 of the second embodiment communicates with the host CPU 3 via the external terminal P01 and an external terminal for communication interface (not shown) (clock terminal, data terminal, etc.). It is configured to be possible. Further, the semiconductor device 1 of the second embodiment is configured to be able to communicate with either the debug device 2 (device that executes the debugger) or the host CPU 3 via the external terminal DBG / P00 by switching the switch 4. Has been. The external terminal DBG / P00 functions as an external terminal DBG for debugging when electrically connected to the debug device 2 by the switch 4, and is used for general purpose input / output when electrically connected to the host CPU 3 by the switch 4. Functions as an external terminal P00.

  The GPIO circuit 62 is a signal input / output interface circuit between the external terminal DBG / P00 (an example of a first external terminal) and the processor 10, and propagates a signal input from the external terminal DBG / P00 to the processor 10. Alternatively, a desired signal output from the processor 10 is propagated to the external terminal DBG / P00.

  The mask circuit 80 is a circuit that disconnects the electrical connection between the external terminal DBG / P00 and the debug circuit 70 for a predetermined period from the reset release. Also in the second embodiment, the mask circuit 80 sets an unillustrated mask period signal mask, which is an internal signal, to a high level only during this predetermined period. Then, the mask circuit 80 does not propagate the debug request signal dbgreq or the debug command input from the external terminal DBG / P00 while the mask period signal mask is at a high level, and after a predetermined period has passed since the reset release (mask period signal After the mask becomes low level, the debug request signal dbgreq and the debug command are propagated. Thereby, also in this embodiment, all signals input to the external terminal DB / P00G are invalidated at least for a predetermined period from reset cancellation, and the debug circuit 70 cannot be accessed from the external terminal DBG / P00.

The control circuit 90 determines whether or not to disconnect the electrical connection between the external terminal DBG / P00 and the debug circuit 70 even after the predetermined period has elapsed in a predetermined period (period in which the mask period signal mask is at a high level) after reset is released. This is a circuit for controlling the above. For example, after the reset is released, the control circuit 90 electrically connects the external terminal DBG / P00 and the mask circuit 80 and disconnects the electrical connection between the external terminal DBG / P00 and the GPIO 62. When the processor 10 executes a debug terminal invalid instruction (an example of a first instruction) included in the program in a predetermined period (a period in which the mask period signal mask is at a high level), the control terminal 90 outputs the external terminal DBG. / P00 and the GPIO circuit 62 are electrically connected, and the external terminal DBG / P00 and the debug circuit 70 are disconnected, so that the external terminal DBG / P00 is maintained even after the predetermined period has elapsed. And the debug circuit 70 may be disconnected from the electrical connection. If the processor 10 does not execute the debug terminal invalid instruction in the predetermined period, the control circuit 90 electrically connects the external terminal DBG / P00 and the mask circuit 80 even after the predetermined period has elapsed. The external terminal DBG / P00 and the debug circuit 70 may be electrically connected by connecting and disconnecting the electrical connection between the external terminal DBG / P00 and the GPIO circuit 62.

  In the present embodiment, the control circuit 90 includes a terminal control circuit 94 and a selector 96.

  Similarly to the first embodiment (FIG. 1), the terminal control circuit 94 sets the debug enable signal dbgen to high level after reset release, and the processor 10 sets a predetermined period after the reset release (mask period signal mask is high level). Thereafter, the debug enable signal dbgen is fixed to the low level.

  The selector 96 electrically connects the external terminal DBG / P00 and one of the debug circuit 70 and the GPIO circuit 62 in response to the debug enable signal dbgen from the terminal control circuit 94, and debugs the external terminal DBG / P00. It is a circuit that disconnects electrical connection with the other of the circuit 70 and the GPIO circuit 62.

  For example, when the debug enable signal dbgen is at a high level, the selector 96 propagates an input signal (for example, a debug request signal dbgreq or a debug command) from the external terminal DBG / P00 to the mask circuit 80, or Output signal (the output signal of the debug circuit 70 (eg, debug response signal dbback)) is propagated to the external terminal DBG / P00. Further, when the debug enable signal dbgen is at a low level, the selector 96 propagates the input signal from the external terminal DBG / P00 to the GPIO circuit 62 or propagates the output signal of the GPIO circuit 62 to the external terminal DBG / P00. Let

  Other configurations and functions of the semiconductor device 1 according to the second embodiment are the same as those of the semiconductor device 1 according to the first embodiment, and thus description thereof is omitted. Further, since the operation example of the semiconductor device 1 of the second embodiment may be the same as the operation examples 1 to 4 (FIGS. 2 to 7) illustrated in the first embodiment, for example, the illustration and description thereof will be omitted. Omitted.

  According to the semiconductor device 1 of the second embodiment configured as described above, if the processor 10 does not execute the debug terminal invalid instruction in a predetermined period after reset release, the external terminal DBG / P00 is passed after the predetermined period has elapsed. Thus, the debug circuit 70 can be accessed. Therefore, it is possible to debug programs and data stored in the nonvolatile memory 20.

  On the other hand, when the processor 10 executes the debug terminal invalid instruction during a predetermined period after the reset is released, the debug circuit 70 cannot be accessed from the external terminal DBG / P00 even after the predetermined period has elapsed. Therefore, after the debugging of the program and data stored in the nonvolatile memory 20 is completed, for example, by adding or replacing the debug terminal invalid instruction in the vicinity of the head of the program, the debug circuit is connected from the external terminal DBG / P00. 70 becomes inaccessible, and the possibility of unauthorized use of programs and data via the debug circuit 70 can be reduced.

  Furthermore, according to the semiconductor device 1 of the second embodiment, since one external terminal DBG / P00 is used as both the debugging external terminal DBG and the general-purpose input / output external terminal P00, the number of external terminals is limited. It can also be applied to.

1-3. Third Embodiment FIG. 10 is a diagram illustrating a configuration example of a semiconductor device according to a third embodiment. In FIG. 10, FIG.
Constituent elements similar to those in FIG. As shown in FIG. 10, the semiconductor device 1 according to the third embodiment includes a processor 10, a nonvolatile memory 20, a RAM 30, a reset circuit 40, an oscillation circuit 50, a GPIO circuit 60, a test circuit 72, a mask circuit 80, and a control circuit 90. And a bus 100 to which these elements are connected. Note that the semiconductor device 1 of the present embodiment may have a configuration in which some of these elements are omitted or changed, or other elements are added. Hereinafter, the semiconductor device 1 of the third embodiment will be described focusing on the differences from the semiconductor device 1 of the first embodiment, and overlapping descriptions will be omitted or simplified as appropriate.

  In the semiconductor device 1 of the third embodiment, the debug circuit 70 is replaced with the test circuit 72 and the functions of the mask circuit 80 and the control circuit 90 are compared with the semiconductor device 1 (FIG. 1) of the first embodiment. Different.

  Similar to the semiconductor device 1 of the first embodiment, the semiconductor device 1 of the third embodiment communicates with the host CPU 3 via the external terminal P01 and an external terminal for a communication interface (not shown) (clock terminal, data terminal, etc.). It is configured to be possible. The semiconductor device 1 is configured to be able to communicate with the inspection device 5 via the external terminal TST.

  The test circuit 72 is an inspection circuit for testing whether or not each circuit included in the semiconductor device 1 operates as designed. That is, the external terminal TST (an example of the first external terminal) is an external terminal used for the inspection of the semiconductor device 1, and the inspection device 5 accesses the test circuit 72 via the external terminal TST, and thus the semiconductor. An inspection of the device 1 can be performed. Specifically, the inspection device 5 transmits a test command (command for testing the operation of each circuit) to the test circuit 72 via the external terminal TST, and the test circuit 72 performs a test process according to the test command. Then, the test circuit 72 transmits a test result corresponding to the test command to the inspection device 5 via the external terminal TST.

  The mask circuit 80 is a circuit that disconnects the electrical connection between the external terminal TST and the test circuit 72 for a predetermined period from the reset release. Also in the third embodiment, the mask circuit 80 sets an unillustrated mask period signal mask, which is an internal signal, to a high level only during this predetermined period. Then, the mask circuit 80 does not propagate the test command input from the external terminal TST while the mask period signal mask is in the high level, and after a predetermined period has elapsed since the reset was released (the mask period signal mask became low level). After), the test command is propagated. As a result, in this embodiment, all signals input to the external terminal TST are invalidated at least for a predetermined period from reset cancellation, and the test circuit 72 cannot be accessed from the external terminal TST.

  The control circuit 90 determines whether or not to disconnect the electrical connection between the external terminal TST and the test circuit 72 even after the predetermined period elapses in a predetermined period (period in which the mask period signal mask is high level) after reset is released. It is a circuit to control. For example, when the processor 10 executes a test terminal invalid instruction (an example of a first instruction) included in the program in a predetermined period (a period in which the mask period signal mask is high level), the predetermined period After the elapse of time, the electrical connection between the external terminal TST and the test circuit 72 may be disconnected. In addition, when the processor 10 does not execute the test terminal invalid instruction during the predetermined period, the control circuit 90 electrically connects the external terminal TST and the test circuit 72 after the predetermined period has elapsed. It may be. A predetermined period after the reset is released (a period in which the mask period signal “mask” is at a high level) is set longer than the time required for the processor 10 to execute the test terminal invalid instruction.

  Also in the third embodiment, the control circuit 90 includes a switch circuit 92 and a terminal control circuit 94 as in the first embodiment.

  When the test enable signal tsten from the terminal control circuit 94 is at a high level, the switch circuit 92 propagates the output signal (for example, a test command) of the mask circuit 80 to the test circuit 72 or the output signal of the test circuit 72 (For example, a test result) is propagated to the mask circuit 80. The switch circuit 92 does not propagate the output signal of the mask circuit 80 to the test circuit 72 and does not propagate the output signal of the test circuit 72 to the mask circuit 80 when the test enable signal tsten is at a low level.

  The terminal control circuit 94 sets the test enable signal tsten to the high level after the reset is released, and the processor 10 executes the test terminal invalid instruction in a predetermined period after the reset is released (the period in which the mask period signal mask is at the high level). Thereafter, the test enable signal tsten is fixed at a low level. For example, the terminal control circuit 94 includes a register (not shown) including a test enable bit (initial value is 1) corresponding to the test enable signal tsten, and the test terminal invalid instruction is a load that sets this test enable bit to 0. It may be an instruction.

  Other configurations and functions of the semiconductor device 1 according to the third embodiment are the same as those of the semiconductor device 1 according to the first embodiment, and thus description thereof is omitted. Further, the operation example of the semiconductor device 1 of the third embodiment is, for example, in the operation examples 1 to 4 (FIGS. 2 to 7) illustrated in the third embodiment, the “debug terminal invalid instruction” is changed to the “test terminal invalid instruction”. ”,“ Debug enable signal dbgen ”as“ test enable signal tsten ”,“ debug request signal dbgreq ”or“ debug command ”as test command,“ debug response signal dbgack ”as“ test result ”,“ debug terminal ” Since the “valid command” may be the same as the “test terminal valid command” respectively replaced, illustration and description thereof will be omitted.

  According to the semiconductor device 1 of the third embodiment configured as described above, if the processor 10 does not execute the test terminal invalid command in a predetermined period after the reset is released, the test is performed from the external terminal TST after the predetermined period has elapsed. Access to the circuit 72 becomes possible. The semiconductor device 1 can be inspected.

  On the other hand, when the processor 10 executes the test terminal invalid instruction in a predetermined period after reset is released, the test circuit 72 cannot be accessed from the external terminal TST even after the predetermined period has elapsed. Therefore, after the inspection of the semiconductor device 1 is completed, for example, an access to the test circuit 72 from the external terminal TST is performed by adding or replacing a test terminal invalid instruction near the beginning of the program stored in the nonvolatile memory 20. The possibility of unauthorized use (including unintended use) of the test circuit 72 can be reduced.

  In addition, according to the semiconductor device 1 of the third embodiment, the same effects as the semiconductor device 1 of the first embodiment can be obtained.

2. Electronic Device FIG. 11 is a functional block diagram showing an example of the configuration of the electronic device of the present embodiment. FIG. 12A is a diagram illustrating an example of the appearance of a smartphone that is an example of the electronic device of the present embodiment, and FIG. 12B is a diagram of an electronic timepiece that is an example of the electronic device of the present embodiment. It is a figure which shows an example of an external appearance.

  The electronic device 300 according to this embodiment includes a semiconductor device 310, a power generation unit 320, an operation unit 330, a CPU (Central Processing Unit) 340, a communication unit 350, a display unit 360, and a sound output unit 370. Note that the electronic device of the present embodiment may have a configuration in which some of the components (each unit) in FIG. 11 are omitted or changed, or other components are added.

  The power generation unit 320 is for generating various power sources used in the electronic device 300.

  The operation unit 330 is an input device including operation keys, button switches, and the like, and outputs an operation signal corresponding to an operation by a user to the semiconductor device 310 or the CPU 340.

  The CPU 340 performs various types of calculation processing and control processing, and may be, for example, the host CPU 3 in each of the above embodiments.

  The communication unit 350 performs various controls for establishing data communication between the semiconductor device 310 and an external device.

  The display unit 360 is a display device configured by an LCD (Liquid Crystal Display) or the like, and displays various types of information based on display signals input from the semiconductor device 310 or the CPU 340. The display unit 360 may be provided with a touch panel that functions as the operation unit 330.

  The sound output unit 370 is for outputting various sounds (including sound) based on a sound signal input from the semiconductor device 310 or the CPU 340, and is configured by, for example, a speaker or a buzzer.

  The semiconductor device 310 includes various processes according to operation signals from the operation unit 330, various processes based on data communication with the CPU 340, data communication processes performed with an external device via the communication unit 350, and a display unit 360. A process for generating a display signal for displaying various types of information on the screen, a process for generating a sound output signal for causing the sound output unit 370 to output various types of sound, and the like are performed. The semiconductor device 310 may be an MCU, for example.

  By applying, for example, the semiconductor device 1 of each embodiment described above as the semiconductor device 310, it is possible to realize a highly reliable electronic device with reduced risk of unauthorized use.

  Various electronic devices can be considered as such an electronic device 300, for example, a personal computer (for example, a mobile personal computer, a laptop personal computer, a tablet personal computer), a mobile terminal such as a smartphone or a mobile phone, Digital still cameras, inkjet discharge devices (for example, inkjet printers), storage area network devices such as routers and switches, local area network devices, mobile terminal base station devices, televisions, video cameras, video recorders, car navigation devices, Electronic clock, real-time clock device, pager, electronic notebook (including communication function), electronic dictionary, calculator, electronic game device, game controller, word Processor, workstation, video phone, TV monitor for crime prevention, electronic binoculars, POS terminal, medical equipment (for example, electronic thermometer, blood pressure monitor, blood glucose meter, electrocardiogram measuring device, ultrasonic diagnostic device, electronic endoscope), fish finder , Various measuring devices, instruments (for example, vehicles, aircraft, ships), flight simulators, head mounted displays, motion traces, motion tracking, motion controllers, PDR (pedestrian position direction measurement), and the like.

  The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention.

For example, the semiconductor device 1 according to the third embodiment is a modification of the semiconductor device 1 according to the first embodiment so that the test circuit 72 can be protected from unauthorized use. The semiconductor device according to the second embodiment is obtained by a method similar to that in which the semiconductor device 1 according to the first embodiment is transformed into the semiconductor device 1 according to the third embodiment so that the test circuit 72 can be protected from unauthorized use. The present invention can also be applied to a semiconductor device in which the device 1 is modified.

  The above-described embodiments and modifications are merely examples, and the present invention is not limited to these. For example, it is possible to appropriately combine each embodiment and each modification.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Debugging device, 3 Host CPU, 4 Switch, 5 Inspection device, 10 Processor, 20 Non-volatile memory, 30 RAM, 40 Reset circuit, 50 Oscillation circuit, 60 GPIO circuit, 62 GPIO circuit, 70 Debug circuit, 72 test circuit, 80 mask circuit, 90 control circuit, 92 switch circuit, 94 terminal control circuit, 96 selector, 100 bus, 300 electronic device, 310 semiconductor device, 320 power generation unit, 330 operation unit, 340 CPU, 350 communication unit 360 display unit, 370 sound output unit

Claims (6)

Non-volatile memory,
A processor for executing a program stored in the nonvolatile memory;
A debugging circuit having a debugging function of the program;
A first external terminal used for debugging the program;
A second external terminal;
A mask circuit for disconnecting the electrical connection between the first external terminal and the debug circuit for a predetermined period from reset release;
Wherein the predetermined period, see contains a control circuit for controlling whether or not to disconnect after also with the first external terminal electrical connection between the debug circuit of the predetermined period,
The control circuit includes:
In the predetermined period, when the processor executes a first instruction included in the program, the electrical connection between the first external terminal and the debug circuit is disconnected even after the predetermined period has elapsed,
The nonvolatile memory is
A plurality of storage areas;
When a predetermined signal is input to the second external terminal, the stored information is erased for each storage area, and the information in the storage area in which the first instruction is stored is erased last. A semiconductor device. A signal input / output interface circuit between the first external terminal and the processor;
The control circuit includes:
Wherein the predetermined period, when the processor executes the first instruction, electrically connecting the first external terminal and the input-output interface circuit, a semiconductor device according to claim 1. The predetermined period, the longer than the time required to execute the first instruction processor, a semiconductor device according to claim 1 or 2. The control circuit includes:
When the processor executes the second instruction, the first electrically connecting the external terminal and the debug circuit, a semiconductor device according to any one of claims 1 to 3. Non-volatile memory,
A processor for executing a program stored in the nonvolatile memory;
An inspection circuit;
A first external terminal used for inspection;
A second external terminal;
A mask circuit for disconnecting the electrical connection between the first external terminal and the inspection circuit for a predetermined period from reset release;
Wherein the predetermined period, see contains a control circuit for controlling whether or not to disconnect after also with the first external terminal electrically connected with the inspection circuit of the predetermined period,
The control circuit includes:
In the predetermined period, when the processor executes a first instruction included in the program, the electrical connection between the first external terminal and the inspection circuit is disconnected even after the predetermined period has elapsed,
The nonvolatile memory is
A plurality of storage areas;
When a predetermined signal is input to the second external terminal, the stored information is erased for each storage area, and the information in the storage area in which the first instruction is stored is erased last. A semiconductor device. Comprising the semiconductor device according to any one of claims 1 to 5, electronic apparatus.

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