JP6320341B2 - Receiving machine - Google Patents

Description

  The present invention relates to a receiver.

  High reliability is required for communication between an artificial satellite that cannot be repaired and a ground station. In communication between an artificial satellite and a ground station, a technique for realizing high reliability by controlling transmission and reception at the ground station has been proposed (see, for example, Patent Document 1). In the technique proposed in Patent Document 1, the transmission side performs phase control to increase the power of the signal received by the satellite. The receiving side receives signals from the satellite with a plurality of antennas, adjusts the timing and amplitude of each received signal, and performs maximum ratio combining.

Japanese Patent No. 5474886

  However, the technique proposed in Patent Document 1 has a problem that diversity gain cannot be obtained in the receiver.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a receiver capable of obtaining a diversity gain.

In order to solve the above-described problems and achieve the object, a receiver according to the present invention has a receiver main system and a receiver sub system, and the receiver main system amplifies the power of the received signal. A main system high frequency circuit; a main system adder circuit; and a main system demodulator that demodulates a signal obtained by the main system adder circuit, wherein the receiver slave system amplifies the power of the received signal. A system high-frequency circuit, a sub-system adder circuit, and a sub-system demodulator that demodulates a signal obtained by the sub-system adder circuit, the main system adder circuit is a signal obtained by the main system high-frequency circuit And the signal obtained by the slave high-frequency circuit, and the slave adder circuit adds the signal obtained by the slave high-frequency circuit and the signal obtained by the master high-frequency circuit. . The receiver main system includes a main delay circuit that delays transmission of the signal obtained by the main high frequency circuit, and the receiver sub system transmits the signal obtained by the sub high frequency circuit. A slave delay circuit for delaying is included. The receiver according to the present invention includes a time for a known test signal to reach the main adder circuit of the receiver main system, and a time for the test signal to reach the subordinate adder circuit of the receiver slave. And a correlation unit for setting a delay time in at least one of the main delay circuit and the subordinate delay circuit based on the calculated difference.

  According to the present invention, it is possible to obtain a diversity gain.

FIG. 3 illustrates a configuration of a receiver in the first embodiment. FIG. 9 illustrates a configuration of a receiver according to a second embodiment. FIG. 11 illustrates a configuration of a receiver according to a third embodiment. FIG. 10 illustrates a configuration of a receiver according to a fourth embodiment.

  Hereinafter, a receiver according to an embodiment of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited by this Embodiment.

Embodiment 1 FIG.
First, the receiver 1 of Embodiment 1 is demonstrated. FIG. 1 is a diagram illustrating a configuration of a receiver 1 according to the first embodiment. The receiver 1 includes a receiver main system 11 that demodulates a signal, a receiver slave system 21 that demodulates the signal, a signal received from the outside of the receiver 1, and receives the received signal as a receiver main system 11 and a receiver. And an antenna unit 30 that transmits to the subordinate system 21. The antenna unit 30 includes an antenna and a circuit that transmits a signal received by the antenna to the receiver main system 11 and the receiver slave system 21. The receiver main system 11 and the receiver slave system 21 have the same function.

  The receiver main system 11 converts a reception signal from the antenna unit 30 into a frequency of an IF (Intermediate Frequency) band, and a main high-frequency circuit 101 that amplifies the power of the reception signal, and the main high-frequency circuit 101 changes the frequency. And a local signal generation unit 102 that outputs a signal necessary for conversion. The local signal generation unit 102 is realized by a circuit, for example. The receiver slave system 21 converts the received signal from the antenna unit 30 into an IF band frequency, and a slave high frequency circuit 121 that amplifies the power of the received signal, and when the slave high frequency circuit 121 converts the frequency. And a local signal generation unit 122 that outputs a necessary signal. The local signal generation unit 122 is realized by a circuit, for example. For amplification performed in the main high frequency circuit 101 and the sub high frequency circuit 121, for example, an amplifier such as an LNA (Low Noise Amplifier) is used.

  The receiver main system 11 includes an ADC (Analog to Digital Converter) 103 that converts an analog signal obtained by the main high-frequency circuit 101 into a digital signal, an NCO (Numerical Controlled Oscillator) 104 that outputs a sine wave and a cosine wave, and the like. , And a multiplier 105 that multiplies the signal from the ADC 103 by the sine wave and cosine wave from the NCO 104. The NCO 104 receives the frequency offset information of the received signal from the amplitude phase detection unit 108 described later, and outputs a sine wave and a cosine wave to the multiplier 105 in order to cause the multiplier 105 to output a signal with the corrected frequency offset.

  The receiver slave 21 includes an ADC 123 that converts an analog signal obtained by the slave high-frequency circuit 121 into a digital signal, an NCO 124 that outputs a sine wave and a cosine wave, and a sine wave and cosine from the NCO 124 that are signals from the ADC 123. And a multiplier 125 for multiplying the waves. The NCO 124 receives frequency offset information of the received signal from the amplitude phase detection unit 128 described later, and outputs a sine wave and a cosine wave to the multiplier 125 in order to cause the multiplier 125 to output a signal with the corrected frequency offset. The frequency offset is caused by, for example, a difference between a ground station signal and a satellite local signal when the receiver 1 is installed on a satellite, or a Doppler frequency generated from a relative speed of the satellite with respect to the ground station.

  The receiver main system 11 includes an LPF (Low Pass Filter) 106 that attenuates noise other than the signal band when the signal output from the multiplier 105 is oversampled with respect to the transmission rate. When the signal output from the multiplier 105 is oversampling with respect to the transmission rate, it means that the amount of the signal output from the multiplier 105 exceeds the transmission rate. The receiver slave system 21 has an LPF 126 that attenuates noise other than the signal band when the signal output from the multiplier 125 is oversampling with respect to the transmission rate. When the signal output from the multiplier 125 is oversampling with respect to the transmission rate, it means that the amount of the signal output from the multiplier 125 exceeds the transmission rate. The LPF 106 and the LPF 126 may perform decimation.

  The receiver main system 11 includes a main system pre-stage amplitude adjustment unit 107 that adjusts the amplitude of the signal obtained by the LPF 106. The main-system pre-stage amplitude adjustment unit 107 is obtained by the LPF 106 so that the amplitude of the signal output from the main-system pre-stage amplitude adjustment unit 107 is constant based on amplitude information obtained by the amplitude phase detection unit 108 described later. Adjust the amplitude of the generated signal. The receiver main system 11 includes an amplitude phase detection unit 108 that detects the amplitude and phase of the signal obtained by the main system pre-stage amplitude adjustment unit 107. The main system pre-stage amplitude adjustment unit 107 and the amplitude phase detection unit 108 are realized by a circuit, for example.

  The receiver slave system 21 includes a slave front-stage amplitude adjustment unit 127 that adjusts the amplitude of the signal obtained by the LPF 126. The secondary upstream amplitude adjustment unit 127 is obtained by the LPF 126 so that the amplitude of the signal output from the secondary upstream amplitude adjustment unit 127 is constant based on amplitude information obtained by the amplitude phase detection unit 128 described later. Adjust the amplitude of the generated signal. The receiver slave system 21 includes an amplitude phase detector 128 that detects the amplitude and phase of the signal obtained by the slave upstream-stage amplitude adjuster 127. The secondary upstream amplitude adjustment unit 127 and the amplitude phase detection unit 128 are realized by a circuit, for example.

  The amplitude / phase detector 108, the NCO 104, and the multiplier 105 constitute a feedback circuit, and the feedback circuit is called AFC (Automatic Frequency Control). The amplitude / phase detector 128, the NCO 124, and the multiplier 125 also constitute a feedback circuit, and the feedback circuit is also called AFC. The amplitude phase detection unit 108 and the main system pre-stage amplitude adjustment unit 107 constitute a feedback circuit, and the feedback circuit is called AGC (Automatic Gain Control). The amplitude phase detector 128 and the subordinate upstream amplitude adjuster 127 also constitute a feedback circuit, and the feedback circuit is also called AGC. With AFC and AGC, a baseband signal having a constant amplitude and no frequency offset is obtained.

  The amplitude phase detection unit 108 that generates control information in AFC and AGC is located in the latter stage of the LPF 106 in the first embodiment. However, in order to obtain further averaged amplitude phase information, the main phase demodulation in the last stage is performed. It may be provided inside the part 111. The main demodulation unit 111 will be described later. Similarly, the amplitude / phase detection unit 128 is located in the subsequent stage of the LPF 126 in the first embodiment, but may be provided in the slave demodulation unit 131 in the final stage. The sub demodulator 131 will be described later.

  The receiver main system 11 includes a switch 109 that receives a signal obtained by the main-system pre-stage amplitude adjustment unit 107 and whose amplitude and frequency offset are corrected, a switch control unit 110 that switches the switch 109, and a switch 109. Main system demodulation section 111 for demodulating the signal from The switch 109 receives not only the signal from the main-system pre-stage amplitude adjustment unit 107 of the receiver main system 11 but also the signal from the sub-system pre-stage amplitude adjustment unit 127 of the receiver sub-system 21. The switch control unit 110 and the main demodulation unit 111 are realized by a circuit, for example.

  The receiver slave system 21 includes a switch 129 that receives the signal obtained by the slave pre-stage amplitude adjustment unit 127 and whose amplitude and frequency offset are corrected, a switch control unit 130 that switches the switch 129, and a switch 129. And a slave demodulation unit 131 for demodulating the signal from the. The switch 129 receives not only the signal from the slave pre-stage amplitude adjustment unit 127 of the receiver slave system 21 but also the signal from the master pre-stage amplitude adjustment unit 107 of the receiver main system 11. The switch control unit 130 and the slave demodulation unit 131 are realized by a circuit, for example.

  The master demodulator 111 of the receiver master 11 and the slave demodulator 131 of the receiver slave 21 perform demodulation and simultaneously calculate SNR (Signal to Noise Ratio). The SNR information calculated by the main system demodulation unit 111 is output to the switch control unit 110 of the receiver main system 11 and is also output to the switch control unit 130 of the receiver slave system 21 via the switch control unit 110. The The SNR information calculated by the slave demodulation unit 131 is output to the switch control unit 130 of the receiver slave system 21 and is also output to the switch control unit 110 of the receiver master system 11 via the switch control unit 130. The

  The switch control unit 110 of the receiver master system 11 and the switch control unit 130 of the receiver slave system 21 compare the SNR of the receiver master system 11 with the SNR of the receiver slave system 21. The switch control unit 110 switches the switch 109 of the receiver main system 11 so that the signal of the higher SNR of the receiver main system 11 and the receiver sub system 21 is output to each demodulation unit, The switch control unit 130 switches the switch 129 of the receiver slave system 21.

  In the initial setting, since the signal input from the other system is turned off, the signal of the receiver main system 11 is output to the main demodulator 111 of the receiver main system 11, and the signal of the receiver sub system 21 is The signal is output to the slave demodulation unit 131 of the receiver slave 21.

  As described above, the switch 109 and the switch 129 are switched so that the signal of the higher SNR of the receiver main system 11 and the receiver slave system 21 is output to each demodulator. Thereby, even if the SNR of one system is lowered, the receiver 1 can exhibit the demodulation performance equivalent to that before the SNR is lowered. Further, when an abnormality is detected in the demodulated signal, for example, the switch control unit 110 and the switch control unit 130 switch the switch 109 and the switch 129, and the path from the main system pre-stage amplitude adjustment unit 107 to the main system demodulation unit 111, The path from the main system pre-stage amplitude adjustment unit 107 to the sub system demodulation unit 131, the path from the sub system pre-stage amplitude adjustment unit 127 to the main system demodulation unit 111, and the path from the sub system pre-stage amplitude adjustment unit 127 to the sub system demodulation unit 131 By calculating each SNR in the path, it is possible to determine whether the abnormality occurrence location exists in the receiver main system 11 or the receiver slave system 21 and the abnormality occurrence location is before or after each switch. Can be determined.

Embodiment 2. FIG.
Next, the receiver 2 according to the second embodiment will be described. FIG. 2 is a diagram illustrating a configuration of the receiver 2 according to the second embodiment. Similarly to the receiver 1 of the first embodiment, the receiver 2 receives a receiver main system 12 that demodulates signals, a receiver slave system 22 that demodulates signals, and signals from the outside of the receiver 2. The antenna unit 30 transmits the received signal to the receiver main system 12 and the receiver slave system 22. The receiver main system 12 and the receiver slave system 22 have the same function. The path length of the receiver main system 12 and the path length of the receiver slave system 22 are the same.

  The receiver main system 12 includes a main high-frequency circuit 101 included in the receiver main system 11 according to the first embodiment, a local signal generation unit 102, an ADC 103, an NCO 104, a multiplier 105, an LPF 106, and a pre-stage of the main system. An amplitude adjustment unit 107, an amplitude phase detection unit 108, and a main system demodulation unit 111 are included. The receiver slave 22 includes a slave high-frequency circuit 121, a local signal generator 122, an ADC 123, an NCO 124, a multiplier 125, an LPF 126, and a slave pre-stage included in the receiver slave 21 of the first embodiment. An amplitude adjustment unit 127, an amplitude phase detection unit 128, and a secondary demodulation unit 131 are included.

  The receiver main system 12 is obtained by a main system first amplitude adjusting unit 201 that adjusts the amplitude of the signal obtained by the main system pre-stage amplitude adjusting unit 107 and a sub-system pre-stage amplitude adjusting unit 127 of the receiver sub-system 22. And a main second amplitude adjusting unit 202 for adjusting the amplitude of the received signal. That is, the main system first amplitude adjustment unit 201 adjusts the amplitude of the signal obtained by the main system high frequency circuit 101, and the main system second amplitude adjustment unit 202 adjusts the amplitude of the signal obtained by the sub system high frequency circuit 121. To do. The main system first amplitude adjusting unit 201 and the main system second amplitude adjusting unit 202 are realized by a circuit, for example.

  The receiver main system 12 further includes a main system addition circuit 203 that adds the signal obtained by the main system first amplitude adjustment unit 201 and the signal obtained by the main system second amplitude adjustment unit 202. That is, the main addition circuit 203 adds the signal obtained by the main high frequency circuit 101 and the signal obtained by the sub high frequency circuit 121. In the second embodiment, the main demodulation unit 111 demodulates the signal obtained by the main addition circuit 203.

  The receiver main system 12 further includes an amplitude control unit 204 that determines an adjustment value used when the main system first amplitude adjustment unit 201 and the main system second amplitude adjustment unit 202 adjust the amplitude. Main system first amplitude adjustment section 201 and main system second amplitude adjustment section 202 adjust the amplitude of the signal based on the adjustment value determined by amplitude control section 204. In the initial setting, the adjustment value for the main system second amplitude adjustment unit 202 is zero. That is, in the initial setting, the amplitude of the signal from the slave upstream amplitude adjustment unit 127 of the receiver slave 22 is converted to zero. The amplitude control unit 204 is realized by a circuit, for example.

  The receiver slave 22 is obtained by the slave first amplitude adjuster 221 that adjusts the amplitude of the signal obtained by the slave pre-stage amplitude adjuster 127 and the master pre-stage amplitude adjuster 107 of the receiver main system 12. And a secondary second amplitude adjusting unit 222 that adjusts the amplitude of the received signal. That is, the slave first amplitude adjustment unit 221 adjusts the amplitude of the signal obtained by the slave high frequency circuit 121, and the slave second amplitude adjustment unit 222 adjusts the amplitude of the signal obtained by the master high frequency circuit 101. To do. The subordinate first amplitude adjusting unit 221 and the subordinate second amplitude adjusting unit 222 are realized by a circuit, for example.

  The receiver slave system 22 further includes a slave adder circuit 223 that adds the signal obtained by the slave first amplitude adjuster 221 and the signal obtained by the slave second amplitude adjuster 222. That is, the subordinate adder circuit 223 adds the signal obtained by the subordinate high frequency circuit 121 and the signal obtained by the main high frequency circuit 101. In the second embodiment, the secondary demodulation unit 131 demodulates the signal obtained by the secondary addition circuit 223.

  The receiver slave 22 further includes an amplitude controller 224 that determines an adjustment value used when the slave first amplitude adjuster 221 and the slave second amplitude adjuster 222 adjust the amplitude. The subordinate first amplitude adjustment unit 221 and the subordinate second amplitude adjustment unit 222 adjust the amplitude of the signal based on the adjustment value determined by the amplitude control unit 224. In the initial setting, the adjustment value for the secondary second amplitude adjustment unit 222 is zero. That is, in the initial setting, the amplitude of the signal from the main system pre-stage amplitude adjustment unit 107 of the receiver main system 12 is converted to zero. The amplitude control unit 224 is realized by a circuit, for example.

  The master demodulation unit 111 of the receiver master system 12 demodulates the signal obtained by the master adder circuit 203 and simultaneously calculates the SNR. The slave demodulator 131 of the receiver slave system 22 calculates the slave adder circuit 223. SNR is calculated simultaneously with the demodulation of the signal obtained by the above. The amplitude control unit 204 of the receiver main system 12 acquires the SNR information calculated by the slave demodulation unit 131 via the amplitude control unit 224 of the receiver slave system 22. The amplitude control unit 224 of the receiver slave system 22 acquires the SNR information calculated by the main system demodulation unit 111 via the amplitude control unit 204 of the receiver main system 12.

  The amplitude control unit 204 of the receiver main system 12 calculates the ratio of the signal power obtained by the main first amplitude adjustment unit 201 and the signal power obtained by the main second amplitude adjustment unit 202 to the receiver main system. The adjustment value is determined so as to be a ratio of the SNR of 12 and the SNR of the receiver slave 22. The amplitude control unit 224 of the receiver slave system 22 calculates the ratio of the signal power obtained by the slave second amplitude adjustment unit 222 and the signal power obtained by the slave first amplitude adjustment unit 221 to the receiver main system. The adjustment value is determined so as to be a ratio of the SNR of 12 and the SNR of the receiver slave 22.

  Since there is no correlation between the main system and the sub system with respect to the noise generated in the amplifier of the high frequency circuit, the maximum ratio combining of the main system signal and the sub system signal provides a diversity gain of 3 dB at maximum in the case of the second system. can get. That is, the receiver 2 of Embodiment 2 can obtain diversity gain. In the second embodiment, the adjustment value for amplitude control is set according to the ratio of the SNR. However, the amplitude control method is not limited to the method described in the second embodiment, and any method may be used. .

  The receiver 2 of the second embodiment further includes an abnormality specifying circuit 40 that specifies an abnormality occurrence location. The abnormality specifying circuit 40 turns on and off the main system first amplitude adjustment unit 201, the main system second amplitude adjustment unit 202, the sub system first amplitude adjustment unit 221 and the sub system second amplitude adjustment unit 222. SNR for signals on each path to the main system first amplitude adjustment unit 201, the main system second amplitude adjustment unit 202, the sub system first amplitude adjustment unit 221 and the sub system second amplitude adjustment unit 222 By calculating (signal-to-noise ratio) and comparing, the location where an abnormality has occurred is identified. That is, the abnormality identification circuit 40 can identify an abnormality occurrence location when an abnormality occurs in the receiver 2.

Embodiment 3 FIG.
Next, the receiver 3 of Embodiment 3 will be described. FIG. 3 is a diagram illustrating a configuration of the receiver 3 according to the third embodiment. Similarly to the receiver 2 of the second embodiment, the receiver 3 receives a receiver main system 13 that demodulates a signal, a receiver slave system 23 that demodulates the signal, and a signal from outside the receiver 3. The antenna unit 30 transmits the received signal to the receiver main system 13 and the receiver slave system 23. The receiver main system 13 and the receiver slave system 23 have the same function. In the receiver 2 of the second embodiment, the path length of the receiver main system 12 is the same as the path length of the receiver slave system 22, but in the receiver 3 of the third embodiment, the path length of the receiver main system 13 is the same. And the path length of the receiver slave system 23 is different. Since the second embodiment and the third embodiment are different only in respect of the path length, in the third embodiment, only the difference from the second embodiment will be described.

  As described above, in the receiver 3 according to the third embodiment, the path length of the receiver main system 13 and the path length of the receiver slave system 23 are different. Since the path lengths are different, if maximum ratio combining is performed without adjusting the timing, the signal of the receiver main system 13 and the signal of the receiver slave system 23 cancel each other, and the demodulation performance deteriorates. The receiver 3 includes a main delay circuit 301 and a sub delay circuit 321 that suppress degradation of demodulation performance due to different path lengths. Specifically, the receiver main system 13 includes a main system delay circuit 301 in addition to all the constituent elements of the receiver main system 12 of the second embodiment. The receiver slave system 23 includes a slave delay circuit 321 in addition to all the constituent elements of the receiver slave system 22 of the second embodiment.

  The main delay circuit 301 of the receiver main system 13 is a circuit that delays transmission of the signal obtained by the main high-frequency circuit 101. More specifically, the main system delay circuit 301 is provided between the main system pre-stage amplitude adjusting unit 107 and the main system first amplitude adjusting unit 201, and the signal obtained by the main system pre-stage amplitude adjusting unit 107. Delays transmission. The slave delay circuit 321 of the receiver slave 23 is a circuit that delays transmission of the signal obtained by the slave high-frequency circuit 121. More specifically, the secondary delay circuit 321 is provided between the secondary upstream amplitude adjustment unit 127 and the secondary first amplitude adjustment unit 221, and the signal obtained by the secondary upstream amplitude adjustment unit 127. Delays transmission.

  The diversity gain is maximized by adjusting the timing of performing the maximum ratio combining by the master delay circuit 301 of the receiver master system 13 and the slave delay circuit 321 of the receiver slave system 23. The receiver main system 13 further includes a main correlator 302 that sets the delay time of the main delay circuit 301. The receiver slave 23 further includes a slave correlator 322 that sets the delay time of the slave delay circuit 321. The primary correlator 302 and the secondary correlator 322 constitute a correlation unit 50.

  The master correlator 302 of the receiver master system 13 and the slave correlator 322 of the receiver slave system 23 obtain the correlation between the signal of the receiver master system 13 and the signal of the receiver slave system 23 to obtain the receiver master. The difference between the path of the system 13 and the path of the receiver slave system 23 is calculated. The master correlator 302 and the slave correlator 322 set a delay time in the master delay circuit 301 or the slave delay circuit 321 by the calculated path difference. As a result, the main adder circuit 203 of the receiver main system 13 and the subordinate adder circuit 223 of the receiver slave system 23 can receive signals having the same contents at the same timing. Therefore, the receiver 3 can perform the maximum ratio combining without degrading the demodulation performance, although the path length of the receiver main system 13 and the path length of the receiver slave system 23 are different.

  When the difference between the path length of the receiver main system 13 and the path length of the receiver slave system 23 is known, the delay time set in the master delay circuit 301 or the slave delay circuit 321 can be fixed. The main correlator 302 and the sub correlator 322 are not necessary.

  In the receiver main system 13, since the delay processing performed by the main delay circuit 301 and the amplitude adjustment performed by the main first amplitude adjustment unit 201 and the main second amplitude adjustment unit 202 are both linear operations, The order of the delay processing performed by the system delay circuit 301 and the amplitude adjustment performed by the main system first amplitude adjustment unit 201 and the main system second amplitude adjustment unit 202 is not limited. Similarly, in the receiver slave system 23, the delay process performed by the slave delay circuit 321 and the amplitude adjustment performed by the slave first amplitude adjuster 221 and the slave second amplitude adjuster 222 are both linear operations. Therefore, the order of the delay processing performed by the slave delay circuit 321 and the amplitude adjustment performed by the slave first amplitude adjustment unit 221 and the slave second amplitude adjustment unit 222 is not limited.

  In order to perform the maximum ratio synthesis with higher accuracy, the correlator 50 constituted by the main correlator 302 and the sub correlator 322 transmits a known test signal before transmitting data to be actually processed. The delay time set in the main delay circuit 301 or the sub delay circuit 321 may be calculated so that the correlation peak between the receiver main system 13 and the receiver sub system 23 becomes sharper. That is, the correlator 50 determines the difference between the time required for the known test signal to reach the main adder circuit 203 of the receiver main system 13 and the time required for the test signal to reach the subordinate adder circuit 223 of the receiver slave 23. And a delay time is set in at least one of the main delay circuit 301 and the subordinate delay circuit 321 based on the calculated difference. As a result, maximum ratio synthesis can be performed with high accuracy even for high-speed signals.

Embodiment 4 FIG.
Next, the receiver 4 of Embodiment 4 is demonstrated. FIG. 4 is a diagram illustrating a configuration of the receiver 4 according to the fourth embodiment. The receiver 4 has a receiver main system 14 and a receiver slave system 24 and maintains the function of the receiver 3 of the third embodiment. The circuit scale of the receiver 4 is smaller than that of the receiver 3. Specifically, the receiver 4 does not have the main-system pre-stage amplitude adjustment unit 107 and the amplitude phase detection unit 108 included in the receiver 3, and has a phase detection function of the amplitude phase detection unit 108. 401. Similarly, the receiver 4 does not include the slave upstream amplitude adjustment unit 127 and the amplitude phase detection unit 128 included in the receiver 3, and includes a phase detection unit 421 having a phase detection function of the amplitude phase detection unit 128. Have.

  In the receiver 4 of the fourth embodiment, a set of the main system first amplitude adjustment unit 201 and the main system second amplitude adjustment unit 202, the sub system first amplitude adjustment unit 221 and the sub system second amplitude adjustment unit 222, The amplitude adjustment performed by the AGC in the receiver 3 of the third embodiment is performed. As described above, in the receiver 4, the two components of the main system pre-stage amplitude adjustment unit 107 and the amplitude phase detection unit 108 in the receiver 3 of the third embodiment are replaced with one phase detection unit 401. Similarly, in the receiver 4, two components of the receiver upstream amplitude adjustment unit 127 and the amplitude phase detection unit 128 in the receiver 3 are replaced with one phase detection unit 421. As a result, the circuit scale of the receiver 4 is smaller than that of the receiver 3.

  In the above-described embodiment, it is assumed that each receiver is applied to a wireless device. However, each receiver may be a wireless device or a wired device. Further, in the above-described embodiment, each receiver has a double redundant configuration of a main system and a slave system, but the number of redundant configurations in each receiver is not limited.

  The structure shown in the embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and a part of the structure can be combined without departing from the gist of the present invention. It can be omitted or changed.

  2 receivers, 101 main high frequency circuit, 111 main demodulation unit, 203 main addition circuit, 121 sub high frequency circuit, 131 sub demodulation unit, 223 sub addition circuit.

Claims (3)

It has a receiver main system and a receiver slave system,
The receiver main system has a main high-frequency circuit that amplifies the power of the received signal, a main adder circuit, and a main demodulator that demodulates the signal obtained by the main adder circuit,
The receiver slave system has a slave high-frequency circuit that amplifies the power of the received signal, a slave adder circuit, and a slave demodulator that demodulates the signal obtained by the slave adder circuit,
The main addition circuit adds the signal obtained by the main high frequency circuit and the signal obtained by the sub high frequency circuit,
The slave addition circuit adds the signal obtained by the slave high frequency circuit and the signal obtained by the master high frequency circuit ,
The receiver main system has a main delay circuit that delays transmission of a signal obtained by the main high-frequency circuit;
The receiver slave system has a slave delay circuit that delays transmission of the signal obtained by the slave high-frequency circuit,
Calculate the difference between the time for the known test signal to reach the main adder circuit of the receiver main system and the time for the test signal to reach the subordinate adder circuit of the receiver slave A receiver further comprising a correlator configured to set a delay time in at least one of the main delay circuit and the subordinate delay circuit based on the difference . The receiver main system includes a main first amplitude adjusting unit that adjusts the amplitude of the signal obtained by the main high frequency circuit, and a main second that adjusts the amplitude of the signal obtained by the sub high frequency circuit. An amplitude adjustment unit,
The receiver slave system includes a slave first amplitude adjuster that adjusts the amplitude of the signal obtained by the slave high frequency circuit, and a slave second that adjusts the amplitude of the signal obtained by the master high frequency circuit. An amplitude adjustment unit,
The main system addition circuit adds the signal obtained by the main system second amplitude adjustment unit to the signal obtained by the main system first amplitude adjustment unit,
2. The receiver according to claim 1, wherein the slave addition circuit adds the signal obtained by the slave second amplitude adjustment unit to the signal obtained by the slave first amplitude adjustment unit. . It has a receiver main system and a receiver slave system,
The receiver main system has a main high-frequency circuit that amplifies the power of the received signal, a main adder circuit, and a main demodulator that demodulates the signal obtained by the main adder circuit,
The receiver slave system has a slave high-frequency circuit that amplifies the power of the received signal, a slave adder circuit, and a slave demodulator that demodulates the signal obtained by the slave adder circuit,
The main addition circuit adds the signal obtained by the main high frequency circuit and the signal obtained by the sub high frequency circuit,
The slave addition circuit adds the signal obtained by the slave high frequency circuit and the signal obtained by the master high frequency circuit,
The receiver main system includes a main first amplitude adjusting unit that adjusts the amplitude of the signal obtained by the main high frequency circuit, and a main second that adjusts the amplitude of the signal obtained by the sub high frequency circuit. An amplitude adjustment unit,
The receiver slave system includes a slave first amplitude adjuster that adjusts the amplitude of the signal obtained by the slave high frequency circuit, and a slave second that adjusts the amplitude of the signal obtained by the master high frequency circuit. An amplitude adjustment unit,
The main system addition circuit adds the signal obtained by the main system second amplitude adjustment unit to the signal obtained by the main system first amplitude adjustment unit,
The slave addition circuit adds the signal obtained by the slave second amplitude adjustment unit to the signal obtained by the slave first amplitude adjustment unit,
The main system first amplitude adjustment unit, the main system second amplitude adjustment unit, the sub system first amplitude adjustment unit, and the sub system second amplitude adjustment unit are operated as a switch for switching between an on state and an off state. The signal-to-noise ratio is calculated for the signals of the respective paths to the main system first amplitude adjusting unit, the main system second amplitude adjusting unit, the subordinate first amplitude adjusting unit, and the subordinate second amplitude adjusting unit. by comparing Te, receiver device further comprising a malfunctioning identification circuit for identifying the abnormal location.

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