JP6293694B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device.

  In a memory with a built-in controller such as eMMC (embedded MultiMediaCard: eMMC), which is one of semiconductor memory devices, for example, it is possible to speed up signal transmission between the memory and the memory controller at the time of writing or reading. It has been demanded.

  A controller built-in type memory such as eMMC includes a memory chip stack having a plurality of memory chips provided on a wiring board. The memory chip stack is electrically connected to the wiring board by bonding wires or the like. In the semiconductor memory device, there is a case where the signal quality is lowered when the transfer speed of the signal used between the memory and the memory controller is increased.

U.S. Pat. No. 7,728,444

  The problem to be solved by the invention of the embodiment is to suppress deterioration in the quality of signals used between the memory and the memory controller.

The semiconductor memory device according to the embodiment includes a first bonding pad, a second bonding pad, a third bonding pad, and a first terminal having one end and the other end electrically connected to the first bonding pad. A second wiring having one end electrically connected to the second bonding pad and the other end electrically connected to the other end of the first wiring, and an electric current to the third bonding pad. A wiring board comprising: a third wiring having a first end electrically connected, a second end electrically connected to a connection portion between the other end of the first wiring and the other end of the second wiring; second comprising a first memory chip stack unit comprising a first memory chips stacked two or more wiring board, a second memory chips stacked two or more first memory chip stack unit on A memory chip stacking unit, and a memory having A memory controller mounted on a wiring substrate, a first bonding wire which electrically connects the first bonding pad and the first memory chip, and the second bonding pad and the second memory chip And a third bonding wire for electrically connecting the third bonding pad and the memory controller. The second bonding pad is provided adjacent to the first bonding pad.

It is a cross-sectional schematic diagram which shows the structural example of a semiconductor memory device. It is a schematic diagram for demonstrating the connection relation of each component in a semiconductor memory device. It is a plane schematic diagram which shows the example of a layout of a part of wiring layer. It is a figure which shows the equivalent circuit of a semiconductor memory device. It is a figure which shows the equivalent circuit of a semiconductor memory device. It is a figure which shows the example of the waveform of a data strobe signal. It is a figure which shows the example of the waveform of a data strobe signal. It is a figure which shows the example of the EYE pattern of the signal input / output via an input / output terminal at the time of reading. It is a figure which shows the example of the EYE pattern of the signal input / output via an input / output terminal at the time of reading. It is a cross-sectional schematic diagram which shows the other structural example of a semiconductor memory device. It is a cross-sectional schematic diagram which shows the other structural example of a semiconductor memory device.

  Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic, and for example, the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like may be different from the actual ones. In the embodiments, substantially the same constituent elements are denoted by the same reference numerals and description thereof is omitted.

  FIG. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor memory device, and FIG. 2 is a schematic diagram for explaining the connection relationship of each component in the semiconductor memory device. The semiconductor memory device 10 includes a wiring board 1, a memory 2, a memory controller 3, bonding wires 4 a to 4 c, an insulating resin layer 5, and a conductor 6.

  The wiring substrate 1 has a first surface (the upper surface of the wiring substrate 1 in FIG. 1) and a second surface opposite to the first surface (the lower surface of the wiring substrate 1 in FIG. 1). Further, the wiring board 1 includes an insulating layer 11, a wiring layer 12, a wiring layer 13, a solder resist 14, a solder resist 15, and a via 16.

  The insulating layer 11 is provided between the first surface and the second surface of the wiring substrate 1. As the insulating layer 11, for example, a semiconductor substrate, a glass substrate, a ceramic substrate, a resin substrate such as glass epoxy, or the like can be used.

  The wiring layer 12 is provided on the first surface of the wiring board 1. The wiring layer 12 includes a plurality of conductive layers including at least bonding pads 121a to 121c and wirings 122a to 122c.

  The bonding pads 121a to 121c function as signal terminals, for example. Examples of the signal terminal include an input / output terminal (I / O) and a data strobe signal terminal (DQS). Further, pads having functions as terminals such as a power supply terminal (VCC, VSS) and a read enable signal terminal (RE) may be separately provided. Further, the bonding pads 121a to 121c and the wirings 122a to 122c may be provided for each signal.

  The power supply terminal is a terminal for supplying the power supply voltage VCC and the power supply voltage VSS. The input / output terminal is a terminal for inputting / outputting at least one of a command, an address, program data, and read data. The data strobe signal terminal is a terminal for inputting / outputting a data strobe signal for controlling the timing of data transmission / reception between the memory and the memory controller. A differential signal (DQS0, DQSZ0) may be used as the data strobe signal. The read enable signal terminal is a status pin for instructing a read operation or the like. A differential signal (RE0, REZ0) may be used as the read enable signal.

  As shown in FIG. 2, the wiring 122a has one end electrically connected to the bonding pad 121a and the other end. The wiring 122b has one end electrically connected to the bonding pad 121b and the other end electrically connected to the other end of the wiring 122a. The wiring 122c has one end electrically connected to the bonding pad 121c and the other end electrically connected to a connection portion between the other end of the wiring 122a and the other end of the wiring 122b. Note that a connection point between the wiring 122a, the wiring 122b, and the wiring 122c is a branch point 123. The wiring 122b preferably has the same length as the wiring 122a. The wiring 122c may be longer than the wiring 122a and the wiring 122b.

  FIG. 3 is a plan view showing a layout example of a part of the wiring layer 12. In FIG. 3, the bonding pad 121a and the bonding pad 121b are disposed adjacent to each other. That is, it is preferable that no other bonding pad be provided between the bonding pad 121a and the bonding pad 121b. As a result, it is possible to suppress the influence of the capacitance component due to the deterioration of the signal quality described later. Note that the layout is not necessarily limited to the layout illustrated in FIG. 3. For example, the bonding pad 121 a and the bonding pad 121 b may be arranged at positions separated from each other with the memory 2 interposed therebetween.

  A wiring 122c electrically connected to the memory controller 3 through a bonding pad 121c (not shown) branches into two wirings, a wiring 122a and a wiring 122b, through a branch point 123. At this time, the wiring 122a is electrically connected to the bonding pad 121a, and the wiring 122b is electrically connected to the bonding pad 121b. Note that the width of the wiring 122b is preferably substantially equal to that of the wiring 122a. Note that “substantially equal” includes a case where errors are substantially equal, for example.

  The wiring layer 13 is provided on the second surface of the wiring board 1. The wiring layer 13 has a plurality of conductive layers including connection pads. The connection pad functions as a land for forming the conductor 6. The surface of the connection pad is covered with the conductor 6.

  The wiring layer 12 and the wiring layer 13 include, for example, copper, silver, gold, nickel, or the like. For example, the wiring layer 12 and the wiring layer 13 may be formed by forming a plating film containing the above material by an electrolytic plating method or an electroless plating method. Alternatively, the wiring layer 12 and the wiring layer 13 may be formed using a conductive paste.

  The solder resist 14 is provided on the wiring layer 12 and has an opening that exposes a part of the wiring layer 12. The solder resist 15 is provided on the wiring layer 13 and has an opening that exposes a part of the wiring layer 13. As the solder resist 14 and the solder resist 15, for example, an insulating resin material can be used. For example, an ultraviolet curable resin, a thermosetting resin, or the like can be used. Moreover, an opening can be formed in a part of the solder resist 14 and the solder resist 15 by, for example, etching or the like.

  The via 16 penetrates the wiring board 1. The via 16 includes, for example, a conductor layer provided along an inner wall of an opening that penetrates the insulating layer 11 and a hole filling material filled inside the conductor layer. The opening is formed using a laser, for example. The conductor layer includes copper, silver, gold, nickel, or the like. For example, the conductor layer may be formed by forming a plating film containing the above material by an electrolytic plating method or an electroless plating method. Alternatively, the conductive layer may be formed using a conductive paste. One or both of the bonding pads 121a to 121c and the wirings 122a to 122c may be formed in the same process as the conductor layer. The hole filling material is formed using, for example, an insulating material or a conductive material. However, the present invention is not limited to this, and the via 16 may be formed by, for example, filling the opening with a conductive material by copper plating or the like.

  The memory 2 is mounted on the first surface of the wiring board 1. The memory 2 includes a memory chip such as an EEPROM (Electrically Erasable Programmable Read-Only Memory: EEPROM). 1 and 2, the memory 2 includes a first memory chip stack portion 2 a including two or more first EEPROM chips 21 stacked on the wiring substrate 1, and two memories 2 on the first memory chip stack portion 2 a. A second memory chip stacking section 2b including the second EEPROM chips 22 stacked as described above.

  The plurality of first EEPROM chips 21 are bonded to each other so as to partially overlap each other with an adhesive layer such as a die attach film interposed therebetween, and the plurality of second EEPROM chips 22 sandwich an adhesive layer such as a die attach film. Are adhered to each other so that a part of them overlap. The number of second EEPROM chips 22 is preferably the same as the number of first EEPROM chips 21. Note that three or more memory chip stacked portions may be provided.

  The plurality of first EEPROM chips 21 are electrically connected by connecting the first electrode pads provided on each of the first EEPROM chips 21 using, for example, wire bonding. The plurality of second EEPROM chips 22 are electrically connected by connecting the second electrode pads provided on each second EEPROM chip 22 using, for example, wire bonding.

  The memory 2 has an adhesive layer 23 such as a die attach film provided between the first memory chip stacking portion 2a and the second memory chip stacking portion 2b. The second memory chip stacking portion 2b is stacked so as to overlap the first electrode pad of the first memory chip stacking portion 2a with the adhesive layer 23 interposed therebetween. By providing the adhesive layer 23, the contact between the bonding wire 4a and the second EEPROM chip 22 can be prevented.

  The memory controller 3 is mounted on the first surface of the wiring board 1 and is electrically connected to the memory 2 via the wiring board 1. The memory controller 3 controls operations such as data writing to and data reading from the memory 2. The memory controller 3 is configured by a semiconductor chip.

  The bonding wire 4a electrically connects the bonding pad 121a and the first EEPROM chip 21. The bonding wire 4b electrically connects the bonding pad 121b and the second EEPROM chip 22. In FIG. 1, the bonding wire 4b is not electrically connected to the bonding wire 4a but is electrically separated as shown in FIG. The bonding wire 4c electrically connects the bonding pad 121c and the memory controller 3.

  As the bonding wires 4a to 4c, for example, gold, silver, copper, aluminum or the like can be used. A bonding wire other than the bonding wires 4a to 4c may be provided. A part of the bonding wire 4 a electrically connected to the uppermost first EEPROM chip 21 in the first memory chip stack portion 2 a is embedded in the adhesive layer 23.

The insulating resin layer 5 contains an inorganic filler (for example, SiO ₂ ). For example, a mold such as a transfer molding method, a compression molding method, or an injection molding method using a sealing resin obtained by mixing the inorganic filler with an organic resin or the like. Formed by law.

  The conductor 6 is provided on the second surface of the wiring board 1. The conductor 6 has a function as an external connection terminal. For example, a signal, a power supply voltage, and the like are supplied to the memory controller 3 via an external connection terminal. At this time, the power supply voltage may be supplied to the memory 2 via the external connection terminal. The conductor 6 is formed using, for example, gold, copper, solder or the like. For example, tin-silver or tin-silver-copper lead-free solder may be used. Alternatively, the conductor 6 may be formed using a stack of a plurality of metal materials. In FIG. 1, the conductor 6 is formed using conductive balls, but the conductor 6 may be formed using bumps.

  In the semiconductor memory device of this embodiment, a plurality of memory chips constituting the memory are divided into two or more groups. A plurality of bonding pads are provided for each signal used between the memory and the memory controller, and each of the plurality of bonding pads is electrically connected to a separate group of memory chips. Furthermore, one end of the wiring that transmits each signal is branched according to the number of bonding pads, each branch destination is electrically connected to the corresponding bonding pad, and the other end is electrically connected to the memory controller. To do.

  Here, the relationship between the connection configuration of the memory and the memory controller and the deterioration of the signal quality will be described with reference to FIGS. 4 and 5 are equivalent circuit diagrams of the semiconductor memory device at the time of reading. 6 and 7 are diagrams showing examples of the waveform of the data strobe signal. 8 and 9 are diagrams showing examples of EYE patterns of signals input / output through the input / output terminals at the time of reading.

  First, as a comparative example, the semiconductor memory device 10 having a configuration in which the plurality of bonding pads are not provided for each signal is represented by an equivalent circuit shown in FIG. 4 at the time of reading. In FIG. 4, the wiring 122 x that electrically connects the memory 2 and the memory controller 3 has an inductance component L. The memory 2 has a resistance component R and a capacitance component C1. The memory controller 3 has a capacitive component C3.

  At this time, series resonance occurs due to the inductance component L and the capacitance component C3. Furthermore, a capacitance component C0 is generated between a plurality of adjacent wires. When the capacitance component C0 occurs, parallel resonance occurs in addition to series resonance. When both series resonance and parallel resonance occur, noise 30 is generated in a signal waveform such as a data strobe signal as shown in FIG. 6, and the signal waveform tends to be stepped.

  In addition, since the value of the capacitive component C1 is much larger than that of the capacitive component C3, ringing of signals input to and output from the input / output terminals is likely to occur. For example, as shown in FIG. 8, variation in signals input / output through the input / output terminals during reading increases, and the EYE pattern 40 is crushed. The above phenomenon becomes more prominent as the transfer rate between the memory 2 and the memory controller 3 increases. On the other hand, it is required that the signal quality does not deteriorate even at a high transfer rate of, for example, 250 Mbps or more, specifically, about 266 Mbps.

  The semiconductor memory device of this embodiment is represented by an equivalent circuit shown in FIG. In FIG. 5, the wiring 122a has an inductance component L1, the wiring 122b has an inductance component L2, and the wiring 122c has an inductance component L3. The memory chip stacked unit 2 a has a resistance component R and a capacitance component C 1 a of the plurality of first EEPROM chips 21. The memory chip stacking portion 2b has a capacitance component C1b of the plurality of second EEPROM chips 22. The memory controller 3 has a capacitive component C3.

  In the equivalent circuit shown in FIG. 5, the resonance frequency (1 / √ (L1 × C1a)) of the LC circuit expressed using L1 and C1a and the resonance frequency (1 / of the LC circuit expressed using L2 and C1b). It is preferable to make √ (L2 × C1b)) equal. That is, it is preferable that the product of L1 and C1a is approximately equal to the product of L2 and C1b. As shown in FIG. 1, when the first memory chip stack 2a and the second memory chip stack 2b are formed of the same type and the same number of memory chips, for example, the length of the wiring 122a (from the bonding pad 121a By making the lengths of the wiring 122a (the length of the wiring 122a to the branching point 123) and the wiring 122b (the length of the wiring 122b from the bonding pad 121b to the branching point 123) substantially equal, the product of L1 and C1a, and L2 and C1b It is easy to make the product of and approximately equal.

  With the above configuration, the magnetic field is canceled between the current flowing in one of the wiring 122a and the wiring 122b and the current flowing in the other, and parallel resonance is suppressed. Therefore, as shown in FIG. 7, the generation of noise 30 can be suppressed.

  Further, since the capacitance component C1 is divided into a plurality of capacitance components C1a and C1b, the load capacitance to the wiring is reduced, and signal ringing is suppressed. Therefore, for example, as shown in FIG. 9, variation in signals input / output via the input / output terminals at the time of reading is reduced, and the collapse of the EYE pattern 40 can be suppressed.

  In the case of writing, the resonance frequency (1 / √ (L1 × C1a)) of the LC circuit expressed using L1 and C1a or the resonance frequency (1 / √ of the LC circuit expressed using L2 and C1b. Preferably, (L2 × C1b)) is equal to the resonance frequency (1 / √ (L3 × C3)) of the LC circuit represented by L3 and C3. That is, it is preferable that the product of L1 and C1a or the product of L2 and C1b is substantially equal to the product of L3 and C3. Thereby, parallel resonance is suppressed. Therefore, generation of noise 30 can be suppressed. Similarly to the case of FIG. 5, dividing the capacitive component C1 into the capacitive component C1a and the capacitive component C1b reduces the load capacitance with respect to one signal wiring, thereby suppressing signal ringing. Therefore, variations in signals input / output via the input / output terminals during reading can be reduced.

  The structure of the wiring board 1 is not limited to the structure described with reference to FIGS. Other structural examples of the semiconductor memory device are shown in FIGS. 10 and 11 are schematic cross-sectional views showing other structural examples of the semiconductor memory device.

  The semiconductor memory device 10 shown in FIG. 10 has a plurality of second EEPROM chips 22 stacked in a staircase pattern on the first memory chip stacking portion 2a as compared with the semiconductor memory device 10 shown in FIG. Is at least different. In addition, the description of FIG. 1 can be used as appropriate for the same portions as those of the semiconductor memory device 10 illustrated in FIG.

  In FIG. 10, the adhesive layer 23 may not be provided. Further, the bonding pad 121a and the bonding pad 121b may be adjacent to each other as in FIG.

  The semiconductor memory device 10 shown in FIG. 11 differs from the semiconductor memory device 10 shown in FIG. 10 at least in the connection position between the second memory chip stack 2b and the wiring board 1, that is, the position of the bonding pad 121b. In addition, the description of FIG. 1 can be used as appropriate for the same portions as those of the semiconductor memory device 10 illustrated in FIGS.

  In FIG. 10, the bonding pad 121b is provided at a position different from the pad portion having the bonding pad 121a. For example, the bonding pad 121a may be provided in the first pad portion, and the bonding pad 121b may be provided in the second pad portion that is separated from the first pad portion with the memory 2 interposed therebetween.

  In the structure shown in FIGS. 10 and 11 as well, by adjusting the product of L1 and C1a, the product of L2 and C1b, and the product of L3 and C3 as described above, signal ringing and noise are suppressed. Therefore, it is possible to suppress a decrease in signal quality.

  This embodiment is presented as an example and is not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2 ... Memory, 2a ... Memory chip laminated part, 2b ... Memory chip laminated part, 3 ... Memory controller, 4a ... Bonding wire, 4b ... Bonding wire, 4c ... Bonding wire, 5 ... Insulating resin layer, 6 DESCRIPTION OF SYMBOLS Conductor, 10 ... Semiconductor memory device, 11 ... Insulating layer, 12 ... Wiring layer, 121a ... Bonding pad, 121b ... Bonding pad, 121c ... Bonding pad, 121x ... Wiring, 122a ... Wiring, 122a ... Wiring, 122b ... Wiring , 122c ... wiring, 123 ... branch point, 13 ... wiring layer, 14 ... solder resist, 15 ... solder resist, 16 ... via, 21 ... chip, 22 ... chip, 23 ... adhesion layer, 30 ... noise, 40 ... EYE pattern .

Claims (5)

A first bonding pad; a second bonding pad; a third bonding pad; a first wiring having one end and the other end electrically connected to the first bonding pad; A second wiring having one end electrically connected to the bonding pad and the other end electrically connected to the other end of the first wiring, and electrically connected to the third bonding pad. And a third wiring having a second end electrically connected to a connecting portion between the other end of the first wiring, the other end of the first wiring, and the other end of the second wiring;
Second comprising a first memory chip stack unit comprising a first memory chips stacked 2 or more over the wiring substrate, the first memory a second memory chips stacked 2 or more chip stack portion on A memory chip stacking unit, and
A memory controller mounted on the wiring board;
A first bonding wire for electrically connecting the first bonding pad and the first memory chip;
A second bonding wire for electrically connecting the second bonding pad and the second memory chip;
A third bonding wire for electrically connecting the third bonding pad and the memory controller;
The semiconductor memory device , wherein the second bonding pad is provided adjacent to the first bonding pad . The first wiring has a first inductance component;
The second wiring has a second inductance component,
The third wiring has a third inductance component,
Two or more of the first memory chips have a first capacitance component;
Two or more of the second memory chips have a second capacitance component;
The memory controller has a third capacitive component;
The product of the second inductance component and the second capacitance component is approximately equal to the product of the first inductance component and the first capacitance component, or the first inductance component and the first capacitance component. The product of a capacitance component or the product of the second inductance component and the second capacitance component is approximately equal to the product of the third inductance component and the third capacitance component. Semiconductor memory device. A first bonding pad; a second bonding pad; a third bonding pad; a first wiring having one end and the other end electrically connected to the first bonding pad; A second wiring having one end electrically connected to the bonding pad and the other end electrically connected to the other end of the first wiring, and electrically connected to the third bonding pad. And a third wiring having a second end electrically connected to a connecting portion between the other end of the first wiring, the other end of the first wiring, and the other end of the second wiring;
A second memory chip including a first memory chip stack including two or more first memory chips stacked on the wiring board; and a second memory chip including two or more stacks on the first memory chip stack. A memory chip stacking unit, and
A memory controller mounted on the wiring board;
A first bonding wire for electrically connecting the first bonding pad and the first memory chip;
A second bonding wire for electrically connecting the second bonding pad and the second memory chip;
A third bonding wire for electrically connecting the third bonding pad and the memory controller;
The first wiring has a first inductance component;
The second wiring has a second inductance component,
The third wiring has a third inductance component,
Two or more of the first memory chips have a first capacitance component;
Two or more of the second memory chips have a second capacitance component;
The memory controller has a third capacitive component;
The product of the second inductance component and the second capacitance component is approximately equal to the product of the first inductance component and the first capacitance component, or the first inductance component and the first capacitance component. A semiconductor memory device, wherein a product of a capacitance component or a product of the second inductance component and the second capacitance component is substantially equal to a product of the third inductance component and the third capacitance component. 4. The semiconductor memory device according to claim 1 , wherein the second wiring has a length substantially equal to that of the first wiring. 5.   The first to third bonding pads have a function as an input / output terminal or a data strobe signal terminal for at least one of command, address, program data, and read data. 5. The semiconductor memory device according to claim 4.

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