JP6284177B2 - Error resilience router, IC using the same, and error resilience router control method - Google Patents

Description

The present invention relates to an error- tolerant router based on an on-demand bypass link for a network on a multi-core chip, a two- or three-dimensional IC having the router, and a method for controlling the error- tolerant router.

  In a multi-core chip (CMP) structure used for two- or three-dimensional ICs, a NoC (network-on-chip) connects a processor node and its private (individual) cache to a shared cache and a memory controller. The NoC also carries other control traffic such as interrupt requests.

  In such a structure, a router exists at each node and connects a core with an adjacent core through a pipeline link. The communication unit between nodes is a packet or a Fritz, and the packet is divided into Fritz or units equal to the link width.

  A three-dimensional IC (3D-IC) is formed by stacking several wafers to reduce wire length and delay. In the 3D-IC, a plurality of cores are arranged and provided on each wafer, and a plurality of routers are provided for each core.

  Each router connects a plurality of cores through a network system on a 3D-IC called a “three-dimensional network on chip (3D-NoC)” system.

Network form of 3D-NoC is, but has come recently been studied, little research that working on the error resilience in the three-dimensional network-on-chip (3D-NoC) system. Studies, target systems can be classified depending on how to handle the type of error, or an error (e.g., using a routing algorithm or structural solution).

Some of the proposed error- tolerant 3D-NoC solutions focus on permanent errors that occur in Through-Silicon-Vias (TSVs) to improve production. For example, some of the spare TSV pad insertion: spare A TSV pads insertion (Non-Patent Document 1), or serialization: is based on the serialization (Non-Patent Document 2).

Other solutions have focused only on link error by applying the error resilience Lou tee ing algorithm. Most of the existing solutions (Non-Patent Documents 3-6) store information on surrounding error links based on the routing table to avoid the occurrence of deadlock. They use virtual channels (VCs) (Non-Patent Document 7). Others avoided the use of VCs and instead used conversion-model routing to avoid deadlock (8).

US Patent Application Publication No. 2012/0155482

I. Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, and Luca Benini.A low-overhead fault tolerance scheme for TSV-based 3D network-on chip links.In ICCAD 08: Proceedings of the 2008 IEEE / ACM International Conference on Computer-Aided Design, pages 598-602, 2008 S. Pasricha. Exploring serial vertical interconnects for 3D ICs. In DAC 09: Proceedings of the 46th Annual Design Automation Conference, pages 581-586, New York, NY, USA, 2009. ACM Ch. Feng. M. Zhang, J. Li. J. Jiang. Z. Lu and A. Jantsch. A Low-overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip.IEEE Computer Society Annual Symposium on VLSI, pages 19-24. July 2011 Y. Li Shietung Peng, and Wanming Chu.Adaptive box-based efficient fault-tolerant routing in 3D torus.pages 71 -77, 2005 Ch. Feng.Z, Lu, A. Jantsch, J. Li and M. Zhang.A Reconfigurable Fault-tolerant Deflection Routing Algorithm Based on Reinforcement Learning for Network-on-Chip.The 3rd International Workshop on Network on Chip Architectures, pages 11-16, December 2010 D. Xiang, Y. Zhang and Y. Pan. Practical Deadlock-Free Fault-Tolerant Routing Based on the Planar Network Fault Model.IEEE Transactions on Computers, 58 (5): 620-633. May 2009 W. J. Dally.Virtual-channel flow control.IEEE Trans. On Parallel and Distributed Systems, 3 (2): 194-205, March 1992 S. Pasricha and Y. Zou. A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip.The 12th International Symposium on Quality Electronic Design, pages 1-8, March 2011 T. Lehtonen, P. Liljeberg and J. Plosila. Online Reconfigurable Self-timed links for Fault Tolerant NoC. VLSI Design, (2007): 1-13, 2007 DeOrio, A. et. Al., A Reliable Routing Architecture and Algorithm for NoCs.IEEE Transactions on CAD of Integrated Circuits and Systems. May 2012, pp. 726-739 A. Ben Ahmed and A. Ben Abdallah.Architecture and Design of High-throughput, Low-latency, and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip (3D-NoC) .The Journal of Supercomputing, DOI: 10.1007 / s 11227-013-0940-9 A. Ben Ahmed and A. Ben Abdallah. Fault-tolerant Routing Algorithm with Deadlock Recovery Support for 3D-NoC Architectures. The 7th IEEE International Symposium on Embedded Multicore SoCs. September 2013 A. Ben Abdallah, Multicore Systems-on-Chip: Practical Hardware / Software Design, 2nd Edition, Publisher: Springer, (2013), ISBN-13: 978-9491216916

As explained above, despite the various existing solutions describing the error resilience problem in 3D-NoC systems, some problems still remain as described below.

First, some solutions focused only on permanent errors and did not consider other types of errors . However, as described in Non-Patent Document 9, most of the errors (80%) are caused by transient errors , and the remaining errors are mainly based on permanent and intermittent errors .

Secondly, many solutions have focused on link errors . However, according to Non-Patent Document 10, the input buffer and the crossbar occupy a large area in the 3D-NoC system reaching 80% and 10%, respectively. On the other hand, each of the remaining elements does not exceed 3% of the total router area. This means that errors in the input buffer and crossbar should be given greater importance. In addition, reliable solutions must be able to handle such types of errors .

Third, research already proposed is based on VCs to avoid the occurrence of deadlocks. VCs ensure that the system does not lead to deadlocks. However, they are based on adjustments that are expensive in terms of hardware complexity in addition to the latency disadvantages required to make the adjustments. Routing algorithms based on diversion models do not require the use of VCs. However, the non-minimal nature results in unnecessary clock cycles that affect system throughput.

  In summary, the conventional system has the following problems.

First, conventional systems focus only on permanent errors and do not consider other error types. However, the majority of errors in NoC are caused by transient errors , while the remaining errors are mainly due to permanent and intermittent errors .

Most conventional solutions have focused on link errors . However, in 2D or 3D-NoC systems, the input buffer and crossbar occupy a large area, and therefore, the error in the input buffer and crossbar should be given great importance.

Furthermore, the occurrence of deadlock is avoided based on VCs. VCs guarantee the avoidance of system deadlocks, but are based on the determination that they are expensive in terms of hardware complexity.

Accordingly, an object of the present invention is to provide an error- tolerant router in which the above problem is solved by dealing with three error types (transient, intermittent and permanent), and an IC using the error- tolerant router. . The proposed solution is directed to different types of errors in links, input buffers, and crossbar circuits provided in 2D or 3D-ICs that use the proposed error resilient router.

In the present invention, the random access buffer technology (RAB) used is based on a smart controller (RAB cntrl) that first detects Fritz, which is the reason for deadlock in the buffer. The detection mechanism relies on a timer to issue a flag and discard the request if the request being processed is not allowed after a certain period of time.

The RAB then frees some slots in the buffer and seeks other fritzs that are allowed to break the dependency. The RAB handles one request at a time in each input buffer. Thus, the presence of coordination is no longer necessary, as is the case for VCs. Furthermore, as the number of VCs increases, the complexity of VC placement also increases. And it is important to use an effective scheduling method. However, for RAB, the depth of the buffer does not affect its performance. In contrast, the probability of looking for unblocked Fritz is increased , resulting in faster deadlock recovery.

A first technical aspect according to the present invention is an error resistant router provided corresponding to each of a plurality of cores provided in a 3D-IC having a laminated wafer,
A plurality of input port portions (1-7) formed to receive input frits from the corresponding core direction by the input buffer (11) ,
A crossbar (13) for connecting outputs of the plurality of input port sections (1-7) to a predetermined output destination;
An error control module (20) having a prediction table (10) for storing traffic information of the input buffer (11) ;
To each of the plurality of input ports (1-7),
The input buffer (11);
An error detection circuit (91) for detecting a slot error in the input buffer (11);
A random access buffer controller (90) ;
When the error detection circuit (91) detects a slot error of the input buffer (11),
The random access buffer controller (90)
Checks whether other remaining slots are occupied, if the other remaining slots are occupied, before Symbol send a flag to the error control module (20),
Based on the traffic information stored in the prediction table (10), to select the best input buffer (11) of said input ports (1-7), notifies the random access buffer controller (90) Then, control is performed to switch to the selected input buffer (11) and store subsequent input flits .

A second technical aspect according to the present invention is a 3D-IC formed of stacked wafers each having a plurality of cores and a router corresponding to each of the plurality of cores,
Each router
A plurality of input port portions (1-7) formed to receive input frits from the corresponding core direction by the input buffer (11) ,
A crossbar (13) for connecting outputs of the plurality of input port sections (1-7) to a predetermined output destination;
An error control module (20) having a prediction table (10) for storing traffic information of the input buffer (11) ;
To each of the plurality of input ports (1-7),
The input buffer (11);
An error detection circuit (91) for detecting a slot error in the input buffer (11);
A random access buffer controller (90) ;
When the error detection circuit (91) detects a slot error of the input buffer (11),
The random access buffer controller (90)
Checks whether other remaining slots are occupied, if the other remaining slots are occupied, before Symbol send a flag to the error control module (20),
Based on the traffic information stored in the prediction table (10), to select the best input buffer (11) of said input ports (1-7), notifies the random access buffer controller (90) Then, control is performed to switch to the selected input buffer (11) and store subsequent input flits .

A third technical aspect according to the present invention is a method for controlling an error-tolerant router corresponding to each of a plurality of cores provided on a wafer forming a 3D-IC,
As the first processing stage,
The random access buffer controller (90) detects the deadlock and error state of the input buffer (11) of each input port section (1-7),
It receives traffic information from the probe that is included with each of the input buffers of the input port unit (1-7) (11),
Get identification information for the next port from the input Fritz
Send a switch request signal to the switch locator (16) ;
As the second processing stage,
The following ports calculated for the next node thus be executed routing module based on the received signal from the error control module (20),
Scheduling between requests from different ports to be managed by the switch placer (16),
A request signal and a control signal for permitting use of the switch arrangement output port requested by the (16), sent to the crossbar (13) having information about the scheduling result,
As the third processing stage,
Check the full Ritz from the input buffer (11) to the appropriate adjacent node.

Most conventional 3D-NoC systems are based on virtual channels (VCs) and avoid deadlocks. VCs ensure that there are no system deadlocks. However, these advantages involve higher levels of additional hardware in addition to the complexity of implementing such techniques. Furthermore, VCs, to handle multiple requests, it is necessary to have an adjustment, as a result, additional extra pipeline stages (usually referred to as VC placer), and thus an additional clock cycles I need it . Thus, this waiting time has an important influence on the throughput of the entire system.

  In the present invention, the random access buffer technology (RAB) used is based on a smart controller (RAB cntrl) that first detects that Fritz is the reason for buffer deadlock. The detection mechanism is based on a timer that issues a flag and discards the request if the request being processed is not allowed after a certain period of time.

The RAB then seeks other Fritz for which the request is granted in order to free some slots in the buffer and break the dependency. The RAB processes one request at a time in each input buffer. Thus, the presence of coordination is no longer necessary, as is the case for VCs. Furthermore, as the number of VCs increases, the complexity of the VC placer also increases. And it is essential to apply an effective scheduling method. However, in the case of RAB, the buffer depth does not affect its performance. In contrast, the probability of looking for unblocked Fritz is increased , resulting in faster deadlock recovery.

FIG. 3 is a block diagram of a proposed 3D error- tolerant OASIS-NoC router structure according to the present invention. It is a figure which shows the block diagram of the random access buffer 9. FIG. It is the schematic explaining the prediction table. It is a figure which shows the counter value when a system starts. It is a figure which shows the number of the input Fritz output after 1st 100 cycles. It is a figure which shows calculation of average Fritz arrival. It is a figure which shows determination of the best candidate buffer. It is a figure which shows transmission of the newest best candidate buffer. It is a figure which shows the algorithm of look-ahead error tolerance routing. FIG. 6 illustrates a bypass link-on-demand mechanism. It is a figure which shows the time chart in operation | movement of 3D error tolerance NoC (3D-FTNoC) according to this invention. It is a figure which shows the time chart of the conventional router used most generally.

Embodiments of the present invention will be described with reference to the accompanying drawings. The example is for better understanding of the invention, and the scope of protection of the invention is not limited to this example.

  The 3D-IC formed by stacking a plurality of small wafers will be mainly described. However, the present invention includes a plurality of cores formed on one wafer and a network connecting the plurality of cores. It can also be applied to 2D-ICs.

[3D- Error Resistant Router-NoC Architecture]
FIG. 1 shows a block diagram of a proposed 3D- error- tolerant-OASIS-NoC router structure according to the present invention.

  In FIG. 1, each NoC router receives local input port 1, north input port 2, east input port 3, south input port 4, and west input that receive inputs from the corresponding directions of the cores formed on the stacked wafers. It has a plurality of input port units which are an input port 5, an up input port 6, and a down input port 7.

Each of the input port units 1-7 has a look-ahead error resilience (LAFT) routing algorithm 8 that was previously proposed in Non-Patent Document 11 and handles error links. In addition to LAFT Rute I ing algorithm 8, in accordance with the present invention, in order to further support the error resilience, two major components are used.

That is, a random access buffer (RAB) mechanism 9 used with a prediction table (PT) 10 that is an element of a traffic prediction unit located in the error control module 20 for errors in the input buffer 11 is Provided in each of the units 1-7. Furthermore, a bypass link on demand (BLOD) 12 for errors in the crossbar 13 is provided.

The random access buffer (RAB) mechanism 9 has a deadlock management function and an error management function in addition to the RAB controller 90.

The RAB controller 90 of the random access buffer (RAB) mechanism 9 regularly monitors the corresponding input buffer 11 for error conditions. When the presence of an error slot is detected, it is checked whether or not the remaining slots are occupied.

If the remaining slots are occupied, the RAB controller (cntrl) 90 sends a single-bit “buffer flag: Buffer-flg” signal to the prediction table 10. This prediction table 10 already has information about the traffic load of each of the remaining input buffers and sends a “Best-buff” signal back to the RAB-controller 90. The RAB-controller 90 redirects the input frits that are split from the packet and equal to the link width to the newly selected input buffer 11 .

When the previously detected error in the input buffer 11 is eliminated, or when the input buffer 11 is almost free and can receive other input frits, the “buffer flag: Buffer-flg” signal returns to 0. Then, the prediction table 10 is notified that it is not necessary to use another input buffer resource. The previous error buffer then starts receiving and storing a new input Fritz.

[Random access buffer controller (RAB buffer cntrl) 90 ]
FIG. 2 shows a block diagram of the proposed random access buffer mechanism 9. The random access buffer mechanism 9 was previously proposed as a basic and low-load solution for ensuring deadlock free in Non-Patent Document 12.

In the present invention, an extended random access buffer controller (hereinafter referred to as buffer controller) 90 is provided, and a random access buffer mechanism (RAB mechanism) 9 is used as a random access buffer mechanism (RAB mechanism) 9 to prevent transient, intermittent, and permanent errors in the input buffer 11. Can be detected and recovered.

The random access buffer mechanism 9 is distributed into two main parallel phases. The first phase is a local process that means that error detection and error recovery are performed. The second phase is the overall (ie, in the entire router) process, where a random access buffer mechanism (hereinafter RAB mechanism) 9 is supported by the prediction table (PT) 10 and, as will be described later, Increase system performance further.

For error detection, an error detection circuit 91 shown in FIG. 2 is used to check the error status of the buffer slot of the input buffer 11. When an error is detected in one of the slots by the error detection circuit 91, the error detection circuit 91 sends a “ error slot: faulty-slot” signal to the RAB module 92 in the buffer controller (Buffer_Contrl) 90, and the buffer controller (Buffer_Contrl) When giving the write address “Wr_adr” and the read address “Read_adr” from the FIFO 93 in the buffer 90, the flagged slot is considered.

In order to maintain a record of error slots, a status register consisting of an array handling n2 bit items (n is the depth of the buffer) is provided in the RAB module 92.

When the value of each item held in the status register is “00”, it notifies that the corresponding Fritz is not deadlocked and the buffer slot is not in error . When “01”, it indicates that the buffer slot is not in error , but the Fritz request being handled is deadlocking. Finally, if an error is detected in the corresponding buffer slot, the element in the status register is updated to “11”. Thus, the slot cannot be used (to avoid additional latency to look for broken slots) nor can it store the incoming Fritz.

[Prediction table (PT) 10]
FIG. 3 shows a simple example illustrating the use of the prediction table 10 provided in the traffic prediction unit 100. An interesting case that often arises is that if a given input buffer 11 has several error slots, the remaining slots are occupied by other Fritz and other input buffers of the same router are emptied. . In order to expand performance and use all router resources completely, the present invention adopts a technique for sharing input buffer resources in all input ports 1-7. This is achieved quickly when the input buffer 11 cannot handle more Fritz (due to the presence of an error slot, the remaining slot is occupied), redirecting the input Fritz to another adjacent empty input buffer. It means you can send it first.

To achieve this goal, it is very important to know the best candidate to receive the redirected Fritz in the available free input buffer. In the present invention, as shown in FIG. 3, a prediction table (PT) 10 is used to collect information on traffic load (signal 50) of each input port at a specific time period. These pieces of information are received from the monitoring probes (Prb0 to Prb6) 14 added to the input buffers 1-7 in the router. A snapshot of the collected traffic is used to calculate the arrival of average frits in each input buffer. The prediction table 10 can determine the best input port that can handle the frits of the error input buffer without causing traffic jams.

When the best input buffer is selected (the east buffer 3 in this embodiment), the prediction table 10 waits for a flag 51 issued from the RAB controller (RAB cntrl 0-6) 90. The buffer error shown in FIG. 2 gives information that the buffer (input buffer 11 of north input port 2) is in error and is full at the same time. In this case, the prediction table 10 returns another signal to the corresponding input buffer of the north input port 2 and designates a new input buffer (for example, the input buffer of the east input port 3). As shown, the input frits are accepted until some slots are opened and the input buffer of the north input port 2 can receive the input frits again.

Several fritzs of a given packet are stored in the buffer and declared to be in error and full. Then, according to the RAB mechanism 9, the remaining Fritz of this packet may be stored in a different buffer. In this case, since the remaining Fritz are stored in different buffers, these Fritz may not reach the order.

As a result, the reaching node requires a reordering process, or there is a delay that must be added to some Fritz so that it can be reached simultaneously with the remaining Fritz. In the present invention, as a simple solution, if a header, it is started only directed Fritz. In this case, the remaining Fritz of this packet is stored in the same buffer as the header Fritz. With this additional restriction, packet frits arrive in order without additional hardware / power overload and performance degradation.

  3A to 3E are diagrams showing details of the operation of the traffic prediction unit 100. FIG.

3A-3E, probes 1-6 are a local probe, a north (Nth) probe, an east (Est) probe, a south (Sth) probe, a west (Wst) probe, an up (Up) probe, and a down probe. Corresponds to each (Dwn) probe. Each of the probes 1-6 has a counter that advances each time a new Fritz reaches the input buffer 11 using a cue signal. The count value of the counter is stored in an 8-bit register that can store the number of fritzs reached in 100 cycles.

  The traffic prediction unit 100 includes a prediction table 10 that can accept seven inputs each of 8 bit size. Each input is assigned to one input port and stores its Fritz arrival rate.

  The traffic prediction unit 100 operates according to the following steps.

  1) Each probe outputs its value and sends it to the prediction table 10 every 100 cycles (to reduce the register size).

  2) The traffic prediction unit 100 calculates the average value of Fritz in 100 cycles (Flits / 100 cycles) using the value coming from the probe and the value already in the prediction table 10.

  3) The new average value is updated in the prediction table 10.

  4) The traffic prediction unit checks the average of the seven input ports and selects the smallest value that is considered the best candidate.

5) When the RAB sets a flag (Buffer_flg signal) that there is an error in the full buffer, it sends the best candidate to be used as a save channel calculated by the traffic prediction unit 100.

  Here, according to the above steps, an example of the operation in the traffic prediction unit 100 will be described.

  In FIG. 3A, when the system starts, the value of the probe counter and the input of the prediction table 10 are initialized to zero.

  In FIG. 3B, after the first 100 cycles, the number of input frits is output from the probe, sent to the traffic prediction unit 100, and the average value cannot be counted, so it is stored directly in the prediction table 10. At the same time, the probe counter is reset to zero. The waist is then calculated as the best candidate buffer when the Fritz average is 10, which is the minimum value.

  In FIG. 3C, every 100 cycles, the probe outputs its value and sends it to the traffic prediction unit 100. The traffic prediction unit 100 reads input information from a predetermined input port, reads the corresponding value in the prediction table 10, and calculates the arrival value of the average fritz.

Then, in FIG. 3D, the probe counter is reset to zero again. The input of the prediction table 10 is updated with the calculated average value. The minimum value in the prediction table 10 is calculated and the best candidate buffer is determined (the local whose average is the smallest 35 is the best candidate).

In FIG. 3E, when the traffic prediction unit 100 receives a buffer flag (Buffer_flg) signal from the RAB module 9 (notifying that the buffer 11 is empty and has an error , see FIG. 1), the traffic prediction unit 100 It is the latest best candidate buffer used as an input buffer for alternatives to input Fritz, send flagged buffer.

[Look-Ahead Error Resilience Router (“LAFT”)]
In order to retain the advantages of prefetch routing, the previously proposed prefetch error resilience (LAFT) [Non-Patent Document 11] executes a routing decision for the next node in consideration of the link state, and the algorithm of FIG. As shown in FIG. 1, the best minimum path is selected.

Error information received from the error control module (FCM) 20 (error links in FIG. 1) is read by each input port LAFT is executed.

  The first phase of the algorithm calculates the next node address. There are up to three possible directions through each of the X, Y, and Z dimensions for a given node that wishes to send a Fritz to a given final destination.

In the second phase, LAFT performs this three-way calculation by simultaneously comparing the X, Y, Z coordinates of both the current and destination nodes. Simultaneously with the calculation of these directions, the error control module 20 reads the next port identifier from the Fritz and sends the appropriate error information to the corresponding input port. By the end of this second phase, LAFT has information about the error status of the next node and about these possible three directions for the minimum route.

In the next phase, route selection is performed. For this determination, the present invention employs a set of prioritization conditions a, b, and c as shown below, and guarantees error resilience and high performance regardless of the presence or absence of errors .

a. The chosen direction guarantees a minimum path and is given high priority in route selection.

b. Direction, then the spread of paths, which is expected to the maximum one is selected.

    c. The congestion state is given the lowest priority.

Based on these priorities, LAFT reads the error status of the next node received from error control module 20 and checks the number of possible non- error minimum directions. When the three possible directions are minimal and have the same spread , route selection is performed depending on the congestion of each output port.

[Bypass link upon request]
FIG. 5 shows the on-demand bypass link mechanism that provides an additional avoidance channel each time the number of errors in the reference 7 × 7 crossbar 13 increases.

In FIG. 5, the two bypass links 131 and 132 have the configuration of the embodiment. Crossbar sub-controller (cntrl Unit) 17 shown in FIG. 5 checks the crossbar link state, if an error is detected in one or several link flag (Faulty_Cross: error Cross) error control Sends to module 20 to disable false crossbar links and allow an appropriate number of bypass links.

The simplest approach is to provide a specified bypass link for every crossbar. In this manner, both error resilience and performance are guaranteed. This is because the input port requirement does not share the bypass link even if all the reference 7 × 7 crossbar links of the reference 7 × 7 crossbar 13 are incorrect . However, this method is the same as duplicating the entire crossbar, thus ensuring additional area and power consumption. Furthermore, when the error rate is small, only two or three bypass links can sufficiently meet the demand for an error crossbar link.

In accordance with this fact, in the present invention, a gradually increasing approach is performed and usage benchmarks and estimated error rates are analyzed. The number of bypass links is gradually increased until the performance is constant or hardly changes.

  The number of bypass links is very important and should be minimized as much as possible to reduce area and power consumption. Therefore, unused crossbar links that already exist in the system are utilized.

These links are basically located at the edge of the network and have no adjacent nodes. Therefore, the corresponding crossbar is not used. This optimization allows for significant area and power savings while maintaining maximum performance.

[ Error control module (FCM) 20]
The error control module (FCM) 20 is one of the main elements of the present invention. This is because it manages the recovery of all three types of errors : the inter-router link, the input buffer, and the crossbar. Starting with an inter-router link, the link status of each router and its neighboring router error status are stored in a small array named “link status”.

These information are always sent to the LAFT routing module 8 and used during the selection of the “next port” corresponding to the next node. For input ports, the prediction table 10 handles the allocation of other buffer resources when needed, as explained above. However, when all buffer resources are in error and can no longer accept Fritz, error control module 20 receives a “buffer error ” signal (shown in FIG. 1) from RAB controller 90.

When receiving this “buffer error ” signal, error control module 20 disables the entire input port to reduce dynamic power. At the same time, error control module 20 updates the flags "link state array" to links connected to the error buffer. These pieces of information are always sent to the error control module 20 in all adjacent nodes.

Finally, with the cross bar 13, to handle the error, the error control module 20, as will be described in detail, the three main tasks.

      1) Update the “Crss_link” status register 22 according to the information received from the control (cntrl) unit 17 (shown in FIG. 1).

2) Activate and deactivate the appropriate number of “bypass links” 131, 132 depending on the number of detected errors .

3) “Sw_req_cntrl” 15 is notified of the erroneous crossbar link so that the request can be changed before being sent to the switch placement unit 16.

As shown in FIG. 1, the control unit 17 is an element between the baseline 7 × 7 crossbar 13 and the additional “bypass link” 12. The first role of the control unit 17 detects the presence of an error in the cross bar 13, the status of the error to continue notifying the error control module 20. The error control module 20 monitors the input error information and stores it in the register 21 with the name “cross-link” (FIG. 1).

When an error is detected, the error control module 20 transmits three signals simultaneously. Two for control unit 17 enable one of the bypass links and disable the erroneous crossbar link. The remaining one is then sent to the “Switch Request Control Sw_req_cntrl” unit 15 to prevent Fritz from requesting an error crossbar link, and instead use one of “Bypass_links”. Ask for permission.

As the number of errors increases, the error control module 20 manages distributing different requests to possible bypass links in a fair manner. On the other hand, the control unit 17 has a role of enabling or disabling the bypass link using a clock gate technique for power reduction in accordance with a signal received from the error control module 20. This is because when the crossbar 13 is enabled, the bypass link is put into a sleep state to reduce dynamic power, and when an error is detected, the control unit 17 responds to the information from the error control module 20, It means to create an appropriate number of bypass links. The control unit 17 includes a multiplexer and a demultiplexer. The demultiplexer is used to redirect the input frits to the activated “bypass link” instead of the erroneous crossbar link, and the multiplexer has the function of switching between the reference crossbar 13 and the “bypass link”. Pass to the next adjacent node of Fritz.

FIG. 6 is a diagram illustrating the operation of 3D error tolerance NoC (3D-FTNoC) according to the present invention. As shown in this figure, 3D-FTNoC includes three main pipeline stages I, II, and III. The first pipeline stage I is the buffer write stage, and the three main elements work in parallel as follows.

1) The RAB controller 90 of the RAB mechanism 9 monitors the deadlock and the error state of the input buffer 11 as described above.

      2) The prediction table 10 receives traffic information from the probe (Prb0-Prb6) 14 attached to the input buffer 11 of each input port 1-7.

      3) The switch adjustment controller (Sw-reqcntrl) 15 reads the identifier of “Next-port” from the input Fritz and issues a “switch request: sw-req” signal to the switch placement unit 16.

The second pipeline stage II is a routing calculation / switch placement stage. In this stage, two main processes are performed simultaneously. The first process is the calculation of the “next port” for the next node executed by the LAFT routing module 8 according to the signal received from the “link status” register 21 in the error control module (FCM) 20. . The second process is scheduling between different requests from different input ports managed by the switch locator 16 having different “switch request signals” as inputs. As an output, the switch placement unit 16 issues a “switch permission” signal for permitting use of the requested output port and a “cross control Crss_contrl” signal for the crossbar 13 having information on the schedule result.

These two stages I, parallelization of II can be achieved by pre-reading (the Look ahead) routing relies a system according to the present invention. With this type of routing, the dependency between two stages I and II, which are usually performed in series in conventional systems, can be eliminated.

Finally, in the crossbar crossing stage as the third pipeline stage III, Fritz is taken from the input buffer 11 of the input port 1-7 and sent to the appropriate adjacent node. As seen in FIG. 6, the error control module 20 controls the communication between the elements of different routers Its main function, therefore is to establish, three pipeline stages I, II, along III , Perform different tasks.

  For an understanding of the novelty of the architecture according to the invention, FIG. 7 shows a time chart of a conventional router used in the most popular system compared to the architecture of the invention.

The first comment on this conventional system is that it lacks error resilience support if no element for error detection or recovery is found. Further, as seen in FIG. 7, there are five pipeline stages IV instead of the three stages of the present invention shown in FIG.

  The first stage is the same as the buffer write stage I having basically the same function as in the system of the present invention. However, instead of using a single buffer 11, virtual channels (VCs) are used to satisfy the deadlock avoidance requirement. The number of VCs depends on the system architecture and routing algorithms that can generally vary between 2-4 VCs.

The next stage II is a routing operation, where most systems employ static XYZ routing or other routing based on the latter. Due to the lack of read-ahead routing, the next two stages cannot operate without receiving results from the XYZ routing module.

The third stage III is a virtual channel arrangement stage. The use of VCs requires adjustment to add additional clock periods. Therefore, all pipeline stages are involved for coordination between different VCs. Compared to FIG. 7, the system of the present invention eliminates this stage thanks to the RAB module used for deadlock avoidance.

  After the VC gives permission, it switches to the switch placement stage IV which is the same as the present invention shown in FIG. However, the only difference is that it is performed independently of the routing operation stage II. And they are not executed in parallel as with the system of the present invention. Finally, in the final stage V (crossbar crossing), the crossbar 13 performs transfer to the adjacent node of Fritz according to the adjustment result received from the switch placement unit 16.

Claims (10)

An error resistant router provided corresponding to each of a plurality of cores included in an IC,
A plurality of input port portions (1-7) formed to receive input frits from the corresponding core direction by the input buffer (11) ,
A crossbar (13) for connecting outputs of the plurality of input port sections (1-7) to a predetermined output destination;
An error control module (20) having a prediction table (10) for storing traffic information of the input buffer (11) ;
In each of the plurality of input port portions (1-7),
The input buffer (11);
An error detection circuit (91) for detecting a slot error in the input buffer (11);
A random access buffer controller (90) ;
When the error detection circuit (91) detects a slot error in the input buffer (11),
The random access buffer controller (90)
Checks whether other remaining slots are occupied, if the other remaining slots are occupied, before Symbol send a flag to the error control module (20),
Based on the traffic information stored in the prediction table (10), to select the best input buffer (11) of said input ports (1-7), notifies the random access buffer controller (90) Then, control is performed to switch to the selected input buffer (11) and store subsequent input flits .
An error-resistant router characterized by that. In claim 1,
The prediction table (10) collects traffic load information from each of the plurality of input port units (1-7) at a predetermined timing period, calculates the average Frits arrival, and accepts the frits of the error input buffer. Determine the input port of the
An error-tolerant router characterized by that. In claim 1,
A plurality of bypass links (131, 132) to the crossbar (13);
A crossbar control unit (17) for checking a link state of the crossbar (13);
When the crossbar controller (17) detects an error in one or more links, it sends a flag to the error control module (20),
The error control module (20) disables an error link of the crossbar, and the crossbar and the plurality of bypass links (131, 132) that are not used until the execution process settles or remains unchanged. ) Increase the number of possible,
An error-tolerant router characterized by that. In any one of claims 1 3,
The error-resistant router, wherein the IC is a 3D-IC composed of a plurality of laminated wafers each having a plurality of cores. A three-dimensional IC comprising a plurality of cores each having a plurality of error-resistant routers corresponding to the plurality of cores,
Each of the plurality of error-tolerant routers is
A plurality of input port portions (1-7) formed to receive input frits from the corresponding core direction by the input buffer (11) ,
A crossbar (13) for connecting outputs of the plurality of input port sections (1-7) to a predetermined output destination;
An error control module (20) having a prediction table (10) for storing traffic information of the input buffer (11) ;
In each of the plurality of input port portions (1-7),
The input buffer (11);
An error detection circuit (91) for detecting a slot error in the input buffer (11);
A random access buffer controller (90),
When the error detection circuit (91) detects a slot error in the input buffer (11),
The random access buffer controller (90)
Other remaining slots is checked whether it is occupied, if the other remaining slots are occupied, send a flag to the error control module (20),
Based on the traffic information stored in the prediction table (10), to select the best input buffer (11) of said input ports (1-7), notifies the random access buffer controller (90) Then, control is performed to switch to the selected input buffer (11) and store subsequent input flits .
A three-dimensional IC characterized by this. In claim 4 ,
The prediction table (10) collects traffic load information from each of the plurality of input port units (1-7) at a predetermined timing cycle, calculates an average flit arrival time, and appropriately handles an error input fritz. Determine the input port,
A three-dimensional IC characterized by this. In claim 4 ,
A plurality of bypass links (131, 132) to the crossbar (13);
A crossbar control unit (17) for checking a link state of the crossbar (13);
When one or more link errors are detected by the crossbar control unit (17), a flag is sent to the error control module (20);
The error control module (20), prior to disabling the error links chrysanthemum crossbar, to enable the appropriate number of the plurality of bypass links (131, 132),
A three-dimensional IC characterized by this. In any one of Claims 5-7 ,
The three-dimensional IC , wherein the IC is a 3D-IC composed of a plurality of wafers each having a plurality of cores. An error-resistant router control method provided for each of a plurality of IC cores,
As the first processing stage,
The random access buffer controller (90) detects the deadlock and error state of the input buffer (11) of each input port section (1-7),
Receiving traffic information from the probe attached to each input buffer (11) of the input port section (1-7);
Get identification information for the next port from the input Fritz
Send a switch request signal to the switch placement unit (16),
As the second processing stage,
Calculating the next port for the next node to be executed by the routing module based on the received signal from the error control module ( 20 );
Scheduling between requests from different ports managed by the switch locator (16);
Sending a request signal and a control signal permitting the use of the output port requested from the switch locator (16) to a crossbar (13) having information on scheduling results;
As the third processing stage,
A method for controlling an error-tolerant router, characterized in that the Fritz from the input buffer (11) is checked and sent to an appropriate adjacent node. In claim 9 ,
The IC is a 3D-IC that includes each of a plurality of cores and is formed of a laminated wafer.
An error-resistant router control method characterized by the above.