JP6199704B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a serial data communication between a master and a slave and a communication system for supplying power to the slave, and a semiconductor integrated circuit used for the communication.

  Conventionally, as described in Patent Document 1 (the same applies to Non-Patent Document 1) or Patent Document 2, one terminal (for both signal / power supply), two wirings (signal line: 1, GND: 1), and master ( There is a technique in which one or a plurality of) and a slave (a plurality) communicate.

US Pat. No. 5,210,846 US Pat. No. 6,532,506

Maxim Japan, “1-Wire Overview”, <URL: http://japan.maximintegrated.com/products/1-wire/pdfs/what_is_1-wire_en.pdf>

  In the inventions described in Patent Document 1 (the same applies to Non-Patent Document 1) and Patent Document 2, since the signal line (1 terminal) and the power supply are combined, power is supplied from the signal line only when the signal line = "Hi" level Yes, power cannot be supplied at "Low" level. For this reason, there are the following problems.

(A) Slave side: In order to hold the power supply between the signal line = “Low” level, a relatively large size smoothing capacitor between the power supply / GND is necessary. In order to reduce the smoothing capacitor, it is necessary to reduce the current consumption while the signal line = "Low" duration.
(C1 × ΔV1 ≧ Icc × Δt1, C1 = smoothing capacitor between power supply / GND, ΔV1 = allowable voltage drop of power supply, Icc = current consumption, Δt1 = “Low” duration)

(B) Master side: When the signal line = "Low"->"High" changes, it is necessary to charge the power supply of each slave together with the parasitic capacitance of the signal line. is necessary. In order to reduce the output driver size, it is necessary to reduce the number of connected slaves, the signal line parasitic capacitance, the change voltage during charging, or increase the allowable signal line rise time.
(I (Drive) × Δt2 ≧ N × C2 × ΔV2, I (Drive) = “High” drive current, Δt2 = signal line rise time, N = number of connected slaves, C2 = signal line parasitic capacitance, ΔV2 = during charging Change voltage)

  As described above, there are restrictions on the data rate, the number of connected slaves, the chip size (master side: output driver size, slave side: size of smoothing capacitor between power supply / GND), and the like.

  In the invention described in Patent Document 1, both the master / slave are open drain type, and the “High” drive uses a pull-up resistor. Therefore, the pull-up resistance value is low for both Low → High and High → Low transition times. There is a problem that it is restricted by the parasitic capacitance of the signal line.

  Further, since the invention described in Patent Document 2 has both “High” and “Low” drives on the master side and “Low” drives on the slave side, there is a possibility that High / Low drives may collide. Collisions) There are problems such as the need for a workaround.

In view of the above-mentioned problems, the present invention has a small number of wires and is limited in data rate, number of connected slaves, chip size (master side: output driver size, slave side: smoothing capacitor size between power supply / GND), etc. An object is to provide a small number of semiconductor integrated circuits.
Furthermore, when sending data from the master side to the slave side, the transmission line is balanced to reduce common mode noise, and the number of transmission line inversion operations required to send 1-bit data. The purpose is to suppress unnecessary radiation to the surroundings by reducing.

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit that performs communication performed between at least one master and a plurality of slaves by two wirings,
The master side
A set of master-side output buffers whose output ends are connected to the two wires;
A master side input circuit for inputting signals from the two wirings and a master side control unit for controlling the overall operation of the master;
The slave side
A set of slave-side output buffers whose output ends are connected to the two wires;
A set of slave side input circuits for inputting signals from the two wires;
A rectifier circuit that rectifies a potential difference between the two wirings and extracts operating power on the slave side, and a slave side control unit that controls the overall operation of the slave;
The master-side control unit controls the length of the duration for fixing the output of the master-side output buffer to “High” / “Low”, or “Low” / “High”. 1 "send and
The slave-side control unit controls the slave-side output buffer so that “High” / “Low” in the slave response section does not respond, or both wires have “Low” output. It is characterized by realizing data transmission to the master.
Another feature of the semiconductor integrated circuit of the present invention is a semiconductor integrated circuit in which communication performed between at least one master and a plurality of slaves is performed with two wires.
The master side
A set of master-side output buffers whose output ends are connected to the two wires;
A set of master side input circuits for inputting signals from the two wirings;
Master power supply / GND,
It has a master side control unit that controls the overall operation of the master,
The slave side
A set of slave-side output buffers whose output ends are connected to the two wires;
A set of slave side input circuits for inputting signals from the two wires;
A rectifier connected between the two wirings and a smoothing capacitor connected to the output of the rectifier (= slave power supply / GND);
It has a slave side controller that controls the overall operation of the slave,
Power supply from the master to the slave is performed by the master side control unit controlling the output of the master side output buffer to either "High" / "Low" or "Low" / "High"
On the slave side, the operation power is taken out from the rectifier circuit connected between the two wires.
Data transmission from the master to the slave is determined by controlling the length of the duration during which the master side control unit fixes the output buffer output to "High" / "Low" or "Low" / "High" And
For data transmission from the slave to the master, the slave side output buffer is controlled so that "High" / "Low" in the slave response section, no response on the slave side, or "Low" output on both wires Thus, data “0” and “1” transmission is executed.

According to the present invention, power can always be supplied from either one of the signal lines (two terminals) except when the slave responds to “1”. As a result, it is possible to reduce the size of the smoothing capacitor between the power supply / GND compared to the slave side: conventional literature.
Further, according to another feature of the present invention, when the signal line on the master side changes from “Low” to “High”, only the parasitic capacitance of the signal line is considered, and charging of the power supply of each slave is considered much. Therefore, the size of the output driver can be reduced as compared with the conventional literature.
Further, unnecessary radiation to the surroundings can be suppressed.

1 is a block diagram illustrating a configuration example of a semiconductor integrated circuit according to a first embodiment of this invention. It is a block diagram which shows the structural example of an output buffer. It is a block diagram which shows the structural example of an output buffer. FIG. 10 is a block diagram illustrating a configuration example of a semiconductor integrated circuit according to the second embodiment of this invention. FIG. 10 is a block diagram illustrating a configuration example of a semiconductor integrated circuit according to a third embodiment of the present invention. It is a figure which shows embodiment and shows a signal timing when transmitting data from a master to a slave. It is a figure which shows embodiment and shows a signal timing when transmitting data from a slave to a master.

(First embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1-1 is a block diagram illustrating a configuration example of the first embodiment of the present invention.
1-1, 100 is a master, 110, 120, and 130 are slaves. Since the slave 110, the slave 120, and the slave 130 have the same circuit configuration, illustration of the circuits of the slave 120 and the slave 130 is omitted. TRX0 and TRX1 are two (one pair) wires used for communication. Moreover, although the three slaves 110-130 are shown in FIG. 1-1, three or more slaves may be sufficient.

  101, 102, 111, 112 are three-state (with Hi-Z function) output buffers, 103, 104, 113, 114 are input circuits, 115 is a rectifier circuit (diode bridge), and 116 is a smoothing capacitor between the power supply / GND. 107 is a master side control unit, and 117 is a slave side control unit. The master side control unit 107 and the slave side control unit 117 are provided for controlling transmission / reception performed between the master 100 and the slave 110. VCC_M is a power source of the master 100, and GND_M is a GND of the master 100. VCC_S1 is a power source of the slave 110, and GND_S1 is a GND of the slave 110.

  Although the detailed configuration of the master side control unit 107 is omitted, in order to control the overall operation of the master 100, the master side control unit 107 is configured by a computer system including a CPU, a ROM, and a RAM, or a logic circuit. In the case of a CPU, the program stored in the ROM is expanded in the RAM and executed by the CPU to realize the operation of the master 100 described later.

  The slave side control unit 117 has the same configuration as the master side control unit 107. In the case of a CPU, the program stored in the ROM is expanded in the RAM and executed by the CPU to realize the operation of the slave 110 described later.

FIG. 4 is a diagram illustrating an example of signal waveforms of the pair of wirings TRX0 and TRX1 at the time of transmission between the master and the slave.
FIG. 5 is a diagram illustrating an example of signal waveforms of the pair of wirings TRX0 and TRX1 at the time of transmission between the slave and the master.

Hereinafter, the operation during transmission between the master 100 and the slave 110 according to the first embodiment of the present invention will be described with reference to FIGS.
When data is transmitted between the master 100 and the slave 110, the output buffer 101 and the output buffer 102 of the master 100 are set to enable output, and the output of the output buffers 101 and 102 is “High” / “Low” or “Low” / ”. Set to either “High” by the master-side control unit 107. Further, the output buffer 111 and the output buffer 112 on the slave 110 side are set by the slave side control unit 117 to the output Hi-Z setting (input enable).

  In this case, the power supply VCC_S1 of the slave 110 is supplied from the pair of wirings TRX0 and TRX1 via the rectifier circuit 115 and is held by the smoothing capacitor 116 between the power supply / GND.

  Data “0” and “1” are determined by the duration of the output of the master 100 being “High” / “Low” or “Low” / “High”. In the present embodiment, “1” is set when the duration is longer than a certain time, and “0” is set when the duration is short. For example, in the master side control unit 107 on the master 100 side, the duration when the data is “0” is set to T0, the duration when the data is “1” is set to T1, and the relative ratio of the time lengths is set to T0: T1 = 1: 3. To do.

  On the slave 110 side, the slave-side control unit 117 sets the threshold value for determining data “0” and “1” to 2 * T0 (= intermediate value between T0 and T1). The transmitted “0” and “1” data can be received on the slave 110 side via the input circuits 113 and 114.

  Usually, the time widths of the durations T0 and T1 are counted by the respective oscillation circuits (oscillators) and timers (both included in 107 and 117) on the master 100 side and the slave 110 side. Due to variations in the oscillation frequency of each oscillator, there is a possibility that the time widths of the durations T0 and T1 may be recognized differently on the master 100 side and the slave 110 side. Therefore, prior to data transmission from the master 100 to the slave 110, a fixed array pattern (SYNC pattern) of “0” and “1” is transmitted, so that the duration of the durations T0 and T1 on the master 100 side is set to the slave 110. The side learns so that the slave 110 can correctly receive “0” and “1”.

If the ratio of the durations T0 and T1 is set to be larger than the maximum and minimum values of T0 and T1 due to oscillation frequency variations of the master and slave oscillators, "0" and "0" before data transmission from the master 100 to the slave 110 It is also possible to determine without transmitting a 1 "fixed array pattern (SYNC pattern).
(Example: T0 (Max.) <(T0, T1 judgment threshold in slave) <T1 (Min.))
In FIG. 4, the duration T0 when the data is “0” and the duration T1 when the data is “1” are set to satisfy T0 <T1, but may be set so that T0> T1. .

Next, the operation at the time of transmission between the slave 110 and the master 100 according to the first embodiment of the present invention will be described with reference to FIGS.
During transmission between the slave 110 and the master 100, the output buffer 101 and the output buffer 102 of the master 100 are set to output enable, and the output buffer 101/102 output = "High" / "Low" or "Low" / "High" Either.
The output buffers 111 and 112 on the slave 110 side are set to output Hi-Z (input enable) except during a “1” response described later.

  In this case, the power supply VCC_S1 of the slave 110 is supplied from the pair of wirings TRX0 and TRX1 via the rectifier circuit 115 and is held by the smoothing capacitor 116 between the power supply / GND. The duration is fixed at T1.

  The slave 110 responds to the range of the dotted frame in FIG. For example, a “0” response is a no response. The “1” response is set by the slave-side control unit 117 so that both the output buffers 111 and 112 are set to “Low” output. At this time, since the pair of wirings TRX0 and TRX1 are close to the short-circuited state, the fact that the pair of wirings TRX0 and TRX1 is set to the “Low” output indicates that the master side via the input circuits 103 and 104 The control unit 107 can detect it. Thereby, the master side control unit 107 on the master 100 side can identify that the slave 110 has responded.

  In this case, power is not supplied from the master 100 to the slave 110 only in the “1” response interval, but the “1” response interval is short and the power level is kept constant by the smoothing capacitor 116 between the power supply / GND of the slave 110. There is no problem because it can be held for a long time.

In the slave 110 response section (the range of the dotted frame in FIG. 5), the current flowing from VCC_M to TRX0 / 1 to GND_M during the slave response is reduced by reducing the "High" drive current of the output buffer on the master 100 side. A method of suppressing can also be applied.
For example, the master-side output buffers 101 and 102 are configured by a plurality of buffer parallel connections as shown in FIG. 1-2, and the “High” and “Low” drive currents of the respective output buffers are set to different values. Normally, all output buffers are turned on, and only a part of the output buffer is turned on (others are turned off) only in the section where current is to be suppressed. It is possible to suppress current consumption on the master side at the time of slave response.

  Since this method can increase the voltage change of the pair of wirings TRX0 and TRX1, the master-side input circuit can have a simple circuit configuration such as a buffer. (In FIG. 5, this corresponds to a case where the voltage drop at the time of “1” response is larger than 0.5 × VCC). However, since the power cannot be supplied to the slave 110 during the response of the slave, the smoothing capacitor 116 between the power supply / GND of the slave 110 needs to be relatively large.

There is also a method of weakening the drive level of the slave side output buffer in the response section of the slave 110 (the range of the dotted frame in FIG. 5).
For example, the slave-side output buffers 111 and 112 are configured by a plurality of buffer parallel connections as shown in FIG. 1-2, and the “High” and “Low” drive currents of the respective output buffers are set to different values. If you want to suppress the current during slave response, turn on a part of the slave side output buffer (others are OFF), and make the "Low" drive capacity of the slave side output buffer smaller than the "High" drive capacity of the master side output buffer. As a result, it is possible to suppress current consumption on the master side during slave response.

This method has an advantage that power can be supplied to the slave even during slave response. The smoothing capacitor 116 between the power supply / GND of the slave 110 can be reduced. (In FIG. 5, this corresponds to the case where the voltage drop at the time of “1” response is smaller than 0.5 × VCC). However, since the voltage change of the pair of wirings TRX0 and TRX1 is small, the change of the power supply current of the output buffers 101 and 102 of the master 100 is detected by the master-side current detection circuits 105a and 105b. Detect response. Thereby, the master side input circuits 103 and 104 can be replaced by master side current detection circuits 105a and 105b. (Refer to “Current detection circuit” in FIG. 1-3. This corresponds to a response “1” when the power supply current is large, and a response “0” when the power supply current is small.)
Further, the “0” response may be such that both the output buffers 111 and 112 output “Low”, and the “1” response does not respond.
In FIG. 5, the time length during which the master 100 changes TRX0 and TRX1 is set to the same time as T1 in FIG. 4, but even if this is set to the same time as T0, either T0 or T1 is set. You may set a different time.

  As described above, according to the semiconductor device of the present embodiment, the number of wires is small, the data rate, the number of connected slaves, and the chip size (master side: output driver size, slave side: size of the smoothing capacitor between the power supply / GND) It is possible to realize a contact-type communication method and circuit with few restrictions on the above.

(Second Embodiment)
FIG. 2 is a block diagram showing a configuration example of the semiconductor integrated circuit according to the second embodiment of the present invention.
Reference numeral 200 denotes a master, and 210, 220, and 230 denote slaves. Since the slaves 210, 220, and 230 have the same circuit configuration, illustration of the circuits of the slave 220 and the slave 230 is omitted. Also in this embodiment, three slaves 210 to 230 are shown in FIG. 2, but there may be three or more slaves. TRX0 and TRX1 are two (one pair) wires used for communication.

  Reference numerals 201, 202, 211, and 212 are “Low” output transistors used as output buffers, and are composed of, for example, N-type MOS transistors. Reference numerals 203, 204, 213, and 214 denote input circuits. Reference numeral 215 denotes a rectifier circuit (diode bridge), and reference numeral 216 denotes a smoothing capacitor between the power supply / GND.

  Reference numeral 207 denotes a master side control unit, and 217 denotes a slave side control unit. These control units control transmission / reception. 209a and 209b are pull-up resistors or active loads. 208a and 208b are switches (for example, P-type MOS transistors) that determine whether the pull-up resistor or active load is valid / invalid. VCC_M is the power supply of the master 200, and GND_M is the GND of the master 200. VCC_S1 is the power supply of the slave 210, and GND_S1 is the GND of the slave 210.

FIG. 4 is a diagram illustrating an example of signal waveforms of the pair of wirings TRX0 and TRX1 at the time of transmission between the master and the slave.
FIG. 5 is a diagram illustrating an example of signal waveforms of the pair of wirings TRX0 and TRX1 at the time of transmission between the slave and the master.

The operation of the semiconductor integrated circuit of the second embodiment is almost the same as that of the first embodiment. The difference is that the “High” output on the master side is output by the output buffers 101 and 102 on the master 100 side in the first embodiment, whereas the pull-up resistor or active active side on the master 200 side in the second embodiment. To do with switches 208a, 208b, pull-up resistors or active loads 209a, 209b to determine load enable / disable;
The “Low” output on the master side is performed by the output buffers 101 and 102 on the master 100 side in the first embodiment, whereas the “Low” output transistors 201 and 202 on the master 200 side are performed in the second embodiment. about,
The “Low” output on the slave side is performed by the output buffers 111 and 112 on the slave 110 side in the first embodiment, whereas the “Low” output transistors 211 and 212 on the slave 210 side are performed in the second embodiment. That is.

  In FIG. 2, the switches 208a and 208b for determining whether the master 200 side pull-up resistor or active load is valid / invalid are removed, and one end of the pull-up resistor or active load 209a or 209b is connected to VCC_M. It doesn't matter.

(Third embodiment)
FIG. 3 is a block diagram showing a configuration example of the third embodiment of the present invention.
In FIG. 3, 300 indicates a master, and 310, 320, and 330 indicate slaves. Since the slave 310, the slave 320, and the slave 330 have the same circuit configuration, the illustration of the circuits of the slave 320 and the slave 330 is omitted. TRX0 and TRX1 are two (one pair) wires used for communication. 3 shows three slaves 310 to 330, but there may be three or more slaves.

  301, 302, 311 and 312 are 3-state (with Hi-Z function) output buffers; 303, 304, 313 and 314 are input circuits; 315 is a rectifier circuit (diode bridge); and 316 is a smoothing capacitor between the power supply and GND 307 is a master side control unit, and 317 is a slave side control unit. The master side control unit 307 and the slave side control unit 317 are provided for controlling transmission / reception performed between the master 300 and the slave 310.

309a and 309b are pull-up resistors or active loads. Reference numerals 308a and 308b denote switches (for example, P-type MOS transistors) that determine whether the pull-up resistor or active load is valid / invalid.
VCC_M is the power supply of the master 300, and GND_M is the GND of the master 300. VCC_S1 is the power supply of the slave 310, and GND_S1 is the GND of the slave 310.

The operation of the semiconductor integrated circuit of the third embodiment is almost the same as that of the first embodiment.
The only difference is that the outputs of the output buffers 301 and 302 are set to Hi-Z only when the slaves 310, 320, and 330 may respond (within the dotted line frame in FIG. 5). The switches 308a and 308b that determine the validity / invalidity of the active load are turned ON, and “High” is driven from the pull-up resistors or active loads 309a and 309b. Is made larger than the equivalent resistance value on the “High” side of the master side output buffers 301 and 302, the current consumption during the slave response can be reduced.

  In this case, power is not supplied from the master 300 to the slave 310 only in the “1” response interval, but the “1” response interval is short, and the power supply level is fixed by the smoothing capacitor 316 between the power supply / GND of the slave 310. Because it can be held for a long time, there is no problem.

  In FIG. 3, the switches 308a and 308b for determining the validity / invalidity of the pull-up resistor or active load on the master 300 side are removed, and one end of the pull-up resistor or active load 309a or 309b is connected to VCC_M. It doesn't matter.

TRX0, TRX1 Two wires (pair) used for communication 100 Master 110, 120, 130 Slave 101, 102, 111, 112 3-state (with Hi-Z function) output buffer 103, 104, 113, 114 Input circuit 105a, 105b Current detection circuit 115 Rectifier circuit (diode bridge)
116 Smoothing capacitor between power supply / GND 107 Master side control unit 117 Slave side control unit
VCC_M / GND_M Master power supply / GND
VCC_S1 / GND_S1 Slave power supply / GND

Claims (6)

A semiconductor integrated circuit that performs communication between at least one master and a plurality of slaves with two wires,
The master side
A set of master-side output buffers whose output ends are connected to the two wires;
A master side input circuit for inputting signals from the two wirings and a master side control unit for controlling the overall operation of the master;
The slave side
A set of slave-side output buffers whose output ends are connected to the two wires;
A set of slave side input circuits for inputting signals from the two wires;
A rectifier circuit that rectifies a potential difference between the two wirings and extracts operating power on the slave side, and a slave side control unit that controls the overall operation of the slave;
The master-side control unit sends data “0” and “1” by controlling the duration of “High” / “Low” or “Low” / “High” for the output of the output buffer. Run,
From the slave to the master, the slave-side control unit controls the output buffer so that “High” / “Low” in the slave response section does not respond or outputs “Low” in both wirings. A semiconductor integrated circuit characterized by realizing the data transmission. A semiconductor integrated circuit that performs communication between at least one master and a plurality of slaves with two wires,
The master side
A set of master-side output buffers whose output ends are connected to the two wires;
A set of master side input circuits for inputting signals from the two wirings;
Master power supply / GND,
It has a master side control unit that controls the overall operation of the master,
The slave side
A set of slave-side output buffers whose output ends are connected to the two wires;
A set of slave side input circuits for inputting signals from the two wires;
Slave power / GND
A rectifier circuit disposed between the slave power supply and GND;
A smoothing capacitor connected in parallel with the rectifier circuit;
It has a slave side controller that controls the overall operation of the slave,
Power supply from the master to the slave is performed by the master side control unit controlling the output of the output buffer to either "High" / "Low" or "Low" / "High"
Data transmission from the master to the slave is performed by the master side control unit controlling the length of the output buffer output to "High" / "Low" or "Low" / "High". Execute "," 1 "transmission
For data transmission from the slave to the master, the output buffer is controlled so that "High" / "Low" is output in the slave response interval, the slave-side control unit does not respond, or both wirings output "Low". A semiconductor integrated circuit characterized by being realized.   3. The semiconductor integrated circuit according to claim 2, wherein the output buffer is constituted by a three-state (with Hi-Z function) output buffer. The output buffer is composed of a "Low" output transistor,
3. The master side is provided with a pull-up resistor or active load connected to the two wirings and a drive transistor for determining validity / invalidity of the pull-up resistor or active load. A semiconductor integrated circuit according to 1.   4. The pull-up resistor or active load connected to the two wirings and a drive transistor for determining validity / invalidity of the pull-up resistor or active load are provided on the master side. A semiconductor integrated circuit according to 1. A semiconductor integrated circuit that performs communication between at least one master and a plurality of slaves with two wires,
The master side
A set of master-side output buffers whose output ends are connected to the two wires;
A current detection circuit that detects a current flowing through the one set of master side output buffers and a master side control unit that controls the overall operation of the master;
The slave side
A set of slave-side output buffers whose output ends are connected to the two wires and have a driving capability smaller than that of the one set of master-side output buffers;
A set of input circuits for inputting signals from the two wirings, a rectifying circuit for rectifying a potential difference between the two wirings to extract operating power on the slave side, and a slave side control unit for controlling the overall operation of the slave; Have
The master-side control unit transmits data "0" and "1" by controlling the length of the duration during which the output of the output buffer is fixed to "High" / "Low" or "Low" / "High" Run
From the slave to the master, the slave-side control unit controls the output buffer so that “High” / “Low” in the slave response section does not respond or outputs “Low” in both wirings. A semiconductor integrated circuit characterized by realizing the data transmission.

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