JP6190915B2 - Detector, PET apparatus and X-ray CT apparatus - Google Patents

Description

  The present invention relates to a detector, a PET apparatus using the same, and an X-ray CT apparatus.

  An X-ray CT (Computed Tomography) apparatus irradiates X-rays from the outside of a living body and detects X-rays transmitted through the living body with a detector. The CT apparatus includes a ring-shaped gantry (stand), a cradle (bed), and a computer for operation. An X-ray source and a plurality of detectors are arranged inside the gantry, and imaging is performed while these rotate in the gantry.

  On the other hand, a positron CT device (Positron Emission Tomography: PET device) introduces a drug labeled with an isotope that emits positrons (positrons) into a living body, and detects γ rays resulting from the drug with a plurality of detectors. The PET apparatus also includes a ring-shaped gantry (stand), a cradle (sleeper), and a computer for operation, and a plurality of detectors arranged around the living body are built in the gantry.

  An efficient detector of X-rays or γ-rays can be configured by combining a scintillator and a photodetector.

  Note that a CT / PET apparatus in which an X-ray CT apparatus and a PET apparatus are combined, and a combined diagnostic apparatus in which an MRI (magnetic resonance imaging diagnosis) apparatus is combined with them are also considered.

  The photodetector (photodiode array) applied to the diagnostic apparatus as described above is described in Patent Document 1 and Patent Document 2, for example.

  In a photodiode array such as SiPM (Silicon Photo Multiplier) or PPD (Pixelated Photon Detector), APDs (avalanche photodiodes) are arranged in a matrix, a plurality of APDs are connected in parallel, and the sum of APD outputs is read. Have. When the APD is operated in the Geiger mode, weak light can be detected.

  That is, when photons (photons) enter the APD, carriers generated inside the APD are output to the outside through a quenching resistor and a signal readout wiring pattern.

  A current flows through a pixel where an avalanche occurs in the APD, but a voltage drop occurs in a quenching resistance of about several hundred kΩ connected in series to the pixel.

  Due to this voltage drop, the voltage applied to the amplification region of the APD is lowered, and the multiplication action due to the electron avalanche is terminated. Thus, one pulse signal is output from the APD by the incidence of one photon. Several improvements have been made on the structure of the photodiode (see Non-Patent Document 1).

European Patent Application Publication No. 1755171 US Patent Application Publication No. 2006/175529

"Improvementof Multi-PixelPhoton Counter (MPPC)", T. Nagano, K. Yamamoto, K. Sato, N. Hosokawa, A. Ishida, T. Baba, IEEE Nuclear Science Symposium and Medical Imaging Conference, Conference Publications, p.1657-1659, 2011

  However, the conventional detector has a problem that characteristics such as time resolution in the whole detector are insufficient. The present invention has been made in view of such problems, and an object of the present invention is to provide a detector capable of improving the above characteristics, and a PET apparatus and an X-ray CT apparatus using the detector.

A detector according to the present invention is a detector including first and second bump electrodes disposed between a semiconductor chip and a wiring board, and the semiconductor chip includes a plurality of light beams arranged in a two-dimensional manner. A semiconductor substrate having a detection unit; and an insulating layer formed on a surface of the semiconductor substrate. Each of the light detection units includes a quenching resistor, and the quenching resistor is disposed on the insulating layer. The quenching resistor is electrically connected to a through electrode extending on the back surface of the semiconductor substrate through a through hole of the semiconductor substrate, and each of the photodetecting portions is a first conductivity type first electrode. A semiconductor region and a second semiconductor region of a second conductivity type that forms a pn junction with the first semiconductor region and outputs carriers, and operates in Geiger mode, and the second semiconductor region of the APD Electrically connected in series The quenching resistor, wherein the first bump electrode electrically connects the through electrode and the wiring board, and the second bump electrode is the first semiconductor region of the APD. And the wiring board are electrically connected, and the quenching resistor comprises SiCr.

  A bias voltage is applied to both ends of an APD (avalanche photodiode) included in each light detection unit via first and second bump electrodes. Carriers generated in a plurality of APDs due to the incidence of light (energy rays) are taken out to the outside through respective quenching resistors.

  Since the APD having this structure has a carrier transmission path shortening structure using a through electrode or the like, the wiring resistance is reduced.

  Therefore, the transmission speed of the carrier from the APD, that is, the time resolution is improved. When a plurality of photons are incident on a single semiconductor chip having a plurality of APDs, the time resolution is improved, so that more accurate photon detection can be performed.

  Further, a scintillator is located on the surface of the semiconductor chip via an insulator.

  The scintillator generates light having a wavelength longer than these in response to incidence of radiation such as X-rays or γ-rays incident thereon. When visible light or infrared light is incident on Si, photoelectric conversion occurs efficiently inside Si.

  When the APD is made of Si, the sensitivity of visible light and infrared light can be improved. The insulator is made of a glass plate or a resin and protects the surface of the APD, and the light from the scintillator can be slightly diffused before reaching the APD. The resin can also have an adhesion function between the scintillator and the semiconductor chip.

  In addition, the photodetecting portion includes a surface electrode that is electrically connected to the second semiconductor region and surrounds the second semiconductor region along an outer edge thereof.

  The PET apparatus includes a cradle and a gantry having an opening in which the cradle is located, and a plurality of any of the above-described detectors are arranged so as to surround the opening of the gantry. A subject is placed in the cradle. Since the detector is arranged so as to surround the opening of the gantry, the γ rays emitted from the subject can be detected by a plurality of detectors, and the subject is processed by image processing of the detection signal. It is possible to obtain an image related to the internal information. In this PET apparatus, since the overall characteristics of the detector are remarkably improved, it is possible to acquire a high-quality image.

  The X-ray CT apparatus includes a cradle and a gantry having an opening in which the cradle is positioned and having an X-ray source that emits X-rays in the opening, and the X-ray from the X-ray source is incident A plurality of the above-described detectors are arranged at a position to be operated. A subject is placed in a cradle located within the opening of the gantry, and the subject is irradiated with X-rays from an X-ray source. X-rays transmitted through the subject can be detected by a plurality of detectors, and an image relating to the internal information of the subject can be obtained by subjecting the detection signal to image processing. In this X-ray CT apparatus, since the overall characteristics of the detector are remarkably improved, it is possible to acquire a high-quality image.

  Characteristics of the entire detector of the present invention such as time resolution can be improved, and a PET apparatus and an X-ray CT apparatus using the detector can obtain a high-quality image, so that the apparatus characteristics can be improved. It becomes.

1 is a schematic view of a subject diagnostic apparatus such as a PET apparatus / CT apparatus. It is a block diagram of a PET apparatus. It is a block diagram of an X-ray CT apparatus. 2 is a perspective view of a detector D. FIG. 4 is a diagram for explaining an interval between detection chips S in a detector D. FIG. It is a perspective view of detector D '. It is a perspective view of detector D ''. 2 is a perspective view of a detection chip S. FIG. 2 is a perspective view of a detection chip S. FIG. It is a top view of semiconductor chip S1. It is an enlarged view of the common electrode peripheral part of semiconductor chip S1. It is a circuit diagram of a detector. It is a top view of the photon detection part of a common electrode peripheral part. It is sectional drawing of a common electrode peripheral part. It is a bottom view of semiconductor chip S1 of FIG. It is a bottom view of semiconductor chip S1 concerning improvement. It is the perspective view (A) of the basic component of a wiring board, and a bottom view (B). It is the top view (A) and bottom view (B) of a wiring board. It is the top view (A) and bottom view (B) of a wiring board. It is sectional drawing of a common electrode peripheral part. FIG. 21 is a bottom view of the semiconductor chip S1 of FIG. 20. It is a bottom view of semiconductor chip S1 concerning improvement. It is the perspective view (A) of the basic component of a wiring board, and a bottom view (B). It is the top view (A) and bottom view (B) of a wiring board. It is a bottom view of a wiring board. It is the top view (A) and bottom view (B) of a wiring board. It is a top view of semiconductor chip S1. FIG. 28 is a bottom view of the semiconductor chip S1 shown in FIG. 27. It is a bottom view of semiconductor chip S1 concerning improvement. It is a figure for demonstrating the manufacturing method of a detector. It is a figure for demonstrating the manufacturing method of a detector. It is a graph which shows the relationship between the number of photons which enter simultaneously, and signal intensity (au). Operating voltage graph showing the variation ΔV (V) and the relationship between the relative frequency (product number ratio) _{F R} of ((A) discrete arrays, (B) a monolithic array) is. It is a perspective view of a photodiode array. It is an AA arrow longitudinal cross-sectional view of a photodiode array. It is a graph which shows the relationship between the wavelength (nm) of the incident light to SiCr, and the transmittance | permeability (%). (A) Photodetector (50 μm spaced), (B) Photodetector (25 μm spaced), (C) Photodetector (20 μm spaced), (D) Photodetector (15 μm spaced: Type A) (E) The light detection part (15-micrometer space | interval arrangement | positioning: Type B), (F) It is a figure which shows the light detection part (10-micrometer space | interval arrangement). It is a graph which shows the relationship between the wavelength (nm) of incident light, and the detection efficiency (%) of a photon. It is a graph which shows the relationship between the output of a photodiode, and time. It is a figure for demonstrating the manufacturing method of a photodiode. It is the longitudinal cross-sectional view of the photodiode array which changed the structure of the board | substrate. It is a top view of a photodiode array. It is a top view of a photodiode array. It is sectional drawing of a photodiode array. It is a figure which shows the connection relationship, such as an electrode and wiring. It is a figure which shows the connection relationship, such as an electrode and wiring. It is a fragmentary top view of a photodiode array (1st example). It is AA arrow sectional drawing of a photodiode array (1st example). It is a fragmentary top view of a photodiode array (2nd example). It is AA arrow sectional drawing of a photodiode array (2nd example). It is a fragmentary top view of a photodiode array (3rd example). It is AA arrow sectional drawing of a photodiode array (3rd example). It is a figure which shows the connection relationship, such as an electrode and wiring. It is a fragmentary top view of a photodiode array (4th example). It is AA arrow sectional drawing of a photodiode array (4th example). It is a fragmentary top view of a photodiode array (5th example). It is AA arrow sectional drawing of a photodiode array (5th example). It is a fragmentary top view of a photodiode array (6th example). It is AA arrow sectional drawing of a photodiode array (6th example). It is a partial top view of a photodiode array (seventh example). It is AA arrow sectional drawing of a photodiode array (7th example). It is the longitudinal cross-sectional view of the photodiode array which changed the structure of the board | substrate. It is a top view of a photodiode array. It is a figure which shows the SEM photograph of the surface of a photodiode array. It is a figure which shows the SEM photograph of the cross section of a photodiode array. It is a top view of a part of photodiode array. FIG. 67 is a cross-sectional view of the photodiode array (second example) taken along the line AA in FIG. 66. It is a graph (Example) which shows the distance tp (ps) from the reference | standard of the distance from each photodiode to an electrode pad (common electrode), and signal transmission time. It is a graph (comparative example) which shows the distance tp (ps) from the reference | standard of the distance from each photodiode to an electrode pad (common electrode), and signal transmission time. It is a graph which shows the relationship between the voltage Vover and FWHM (ps). It is a graph which shows the relationship between time t (beta) (ps) and a count number. It is a figure explaining laser beam irradiation. It is a graph which shows the relationship between time t (alpha) (ns) and output OUT (au). It is sectional drawing of a common electrode peripheral part. It is sectional drawing of a common electrode peripheral part. It is a figure of the photograph which shows the perspective structure of a detector.

  Hereinafter, the detector, the PET apparatus, and the X-ray CT apparatus according to the embodiment will be described. In addition, the same code | symbol shall be used for the element which has the same element or the same function, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a schematic diagram of a subject diagnostic apparatus such as a PET apparatus / CT apparatus.

  The subject diagnosis apparatus includes a cradle 101, a gantry 102 having an opening in which the cradle 101 is located, and a control device 103. The control device 103 controls the drive motor 104 that moves the cradle 101 by a drive motor control signal, and changes the relative position of the cradle 101 with respect to the gantry 102. A subject 105 to be diagnosed is arranged on the cradle 101. The subject 105 is transported into the opening of the gantry 102 by the drive of the drive motor 104. The drive motor 104 may move the cradle 101, but may move the gantry 102.

  A plurality of detection devices 106 are arranged so as to surround the opening of the gantry 102. Each of the detection devices 106 includes a plurality of detectors D (see FIGS. 2 and 3). A control signal for controlling the detection device 106 is output from the control device 103 to the gantry 102, and a detection signal from the detector device 106 is input from the gantry 102 to the control device 103.

  FIG. 2 is a block diagram of a PET apparatus having the structure of FIG.

  In the PET apparatus, a plurality of detectors D are arranged in a ring shape so as to surround the gantry opening. The subject 105 is injected with a radioactive isotope (RI) (positron emitting nuclide) that emits positrons (positrons). Positrons combine with negative electrons in the body to generate annihilation radiation (γ rays). That is, γ rays are emitted from the subject 105. The detector D detects the emitted γ-rays, image-processes the detection signal by the image processing device 103g in the control device 3, and creates an image related to the internal information of the subject 105, that is, a tomographic image. The RI used in the PET apparatus is an element existing in the living body, such as carbon, oxygen, fluorine, and nitrogen.

  The γ rays emitted from the subject 105 can be detected by a plurality of detectors D. In this PET apparatus, since the overall characteristics of the detector D are remarkably improved, it is possible to acquire a high-quality image. The detector D will be described later.

  From the RI position P inside the subject 105, γ rays are emitted in one direction and in the opposite direction. The plurality of detectors D are arranged in a ring shape, and γ-rays are incident on a specific detector D (n) and a detector D (k) facing the RI position across the RI position. When N detectors D are arranged on one ring, the detector D (n) counted clockwise from the detector D at the highest position and the kth detector Γ rays are incident on the device D (k), but when the RI position P is at the center of the ring and the γ rays are directed in opposite directions in the plane of the ring, k = n + (2 / N). . Note that n, k, and N are natural numbers.

  When the PET device is of the TOF type (Time Of Flight), a radiation pair (γ-rays) generated by irradiating an electron / positron pair in a measurement object by administering a substance containing RI to a human body, an animal, a plant, or the like. Is used to obtain information on the distribution and movement of the administered substance in the measurement target. The TOF-PET apparatus includes a radiation detector array (detection apparatus 106) composed of a plurality of detectors D, a plurality of preamplifiers 103a and 103a ′, a plurality of sum amplifiers 103b and 103b ′, an energy discrimination circuit 103e, and a timing extraction. Circuits 103c and 103c ′ and a coincidence counting circuit 103f are provided.

  In addition, the subject 105 is disposed substantially at the center of the radiation detector array (detection device 106). A gamma ray pair is emitted from the subject 105. Gamma ray pairs are emitted in opposite directions. The plurality of detectors D are arranged on a circumference with the subject 105 as a substantial center. The detector D includes a scintillator that converts radiation (γ rays, X-rays) into fluorescence, and a photodetector that detects fluorescence.

  One detector D to which γ rays are incident is connected to a plurality of preamplifiers 103a (one is representatively shown in the drawing), and each of the preamplifiers 103a is connected to both the sum amplifier 103b and the sum amplifier 103b2. Has been. The preamplifier 103a amplifies the output signal from the photodetector D at high speed, and the sum amplifiers 103b and 103b2 each output a logical sum of the output signals of the preamplifier 103a.

  The other detector D to which the γ-rays enter is connected to a plurality of preamplifiers 103a ′ (one is representatively shown in the drawing), and each of the preamplifiers 103a ′ is a sum amplifier 103b ′ and a sum amplifier 103b2 ′. Connected to both. The preamplifier 103a 'amplifies the output signal from the photodetector D at high speed, and the sum amplifiers 103b' and 103b2 'each output a logical sum of the output signals of the preamplifier 103a'.

  These configurations are employed in all detectors D arranged in a ring shape, but for clarity of explanation, only one set is shown in the figure.

  The energy discriminating circuit 103e is connected to the sum amplifiers 103b2 and 103b2 '. The energy discriminating circuit 103e discriminates a signal equal to or higher than a predetermined threshold (hereinafter referred to as threshold SH) as a signal due to incidence of γ rays, and outputs the discrimination result to the coincidence counting circuit 103f. That is, the operation result of the logical sum operation by the sum amplifiers 103b2 and 103b2 ′ is output to the energy discriminating circuit 103e. It is determined whether the signal is a signal, and the determination result is output to the coincidence counting circuit 103f.

  The threshold value SH is set, for example, in the vicinity of 511 keV, which is the photon energy of a pair of γ-rays that are generated with the annihilation of an electron / positron pair. As a result, electrical noise signals, noise signals caused by scattered gamma rays (one or both of annihilation γ rays are γ rays whose directions have been changed by the scattering material, and energy is reduced due to scattering), etc. Is removed. The energy discriminating circuit 103e includes a circuit that integrates signals output from the preamplifiers 103a and 103a 'via the sum amplifiers 103b2 and 103b2', and shapes a waveform so that the amplitude is proportional to the energy.

  The timing extraction circuits 103c and 103c 'output a first timing signal and a second timing signal based on signals output from the sum amplifiers 103b and 103b', respectively. The first and second timing signals are input to the coincidence counting circuit 103f. As a timing extraction method, a leading edge method or a constant fraction method can be used.

  The coincidence counting circuit 103f is connected to the energy discriminating circuit 103e and the timing extracting circuits 103c and 103c '. The coincidence circuit 103f determines whether or not the γ-ray pair detected by the detectors D (n) and D (k) is a γ-ray pair generated with the annihilation of the same electron / positron pair. This determination is made based on whether or not γ rays have been detected by the other detector D (k) during a certain time before and after the detection time at which γ rays have been detected by one detector D (n). . If it is detected under this condition, it can be determined that the pair of γ-rays generated with the annihilation of the same electron / positron pair.

  Of the signals determined by the energy discriminating circuit 103e to have an energy level equal to or higher than the threshold value SH, the signals determined by the coincidence circuit 103f to be true due to the γ-ray pairs generated by the annihilation of electrons and positrons are true. Adopt as data.

  The true data is input to the image processing circuit 103g to create a tomographic image that is an image related to the internal information of the subject. The created image is stored in the storage device 103k and can be displayed on the display 103h. The storage device 103k stores a program for performing image processing and the like, and the program operates according to a command from a central processing unit (CPU) 103i. A series of operations necessary for inspection (output of control signal (ON / OFF of detector) to detector D, control of drive motor, capture of detection signal from detector D, image processing after simultaneous counting, created image Storage in the storage device and display on the display) can be performed by the input device 103j.

  FIG. 3 is a block diagram of an X-ray CT apparatus having the structure of FIG.

  The X-ray CT apparatus also includes the cradle and gantry having the above-described structure, but the gantry includes an X-ray source 103m that emits X-rays. A plurality of detectors D are arranged at positions where X-rays from the X-ray source 103m are incident, and a detection device 106 is configured.

  A subject 105 is placed on the cradle 101 located in the opening of the gantry 102 in FIG. 1, and the subject 105 is irradiated with X-rays from an X-ray source 103m. X-rays transmitted through the subject 105 are detected by a plurality of detectors D, and an image relating to internal information of the subject 105, that is, a computer tomographic image, can be obtained by performing image processing on the detection signals. When the PET apparatus and the X-ray CT apparatus are integrated, the control apparatus 103 can superimpose the image obtained by the PET apparatus and the image obtained by the X-ray CT apparatus. In the X-ray CT apparatus, since the detector D whose overall characteristics are remarkably improved is used, it is possible to acquire a high-quality image.

  The subject 105 is arranged at the center of the detection device 106 arranged in a ring shape. The detection device 106 rotates around the rotation axis AX. From the X-ray source 103m, the subject 105 is irradiated with X-rays, and the X-rays transmitted therethrough are incident on a plurality of detectors D (n). The output of each detector is input to the image processing circuit 103g via the preamplifier 103a and the sum amplifier 103b. The control device 103 of the X-ray CT apparatus includes a display 103h, a CPU 103i, a storage device 103k, and an input device 103j that function in the same manner as the PET apparatus. When the input device 103j instructs to start imaging, the program stored in the storage device 103k is activated, the X-ray source drive circuit 103n is controlled, and a drive signal is output from the drive circuit to the X-ray source 103m. The X-rays are emitted from the X-ray source 103m. Further, the program stored in the storage device 103k is activated, the gantry drive motor 103p is driven, the detection device 106 is rotated around the rotation axis AX, and a control signal (detector ON / OFF) is detected by the detector. Output to D, the detector D is turned ON, and the detection signal is input to the image processing circuit 103g via the preamplifier 103a and the sum amplifier 103b. The image processing circuit 103g creates a computer tomographic image in accordance with the tomographic image creation program input to the storage device 103k. The created image is stored in the storage device 103k and can be displayed on the display 103h.

  As described above, the storage device 103k stores a program for performing image processing and the like, and the program operates according to a command from the central processing unit (CPU) 103i. A series of operations necessary for inspection (output of control signals (ON / OFF of detector) to detector D, control of various drive motors, capture of detection signals from detector D, image processing of detection signals, created image Storage in the storage device and display on the display) can be performed by the input device 103j.

  As various programs, those installed in a conventional apparatus can be used.

  FIG. 4 is a perspective view of the detector D. FIG.

  The detector D includes a wiring board 20 and a plurality of detection chips S (semiconductor chips S1) arranged and fixed on the wiring board 20 so as to be two-dimensionally spaced from each other. A first bump electrode BE and a second bump electrode B2 (see FIG. 15) are interposed between each detection chip S (semiconductor chip S1) and the wiring board 20. In the figure, 4 × 4 detection chips S are arranged, but as long as there are a plurality of detection chips S, other numbers can naturally be employed. In the drawing, an XYZ three-dimensional orthogonal coordinate system is shown, but the opening center (subject 105) of the gantry is located on the extended line in the + Z direction. That is, γ-rays or X-rays travel in the negative direction of the Z-axis and enter the detection chip S, and the output signal is input to the wiring board 20 via the bump electrodes, and the output from the wiring board 20 is the aforementioned. Input to the preamplifier.

  FIG. 5 is a diagram for explaining the interval between the detection chips S in the detector D. FIG.

  The detection chips S are arranged at a distance d1 in both the X-axis direction and the Y direction. The detection chip S is provided with a scintillator on the semiconductor chip S1, but the scintillator is not shown in the figure. The semiconductor chip S1 has a semiconductor region 14 serving as a detection channel on the surface side. The semiconductor region 14 is a region on the surface side of a region that forms a pn junction with the semiconductor substrate in the semiconductor chip S1.

  Let d2 be the minimum value of the separation distance of the semiconductor regions 14 between the adjacent semiconductor chips S1.

  The distance d1 (distance between the side surfaces of the semiconductor chip S1) is set to 100 μm, the distance d2 is set to 200 to 300 μm, and the minimum distance d3 between the side surface of the semiconductor chip S1 and the semiconductor region 14 is set to 50 to 100 μm. Can be set. If the distance d1 = X1 μm, d2 = X1 + 2 × d3 = X1 + 100 to 200 μm is satisfied.

  One semiconductor chip S1 has a plurality of semiconductor detection regions 14 in a two-dimensional shape. However, when a group of semiconductor regions 14 is one detection channel and a single detection channel is provided, a detector is provided. D constitutes a discrete array. When one semiconductor chip S1 includes a plurality of detection channels, a monolithic array is configured. In the case of a discrete array, high-concentration impurities (the same conductivity type as that of the semiconductor substrate: N-type) are added to the side surfaces of the semiconductor chip to form an impurity-added region IS. In the case of a monolithic array, high-concentration impurities (the same conductivity type as that of the semiconductor substrate: N-type) are added between the side surface of the semiconductor chip and the detection channel to form an impurity-added region IS.

  Note that the separation distance between the detection channels in the case of the monolithic array (the minimum value of the distance between the semiconductor regions 14 in the adjacent detection channels) can be set equal to the distance d1. In this case, there is an advantage that the separation distances of all the semiconductor regions 14 are equal.

  FIG. 6 is a perspective view of the detector D '.

  A plurality of wiring boards 20 shown in FIG. 4 are arranged and fixed on the main wiring board or the support board 20 ′, and 8 × 8 detection chips S are arranged as a whole. By adopting such a configuration, an increase in the size of the detector can be achieved.

  FIG. 7 is a perspective view of the detector D ″.

  The wiring board 20 shown in FIG. 4 is shared, and 8 × 8 detection chips S are arranged and fixed on the wiring board 20 as a whole. By adopting such a configuration, an increase in the size of the detector can be achieved. FIG. 76 is a photograph showing a perspective configuration of a detector in which a plurality of detection chips are arranged, and a detector having a larger area could be prototyped.

  Next, the detection chip will be described.

  FIG. 8 is a perspective view of the detection chip S. FIG.

A scintillator S3 is provided on the semiconductor chip S1 via an adhesive layer S2. The adhesive layer S2 is a resin such as Epo-Tek301 (trademark) manufactured by Epoxy Technologies. The scintillator S3 _{are, Lu 2-x Y x SiO} 5: Ce (LYSO), gadolinium aluminum gallium garnet (GAGG), NaI (TI) , Pr: LuAG, LaBr 2, LaBr 3, and _{(Lu x Tb 1-x- y} Ce _y ) ₃ Al ₅ O ₁₂ (that is, LuTAG), at least one selected from the group consisting of two or a mixture of any two or more thereof. In LuTAG, the Lu composition ratio “x” is in the range of 0.5 to 1.5, and the Ce composition ratio “y” is in the range of 0.01 to 0.15. The radiation incident on the scintillator S3 is converted into fluorescence by the scintillator S3, and enters the semiconductor chip S1 via the adhesive layer S2.

  FIG. 9 is a perspective view of a detection chip S having another structure.

  A glass plate S22 is provided on the semiconductor chip S1 via an adhesive layer S21. A scintillator S3 is provided on the glass plate S22 via an adhesive layer S23. The materials for the adhesive layer and scintillator are as described above. The radiation incident on the scintillator S3 is converted into fluorescence by the scintillator S3, and enters the semiconductor chip S1 through the adhesive layer S23, the glass plate S22, and the adhesive layer S21.

  As described above, the scintillator S3 is located on the surface of each semiconductor chip S1 via the insulators (S2, S21, S22, S23). The scintillator S3 generates light having a longer wavelength than these in accordance with the incidence of radiation such as X-rays or γ-rays incident thereon. When visible light or infrared light is incident on Si, photoelectric conversion occurs efficiently inside Si. When the APD in the semiconductor chip S1 is made of Si, the sensitivity of visible light and infrared light can be improved. As described above, the insulator is made of a glass plate or a resin, and protects the surface of the APD, and the light from the scintillator can be slightly diffused before reaching the APD. The resin can also have an adhesion function between the scintillator and the semiconductor chip.

  FIG. 10 is a plan view of the semiconductor chip S1.

  A plurality of light detection units 10 are arranged on the surface of the semiconductor chip S1 along the X axis and the Y axis. In the central part of the semiconductor chip S1, a common electrode E3 for collecting signals from the respective light detection units 10 is arranged. In addition, although the light detection part 10 is formed on the whole surface of the semiconductor chip S1, the light detection part 10 is illustrated only in the vicinity of both ends for the sake of clarity of the common electrode.

  FIG. 11 is an enlarged view of the common electrode peripheral portion (region RS1 in FIG. 10) of the semiconductor chip S1.

  The light detection unit 10 includes an APD and a quenching resistor R1 (resistance layer) connected to one end (anode) of the APD. The quenching resistor R1 is connected to the common electrode E3 via the readout wiring TL. That is, all the APDs in the plurality of light detection units 10 are all connected to the common electrode E3 via the quenching resistor R1 and the readout wiring TL.

  FIG. 12 is a circuit diagram of the detector.

  The semiconductor chip S1 includes one or a plurality of photodiode arrays PDA. The photodiode array PDA includes a plurality of light detection units 10 (APD, quenching resistor R1). In the photodiode array PDA, each APD is operated in the Geiger mode. In the Geiger mode, a reverse voltage (reverse bias voltage) larger than the breakdown voltage of the APD is applied between the anode / cathode of the APD. That is, the (−) potential V1 is applied to the anode and the (+) potential V2 is applied to the cathode. The polarities of these potentials are relative, and one of the potentials can be a ground potential.

The wiring board 20 may be provided with a signal processing unit SP that processes a signal from the photodiode array PDA. The signal processing unit SP is ASIC (Application Specific Integrated).
Circuit). The signal processing unit SP can include a CMOS circuit that converts an output signal from the photodiode array PDA (channel) into a digital pulse.

  FIG. 13 is a plan view of the photodetecting portion around the common electrode.

  The APD has electrodes E1 arranged on the main surface side of the semiconductor substrate. The electrode E1 is electrically connected to the second semiconductor region 14. The first semiconductor region located immediately below the second semiconductor region 14 is electrically connected to the electrode E1 through the second semiconductor region 14.

  On the semiconductor substrate outside the second semiconductor region 14, a readout wiring (signal line) TL and a common electrode E3 are formed via an insulating layer. The common electrode E3 is located in the central region of each channel (photodiode array PDA).

  The read wiring TL includes a plurality of signal lines TL1 and a plurality of signal lines TL2. Each signal line TL1 extends in the Y-axis direction between adjacent APDs in plan view. Each readout wiring TL2 extends between adjacent APDs in the X-axis direction, and electrically connects the plurality of readout wirings TL1. The read wiring TL2 is connected to the common electrode E3. The read line TL1 is electrically connected to the common electrode E3 via the read line TL2, except for the line directly connected to the common electrode E3.

  The photodiode array PDA has a quenching resistor R1 formed through an insulating layer on a semiconductor substrate outside the second semiconductor region 14 for each APD. That is, the quenching resistor R1 is arranged on the main surface side of the semiconductor substrate. The quenching resistor R1 has one end connected to the electrode E1 and the other end connected to the readout wiring TL1.

  FIG. 14 is a sectional view of the periphery of the common electrode.

  The semiconductor region 12 constituting the semiconductor substrate includes a main surface 1Na and a main surface 1Nb facing each other. The semiconductor region 12 is an N-type (first conductivity type) semiconductor substrate made of Si.

  Each photodiode array PDA includes a plurality of APDs formed in the semiconductor region 12. The anode of the APD is a P-type semiconductor region 13 (14), and the cathode is an N-type semiconductor region 12. When a photon enters the APD, photoelectric conversion is performed inside the substrate to generate photoelectrons. Avalanche multiplication is performed in a region near the pn junction interface of the first semiconductor region 13, and the amplified electron group flows toward an electrode formed on the back surface of the semiconductor region 12. That is, when a photon is incident on any pixel (avalanche photodiode APD) of the photodiode array PDA, the photon is multiplied and extracted as a signal from the electrode E3 (through electrode TE).

  A quenching resistor R1 is connected to each APD in series. One APD constitutes one pixel in each photodiode array PDA. Each APD is connected in parallel with each other in series with the quenching resistor R1, and a reverse bias voltage is applied from the power source.

  Each APD has a P-type (second conductivity type) first semiconductor region 13 and a P-type (second conductivity type) second semiconductor region 14. The first semiconductor region 13 is formed on the main surface 1Na side of the semiconductor region 12. The second semiconductor region 14 is formed in the first semiconductor region 13 and has a higher impurity concentration than the first semiconductor region 14. The planar shape of the second semiconductor region 14 is, for example, a polygon (in this embodiment, a quadrangle). The first semiconductor region 13 is deeper than the second semiconductor region 14.

  The semiconductor region 12 has an N-type (first conductivity type) semiconductor region 1PC. The semiconductor region 1PC is formed on the main surface 1Na side of the semiconductor region 12. The semiconductor region 1PC prevents the PN junction formed between the N-type semiconductor region 12 and the P-type first semiconductor region 13 from being exposed to the through hole TH in which the through electrode TE is disposed. The semiconductor region 1PC is formed at a position corresponding to the through hole TH (through electrode TE).

  An insulating layer 16 is formed on the surface of the second semiconductor region 14, and a common electrode E3 and a readout wiring TL are formed thereon. The common electrode E3 and the readout wiring TL are covered with an insulating layer 17. The back surface 1Nb of the semiconductor region 12 is covered with an insulating layer L3. The insulation L3 has an opening, and the through electrode TE passes through the opening. The common electrode E3 is in contact with and electrically connected to the through electrode TE, and the first bump electrode BE is in contact with the through electrode TE through the under bump metal BM. The inner surface of the through hole TH provided in the semiconductor region 12 is covered with the insulating layer L2, and the insulating layer L2 is continuous with the insulating layer L3. The through electrode TE and the insulating layer L3 are covered with a passivation film (protective film) PF. An electroless plating method can be used as a method for forming the UBM. As a method for forming the bump electrode BE, a method of mounting a solder ball or a printing method can be used.

  As described above, each semiconductor chip includes a semiconductor region 12 having a plurality of photodetecting portions 10 arranged two-dimensionally, an insulating layer 16 formed on the surface of the semiconductor region 12, and the insulating layer 16 The common electrode E3 disposed in the first electrode, the quenching resistor R1 of each of the light detection units 10 and the common electrode E3, and the common electrode E3 through the through hole TH of the semiconductor region 12 from the common electrode E3. A through electrode TE extending on the back surface of the semiconductor region 12.

  Each photodiode array PDA includes a through electrode TE. The through electrode TE is provided for each individual photodiode array PDA, that is, for each individual channel. The through electrode TE is formed to penetrate the semiconductor region 12 from the main surface 1Na side to the main surface 1Nb side. That is, the through electrode TE is disposed in the through hole TH that penetrates the semiconductor region 12. The insulating layer L2 is also formed in the through hole TH. Therefore, the through electrode TE is disposed in the through hole TH via the insulating layer L2. The through electrode TE has one end connected to the common electrode E3, and connects the readout wiring TL and the through electrode TE.

  Each photodetection unit 10 includes an APD, and each APD forms a first conductivity type semiconductor region 12 (first semiconductor region) and a pn junction with the semiconductor region 12 and outputs carriers. A second semiconductor region (13, 14) of the second conductivity type is provided. A quenching resistor R1 is electrically connected to the second semiconductor region 14 of the APD.

  The first bump electrode BE electrically connects the through electrode TE and the wiring substrate 20, and the second bump electrode B2 (see FIG. 15 and the like) is connected to the semiconductor region 12 (first semiconductor region) of the APD and the wiring. The substrate 20 is electrically connected.

  The quenching resistor R1 has a higher resistivity than the electrode E1 and the common electrode E3 to which it is connected. Quenching resistor R1 is made of, for example, polysilicon. As a method for forming the quenching resistor R1, a CVD (Chemical Vapor Deposition) method can be used. In addition, SiCr, NiCr, TaNi, FeCr, etc. are mentioned as a resistor which comprises quenching resistance R1.

  The electrodes E1, E3 and the through electrode TE are made of a metal such as aluminum. When the semiconductor substrate is made of Si, AuGe / Ni or the like is often used as the electrode material in addition to aluminum. As a method for forming the electrodes E1, E3 and the through electrode TE, a sputtering method can be used.

  When Si is used, a Group 3 element such as B is used as the P-type impurity, and a Group 5 element such as N, P, or As is used as the N-type impurity. Even if N-type and P-type semiconductors are substituted for each other to form an element, the element can function. As a method for adding these impurities, a diffusion method or an ion implantation method can be used.

As a material of the above-described insulating layer, SiO ₂ or SiN can be used. As a method for forming the insulating layer, when each insulating layer is made of SiO ₂ , a thermal oxidation method or a sputtering method can be used. .

  In the case of the structure described above, an APD is formed by forming a pn junction between the N-type semiconductor region 12 and the P-type first semiconductor region 13. The semiconductor region 12 is directly connected to the back surface of the substrate 1N or electrically connected to an electrode (not shown) formed on the back surface. The first semiconductor region 13 is connected to the wiring substrate 20 through the second semiconductor region 14, the electrode E1, the quenching resistor R1, the readout wiring TL, the common electrode E3, the through electrode TE, and the bump electrode BE in this order. The back surface of the semiconductor region 12 is connected to the wiring substrate 20 via the bump electrode B2. The quenching resistor R1 is connected in series with the APD.

  FIG. 15 is a bottom view of the semiconductor chip S1 of FIG.

  A part of the passivation film PF on the back surface of the semiconductor substrate is removed, and the back surface of the semiconductor region 12 is exposed. The second bump electrode B2 is disposed in this exposed region. In the center of the semiconductor region 12, the first bump electrode BE is located. The second bump electrode B <b> 2 is disposed at a position corresponding to the four corners of the rectangular semiconductor region 12.

  FIG. 16 is a bottom view of the improved semiconductor chip S1.

  Compared with the structure shown in FIG. 15, this structure is such that a conductive film M is formed on the back surface of the semiconductor region 12 exposed by removing the passivation film PF, and a bump electrode B2 is disposed on the conductive film M. The other points are the same. The shape of the conductive film M is rectangular, and the material can be the same as the electrode material. Note that solder can be used as the material of the bump electrode.

  As described above, a bias voltage that operates in the Geiger mode is applied to both ends of the APD included in each light detection unit 10 via the first bump electrode BE and the second bump electrode B2. Carriers generated in the plurality of APDs due to the incidence of light (energy rays) flow to the common electrode E3 on the semiconductor region 12 through the respective quenching resistors R1, and from the common electrode E3 to the through electrode TE and the first electrode. It reaches the wiring board 20 through the bump electrode BE and is taken out to the outside.

  Since the APD having this structure has a carrier transmission path shortening structure using a through electrode or the like, the wiring resistance is reduced. Therefore, the transmission speed of the carrier from the APD, that is, the time resolution is improved. When a plurality of photons are incident on a single semiconductor chip having a plurality of APDs, the time resolution is improved, so that more accurate photon detection can be performed. In another semiconductor chip, it is not guaranteed that the same time resolution is obtained due to a manufacturing error or the like. However, when assembling, a semiconductor chip having a product characteristic within a certain range is selected and wiring is performed. Bonding to the substrate via the bump electrode reduces the characteristic variation for each semiconductor chip.

  Since the two-dimensionally arranged semiconductor chips S1 are separated from each other, the influence of light incident on a specific semiconductor chip leaking to other semiconductor chips and causing crosstalk is suppressed, and between the semiconductor chips. This gap can alleviate the influence of the warping of the wiring board due to the expansion / contraction of the wiring board 20 on the semiconductor chip. That is, characteristics such as time resolution, crosstalk, and resistance to temperature change as a whole detector are remarkably improved.

  FIG. 17 is a perspective view (A) and a bottom view (B) of the basic components of the wiring board.

  The wiring substrate 20 is provided on the surface of the insulating substrate 20C, and includes an electrode 20a that contacts the first bump electrode BE and an electrode 21a that contacts the four second bump electrodes B2. On the back surface of the insulating substrate 20C, an electrode pad 20d that is electrically connected to the electrode 20a is provided via a through electrode 20b that passes through the inside of the insulating substrate 20C. The through electrode 20b and the electrode pad 20d are connected via the connection electrode 20c.

  On the back surface of the insulating substrate 20C, an electrode pad 21d that is electrically connected to the electrode 21a is provided via a through electrode 21b that passes through the inside of the insulating substrate 20C. The through electrode 21b and the electrode pad 21d are connected via the connection electrode 21c.

  Note that the electrodes provided on the insulating substrate 20C are all printed wiring patterns.

  The shape of the first electrode 20a on the surface is a quadrangle, and the second electrode 21a is adjacent to and surrounds the three sides of the first electrode 20a.

  FIG. 18 is a plan view (A) and a bottom view (B) of the wiring board.

  This wiring board 20 is obtained by arranging a plurality of wiring patterns shown in FIG. 17 along the X axis and the Y axis. The left two rows of the second electrodes 21a are arranged so that the lower side is open, but the right two rows of the second electrodes 21a have an axis parallel to the thickness of the wiring board. It is rotated 180 ° in the center and is arranged so that the upper side is open.

  FIG. 19 is a plan view (A) and a bottom view (B) of the wiring board.

  The wiring board 20 has a plurality of wiring patterns shown in FIG. 17 arranged along the X axis and the Y axis, and at the same time, the second electrodes 21a adjacent to each other in the X axis direction are continuously arranged. This is the electrode 210a. The electrode 210a extends along the Y axis, and all the second electrodes 21a are electrically connected on the surface side. In this case, there is an advantage that the structure is simplified because the through electrode 210d may be provided directly below one of the electrodes 210a and exposed on the back surface.

  FIG. 20 is a cross-sectional view of the periphery of the common electrode.

  In the above description, the first bump electrode BE is disposed in the through hole provided in the semiconductor region 12, but may be provided at a position different from this. The through electrode TE is located on the insulating layer L3 on the back surface of the semiconductor substrate along the inner surface of the through hole. A contact hole is formed in the insulating layer L3 to expose the through electrode TE, and the first bump electrode BE can be provided on the exposed surface via the amber bump electrode metal BM. Note that the under bump metal BM can be provided so as to contact the through electrode TE in the removed region by removing the passivation film PF at the bottom of the through hole TH. Depending on the design, a bump electrode can also be arranged on the bottom under bump metal BM.

  FIG. 21 is a bottom view of the semiconductor chip S1 of FIG.

  A part of the passivation film PF on the back surface of the semiconductor region 12 is removed, and the back surface of the semiconductor region 12 is exposed. The second bump electrode B2 is disposed in this exposed region. Four first bump electrodes BE are located around the center of the semiconductor region 12. The second bump electrode B <b> 2 is disposed at a position corresponding to the four corners of the rectangular semiconductor region 12. The first bump electrode BE is provided so that the opening shape is adjacent to each side of the rectangular through hole. The shape of the through hole is a square pyramid.

  FIG. 22 is a bottom view of the semiconductor chip S1 according to the improvement.

  Compared with the structure shown in FIG. 21, this structure is such that a conductive film M is formed on the back surface of the semiconductor region 12 exposed by removing the passivation film PF, and a bump electrode B2 is disposed on the conductive film M. The other points are the same. The shape of the conductive film M is rectangular, and the material can be the same as the electrode material. Note that solder can be used as the material of the bump electrode.

  FIG. 23 is a perspective view (A) and a bottom view (B) of the basic components of the wiring board.

  The wiring substrate 20 is provided on the surface of the insulating substrate 20C, and includes an electrode 20a that contacts the four first bump electrodes BE, and an electrode 21a that contacts the four second bump electrodes B2. On the back surface of the insulating substrate 20C, an electrode pad 20d that is electrically connected to the electrode 20a is provided via a through electrode 20b that passes through the inside of the insulating substrate 20C. The through electrode 20b and the electrode pad 20d are connected via the connection electrode 20c.

  On the back surface of the insulating substrate 20C, an electrode pad 21d that is electrically connected to the electrode 21a is provided via a through electrode 21b that passes through the inside of the insulating substrate 20C. The through electrode 21b and the electrode pad 21d are connected via the connection electrode 21c.

  Note that the electrodes provided on the insulating substrate 20C are all printed wiring patterns.

  The shape of the first electrode 20a on the surface is a cross shape, and the second electrode 21a has a substantially U shape adjacent to the first electrode 20a and having one end open while surrounding the first electrode 20a.

  FIG. 24 is a plan view (A) and a bottom view (B) of the wiring board.

  The wiring board 20 is obtained by arranging a plurality of wiring patterns shown in FIG. 23 along the X axis and the Y axis. The left two rows of the second electrodes 21a are arranged so that the lower side is open, but the right two rows of the second electrodes 21a have an axis parallel to the thickness of the wiring board. It is rotated 180 ° in the center and is arranged so that the upper side is open.

  FIG. 25 is a bottom view of the wiring board.

  In the wiring board described above, the wiring SR1 that connects the electrode pads 20d and the wiring SR2 that connects the electrode pads 21d may be provided. Thereby, the output from each 1st bump electrode BE can be output outside via wiring SR1, and the output from 2nd bump electrode B2 can be output outside via wiring SR2.

  FIG. 26 is a plan view (A) and a bottom view (B) of the wiring board.

  The wiring board 20 has a plurality of wiring patterns shown in FIG. 23 arranged along the X axis and the Y axis, and at the same time, the second electrodes 21a adjacent to each other in the X axis direction are continuously arranged. This is the electrode 210a. The electrode 210a extends along the Y axis, and all the second electrodes 21a are electrically connected on the surface side. In this case, there is an advantage that the structure is simplified because the through electrode 210d may be provided directly below one of the electrodes 210a and exposed on the back surface.

  FIG. 27 is a plan view of the semiconductor chip S1.

  A plurality of light detection units 10 are arranged on the surface of the semiconductor chip S1 along the X axis and the Y axis. In the central part of the semiconductor chip S1, a plurality of common electrodes E3 from which signals from the respective light detection units 10 are collected are arranged. In addition, although the light detection part 10 is formed on the whole surface of the semiconductor chip S1, the light detection part 10 is illustrated only in the vicinity of both ends for the sake of clarity of the common electrode.

  In the figure, four common electrodes E3 are shown in the semiconductor chip S1. The cross-sectional structure of the peripheral region RS1 of each common electrode E3 is the same as that shown in FIG.

  FIG. 28 is a bottom view of the semiconductor chip S1 shown in FIG. In the same figure, as the cross-sectional structure, since the case shown in FIG. 20 is used, the number of first bump electrodes BE is four for each common electrode, but the one used in FIG. 14 is adopted. In this case, the number of first bump electrodes BE is one for each common electrode.

  A portion of the passivation film PF on the back surface of the semiconductor substrate is removed, and the back surface of the semiconductor region 12 (rectangular annular region, central region) is exposed. Second bump electrodes B2 are arranged at five locations in the exposed region. The second bump electrodes B2 are disposed at positions corresponding to the four corners and the center of the rectangular semiconductor region 12. Four first bump electrodes BE are located at locations corresponding to the four common electrodes in the semiconductor region 12.

  FIG. 29 is a bottom view of the improved semiconductor chip S1.

  The semiconductor chip S1 is different from that shown in FIG. 28 in that the second bump electrode B2 is provided only at one central position of the semiconductor chip S1, and the other configuration is that shown in FIG. Is the same.

  Next, with reference to FIGS. 30 and 31, a method for manufacturing the above-described detector will be described.

First, portions (first semiconductor region 13, second semiconductor region 14, insulating layer 16, quenching resistor R1, electrodes E1, E3, and signal line TL) corresponding to each channel (photodiode array PDA) were formed. A semiconductor region 12 is prepared. Next, the insulating layer 17 is formed on the main surface 1Na side of the semiconductor region 12, and then the semiconductor region 12 is thinned from the main surface 1Nb side (see FIG. 30A). Insulating layer 17 is made of SiO _2. As a method of forming the insulating layer 17, a CVD (Chemical Vapor Deposition) method can be used. As a thinning method of the semiconductor region 12, a mechanical polishing method or a chemical polishing method can be used.

Next, an insulating layer L3 is formed on the back surface 1Nb side of the prepared semiconductor region 12 (see FIG. 30B). Insulating layer L3 is made of SiO _2. As a method of forming the insulating layer L3, a CVD (Chemical Vapor Deposition) method can be used.

  Next, a region where the through hole TH is formed in the insulating layer L3 is removed (see FIG. 30C). As a method for removing the insulating layer L3, a dry etching method can be used.

  Next, a through hole TH for arranging the through electrode TE is formed in the semiconductor region 12 (see FIG. 30D). As a method for forming the through hole TH, a dry etching method and a wet etching method can be appropriately selected and applied. When an alkali etching method is used as the wet etching method, the insulating layer 16 functions as an etching stop layer. Since an undercut occurs in the insulating layer L3 when the through hole is formed by alkali etching, the insulating layer L3 is etched by a dry etching method. At this time, the insulating layer 16 is also etched at the same time.

Next, after forming the insulating layer L2 made of SiO ₂ on the main surface 1Nb side of the prepared semiconductor region 12, a part of the insulating layer L2 is removed to expose the electrode E3 (FIG. 30E). reference). As a method for removing the insulating layer L1 and the insulating layer L2, a dry etching method can be used.

  Next, the through electrode TE is formed (see FIG. 30F)). As described above, the through electrode TE can be formed by sputtering.

  Next, a passivation film PF having an opening formed at a position corresponding to the bump electrode BE is formed on the main surface 1Nb side of the semiconductor region 12, and then the bump electrode BE is formed (see FIG. 31G). Thereby, a semiconductor chip is obtained. Prior to the formation of the bump electrode BE, an under bump metal BM is formed in a region exposed from the passivation film PF in the through electrode TE. The BM is made of a material that is electrically and physically connected to the bump electrode BE. As a method for forming BM, an electroless plating method can be used. As a method for forming the bump electrode BE, a method of mounting a solder ball or a printing method can be used.

  Next, the glass substrate S22 is bonded to the semiconductor chip S1 via an optical adhesive (see FIG. 31H). Thereby, the glass substrate S22 and the semiconductor chip S1 are optically connected. Similarly to the semiconductor region 12, the glass substrate S22 is also prepared in the form of a glass substrate base material including a plurality of glass substrates. The step of bonding the glass substrate S22 and the semiconductor chip S1 may be performed after the insulating layer L3 is formed in the semiconductor region 12. In addition, when it is not necessary to use the glass substrate S22, it can be omitted.

  Next, the laminated body which consists of glass substrate S22 (glass substrate base material) and semiconductor chip S1 (semiconductor wafer) is cut | disconnected by dicing. Thereby, the side surface of the semiconductor region 12 and the side surface 30c of the glass substrate S22 are flush with each other.

  Next, the semiconductor photodetecting element 10 on which the glass substrate S22 is arranged opposite to the mounting substrate 20 prepared separately is connected to the bump electrode (see FIG. 31I). By these processes, the detection chip S is obtained. On the wiring board 20, a bump electrode BE is formed at a position corresponding to the electrode 20a on the main surface 20U side, and a signal extraction electrode is formed on the opposite surface 20D.

  When the photodiode array PDA is used as one channel and a plurality of channels are provided, a detection chip with a large area can be realized.

  A through electrode TE that is electrically connected to the signal line TL and penetrates from the main surface 1Na side to the main surface 1Nb side is formed in the semiconductor region 12 for each channel, and the through electrode TE and the electrode of the wiring substrate 20 are bumped. It is electrically connected via an electrode. As a result, the distance of the wiring for guiding the signal from each channel can be made extremely short, and the values can be made uniform without variation. Therefore, the influence of the resistance and capacitance of the wiring is remarkably suppressed, and the time resolution is improved.

  The detection chip S includes a glass substrate S22 disposed on the main surface 1Na side of the semiconductor region 12. Thereby, the mechanical strength of the semiconductor region 12 can be increased by the glass substrate S22. The side surface of the semiconductor region 12 and the side surface of the glass substrate S22 are flush with each other. Thereby, dead space can be reduced.

  The main surface 30b of the glass substrate S22 is flat. Thereby, the scintillator can be installed on the glass substrate S22 very easily.

  The through electrode TE is located in the central region of each channel. Thereby, in each channel, the wiring distance from each APD to the penetration electrode TE can be shortened.

  The semiconductor chip S1 is disposed on the main surface 1Na side of the semiconductor region 12, and includes a common electrode E3 that connects the signal line TL and the through electrode TE. Thereby, the signal line TL and the through electrode TE can be reliably electrically connected.

  The through electrode TE may be located in a region between each channel (photodiode array PDA). In this case, it is possible to prevent a decrease in the aperture ratio in each channel.

  As described above, the bump electrode BE may be disposed outside the through hole TH. In this case, a plurality of bump electrodes (four bump electrodes in this example) BE are formed for one through electrode TE. The bump electrode BE can be disposed on an electrode portion that is continuous with the through electrode TE and is disposed on the main surface 1Nb side of the semiconductor region 12.

  The shape of the semiconductor regions 13 and 14 is not limited to the shape described above, and may be another shape (for example, a circular shape). Further, the number (number of rows and number of columns) and arrangement of APDs (second semiconductor regions 14) are not limited to those described above. Further, the number and arrangement of channels (PDA) are not limited to those described above.

Figure 32 is a graph showing the relationship between the number of photons _{N P} and the signal intensity _{I S} (a.u.) incident simultaneously.

With an increase in the number of photons N _P, although the signal intensity I _S increases, in the case where the cell pitch is 10μm, these linearity is higher than that of the cell pitch 15 [mu] m. The cell pitch is the distance between the centers of the adjacent light detection units 10.

Figure 33 is a graph voltage variation ΔV (V) and shows the relationship between relative frequency _{F R} ((A) discrete arrays, (B) a monolithic array). The relative frequency F _R denotes the number of occurrences of the voltage variation ΔV in the array.

  A common bias potential is applied to the cathode of the APD of the semiconductor chip, and the applied voltage is common to all APDs. The operation of the light detection unit depends on ΔVover = Vop−Vbr obtained by subtracting the breakdown voltage Vbr of each channel from the operation voltage Vop. Therefore, if the breakdown voltage of each channel is not uniform, detection efficiency, darkness, noise, etc. Affects various characteristics. Therefore, the breakdown voltage of all APDs is preferably as uniform as possible. However, the uniformity of breakdown voltage is limited by the ability of the wafer material and process.

  In a discrete array in which 3 × 3 mm active channels (semiconductor chips) are used as one chip and elements with similar characteristics are selected and 16 × 16 elements are arranged on the substrate, the voltage variation is reduced to an average of 0.06 V (FIG. 33 (A)). In the case of a discrete array, detection chips whose characteristics deviate from the reference value can be removed, and those with uniform characteristics can be arranged on the same wiring board. Is more suppressed. In addition, in the discrete array using the through electrode, the dead space is small.

  On the other hand, the voltage gain variation is large in the monolithic array type in which 3 × 3 mm active channels 4 rows and 4 columns are arranged on the same semiconductor chip. At a constant applied voltage, the voltage variation of all 16 channels (semiconductor chips) averages 0.21 V (FIG. 33B).

  Next, an example in which only the structure of the light detection unit is modified will be described.

  FIG. 34 is a perspective view of the photodiode array, and FIG. 35 is a vertical cross-sectional view of the photodiode array along arrow AA.

  This photodiode array has a light receiving region on the surface side of a semiconductor substrate made of Si. The light receiving area includes a plurality of light detection units 10, and these light detection units 10 are two-dimensionally arranged in a matrix. In FIG. 34, the light detection units 10 in 3 rows and 3 columns are arranged, and these constitute a light receiving region, but the number of the light detection units 10 may be larger or smaller, A one-dimensionally arranged configuration is also possible.

  On the surface of the substrate, a signal reading wiring pattern (upper surface electrode) 3C (reading wiring TL) is arranged in a lattice pattern. In FIG. 34, the illustration of the insulating layer 17 shown in FIG. 35 is omitted so that the internal structure can be understood. A light detection region is defined in the opening of the grid-like wiring pattern 3C. The light detection unit 10 is disposed in the light detection region, and the output of the light detection unit 10 is connected to the wiring pattern 3C.

  A bottom electrode E4 is provided on the back surface of the substrate as necessary. However, it may not be used when the contact resistance between the bump electrode provided on the back surface and the semiconductor substrate is small. Therefore, if the drive voltage of the photodetection unit 10 is applied between the wiring pattern 3C that is the upper surface electrode and the lower surface electrode E4, the light detection output can be taken out from the wiring pattern 3C.

  In the pn junction, the p-type semiconductor region constituting this constitutes an anode, and the n-type semiconductor region constitutes a cathode. When a drive voltage is applied to the photodiode so that the potential of the p-type semiconductor region is higher than the potential of the n-type semiconductor region, this is a forward bias voltage, and the drive voltage opposite to this is applied to the photo-diode. When applied to the diode, this is a reverse bias voltage.

  The drive voltage is a reverse bias voltage applied to a photodiode configured by an internal pn junction in the light detection unit 10. When this drive voltage is set to be equal to or higher than the breakdown voltage of the photodiode, an avalanche breakdown occurs in the photodiode, and the photodiode operates in the Geiger mode. That is, each photodiode is an avalanche photodiode (APD). Even when a forward bias voltage is applied to the photodiode, the photodiode has a light detection function.

  A resistor portion (quenching resistor R1) 4 electrically connected to one end of the photodiode is disposed on the substrate surface. One end of the resistor section 4 constitutes a contact electrode 4A that is electrically connected to one end of the photodiode via a contact electrode made of another material located immediately below this, and the other end is used for signal readout. A contact electrode 4C is formed in contact with and electrically connected to the wiring pattern 3C. That is, the resistance part 4 in each photodetection part 10 is connected to the contact electrode 4A connected to the photodiode, the resistance layer 4B extending in a curve continuously to the contact electrode 4A, and the terminal part of the resistance layer 4B. A contact electrode 4C is provided. Note that the contact electrode 4A, the resistance layer 4B, and the contact electrode 4C are composed of resistance layers of the same resistance material, and these are continuous.

  In this way, the resistance portion 4 extends in a curved manner from the electrical connection point with the photodiode, and is connected to the signal reading wiring pattern 3C. Since the resistance value of the resistance unit 4 is proportional to its length, the resistance value can be increased by extending the resistance unit 4 in a curved line. In addition, the presence of the resistance portion 4 can stabilize the surface level of the semiconductor region existing thereunder and stabilize the output.

  In the example shown in FIG. 34, the wiring pattern 3C includes a shape surrounding the individual light detection units 10, but the shape of the wiring pattern 3C is not limited to this, and for example, two or more light detection units 10 or a shape surrounding one or more rows of the light detection units 10 (see FIG. 42). In FIG. 42, a plurality of rows of photodetecting portions are grouped into one group, and a wiring pattern 3C (reading wiring TL) extends therebetween.

  Further, as shown in FIG. 42, the surface level of the semiconductor region 14 can be further stabilized by disposing the resistance layer 4 </ b> B so as to cover the edge of the semiconductor region 14 in each photodetector. More specifically, the resistance layer 4B is disposed on the outline of the semiconductor region 14 as viewed from the thickness direction.

  In principle, one end of the photodiode included in the light detection unit 10 is connected to the wiring pattern 3C having the same potential at all positions, and the other end is connected to the lower surface electrode E4 that applies the substrate potential. That is, the photodiodes in all the light detection units 10 are connected in parallel.

  A common electrode E3 is provided on the surface of the semiconductor chip S1, and all the read wirings TL are connected to the common electrode E3. The cross-sectional structure around the common electrode E3 and the structure of the wiring board disposed under the bump electrode are the same as those described above.

  In the example shown in FIG. 34, each contact electrode 4A is located at the center of each photodetection region surrounded by the wiring pattern 3C. The two-dimensional pattern of the resistance portion 4B includes a shape extending so as to rotate around the contact electrode 4A. By placing the contact electrode 4A in the center of each light detection region and arranging the resistance layer 4B so as to rotate around the contact electrode 4A, the length of the resistance layer 4B can be set long.

  As shown in FIG. 35, each of the light detection units 10 includes a first conductivity type (n-type) first semiconductor region (layer) 12 and a second conductivity type that forms a pn junction with the first semiconductor region 12. A p-type second semiconductor region (semiconductor layer 13 and high impurity concentration region 14) is provided.

  The first contact electrode 3A is in contact with the high impurity concentration region (semiconductor region) 14 in the second semiconductor region. The high impurity concentration region 14 is a diffusion region (semiconductor region) formed by diffusing impurities into the semiconductor layer 13, and has a higher impurity concentration than the semiconductor layer 13. In this example (type 1), a p-type semiconductor layer 13 is formed on the n-type first semiconductor region 12, and a p-type high-concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. . Therefore, the pn junction constituting the photodiode is formed between the first semiconductor region 12 and the semiconductor layer 13.

  As the layer structure of the semiconductor substrate, a structure in which the conductivity type is reversed from the above can be adopted. That is, in the (type 2) structure, the n-type semiconductor layer 13 is formed on the p-type first semiconductor region 12, and the n-type high-concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. Formed.

  Also, the pn junction interface can be formed on the surface layer side. In this case, in the (type 3) structure, the n-type semiconductor layer 13 is formed on the n-type first semiconductor region 12, and the p-type high-concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. It becomes a structure to be. In the case of this structure, the pn junction is formed at the interface between the semiconductor layer 13 and the semiconductor region 14.

  Of course, even in such a structure, the conductivity type can be reversed. That is, in the (type 4) structure, the p-type semiconductor layer 13 is formed on the p-type first semiconductor region 12, and the n-type high concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. It becomes a structure.

  Note that the structure shown in FIG. 41 can also be employed as the structure of the semiconductor substrate.

  FIG. 41 is a longitudinal sectional view of a photodiode array in which the structure of the substrate is changed.

  This structure is different from the above-described type 1 to type 4 structure in that the semiconductor region 15 is disposed immediately below the semiconductor region 14, and the other points are the same. The semiconductor region 15 has the same conductivity type as the semiconductor region 14 or a different conductivity type. Those having the same conductivity type are referred to as (type 1S) to (type 4S), and those having different conductivity types are referred to as (type 1D) to (type 4D). The impurity concentration in the semiconductor region 15 is smaller than the impurity concentration in the semiconductor region 14. Further, B (boron) can be adopted as the p-type impurity, and P (phosphorus) or As (arsenic) can be adopted as the n-type impurity.

The preferred ranges of the conductivity type, impurity concentration, and thickness of each layer in the semiconductor structure described above are as follows.
(Type 1)
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(N-type / 5 × 10 ¹¹ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Semiconductor region 14 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 10 to 1000 nm)
(Type 2)
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(P-type / 5 × 10 ¹¹ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Semiconductor region 14 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 10 to 1000 nm)
(Type 3)
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(N-type / 5 × 10 ¹¹ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Semiconductor region 14 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 10 to 1000 nm)
(Type 4)
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(P-type / 5 × 10 ¹¹ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Semiconductor region 14 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 10 to 1000 nm)
(Type 1S)
The parameters of the semiconductor regions 12, 13, and 14 are the same as those of the type 1.
Semiconductor region 15 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
(Type 2S)
The parameters of the semiconductor regions 12, 13, and 14 are the same as those of the type 2.
Semiconductor region 15 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
(Type 3S)
The parameters of the semiconductor regions 12, 13, and 14 are the same as those of the type 3.
Semiconductor region 15 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
(Type 4S)
The parameters of the semiconductor regions 12, 13 and 14 are the same as type 4.
Semiconductor region 15 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
(Type 1D)
The parameters of the semiconductor regions 12, 13, and 14 are the same as those of the type 1.
Semiconductor region 15 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
(Type 2D)
The parameters of the semiconductor regions 12, 13, and 14 are the same as those of the type 2.
Semiconductor region 15 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
(Type 3D)
The parameters of the semiconductor regions 12, 13, and 14 are the same as those of the type 3.
Semiconductor region 15 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
(Type 4D)
The parameters of the semiconductor regions 12, 13 and 14 are the same as type 4.
Semiconductor region 15 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)

  In the above-described example, the lowermost semiconductor region 12 constitutes a semiconductor substrate having a large thickness. However, the light detection unit 10 may further include a semiconductor substrate below, in this case. The semiconductor region 12 has a thinner thickness than such an additional semiconductor substrate.

  The semiconductor region 13 can be formed on the semiconductor region 12 by an epitaxial growth method, but may be formed by impurity diffusion or ion implantation with respect to the substrate. The semiconductor regions 14 and 15 can be formed by impurity diffusion or ion implantation with respect to the semiconductor region 13.

  Next, the contact electrode 3A and the resistance portion 4 shown in FIGS. 34, 35, and 41 will be described.

  Each photodetecting section 10 includes an insulating layer 16 formed on the surface of the semiconductor substrate. The surfaces of the semiconductor region 13 and the semiconductor region 14 are covered with an insulating layer 16. The insulating layer 16 has a contact hole, and a contact electrode 3A is formed in the contact hole. The contact electrode 3A in this example is made of the same material as the wiring pattern 3C and is formed on the insulating layer 16 by the same process. The contact electrode 3A and the wiring pattern 3C are made of metal, specifically, aluminum (Al). Other low resistance metal materials (Au, Ag, Cu) can be used as the material of the contact electrode 3A and the wiring pattern 3C, and a structure or alloy of two or more layers can also be adopted. As the alloy, for example, a compound containing some of metal elements such as Al, Ag, Au, Ge, Ni, Cr and Ti can be used.

An upper insulating layer 17 is formed on the lower insulating layer 16 and the first contact electrode 3A. The insulating layers 16 and 17 are made of an inorganic insulator having high heat resistance such as SiO ₂ or silicon nitride (SiNx). The insulating layer 17 has a contact hole arranged coaxially with the first contact electrode 3A, and the second contact electrode 4A is formed in the contact hole. Therefore, the first contact electrode 3A and the second contact electrode 4A are arranged coaxially.

  The second contact electrode 4A includes a material different from that of the first contact electrode 3A. The second contact electrode 4A is a part of the resistance portion 4 and has a higher resistivity than the first contact electrode 3A. The second contact electrode 4A is disposed at a position overlapping the first contact electrode 3A, and is in contact with the first contact electrode 3A. In the second contact electrode 4A, the resistance layer 4B is continuous.

  By arranging the second contact electrode 4A coaxially at a position overlapping the first contact electrode 3A, the space required for connection between the resistance layer 4B and the first contact electrode 3A can be minimized. Of course, the first contact electrode 3A and the second contact electrode 4A are inevitably not on the same plane but have different height positions, and the resistance layer 4B extends continuously from the second contact electrode 4A. It becomes. Thereby, the wiring in the photodetection unit 10 can be omitted, and the aperture ratio of the photodetection unit can be remarkably increased.

  A contact electrode 4C is located at the end of the resistance layer 4B. The contact electrode 4 </ b> C is also a part of the resistance portion 4. A wiring pattern 3C formed on the insulating layer 16 is located immediately below the contact electrode 4C, and the contact electrode 4C is in contact with and connected to the wiring pattern 3C.

  Carriers generated in the pn junction by the incidence of photons flow to the resistance layer 4B through the first contact electrode 3A and the second contact electrode 4A, and the wiring pattern 3C connected to the resistance layer 4B through the contact electrode 4C. Through the outside.

  The contact electrodes 4A and 4C and the resistance layer 4B are made of the same resistance material, but they may be made of different materials. A semiconductor alone or an alloy or a compound containing a semiconductor and a metal in an appropriate ratio can be used as the resistance material. For example, as the resistor, there are NiCr, TaNi, FeCr and the like in addition to SiCr.

  Of course, the contact electrodes 4A and 4C and the resistance layer 4B are preferably made of SiCr. Since SiCr has a high light transmittance, even if a resistance layer is present in the light detection unit 10, an incident photon is transmitted through the resistance layer 4B, so that an effective aperture ratio can be increased. It should be noted that SiCr has a small variation in resistance value within the wafer surface and can be easily thinned if it is about 1 μm. Further, the sheet resistance can be increased. The sheet resistance of polysilicon is 1 to 30 (kΩ / sq.), While SiCr is 1 to 50 (kΩ / sq.). That is, if SiCr is used, a high resistance value can be realized with a small size.

  The thickness of the resistance layer 4B is preferably 3 nm or more and 50 nm or less. When the value is not less than the lower limit value, the uniformity of the resistance layer can be ensured.

  FIG. 36 is a graph showing the relationship between the wavelength (nm) of incident light on the SiCr constituting the resistance layer and the transmittance (%). The thickness of this SiCr layer is 20 nm.

  SiCr has a transmittance of 80% or more for light having a wavelength of 400 nm or more. Light having a wavelength of less than 400 nm tends to be blocked. According to the graph, a small spectral peak is shown for light having a wavelength of 400 nm or more and less than 500 nm. This means that even when light having a wavelength of 500 nm or more is blocked by a filter, light having a wavelength of 400 nm or more and less than 500 nm can be selectively transmitted. If such a filter is not combined, light having a wavelength of 400 nm or more and at least a wavelength of 1200 nm can be transmitted with a transmittance of 80% or more.

  The photodiode array described above was manufactured.

  The manufacturing conditions are as follows.

(1) Structure (Numerical example in the structure of FIGS. 34 and 35)
-Semiconductor region 12:
Conduction type: n-type (impurity: Sb (antimony))
Impurity concentration: 5.0 × 10 ¹¹ cm ⁻³
Thickness: 650 μm
・ Semiconductor region 13
Conduction type: p-type (impurity: B (boron))
Impurity concentration: 1.0 × 10 ¹⁴ cm ⁻³
Thickness: 30μm
-Semiconductor region 14
Conduction type: p-type (impurity: B (boron))
Impurity concentration: 1.0 × 10 ¹⁸ cm ⁻³
Thickness: 1000nm
Insulating layer 16:
SiO ₂ (thickness: 1000 nm)
Insulating layer 17:
SiO ₂ (thickness: 2000 nm)
Contact electrode 3A:
(Aluminum (Al))
Contact hole diameter: 2.0 μm
-Wiring pattern 3C: (Aluminum (Al))
Thickness: 1.0μm
Width W0 of wiring pattern 3C: 1.0 to 3.0 μm
Area S (photodetection region) surrounded by the wiring pattern 3C of one photodetection unit 10: 100 to 2500 μm ²
Spacing X between the centers of adjacent light detection units 10: 50 μm to 10 μm

・ Resistance part 4:
SiCr (Contact electrode 4A)
Contact hole diameter: 1.0 μm
(Resistance layer 4B)
Resistance layer 4B thickness: 20 nm
Resistance layer 4B width W1: 1.0 to 3.0 μm
Resistance layer 4B length L1: 10-50 μm
Resistance value of resistance unit 4: 200 to 500 kΩ
(Contact electrode 4C)
Contact hole diameter: 1.0 μm

(2) Manufacturing conditions / semiconductor region 12: CZ method ((001) Si semiconductor substrate)
Semiconductor region 13: Si epitaxial growth method (raw materials: gas phase silicon tetrachloride (SiCl ₄ ), silane trichloride (trichlorosilane, SiHCl ₃ ), growth temperature 1200 ° C.)
Semiconductor region 14: impurity thermal diffusion method (impurity raw material: diborane (B ₂ H ₆ ), diffusion temperature 1200 ° C.)
Insulating layer 16: (Si thermal oxidation method: oxidation temperature (1000 ° C.))
Insulating layer 17: (plasma CVD method: raw material gas (tetraethoxysilane (TEOS) and oxygen gas): growth temperature (200 ° C.))
Contact electrode 3A and wiring pattern 3C: evaporation method (raw material: aluminum)
Resistor 4: Sputtering method (target material: SiCr)

  FIG. 37 shows (A) light detectors (50 μm spaced), (B) light detectors (25 μm spaced), (C) light detectors (20 μm spaced), (D) light detectors (15 μm spaced). : Type A), (E) Photodetectors (15 μm spacing: Type B), (F) Light detectors (10 μm spaced).

The parameters of the structure in FIG. 37A are as follows. The length of the resistance layer 4B is the length of the center line in the width direction.
・ Width W0 of wiring pattern 3C = 2.0 μm
-Photodetection area S = 2025 μm ²
-Width of resistance layer 4B W1 = 3.0 μm
The length of the resistance layer 4B (total length) L1 = 200 μm
-Resistance value of resistance unit 4 = 160 kΩ

  The shape of the resistance layer 4B is formed in an annular shape along the inner surface of the grid-like wiring pattern 3C as a whole. In this structure, the resistance layer 4B has two paths from the position of the second contact electrode 4A to the contact electrode 4C for signal output. That is, the resistance layer 4B includes a resistance layer 4B1 having a relatively short length and a resistance layer 4B2 having a relatively long length. The resistance value of the resistance layer 4B is given by the combined resistance of the resistance layers 4B1 and 4B2 having different lengths.

  A contact electrode 4C is arranged at an intersection of the grid-like wiring pattern 3C. Therefore, the contact electrode 4C is located at four locations on the diagonal line of the light detection region, and the intersection of these diagonal lines becomes the center (center of gravity) G of the light detection region (light detection unit). The distance X between the centers G of the adjacent photodetectors 10 is 50 μm.

  The resistance layers 4B1 and 4B2 have a generally rectangular ring shape as a whole, but the shape at the corners is smoothly bent. The curvature centers O of the outer edges of the corners of the resistance layers 4B1 and 4B2 are located on the diagonal line passing through the center G, the curvature radius R is 5.0 μm, and both ends of the arc of the outer edge are directed toward the curvature center O. The angle θ formed by the two extending strings is 8 °. In order to avoid electric field concentration, the curvature radius R is set to 2 to 10 μm, and the angle θ is set to 3 to 14 °.

  The carriers taken out from the second contact electrode 4A reach the contact electrode 4C through the resistance layer 4B, and are taken out to the outside through the wiring pattern 3C.

  FIG. 37B is a diagram showing the manufactured light detection unit 10 (interval between adjacent centers X = 25 μm).

The parameters of the structure in this example are as follows.
・ Width W0 of wiring pattern 3C = 1.5 μm
-Photodetection area area S = 420 μm ²
-Width of resistance layer 4B W1 = 3.0 μm
-Length L1 of the resistance layer 4B = 70 μm
・ Resistance value of resistance section 4 = 250 kΩ

  The shape of the resistance layer 4B as a whole is formed in a shape in which a part of the ring is missing along the inner surface of the lattice-like wiring pattern 3C. In this structure, the resistance layer 4B has one path from the position of the second contact electrode 4A to the contact electrode 4C for signal output.

  A contact electrode 4C is arranged at an intersection of the grid-like wiring pattern 3C. Therefore, the contact electrode 4C is located at four locations on the diagonal line of the light detection region, and the intersection of these diagonal lines becomes the center (center of gravity) G of the light detection region (light detection unit). The distance X between the centers G of the light detection units 10 adjacent in the horizontal direction is 25 μm.

  The resistance layer 4B has three corners constituting a part of the ring shape, but the shape at each corner is smoothly bent. The center of curvature O of the outer edge of the corner of the resistance layer 4B is located on the diagonal line passing through the center G, the radius of curvature R is 5.0 μm, and extends from both ends of the arc of the outer edge toward the center of curvature O 2. The angle θ formed by the two strings is 8 °. In order to avoid electric field concentration, the curvature radius R is set to 2 to 10 μm, and the angle θ is set to 6 to 37 °.

  The carriers taken out from the second contact electrode 4A reach the contact electrode 4C through the resistance layer 4B, and are taken out to the outside through the wiring pattern 3C.

  FIG. 37C is a diagram showing the manufactured light detection unit 10 (interval between adjacent centers X = 20 μm).

The parameters of the structure in this example are as follows.
・ Width W0 of wiring pattern 3C = 1.5 μm
-Photodetection area area S = 240 μm ²
・ Width W1 of the resistance layer 4B = 2.0 μm
The length L1 of the resistance layer 4B = 55 μm
・ Resistance value of resistance part 4 = 300 kΩ

  The basic structure of the light detection unit is the same as that shown in FIG. The distance X between the centers G of the adjacent photodetectors 10 is 20 μm. The difference is that in the case shown in FIG. 37C, the contact electrode 4A detects the light with respect to the width W1 of the resistive layer 4B. The ratio of protruding toward the inside of the region is larger than that in FIG. In any form of the light detection unit, the centers of the contact electrodes 4A and 4C are recessed. The distance between the wiring pattern 3C adjacent to the contact electrode 4C and the center position of the contact electrode 4A is larger than the distance from the wiring pattern 3C to the inner edge line of the resistance layer 4B.

  The resistance layer 4B has three corners constituting a part of the ring shape, but the shape at each corner is smoothly bent. The center of curvature O of the outer edge of the corner of the resistance layer 4B is located on the diagonal line passing through the center G, the radius of curvature R is 3.0 μm, and extends from both ends of the arc of the outer edge toward the center of curvature O 2. The angle θ formed by the two strings is 13 °. In order to avoid electric field concentration, the radius of curvature R is set to 2 to 5 μm, and the angle θ is set to 8 to 23 °.

  The carriers taken out from the second contact electrode 4A reach the contact electrode 4C through the resistance layer 4B, and are taken out to the outside through the wiring pattern 3C.

  FIG. 37 (D) is a diagram showing the manufactured light detection section (interval between adjacent centers X = 15 μm: type A). In the type A photodetection section, the contact electrode 4A is arranged at the center of the photodetection region, and the resistance layer 4B is continuous to the positive direction rotation region 4Ba extending rightward from the center and the positive direction rotation region 4Ba. And a reverse rotation region 4Bb extending while rotating counterclockwise. Here, the clockwise rotation is defined as the forward rotation. Of course, it is also possible to manufacture a structure in which the leftward rotation is the forward rotation.

The parameters of the structure in this example are as follows.
・ Width W0 of wiring pattern 3C = 1.2 μm
-Photodetection area area S = 132 μm ²
-Width W1 of resistance layer 4B = 1.0 μm
The length L1 of the resistance layer 4B = 78 μm
・ Resistance value of resistance unit 4 = 600 kΩ

  Contact electrodes 4C are arranged at the intersections of the grid-like wiring pattern 3C, and the contact electrodes 4C are located at four positions on the diagonal lines of the light detection region. The intersections of these diagonal lines are the light detection regions (light It becomes the center (center of gravity) G of the detector. The distance X between the centers G of the adjacent photodetectors 10 is 15 μm.

  As described above, the resistance layer 4B includes the forward direction rotation region 4Ba and the reverse direction rotation region 4Bb. In this structure, the resistance layer 4B has one path from the position of the second contact electrode 4A to the signal output contact electrode 4C, but is formed by the regions 4Ba and 4Bb having different rotation directions. The direction of the magnetic field at the center G is reversed. That is, the influence of the magnetic field formed by the progress of the detected electrons has a structure that cancels out at the center position, and the influence of the self-formed magnetic field on the detection output is reduced.

  The forward rotation region 4Ba has three corners that bend gently, but the curvature centers Oa1, Oa2, and Oa3 of the outer edges of the corners are located on the diagonal line passing through the center G. Each curvature radius Ra is 2.0 μm, and an angle θa formed by two strings extending from both ends of each outer edge arc toward each curvature center Oa1, Oa2, Oa3 is 19 °. Regarding the positive direction rotation region 4Ba, the curvature radius Ra of the corner is set to 2 to 5 μm and the angle θa is set to 19 to 58 ° in order to avoid electric field concentration.

  The reverse rotation region 4Bb also has three corners that bend gently, and each corner has the same shape except for the direction. Explaining one angle, the curvature center Ob of the outer edge of the corner is located on the diagonal line passing through the center G, the curvature radius Rb is 2.0 μm, and the respective curvature centers from both ends of the arc of the outer edge. The angle θb formed by the two strings extending toward Ob is 8 °. Regarding the reverse rotation region 4Bb, the radius of curvature Rb of the corner is set to 2 to 5 μm and the angle θb is set to 8 to 23 ° in order to avoid electric field concentration.

  Note that the angle θa is set to be larger than the angle θb because the forward rotation region 4Ba is located inside the reverse rotation region 4Bb.

  The outer edge of the forward rotation region 4Ba located on the inner side and the inner edge of the reverse rotation region 4Bb located on the outer side face each other, but the minimum value D1 of these separation distances is 0.6 μm. The minimum value D1 of the separation distance is set to 0.6 to 2.0 μm.

  The carriers taken out from the second contact electrode 4A reach the contact electrode 4C through the resistance layer 4B, and are taken out to the outside through the wiring pattern 3C.

  FIG. 37E is a diagram showing the manufactured light detection unit (interval between adjacent centers X = 15 μm: type B).

  In the type B photodetection section, the contact electrode 4A is disposed at the center of the photodetection region, and the resistance layer 4B includes a rotation region that extends while rotating in one direction from the center. Of course, in any of the embodiments, it is also possible to manufacture a structure having a reverse rotation direction.

The parameters of the structure in this example are as follows.
・ Width W0 of wiring pattern 3C = 1.2 μm
-Photodetection area area S = 132 μm ²
-Width W1 of resistance layer 4B = 1.0 μm
The length L1 of the resistance layer 4B = 55 μm
-Resistance value of the resistance part 4 = 420 kΩ

  Contact electrodes 4C are arranged at the intersections of the grid-like wiring pattern 3C, and the contact electrodes 4C are located at four positions on the diagonal lines of the light detection region. The intersections of these diagonal lines are the light detection regions (light It becomes the center (center of gravity) G of the detector. The distance X between the centers G of the adjacent photodetectors 10 is 15 μm.

  The resistance layer 4B has three corners that are gently bent, and the center of curvature O of the outer edge of each corner is located on the diagonal line passing through the center G, and each radius of curvature is R is 2.0 μm, and the angle θ formed by the two chords extending from both ends of the arc of each outer edge toward the center of curvature O is 8 °. In order to avoid electric field concentration, the radius of curvature R of the corner is set to 2 to 5 μm, and the angle θ is set to 8 to 23 °.

  The carriers taken out from the second contact electrode 4A reach the contact electrode 4C through the resistance layer 4B, and are taken out to the outside through the wiring pattern 3C.

  FIG. 37 (F) is a diagram showing the manufactured photodetection section (interval between adjacent centers X = 10 μm). Since the basic structure of the light detection unit 10 is the same as that shown in FIG. 8, the description of the same structure is omitted.

The parameters of the structure in this example are as follows.
・ Width W0 of wiring pattern 3C = 1.2 μm
-Photodetection area area S = 42 μm ²
-Width W1 of resistance layer 4B = 1.0 μm
-Length L1 of the resistance layer 4B = 29 μm
・ Resistance value of resistance section 4 = 700 kΩ

  Also in this structure, the carrier taken out from the second contact electrode 4A reaches the contact electrode 4C through the resistance layer 4B, and is taken out to the outside through the wiring pattern 3C.

  In this example, the width W1 of the resistance layer 4B is smaller than the width W0 of the wiring pattern 3C, and a sufficient resistance value can be obtained although the resistance portion 4 is miniaturized. It has a configuration.

  Next, the characteristics of the photodiode will be described.

  FIG. 38 is a graph showing the relationship between the wavelength (nm) of incident light and the photon detection efficiency (%) in the photodiode described above. The graph shows data of the structure of FIG. 37A (50 μm interval), the structure of FIG. 37D (15 μm interval), and the structure of FIG. 37F (10 μm interval). Note that the number of light detection units included in one photodiode array is 400, 4489, and 1000, respectively. The reverse bias voltage to the photodiode was 74V and operated in Geiger mode. The breakdown voltage is 71V.

  As for the photon detection efficiency (PDE) (%), the larger the photodetection area, the smaller the shadow area due to the resistance layer, and the higher the detection efficiency. However, the area of the photodetection region when the adjacent interval of the photodetection region is 50 μm is about 1/25 of the area of the photodetection region when it is 10 μm, but the detection efficiency is 30% or more. Is maintained. Similarly, in the case of 15 μm, relatively high detection efficiency is maintained.

  The positions of these spectrum peaks exist in the wavelength range of 400 nm to 500 nm. Within this wavelength range (400 nm or more and 500 nm or less), the detection efficiency is 44% or more in the case of photodiodes at intervals of 50 μm, and the detection efficiency is 36% or more in the case of photodiodes at intervals of 15 μm. In the case of a diode, the detection efficiency is 17% or more.

  As Comparative Example 1, a first contact electrode is provided at an inner position of the resistance layer in FIG. 37A with an interval X between adjacent centers of X = 50 μm, and the first contact electrode has a shape substantially the same as that of the resistance layer 4B. A small annular wiring pattern (aluminum) was formed. The annular wiring pattern (extended electrode) is located on the outline of the semiconductor region 14 and has a function of stabilizing the level in the light detection region. When a resistor (polysilicon: 160 kΩ) that is continuous with the annular wiring pattern is formed in the same manner as that shown in FIG. 37A, the detection efficiency (%) has a wavelength of 400 nm to 500 nm. In the range, the minimum was 28% and the maximum was 36%. In the structure of Comparative Example 1, the position of the first contact electrode and the connection position of the annular wiring pattern of the resistor are shifted.

  Further, as Comparative Example 2, a first contact electrode is provided at an inner position of the resistance layer in FIG. 37E with an interval X = 15 μm in Comparative Example 1, and the first contact electrode is slightly the same shape as the resistance layer 4B. A small annular wiring pattern (aluminum) was formed. The annular wiring pattern (extended electrode) is located on the outline of the semiconductor region 14 and has a function of stabilizing the level in the light detection region. When a resistor (polysilicon: 500 kΩ) continuous with the annular wiring pattern is formed in the same manner as that shown in FIG. 37E, the detection efficiency (%) has a wavelength of 400 nm to 500 nm. In the range, the minimum was 18% and the maximum was 26%. In the structure of Comparative Example 2, the position of the first contact electrode is shifted from the connection position of the annular wiring pattern of the resistor.

  Since the position of the first contact electrode and the connection position of the annular wiring pattern of the resistor are shifted, it is difficult in the manufacturing process to set the interval X = 10 μm or less.

  In the structures of Comparative Examples 1 and 2, all of the annular wiring pattern and the resistance portion having a low light transmittance function as a light shielding element for reducing the effective aperture ratio, and the light detection sensitivity is lowered. On the other hand, in the photodiode array according to the embodiment, the resistance layer 4B has a high light transmittance while achieving the same surface level stabilization function as that of the annular wiring pattern, and is added like polysilicon. Since a typical resistor is not used, the light detection sensitivity can be remarkably improved.

  Next, the influence of the recovery time (voltage recovery time) was examined.

  FIG. 39 is a graph showing the relationship between the output (Geiger mode) from the photodiode and time. The output video of the oscilloscope is shown, the vertical axis indicates the output intensity of the photodiode, one interval on the vertical axis indicates 50 mV, and one interval on the horizontal axis indicates 5 (ns). . In the graph, a plurality of data having different peak intensity voltages are shown. This is due to the difference in the number of photons incident on the photodiode, and the output intensity increases as the number of photons increases. In the graph, a bias voltage of 73 (V) is applied. Note that Vover = the bias voltage to the photodiode−the breakdown voltage of the photodiode is in the range of Vover = 1 (V) to 4 (V).

  The recovery time (τ) of the output signal of the photodiode is 37% of the intensity peak value from the time when the intensity peak value of the output from the light detection unit 10 is given when the photon is incident on the light detection unit 10. It is defined by the period until the time when the output from the unit 10 becomes.

  In the case where the interval X between the light detection portions is 50 μm (FIG. 37A) (FIG. 39A), when the bias voltage to the photodiode is 73V, the recovery time (τ) is 13 ns.

  In the case where the interval X between the light detection portions is 20 μm (FIG. 37C) (FIG. 39B), when the bias voltage to the photodiode is 73 V, the recovery time (τ) is 5.0 ns.

  In the case of the interval X of the light detection section X = 15 μm (type A: FIG. 39D) (FIG. 39C), the recovery time (τ) is 4.3 ns when the bias voltage to the photodiode is 73V. is there.

  In the case where the interval X between the light detection portions is 10 μm (FIG. 37 (F)) (FIG. 39 (D)), the recovery time (τ) is 2.3 ns or less when the bias voltage to the photodiode is 73V. Can do.

  In the case of Comparative Example 1 described above, the recovery time (τ) was 13 ns, and in the case of Comparative Example 2, the recovery time (τ) was 4.3 ns.

Specifically, in the case of the structure of Comparative Example 1 (the separation interval X of the light detection unit 10 = 50 μm), the aperture ratio is 60%, the junction capacitance Cj = 80 fF, the gain = 7.5 × 10 ⁵ , and the recovery time 13 ns. Pixel number density (400 / mm ² ) and photon detection efficiency is 36% at the maximum.

Further, in the case of the structure of Comparative Example 2 (the separation interval X of the light detection unit 10 = 15 μm), the aperture ratio is 35%, the junction capacitance Cj = 11 fF, the gain = 2.0 × 10 ⁵ , and the recovery time 4.3 ns. The pixel number density (4489 / mm ² ) and the maximum photon detection efficiency are 26%.

When X = 15 μm, in the structure of the embodiment of FIGS. 7 and 8, the aperture ratio can be 60%, the junction capacitance Cj = 11 fF, the gain = 2.0 × 10 ⁵ , the recovery time 4 .3 ns, pixel number density (4489 / mm ² ).

  Thus, in the structure of the embodiment, it is possible to reduce the junction capacitance Cj and shorten the recovery time while achieving the same aperture ratio as that of the comparative example 1. In addition, since the number of pixels included per unit area is large, the dynamic range can be improved.

  As described above, when the interval X between adjacent second contact electrodes (interval between the centers of the light detection regions) X is 20 μm or less, the recovery time (τ) is remarkably shortened. The recovery time (τ) can be set to 10 ns or less if the interval X between the light detection parts is 15 μm or less. If the interval X is 10 μm or less, the recovery time (τ) is further shortened. This is a significant improvement that could not be achieved previously.

Note that the size (pixel size) of the light detection unit 10 affects the pulse recovery time. The smaller the pixel size, the wider the dynamic range. In a 1 mm × 1 mm square chip, the number of cells is 400 when the pixel size is 50 μm, 2500 when the pixel size is 20 μm, 4489 when 15 μm, and 10,000 when 10 μm. The pixel size can be selected according to the desired resolution and dynamic range. When the pixel size is 50 μm, 20 μm, 15 μm, and 10 μm, the gain at the operating voltage is 7.5 × 10 ⁵ , 2.4 × 10 ⁵ , 2.0 × 10 ⁵ , and 1.0 × 10 ⁵ . The light detection efficiency (PDE) at a wavelength of 420 nm can be 51%, 43%, 38%, and 19%.

In application to an X-ray CT apparatus, from the viewpoint of position resolution (resolution), the semiconductor chip size or active channel (a collection region of a plurality of light detection units electrically separated from adjacent elements) is used. The size is preferably about 1 × 1 mm. If energy degrade X-ray of 10~140keV / mm ^2, a wide dynamic range is required. A pixel number of about 4500 to 10000 is preferable, and a pitch of 10 to 15 mm is preferable.

  In addition, in application to a PET apparatus, a pixel size of about 3 × 3 mm is suitable for detecting the center of gravity, and about 3600 pixels are sufficient for receiving light emitted from the scintillator. In order to reduce the reading of the ASIC, a large area chip of about 6 × 6 mm can be adopted. Pixel pitch with high temporal resolution and high detection efficiency. A large one of 50 μm or more is suitable.

  In the above structure, when the through electrode is used, the width of the dead space along the outer edge of the semiconductor chip becomes uniform. Further, the gap between the channels when the semiconductor chips are two-dimensionally arranged can be made uniform, and the alignment when fixing the scintillator on the light receiving surface is facilitated.

  As described above, in the photodiode array according to the embodiment, using the high transmittance of the metal thin film resistor, instead of the overhanging electrode used in Comparative Examples 1 and 2, by the metal thin film resistor patterned in a linear shape, An overhang structure is formed to reduce dead space. In order to obtain a desired resistance value, in the case of the structure shown in FIGS. 37B to 37F, a part of the outline (edge) of the semiconductor region 14 (the position of the right corner) is covered with the resistance layer 4B. However, this portion is about the width of the resistance layer 4B, and the influence of the characteristic deterioration on the surface state stabilization is small. In the structure shown in FIG. 37A, the entire outline (edge) of the semiconductor region 14 is covered.

  FIG. 40 is a diagram for explaining a manufacturing method of the photodiode array shown in FIGS. 34 and 35.

First, as shown in FIG. 40A, a semiconductor region 13 is formed on a semiconductor region (semiconductor substrate) 12 by an epitaxial growth method, an impurity diffusion method, or an ion implantation method. The semiconductor region 12 is a (100) Si semiconductor substrate formed by the CZ method or the FZ method, but a semiconductor substrate having another plane orientation can also be used. When the Si epitaxial growth method is used, for example, gaseous silicon tetrachloride (SiCl ₄ ) and trichlorosilane (trichlorosilane, SiHCl ₃ ) are used as raw materials, and these are formed on the substrate surface at a growth temperature of 1200 ° C. Flow gas. In the case of the impurity diffusion method, an impurity corresponding to the conductivity type of the semiconductor region 13 is diffused into the semiconductor region 12 with gas or solid. In the case of the ion implantation method, an impurity corresponding to the conductivity type of the semiconductor region 13 is ion implanted into the semiconductor region 12.

Next, the semiconductor region 14 is formed in the region on the surface side of the semiconductor region 13. For this, an impurity diffusion method or an ion implantation method can be used. For example, in the diffusion method, when diborane (B ₂ H ₆ ) is used as the impurity raw material, the diffusion temperature can be set to 1200 ° C. In forming the semiconductor region 14, first, a resist pattern having an opening is formed on the semiconductor region 13 by a photolithography technique, and then an impurity is added using the resist pattern as a mask. The impurity may be added by ion implantation after forming the grid-like wiring pattern 3C and using this as a mask through the insulating layer 16.

Next, the insulating layer 16 is formed on the semiconductor substrate. The insulating layer 16 can be formed using a Si thermal oxidation method. The oxidation temperature is 1000 ° C., for example. Thereby, the surfaces of the semiconductor regions 13 and 14 are oxidized, and the insulating layer 16 made of SiO ₂ is formed. The insulating layer 16 can be formed by a CVD method.

  Next, a contact hole is formed at a position on the semiconductor region 14 in the insulating layer 16. In forming the contact hole, first, a resist pattern having an opening is formed on the insulating layer 16 by photolithography, and then the insulating layer 16 is etched using the resist pattern as a mask. As the etching method, in addition to the dry etching method, wet etching with an etching solution containing an HF aqueous solution can be used.

  Next, the first contact electrode 3A and the wiring pattern 3C are formed on the insulating layer 16 by vapor deposition. In these formations, first, a predetermined resist pattern is formed on the insulating layer 16 by photolithography, and then an electrode material is deposited on the insulating layer 16 using the resist pattern as a mask. Here, a sputtering method can be used instead of the vapor deposition method.

  On the insulating layer 16, the common electrode E3 is also formed at the same time as the wiring pattern 3C by the same method.

  Next, as illustrated in FIG. 40B, the insulating layer 17 is formed over the insulating layer 16. The insulating layer 17 can be formed using a sputtering method or a plasma CVD method. When using the plasma CVD method, tetraethoxysilane (TEOS) and oxygen gas are used as raw material gases, and the growth temperature is set to about 200 ° C. to grow the insulating layer 17. The thickness of the insulating layer 17 is preferably set to such a thickness that the surface is flattened, and is preferably larger than the height from the surface of the insulating layer 16 to the upper surface of the wiring pattern 3C.

  Next, as illustrated in FIG. 40C, the resistance portion 4 is formed over the insulating layer 17. In this formation, first, a predetermined resist pattern is formed on the insulating layer 17 by a photolithography technique, and then, using this resist pattern as a mask, a resistance material is used on the insulating layer 17 by sputtering or vapor deposition. And accumulate. When the resistor is made of SiCr, a sputtering method is used. As a target material, for example, SiCr having a composition ratio of Si and Cr of 70% / 30% can be used, and the thickness is set to 3 to 50 nm. Can do.

  After the above steps are completed, a through hole is formed from the back surface of the semiconductor substrate in the same step as FIGS. 30 and 31, and the surface of the through hole is covered with an insulating layer, and then connected to the common electrode E3. A through electrode is formed, and a bump electrode is brought into contact with the through electrode. Finally, similarly to the above-described steps, first and second bump electrodes are formed on the back surface of the semiconductor substrate, and are bonded to the wiring substrate via the bump electrodes.

  In the case of manufacturing the photodetection portion having the structure shown in FIG. 41, the semiconductor region 15 may be formed on the surface side of the semiconductor region 13 by using an impurity diffusion method or an ion implantation method before the formation of the semiconductor region 14. That's fine. In the case of the impurity diffusion method, impurities corresponding to the conductivity type of the semiconductor region 15 are diffused into the semiconductor region 13 with gas or solid. In the case of the ion implantation method, an impurity corresponding to the conductivity type of the semiconductor region 15 is ion implanted into the semiconductor region 13.

  In the plurality of semiconductor chips after FIG. 34 as well, the glass plate or resin adhesive layer is provided on the semiconductor chip and the scintillator is disposed on the semiconductor chip, as in the structure before FIG. A chip is formed.

  34 to 42, the first contact electrode 3A in contact with the second semiconductor region 14 and a material different from the first contact electrode 3A are provided at a position overlapping the first contact electrode 3A. And a second contact electrode 4A that is in contact with the first contact electrode 3A, and the quenching resistance R1 (resistance portion 4 (resistance layer 4B)) is continuous with the second contact electrode 4A. Carriers generated at the pn junction by the incidence of photons flow to the quenching resistor R1 via the first contact electrode 3A and the second contact electrode 4A, and are connected to the readout wiring TL, the common electrode E3, and the through-holes connected to the quenching resistor. The wiring board 20 is reached via the electrode TE and the first bump electrode BE (FIGS. 14 and 20).

  By disposing the second contact electrode 4A at a position overlapping the first contact electrode 3A, the space required for connection between the quenching resistor and the first contact electrode 3A can be minimized. Of course, the first contact electrode 3A and the second contact electrode 4A are not necessarily on the same plane, but have different height positions, and the quenching resistance continuously extends from the second contact electrode 4A. It becomes. Thereby, the wiring in the photodetection unit 10 can be omitted, and the aperture ratio of the photodetection unit can be remarkably increased.

  In addition, the second contact electrode 4A and the quenching resistor include SiCr, and since SiCr has a high light transmittance, even if a quenching resistor is present in the light detection unit 10, incident photons are not generated. Since it penetrates the quenching layer, the effective aperture ratio can be increased.

  In the case of the above-described embodiment, the planar shape of the resistance layer 4B is an annular shape, a partial ring shape, or a spiral shape, but this is a meandering shape such as a square wave, a triangular wave, or a sine wave. May be.

  Further, effects of the photodiode array according to the embodiment will be further described.

  When the photodiode array is operated in the Geiger mode, the recovery time (voltage recovery time) τ when a photon enters one photodetection unit 10 is a depletion that extends from the area of the photodetection region and the pn junction in the photodetection unit 10. It depends on the product (RC constant = Cj × Rq) of the junction capacitance (pixel capacitance) Cj defined by the layer width and the resistance value (quenching resistance value Rq) of the resistor section 4.

  When the pixel size (area of the light detection unit) is reduced, the junction capacitance Cj is reduced. Therefore, in order to obtain the same recovery time τ, that is, the same RC constant, it is necessary to increase the quenching resistance value Rq. . The quenching resistance value Rq can be determined by adjusting the resistivity, thickness, width and length. Since the resistivity, width, and thickness are limited by process conditions, it is reasonable to adjust the resistance value Rq by changing the length. In order to obtain the same recovery time τ, the resistance layer 4B is set shorter as the pixel size is larger, and the resistance layer 4B is set longer as the pixel size is smaller.

  When the RC constant is too small, quenching after avalanche multiplication occurs is insufficient, a phenomenon called latching current occurs, and normal operation is not exhibited. On the other hand, when the RC constant is too large, the recovery time (voltage recovery time) becomes long. Therefore, the RC constant value is set to an optimum value (2 to 20 ns) according to the device.

  The gain depends on the junction capacitance Cj and the applied voltage, and the structure of the embodiment reduces the gain by reducing the junction capacitance Cj. In addition to the dark pulse, the noise component of the photodiode array includes an after pulse and a pseudo output signal due to optical crosstalk. An after pulse is a pulse in which a part of electrons and holes generated by avalanche multiplication is trapped in an impurity level, etc., and is emitted later after a certain time interval, resulting in avalanche multiplication again. is there. Optical crosstalk is due to a pulse generated by avalanche multiplication caused by a pair of electrons and holes generated when a photon generated at low probability during avalanche multiplication enters and is absorbed by an adjacent pixel. Both are noise components that cause the output for one photon to be multiple pulses instead of one pulse.

  As in the structure of the embodiment, since the total number of electron-hole pairs generated by avalanche multiplication is reduced when the junction capacitance Cj, that is, the gain is small, the probability of occurrence of pulses due to after pulses and optical crosstalk is reduced. The effect of noise reduction can be obtained.

  The larger the junction capacitance Cj and the larger the gain, the longer the time to sweep out the generated carriers. Therefore, the voltage recovery time is longer and the smaller the gain, the shorter the recovery time. When the pixel pitch is reduced as in the embodiment, the voltage recovery time is shortened, and the photon count rate can be improved.

  Next, an example in which the read wiring has a two-layer structure will be described.

  FIG. 43 is a plan view of the photodiode array.

  The photodiode array includes a semiconductor substrate 100 having a plurality of light detection units 10. The photodiode array includes a light receiving region in which the light detection unit 10 is two-dimensionally arranged, and a common electrode E3 provided in a region surrounded by the light detection unit 10 of the semiconductor substrate 100. A signal from each photodiode APD is read out through the common electrode E3. The photodiode of this embodiment is an avalanche photodiode (APD) that operates in Geiger mode. In the figure, the light detection units 10 are arranged in a matrix along the X-axis direction and the Y-axis direction. The thickness direction of the semiconductor substrate 100 is the Z-axis direction, and the XYZ axes constitute an orthogonal coordinate system. In FIG. 43, the light detection units 10 in 3 rows and 3 columns are arranged, and these constitute the light receiving region, but the number of the light detection units 10 may be larger or smaller, A one-dimensionally arranged configuration is also possible. The common electrode E3 is disposed at the center of the plurality of light detection units 10.

  Each light detection unit 10 includes an APD, a connection electrode 3, a quenching resistor 4, and a connection wiring 6. One end of the APD is connected to the connection electrode 3, and the connection electrode 3 is connected to the readout wiring (wiring pattern) 5 </ b> B <b> 2 serving as the above-described readout wiring TL through the quenching resistor 4 and the connection wiring 6 in order. The readout wiring 5B2 is located between adjacent APDs and is present at the boundary position between the light detection units 10.

  The readout wiring 5B2 forms a lattice pattern, and one light detection unit 10 is arranged in one opening pattern. The read wiring 5B2 can adopt patterns of various shapes. A plurality of light detection units 10 may be arranged in one opening of the pattern of the readout wiring 5B2. One row or a plurality of examples of the light detection units 10 may be arranged in one opening pattern.

  When a photon is incident on one photodetecting section 10, carriers are generated in the APD, and this carrier sequentially passes through the connection electrode 3, the quenching resistor 4, the connection wiring 6, and the readout wiring 5B2 (connection wiring 5B) to the common electrode. E3 is reached. Therefore, each time a photon enters the photodiode array, a pulse signal is output from the common electrode E3. Even when photons are incident on a plurality of APDs at the same time, the signal from the APD that is located far from the common electrode E3 has a longer time to reach the common electrode E3 than the signal from the APD that is located near the common electrode E3. Becomes slower. That is, the signal transmission time varies depending on the position of the APD.

  The signal transmission time from each APD is short, the variation in the signal transmission time is less, and the larger the output signal, the better the photodiode array. The former two characteristics can be improved by reducing the time constant in the signal transmission path. This is because if the time constant is decreased, the signal transmission speed increases and the difference for each photodiode also decreases. If the width of the readout wiring is increased, the time constant becomes smaller. On the other hand, the latter characteristic can be improved by improving the aperture ratio of each photodiode, but generally the aperture ratio decreases if the width of the readout wiring is increased. Therefore, in the photodiode array of this embodiment, the readout wiring 5B2 is arranged on the upper layer side than the surface electrode 3B, which is the main part of the connection electrode 3, and the aperture ratio decreases even if the width of the readout wiring is widened. The structure was not.

  FIG. 44 is a cross-sectional view of a photodiode array, and FIG. 45 is a diagram showing a connection relationship between electrodes and wirings.

  As shown in FIG. 44, each photodetecting section 10 includes a first conductivity type (n-type) first semiconductor region (layer) 12 and a second conductivity type (a pn junction that forms a pn junction with the first semiconductor region 12). A p-type second semiconductor region (semiconductor layer 13 and high impurity concentration region 14) is provided, and these constitute a semiconductor substrate. The semiconductor region 14 or a region immediately below the semiconductor region 14 generates a carrier at the pn junction, and thus functions as a photosensitive region and outputs a carrier. When a potential lower than that of the n-type semiconductor is applied to the p-type semiconductor, a reverse bias voltage is applied to the photodiode. Carriers that are relatively attracted to a negative potential are holes, and carriers that are relatively attracted to a positive potential are electrons. If the reverse bias voltage is greater than the APD breakdown voltage, the APD operates in Geiger mode. The bias voltage is applied between the common electrode E3 and a back electrode E4 provided on the back surface of the semiconductor substrate (first semiconductor region 12) as necessary.

  The first contact electrode 3A (see FIG. 45) is in contact with the high impurity concentration region (semiconductor region) 14 in the second semiconductor region. The high impurity concentration region 14 is a diffusion region (semiconductor region) formed by diffusing impurities into the semiconductor layer 13, and has a higher impurity concentration than the semiconductor layer 13. In this example (type 1), a p-type semiconductor layer 13 is formed on the n-type first semiconductor region 12, and a p-type high-concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. . Therefore, the pn junction constituting the photodiode is formed between the first semiconductor region 12 and the semiconductor layer 13.

  As the layer structure of the semiconductor substrate, a structure in which the conductivity type is reversed from the above can be adopted. That is, in the (type 2) structure, the n-type semiconductor layer 13 is formed on the p-type first semiconductor region 12, and the n-type high-concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. Formed.

  Also, the pn junction interface can be formed on the surface layer side. In this case, in the (type 3) structure, the n-type semiconductor layer 13 is formed on the n-type first semiconductor region 12, and the p-type high-concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. It becomes a structure to be. In the case of this structure, the pn junction is formed at the interface between the semiconductor layer 13 and the semiconductor region 14.

  Of course, even in such a structure, the conductivity type can be reversed. That is, in the (type 4) structure, the p-type semiconductor layer 13 is formed on the p-type first semiconductor region 12, and the n-type high concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. It becomes a structure.

  As shown in FIG. 45, the first contact electrode 3A is in contact with the semiconductor region 14, the annular electrode 3B is continuous with the first contact electrode, and the annular electrode 3B is quenched via the second contact electrode 3C. The resistor (resistive layer) 4 is connected. That is, the connection electrode 3 including the first contact electrode 3 </ b> A, the annular surface electrode 3 </ b> B, and the second contact electrode 3 </ b> C electrically connects the semiconductor region 4 and one end of the quenching resistor 4.

  As shown in FIG. 44, the first insulating layer 16 is formed on the semiconductor regions 13 and 14, and the quenching resistor 4 is formed on the first insulating layer 16. A second insulating layer 17 is formed so as to cover the quenching resistor 4 and the first insulating layer 16. A contact hole through which the first contact electrode 3A (FIG. 45) penetrates is formed in the first insulating layers 16 and 17, and a contact hole through which the second contact electrode 3C (FIG. 45) penetrates in the second insulating layer 17. Is formed. Further, the connection wiring 6 is in contact with and electrically connected to the other end of the quenching resistor 4. The connection wiring 6 is composed of a contact electrode penetrating a contact hole provided in the second insulating layer 17 and a connection portion that crawls on the second insulating layer 17, and the connection portion is an auxiliary read wiring (lower layer read wiring) 5A. It is continuous.

A third insulating layer 18 is formed on the auxiliary read wiring 5A, the surface electrode 3B, and the second insulating layer. The first to third insulating layers 16, 17, and 18 are made of an inorganic insulator having high heat resistance such as SiO ₂ or silicon nitride (SiNx). On the third insulating layer 18, the read wiring 5B2 is formed. As shown in FIG. 45, the connection wiring 5B includes a contact electrode 5B1 penetrating through a contact hole provided in the third insulating layer 18, and a readout wiring 5B2 that is continuous with the contact electrode 5B1 and is located on the third insulating layer 18. It consists of. In the example shown in FIG. 45, the auxiliary read wiring 5A and the read wiring 5B2 are arranged in parallel with a separation in the thickness direction, and both ends are electrically connected to the common electrode E3.

  74 and 75 corresponding to FIG. 14 or FIG. 20, the insulating layer 18 is formed on the insulating layer 17 in the cross-sectional structure around the common electrode E3. Further, the common electrode E3 and the readout wiring 5B2 (TL) are formed on the insulating layer 18, and the corresponding insulating layers 16, 17, 18 are removed until the through hole TH reaches the back surface of the common electrode E3. However, the other points are the same. On such a semiconductor chip, an insulator such as a glass plate, an adhesive layer, or a resin is disposed as described above, and a scintillator is bonded thereon.

  The common electrode E3 may be formed on the second insulating layer 17. In this case, the common electrode E3 is formed on the region where the third insulating layer 18 is removed at the end of the read wiring 5B2. The auxiliary readout wiring 5A and readout wiring 5B2 are connected to this. When the common electrode E3 is formed on the third insulating layer 18, the readout wiring 5B2 is connected to the common electrode E3, and the contact provided on the third insulating layer 18 at the end of the auxiliary readout wiring 5A. The auxiliary readout wiring 5A is connected to the common electrode E3 through the hole.

  The annular surface electrode 3B is located on the second insulating layer 17 and is provided along the outer edge of the semiconductor region 14 when viewed from the Z-axis direction. The surface electrode 3B improves the stability of the photodiode output by generating a constant electric field at the outer edge of the semiconductor region 14 (boundary with the semiconductor region 13).

  Here, in FIG. 44, when a plane including the surface of the semiconductor region 14 is a reference plane (XY plane), a distance tb from the reference plane to the read wiring 5B2 is a distance ta from the reference plane to the surface electrode 3B. Bigger than. This is because the third insulating layer 18 is interposed between the read wiring 5B2 and the second insulating layer 17. With this structure, the degree of freedom in designing the width of the readout wiring 5B2 can be increased without reducing the aperture ratio of the photodiode. As a result, the width of the readout wiring 5B2 can be increased, the resistance value per unit length can be reduced, the parasitic capacitance can be reduced, and the signal transmission speed can be improved.

  The APD is composed of a semiconductor region 14 and a region immediately below the semiconductor region 14 and includes semiconductor regions 13 and 12. The read wiring 5B2 is formed in a region between the semiconductor regions 14 (APD). Even if the width of the readout wiring 5B2 is increased, the aperture ratio does not decrease until the exposed region of the semiconductor region 14 is covered, and the signal output can be increased.

  As described above, the photodiode array described above is a photodiode array including a plurality of photodetectors 10 each having an APD that operates in Geiger mode. Each photodetector 10 includes a semiconductor region 14 that outputs a carrier. A surface electrode 3B that is electrically connected to the semiconductor region 14 and surrounds the semiconductor region 14 along the outer edge thereof, and a quenching resistor 4 that connects the surface electrode 3B and the readout wiring 5B2. ing. When a plane including the surface of the semiconductor region 14 is a reference plane, a distance tb from the reference plane to the readout wiring 5B2 is larger than a distance ta from the reference plane to the surface electrode 3B, and the readout wiring 5B2 is Located between adjacent APDs. According to this photodiode array, characteristics such as signal readout speed can be improved.

  In the above description, an annular electrode is used as the surface electrode 3B, but this may be partially cut off. Moreover, although the shape of the quenching resistor 4 is shown as extending linearly in the above, various shapes are conceivable.

  FIG. 46 is a diagram illustrating a connection relationship between electrodes and wirings.

  The quenching resistor 4 of this example extends so as to surround the outside of the surface electrode 3B, and has a ring shape that is cut off in the middle. One end of the quenching resistor 4 is electrically connected to the semiconductor region 14 via the connection electrode 3. The other end of the quenching resistor 4 is connected to the auxiliary readout wiring 5A through the connection wiring 6, and the auxiliary readout wiring 5A is electrically connected to the readout wiring 5B2 through the contact electrode 5B1. In this example, since the quenching resistance 4 is lengthened, the resistance value can be increased. However, the longitudinal cross-sectional structure along the carrier passage path has a portion where the connection wiring 6 extends horizontally. It is the same as that shown in FIG. 44 except that it is directly connected to the lower surface of the auxiliary readout wiring 5A.

  Next, examples of the structure of various readout wirings 5B and auxiliary readout wirings 5A will be described.

  First Example FIG. 47 is a partial plan view of a photodiode array (first example), and FIG. 48 is a cross-sectional view of the photodiode array (first example) shown in FIG.

  In the structure of the first example, in the structure shown in FIG. 46, the readout wiring 5B2 extends between the adjacent semiconductor regions 14, and the width of the readout wiring 5B2 is larger than the separation distance between the adjacent surface electrodes 3B. This is the case. The auxiliary read wiring 5A has the same width as the read wiring 5B2, and these extend in parallel. Here, when the thickness of the third insulating layer 18 is not sufficiently thick or when the surface polishing is not performed, as shown in FIG. 48, the surface of the third insulating layer 18 is a lower surface electrode. Due to the shape of 3B, it will have irregularities. Of course, due to the shape of the auxiliary readout wiring 5A, the surface of the third insulating layer 18 is also deformed with irregularities, but such deformation is not shown in FIG.

  In this example, since the two readout wirings 5A and 5B2 are provided, the wiring resistance can be reduced, the time constant can be reduced, and the signal readout speed can be improved.

  (Second Example) FIG. 49 is a partial plan view of a photodiode array (second example), and FIG. 50 is a cross-sectional view of the photodiode array (second example) shown in FIG.

  The structure of the second example is the structure shown in FIG. 46, in which the readout wiring 5B2 extends between the adjacent semiconductor regions 14, and the width of the readout wiring 5B2 is close to the separation distance between the adjacent surface electrodes 3B. This is the case. The auxiliary readout wiring 5A has a narrower width than the readout wiring 5B2, and these extend in parallel. Here, when the thickness of the third insulating layer 18 is not sufficiently thick or when the surface polishing is not performed, the surface of the third insulating layer 18 is a lower surface electrode as shown in FIG. Due to the shape of 3B, it will have irregularities. Of course, due to the shape of the auxiliary readout wiring 5A, the surface of the third insulating layer 18 is also deformed with irregularities, but such deformation is not shown in FIG.

  In this example, since the two readout wirings 5A and 5B2 are provided, the wiring resistance can be reduced, the time constant can be reduced, and the signal readout speed can be improved. Furthermore, since the width of the readout wiring 5B2 is wide, the wiring resistance can be greatly reduced.

  In the above first and second examples, when the thickness of the third insulating layer 18 is sufficiently thick (1 μm to 5 μm), or when the surface is polished and flattened, the readout wiring Since 5B is formed on a flat surface, there is an effect that disconnection due to a step on the surface is suppressed. The thicknesses of the surface electrode 3B and the auxiliary readout wiring 5A are both 0.6 μm to 3.0 μm.

  (Third Example) FIG. 51 is a partial plan view of a photodiode array (third example), and FIG. 52 is a cross-sectional view of the photodiode array (third example) shown in FIG. .

  The structure of the third example is the structure shown in FIG. 46, in which the readout wiring 5B2 extends between the adjacent semiconductor regions 14, and the width of the readout wiring 5B2 is the separation distance (outer edge) between the adjacent surface electrodes 3B. It is a case where it is larger than the minimum value of the distance between them. The width of the read wiring 5B2 is equal to or smaller than the minimum value of the separation distance between the inner edges of the adjacent surface electrodes 3B.

  The auxiliary readout wiring 5A has a narrower width than the readout wiring 5B2, and these extend in parallel. Here, since the thickness of the third insulating layer 18 is sufficiently thick or surface polishing is performed, the surface of the third insulating layer 18 is flattened as shown in FIG.

  In this example, since the two readout wirings 5A and 5B2 are provided, the wiring resistance can be reduced, the time constant can be reduced, and the signal readout speed can be improved. In addition, since the width of the read wiring 5B2 is significantly widened, the wiring resistance is further reduced.

  Next, an example in which the above-described auxiliary readout wiring 5A is substantially omitted will be described.

  FIG. 53 is a diagram showing a connection relationship between electrodes and wirings. The difference from the structure shown in FIG. 46 is that the auxiliary readout wiring 5A is not directly connected to the common electrode, but is used only to connect the connection wiring 6 and the contact electrode 5B1. Yes, the other points are the same. That is, the auxiliary readout wiring 5A is not electrically connected to the common electrode without passing through the readout wiring 5B2. An example using such a structure will be described below.

  (Fourth Example) FIG. 54 is a partial plan view of a photodiode array (fourth example), and FIG. 55 is a cross-sectional view of the photodiode array (fourth example) shown in FIG. .

  In the structure of the fourth example, in the structure shown in FIG. 53, the readout wiring 5B2 extends between the adjacent semiconductor regions 14, and the width of the readout wiring 5B2 is larger than the separation distance between the adjacent surface electrodes 3B. This is the case. The auxiliary readout wiring 5A has the same width as the readout wiring 5B2, and has a slight portion extending in parallel, but is interrupted on the way to the common electrode. Here, when the thickness of the third insulating layer 18 is not sufficiently thick or when the surface polishing is not performed, as shown in FIG. 55, the surface of the third insulating layer 18 is a lower surface electrode. Due to the shape of 3B, it will have irregularities. Since the auxiliary read wiring 5 </ b> A does not substantially exist, the unevenness due to this is not substantially present on the surface of the third insulating layer 18.

  In this example, since the readout wiring 5B2 passes through the upper layer, the thickness and width can be freely designed, the wiring resistance can be reduced, the time constant can be reduced, and the signal readout speed can be improved. .

  (Fifth Example) FIG. 56 is a partial plan view of a photodiode array (fifth example), and FIG. 57 is a cross-sectional view of the photodiode array (fifth example) shown in FIG. .

  In the structure of the fifth example, in the structure shown in FIG. 54, the readout wiring 5B2 extends between the adjacent semiconductor regions 14, and the width of the readout wiring 5B2 is close to the separation distance between the adjacent surface electrodes 3B. This is the case. The auxiliary readout wiring 5A has the same width as the readout wiring 5B2, and has a portion extending in parallel, but is interrupted on the way to the common electrode E3. Here, when the thickness of the third insulating layer 18 is not sufficiently thick or when the surface polishing is not performed, as shown in FIG. 57, the surface of the third insulating layer 18 is a lower surface electrode. Due to the shape of 3B, it will have irregularities. Since the auxiliary read wiring 5 </ b> A does not substantially exist, the unevenness due to this is not substantially present on the surface of the third insulating layer 18.

  In this example, since the width of the readout wiring 5B2 is wide, the wiring resistance can be reduced, the time constant can be reduced, and the signal readout speed can be improved. In addition, since the auxiliary read wiring 5A does not substantially exist, there is no step in the third insulating layer 18 due to this, and there is an effect that disconnection of the read wiring 5B2 due to this step is suppressed.

  In the fourth and fifth examples described above, the thickness of the third insulating layer 18 can be made sufficiently thick, or the surface can be polished to flatten the surface. The range of the thickness of the third insulating layer 18 and the range of the thickness of the surface electrode 3B that can be planarized are the same as those described in the second example.

  (Sixth Example) FIG. 58 is a partial plan view of a photodiode array (sixth example), and FIG. 59 is a cross-sectional view of the photodiode array (sixth example) shown in FIG. .

  The structure of the sixth example is the structure shown in FIG. 53, in which the readout wiring 5B2 extends between the adjacent semiconductor regions 14, and the width of the readout wiring 5B2 is the separation distance (outer edge) between the adjacent surface electrodes 3B. It is a case where it is larger than the minimum value of the separation distance between them. The width of the read wiring 5B2 is equal to or smaller than the minimum value of the separation distance between the inner edges of the adjacent surface electrodes 3B.

  The auxiliary readout wiring 5A has the same width as the readout wiring 5B2, and has a slight portion extending in parallel, but is interrupted on the way to the common electrode. Here, since the thickness of the third insulating layer 18 is sufficiently thick or surface polishing is performed, the surface of the third insulating layer 18 is flattened as shown in FIG.

  In this example, since the width of the readout wiring 5B2 is sufficiently wide, the wiring resistance can be reduced, the time constant can be reduced, and the signal readout speed can be improved. Further, the auxiliary read wiring 5A is not substantially present, and the surface of the third insulating layer 18 is flattened, so that there is no step in the third insulating layer 18, and the read wiring 5B2 caused by this step is not present. There is an effect that disconnection is suppressed.

  (Seventh Example) FIG. 60 is a partial plan view of a photodiode array (seventh example), and FIG. 61 is a cross-sectional view of the photodiode array (seventh example) shown in FIG. .

  The structure of the seventh example is the same as the structure of the sixth example, except that the separation distance of the semiconductor region 14 is narrowed and the aperture ratio of the photodiode is improved instead of narrowing the width of the read wiring 5B2. Other points are the same as in the sixth example. In any example, the contact electrode 5B1 may be provided outside the region surrounded by the quenching resistor 4.

  In this example, since the width of the readout wiring 5B2 is sufficiently wide, the wiring resistance can be reduced, the time constant can be reduced, and the signal readout speed can be improved. Further, the auxiliary read wiring 5A is not substantially present, and the surface of the third insulating layer 18 is flattened, so that there is no step in the third insulating layer 18, and the read wiring 5B2 caused by this step is not present. There is an effect that disconnection is suppressed. Further, since the aperture ratio of the photodiode is improved, there is an advantage that the output signal is increased.

  In any of the above structures, the structure shown in FIG. 62 can also be employed as the structure of the semiconductor substrate.

  FIG. 62 is a longitudinal sectional view of a photodiode array in which the structure of the substrate is changed. In the figure, as compared with the photodiode array, only the changed points are indicated by solid lines, and the remaining points are indicated by alternate long and short dash lines.

  This structure is the same as the structure of type 1 to type 4 described in FIG. 43 and subsequent drawings, except that the semiconductor region 15 is disposed immediately below the semiconductor region 14, and the other points are the same. The semiconductor region 15 has the same conductivity type as the semiconductor region 14 or a different conductivity type. Those having the same conductivity type are referred to as (type 1S) to (type 4S), and those having different conductivity types are referred to as (type 1D) to (type 4D). The impurity concentration in the semiconductor region 15 is smaller than the impurity concentration in the semiconductor region 14. Further, B (boron) can be adopted as the p-type impurity, and P (phosphorus), As (arsenic) or Sb (antimony) can be adopted as the n-type impurity.

  Note that the preferable ranges of the conductivity type, impurity concentration, and thickness of each layer in the semiconductor structure described above are as described in FIG.

  In the above-described example, the lowermost semiconductor region 12 constitutes a semiconductor substrate having a large thickness. However, the light detection unit 10 may further include a semiconductor substrate below, in this case. The semiconductor region 12 has a thinner thickness than such an additional semiconductor substrate.

  The semiconductor region 13 can be formed on the semiconductor region 12 by an epitaxial growth method, but may be formed by impurity diffusion or ion implantation with respect to the substrate. The semiconductor regions 14 and 15 can be formed by impurity diffusion or ion implantation with respect to the semiconductor region 13.

  FIG. 63 is a plan view of the photodiode array. This example has an electrode pattern of the type shown in FIG. On the surface, a grid-like readout electrode (readout wiring) 5B2 and a common electrode E3 connected to the readout electrode 5B2 are formed, and the light detection unit 10 is located in each opening of the grid. .

  Each photodetection section 10 has a connection electrode 3 connected to the semiconductor region 14 (see FIG. 45), and the connection electrode 3 is connected to the readout wiring 5B2 via the quenching resistor 4. . The vertical cross-sectional structure along the carrier traveling path of this photodiode array is as shown in FIG. 44, but the above-described types 1 to 4 (types 1S to 4S, 1D to 4D) may be adopted. Is possible. Further, the upper layer readout wiring 5B2 is essential, but the lower layer auxiliary readout wiring 5A may be used, but may be omitted. In other words, the structures of the first to seventh examples described above can be applied as the structure of the readout wiring 5B2 and the auxiliary readout wiring 5A.

  It is also possible to have a plurality of light detection units 10 in one opening of the readout wiring 5B2.

  The cross-sectional structure around the common electrode E3, the structure for attaching the scintillator to the semiconductor chip, the structure for fixing the detection chip composed of these to the wiring board, and the like are the same as those described above.

  FIG. 64 is a diagram showing an SEM (scanning electron microscope) photograph of the surface of such a photodiode array, and FIG. 65 is a diagram showing an SEM photograph of a section of the photodiode array (a section taken along line AA). is there. This example shows the structure of the fifth example, and the auxiliary read electrode 5A is not substantially used.

  In FIG. 64, it is observed that the quenching resistor 4 connected to the surface electrode 3B exists due to the change in the surface shape of the third insulating layer 18, and the readout wiring 5B2 extends alongside the quenching resistor 4. Is observed. FIG. 65 shows that the readout electrode 5B2 is present in an upper layer than the surface electrode 3B.

  FIG. 66 is a plan view of a part of the photodiode array. This example has an electrode pattern having the structure shown in FIG. On the surface, a grid-shaped readout electrode 5B2 having a rectangular opening is formed, and a plurality of light detection units 10 are located in each opening of the grid. This structure shows the photodiode array of the second example.

  Each of the light detection units 10 includes an avalanche photodiode having a semiconductor region 14 that outputs carriers, and the surface electrode 3B is electrically connected to the semiconductor region 14 and has a semiconductor region along its outer edge. 14 is enclosed. The surface electrode 3B and the readout wiring 5B2 are connected by a quenching resistor 4.

  Two photodetecting units 10 adjacent in the horizontal direction are connected to one readout wiring 5B2 extending in the vertical direction via a common connection wiring (contact electrode) 6, and these photodetecting units 10 are connected to each other. Has a line-symmetric structure with respect to the longitudinal central axis of the readout wiring 5B2. Thereby, the number of read-out wiring 5B2 can be reduced.

  67 is a cross-sectional view taken along the line AA of the photodiode array (second example) shown in FIG.

  A semiconductor region 13 is formed on the semiconductor layer 12, and a first insulating layer 16 is formed on the semiconductor region 13. A quenching resistor 4 is formed on the first insulating layer 16, and a second insulating layer 17 is formed thereon. An auxiliary read wiring 5A is provided on the second insulating layer 17 through a contact hole of the second insulating layer 17, and a third insulating layer 18 is formed on the auxiliary read wiring 5A. A contact electrode 5B1 is provided in the contact hole provided in the third insulating layer 18, and the lower auxiliary read wiring 5A and the upper read wiring 5B2 are physically and electrically connected.

  In the case where the contact electrode 5B1 is located at the terminal position of the auxiliary read wiring 5A and the auxiliary read wiring 5A on the output side is omitted from the contact electrode 5B1, this example is the photodiode array of the fifth example described above. Note that the wiring connection structure of this example can be applied to any of the structures of the first to seventh examples.

  When the auxiliary wiring electrode 5A is not provided, the contact electrode 5B1 can be disposed immediately above the quenching resistor 4, and the quenching resistor 4 and the readout wiring 5B2 can be directly connected by the contact electrode 5B1. is there. Thus, a structure in which the auxiliary read wiring 5A is completely omitted is possible.

  In any structure and in any example, the photodiode array described above includes an insulating layer 18 formed on the quenching resistor 4, and the readout wiring 5B 2 is provided in the insulating layer 18. The quenching resistor 4 is electrically connected to the quenching resistor 4 through the contact hole, and the quenching resistor 4 and the common electrode are electrically connected.

  Next, constituent materials for the photodiode array will be described.

The constituent material of the semiconductor regions 12, 13, and 14 constituting the semiconductor substrate is Si as described above and contains a desired impurity. The constituent material of the insulating layers 16, 17, and 18 is SiO ₂ or silicon nitride, respectively. The constituent materials of the connection electrode 3, the connection wiring 6, the auxiliary connection wiring 5A, the connection wiring 5B (readout wiring 5B2, contact electrode) common electrode and the through electrode are each a metal, preferably Al, Cu, Au, Cr, Ag. Or a metal such as Fe, or an alloy containing two or more of these metals. The constituent material of the quenching resistor 4 is a material having a higher resistivity than the readout wiring 5B2, and is polysilicon, SiCr, NiCr, or TaNi.

In the above SEM photograph, SiO ₂ is used as the constituent material of the insulating layers 16, 17, and 18, and the connection electrode 3, the connection wiring 6, the auxiliary connection wiring 5A, the connection wiring 5B (reading wiring 5B2, contact electrode) and the common are used. In this example, Al is used as the constituent material of the electrode E3, and polysilicon is used as the constituent material of the quenching resistor 4.

  Next, referring to FIG. 44 again, a manufacturing method of the above-described photodiode array will be described.

First, the semiconductor region 13 is formed on the semiconductor region (semiconductor substrate) 12 by an epitaxial growth method, an impurity diffusion method, or an ion implantation method. The semiconductor region 12 is preferably a (100) Si semiconductor substrate formed by the CZ method or the FZ method, but a semiconductor substrate having another plane orientation can also be used. When the Si epitaxial growth method is used, for example, gaseous silicon tetrachloride (SiCl ₄ ) and trichlorosilane (trichlorosilane, SiHCl ₃ ) are used as raw materials, and these are formed on the substrate surface at a growth temperature of 1200 ° C. Flow gas. In the case of the impurity diffusion method, an impurity corresponding to the conductivity type of the semiconductor region 13 is diffused into the semiconductor region 12 with gas or solid. In the case of the ion implantation method, an impurity corresponding to the conductivity type of the semiconductor region 13 is ion implanted into the semiconductor region 12.

Next, the semiconductor region 14 is formed in the region on the surface side of the semiconductor region 13. For this, an impurity diffusion method or an ion implantation method can be used. For example, in the diffusion method, when diborane (B ₂ H ₆ ) is used as the impurity raw material, the diffusion temperature can be set to 1200 ° C. In forming the semiconductor region 14, first, a resist pattern having an opening is formed on the semiconductor region 13 by a photolithography technique, and then an impurity is added using the resist pattern as a mask. The impurity may be added by ion implantation after forming the grid-like wiring pattern 3C and using this as a mask through the insulating layer 16.

Next, the insulating layer 16 is formed on the semiconductor substrate. The insulating layer 16 can be formed using a Si thermal oxidation method. The oxidation temperature is 1000 ° C., for example. Thereby, the surfaces of the semiconductor regions 13 and 14 are oxidized, and the insulating layer 16 made of SiO ₂ is formed. The insulating layer 16 can be formed by a CVD method.

  Next, a mask is formed at a desired position in the insulating layer 16 using resist patterning by photolithography, and a resistive material is deposited in the opening of the resist using the mask, and a quenching resistance is formed in the opening. 4 is formed and the resist is removed. The resistive material can be deposited using sputtering methods that target this. For example, polysilicon is used as the resistance material to form polysilicon quenching resistance 4.

Next, the insulating layer 17 is formed on the insulating layer 16. The insulating layer 17 can be formed using a sputtering method or a plasma CVD method. When using the plasma CVD method, tetraethoxysilane (TEOS) and oxygen gas are used as raw material gases, and the growth temperature is set to about 200 ° C. to grow the insulating layer 17. The thickness of the insulating layer 17 is preferably set to such a thickness that the surface is flattened, and is preferably larger than the height from the surface of the insulating layer 16 to the upper surface of the wiring pattern 3C. Thereby, the insulating layer 17 made of SiO ₂ is formed.

  Next, a contact hole is formed at a position on the semiconductor region 14 in the insulating layer 17 and the insulating layer 16. In forming the contact hole, first, a resist pattern having an opening is formed on the insulating layer 17 by photolithography, and then the insulating layer 17 and the insulating layer 16 are etched using the resist pattern as a mask. As the etching method, in addition to the dry etching method, wet etching with an etching solution containing an HF aqueous solution can be used.

  Next, a mask is formed on the insulating layer 17 at a desired position by using a resist patterning by photolithography technique, and the mask is used to deposit in the resist opening. The first contact electrode 3A, the surface electrode 3B, the second contact electrode 3C, the connection wiring 6 and the auxiliary readout electrode 5A are formed at the same time, and the resist is removed after forming these. In this example, aluminum is used as a vapor deposition material, but a sputtering method or the like can also be used.

  Next, the insulating layer 18 is formed on the insulating layer 17. The formation method of the insulating layer 18 is the same as that of the insulating layer 17.

  Thereafter, a mask is formed at a desired position of the insulating layer 18 using resist patterning by photolithography, and the insulating layer 18 is etched using this mask to form a contact hole. Remove. As the etching method for forming the contact hole, in addition to the dry etching method, wet etching with an etching solution containing an HF aqueous solution can be used. In this contact hole, the contact electrode 5B1 is formed, and at the same time, the readout wiring 5B2 continuous to the contact electrode 5B1 is formed.

  In the formation of the contact electrode 5B1 and the readout wiring 5B2, first, a mask is formed at a desired position of the insulating layer 18 by using resist patterning by a photolithography technique, and the contact electrode 5B1 and the readout in the opening of the mask. A wiring 5B2 is deposited. As the deposition method, an evaporation method or a sputtering method can be used.

  In the case of manufacturing the photodetection portion having the structure shown in FIG. 62, the semiconductor region 15 may be formed on the surface side of the semiconductor region 13 by using the impurity diffusion method or the ion implantation method before the formation of the semiconductor region 14. That's fine. In the case of the impurity diffusion method, impurities corresponding to the conductivity type of the semiconductor region 15 are diffused into the semiconductor region 13 with gas or solid. In the case of the ion implantation method, an impurity corresponding to the conductivity type of the semiconductor region 15 is ion implanted into the semiconductor region 13.

  When the common electrode E3 is formed on the second insulating layer 17, the common electrode E3 can be formed simultaneously with the surface electrode 3B by resist patterning. When the common electrode E3 is formed on the third insulating layer 18 and the auxiliary read wiring 5A is connected to the common electrode E3, the auxiliary read wiring 5A and the common electrode E3 are connected to the third insulating layer 18. After the contact hole is formed, the contact electrode and the common electrode in the contact hole may be formed simultaneously with the formation of the readout wiring 5B2.

  In the case of the above-described embodiment, the planar shape of the quenching resistor 4 is annular, but this may be a partial shape of the ring or a spiral shape.

  Next, an effect when the photodiode array having the structure of the above-described fifth example (FIGS. 56 and 57) is prototyped will be described. In this example, the common electrode E3 and the through electrode are not manufactured.

The manufacturing conditions are as follows.
(1) Structure (1-1)
Semiconductor region 12:
Conduction type: n-type (impurity: Sb (antimony))
Impurity concentration: 5.0 × 10 ¹¹ cm ⁻³
Thickness: 650 μm
(1-2)
Semiconductor region 13:
Conduction type: p-type (impurity: B (boron))
Impurity concentration: 1.0 × 10 ¹⁴ cm ⁻³
Thickness: 30μm
(1-3)
Semiconductor region 14
Conduction type: p-type (impurity: B (boron))
Impurity concentration: 1.0 × 10 ¹⁸ cm ⁻³
Thickness: 1000nm
(1-4)
Insulating layer 16: SiO ₂ (thickness: 1000 nm)
(1-5)
Insulating layer 17: SiO ₂ (thickness: 2000 nm)
(1-6)
Insulating layer 18: SiO ₂ (thickness: 2000 nm)
(1-7)
Connection electrode 3: (Aluminum (Al))
(1-8)
Quenching resistance 4 (polysilicon)
Shape: Shape thickness shown in FIG. 63: 500 nm
Width: 2μm
Length: 100μm
Resistance value: 500kΩ
(1-9)
Photodetector 10
Area S of one light detection unit 10: 2025 μm ²
Spacing X between adjacent centers of the light detection units 10: 50 μm
Number of photodiodes in the light receiving area (X axis direction = 100 × 100 Y axis direction)
Light receiving area X-axis direction dimension: 5mm
Dimension of the light receiving area in the Y-axis direction: 5mm
(1-10)
Read wiring 5B2
Width: 5μm
Number of wirings in the X-axis direction: 101 Number of wirings in the Y-axis direction: 101 Number of light detection units 10 existing in one opening: 1
(2) Manufacturing conditions / semiconductor region 12: CZ method ((001) Si semiconductor substrate)
Semiconductor region 13: Si epitaxial growth method (raw materials: gas phase silicon tetrachloride (SiCl ₄ ), silane trichloride (trichlorosilane, SiHCl ₃ ), growth temperature 1200 ° C.)
Semiconductor region 14: impurity thermal diffusion method (impurity raw material: diborane (B ₂ H ₆ ), diffusion temperature 1200 ° C.)
Insulating layer 16: (Si thermal oxidation method: oxidation temperature (1000 ° C.))
Quenching resistance 4: Sputtering method (target material: Si)
Insulating layer 17: (plasma CVD method: raw material gas (tetraethoxysilane (TEOS) and oxygen gas): growth temperature (200 ° C.))
First contact electrode 3A, surface electrode 3B, second contact electrode 3C, connection wiring 6, auxiliary readout wiring 5A, common electrode E3: evaporation method (raw material: aluminum)
Insulating layer 18: (plasma CVD method: raw material gas (tetraethoxysilane (TEOS) and oxygen gas): growth temperature (200 ° C.))
Contact electrode 5B1, readout wiring 5B2, common electrode (electrode pad): evaporation method (raw material: aluminum)

  The characteristics of the photodiode array according to the example were evaluated as follows.

  FIG. 68 shows the distance from each photodiode (pixel) as a base point to an electrode pad (considered as a common electrode E3) provided at one end on the surface of the semiconductor chip, and the difference from the carrier signal transmission time reference. It is a graph (Example) which shows tp (ps). The time difference tp is a transmission time from the reference time. Five photodiodes are arranged around the photodiode as the base point, the number of base points in the X-axis direction is 12, and the number of base points in the Y-axis direction is 18, and in the graph, each base point is The average value of the surrounding photodiode output is shown as one data.

  The photodiode chip has a size of 5 mm × 5 mm, and the foremost position in the graph is the origin on the XY plane, and 100 photos in the X axis direction and 100 photos in the Y axis direction of the light receiving area. A diode is arranged. The electrode pad regarded as the common electrode E3 is provided at the position of E3 existing on the right side of the graph.

  The difference in signal transmission time tp (ps) from each photodiode to the electrode pad tends to increase as the distance from the electrode pad increases, but all the time differences tp are as short as 160 ps or less, and the in-plane variation is small.

  FIG. 69 is a graph (comparative example) showing the distance from each photodiode to the electrode pad and the difference tp (ps) from the carrier signal transmission time reference. In the comparative example, in the first example described above, only the lower auxiliary readout wiring 5A is used for signal transmission, and the upper readout wiring 5B2 is not formed. The width of one auxiliary read wiring 5A in the comparative example is 2 μm.

  The difference in signal transmission time tp (ps) from each photodiode to the electrode pad tends to increase as the distance from the electrode pad E3 increases. However, the majority of the time difference tp exceeds 160 ps and exceeds 300 ps at the maximum. In-plane variation is also large.

  FIG. 70 is a graph showing the relationship between the voltage Vover and the FWHM (ps) indicating the variation in the output pulse arrival time, and FIG. 71 is a graph showing the relationship between the arrival time tβ (ps) and the count number.

  In order to operate the photodiodes in the Geiger mode, a reverse bias voltage (70 + Vover) larger than the breakdown voltage (70V) of the photodiodes by the voltage Vover is applied to each photodiode. In the case where the excess voltage Vover is 1.5 to 4 V (reverse bias voltage = 71.5 V to 74 V), in the embodiment, the full width at half maximum (FWHM) is 200 ps or less, and the minimum is 130 ps. Is 220 ps or more. In addition, the measuring method of this FWHM is as follows. By forming the two-layer metal wiring, the wiring resistance can be reduced and high time resolution can be achieved. Note that the time variation can be further improved by forming not only one semiconductor chip or each active channel but also a plurality of common electrodes and through holes.

  First, the entire surface of the photodiode array is irradiated with laser light. In this case, a plurality of pulse signals corresponding to photon incidence are output from each photodiode. Since the photodiodes are distributed in the plane, even when laser light is incident on each photodiode at the same time, the photodiodes reach the electrode pads with a slight time spread. FIG. 71 is a graph in which the number of pulse signal counts (number of pulses) for each time tβ from when the laser beam is emitted until the carrier reaches the electrode pad is a histogram. The number of pulses with the arrival time tβ in the vicinity of 2040 (ps) is the largest, and the arrival time is normally distributed with this time as a peak. The smaller the FWHM of this graph, the less the arrival time varies.

  In the photodiode array of the example, since the FWHM is sufficiently small, it can be seen that the variation in the in-plane arrival time tβ is more sufficiently suppressed than in the comparative example.

  The graphs of FIGS. 68 and 69 are obtained by using the method of FIGS. 72 and 73 below.

  72 is a diagram for explaining the laser beam irradiation, and FIG. 73 shows the relationship between the time tα (ns) until the carrier reaches the electrode pad from the laser beam emission timing and the output OUT (au). It is a graph (simulation).

  As shown in FIG. 72, a laser beam having a diameter of 1 mm is irradiated to the photodiode group of the embodiment existing at a position A, an intermediate position B, and a close position C far from the electrode pad, and the laser beam is indicated by an arrow in FIG. Scan along the horizontal direction (X-axis direction) shown. The average values of outputs from the far position A, the middle position B, and the near position C after scanning are shown in the graph of FIG.

  In this case, as shown in FIG. 73, the output OUT (au) indicating the output pulse voltage increases as the time tα (ns) increases, and saturates to a constant value at tα = 2.5 ns or more. ing. The rise time tα when the output OUT becomes the threshold value (threshold) = 0.5 or more is 1.4 ns.

  68 and 69 actually measure the output pulse corresponding to the simulation diagram of FIG. 73 and map the time delay of the pulse at each laser irradiation position when the time tα at the position C closest to the pad is used as a reference. It is a thing. This mapping was performed using the time tα at the threshold.

  As described above, the photodiode array according to the above-described embodiment is a photodiode array including a plurality of photodetectors having avalanche photodiodes operating in Geiger mode, and each photodetector 10 outputs a carrier. An avalanche photodiode PD having a semiconductor region 14 to be connected, a surface electrode 3B electrically connected to the semiconductor region 14 and surrounding the semiconductor region 14 along an outer edge thereof, and a surface electrode 3B and a readout wiring 5B2 (TL). When the plane including the surface of the semiconductor region 14 is a reference plane, the distance tb from the reference plane to the readout wiring 5B2 is the distance ta from the reference plane to the surface electrode 3B. The readout wiring 5B2 is larger than the adjacent avalanche photodiode PD (semiconductor Band 14) are located between.

  Carriers generated in response to the incidence of light on the semiconductor region 14 are sequentially supplied from the second semiconductor region 14 through the surface electrode 3B, the quenching resistor 4, and the readout wiring 5B2, to the common electrode E3, the through electrode, the bump electrode, To the wiring board. Since the readout wiring 5B2 is formed in an upper layer than the surface electrode 3B, the spatial restriction by the surface electrode 3B can be released, and the width thereof can be widened. Reading speed can be improved. The surface electrode can generate a constant electric field at the outer edge of the second semiconductor region 14 and can improve the output stability of the APD.

  Further, when the photodiode array is viewed from a direction perpendicular to the reference plane, the readout wiring 5B2 overlaps a part of the surface electrode 3B (third example, sixth example, seventh example). In this case, the formation region of the readout wiring 5B2 uses a region on the surface electrode 3B that becomes a dead space with respect to the incidence of light, so that the readout wiring 5B2 can be formed without reducing the aperture ratio of the photodiode. The dimensions can be expanded and the resistance value can be reduced.

  The photodiode array is electrically connected to the quenching resistor 4 through a first insulating layer 17 formed on the quenching resistor 4 and a contact hole provided in the first insulating layer 17. An auxiliary read wiring 5A and a second insulating layer 18 formed on the auxiliary read wiring 5A are provided, and the read wiring 5B2 is connected to the auxiliary read wiring 5A via a contact hole provided in the second insulating layer 18. They are electrically connected and extend in parallel to the auxiliary read wiring 5A, and are connected to the common electrode E3 together with the auxiliary read wiring 5A (first example, second example, third example).

  By using two readout wirings, the resistance value from the photodiode to the common electrode E3 can be reduced.

  The photodiode array includes an insulating layer 18 formed on the quenching resistor 4, and the readout wiring 5 </ b> B <b> 2 is electrically connected to the quenching resistor 4 through a contact hole provided in the insulating layer 18. The quenching resistor 4 and the common electrode E3 are electrically connected (first to seventh examples). Further, the auxiliary read wiring 5A may not be directly connected to the common electrode (fourth to seventh examples). In these cases, the degree of freedom in designing the readout wiring 5B2 is increased, the time constant can be reduced, and the signal readout speed can be improved.

  The resistance value of the quenching resistor 4 is preferably 100 to 1000 kΩ. The resistance value of the wiring from the semiconductor region 14 of the photodiode to the common electrode as the electrode pad is preferably as low as possible, but is preferably 20Ω or less, and more preferably 5Ω or less.

  As described above, when the through-electrode is used, when performing large area tiling, there is little dead space and a contrasting arrangement makes it easy to reconstruct an image with a PET apparatus, CT apparatus, or the like. This structure is preferably a symmetric shape because an asymmetric chip having a wire bonding pad requires correction for image reconstruction.

  Moreover, the shape of a through-hole can consider the thing of a taper type like a truncated pyramid shape, and a rectangular parallelepiped or a column shape (straight type). The inside of the through hole can be hollow, but may be filled with a metal or an insulator. One or a plurality of through electrodes may be provided for one active channel. The size of the active channel can be 1 × 1 mm, 3 × 3 mm, and 6 × 6, but may be larger or smaller than this. The shape does not have to be square, for example, 2 × 3 mm. The cathode can be directly contacted by a bump electrode from the back surface portion of the bulk semiconductor substrate, for example.

  The detector according to the above-described embodiment includes a wiring board, a plurality of semiconductor chips that are two-dimensionally spaced from each other, and disposed between the semiconductor chip and the wiring board. A first and second bump electrode arranged, wherein each of the semiconductor chips includes a semiconductor substrate having a plurality of photodetection units arranged in a two-dimensional manner; and An insulating layer formed on the surface; a common electrode disposed on the insulating layer; a readout wiring for electrically connecting the quenching resistance of each of the light detection units and the common electrode; and the common electrode A through electrode extending to the back surface of the semiconductor substrate through a through hole of the semiconductor substrate, and each of the light detection portions includes a first semiconductor region of a first conductivity type, and the first Configure the pn junction with the semiconductor region, An APD having a second semiconductor region of the second conductivity type that acts, and the quenching resistor electrically connected to the second semiconductor region of the APD, wherein the first bump electrode is the through electrode And the wiring substrate, and the second bump electrode electrically connects the first semiconductor region of the APD and the wiring substrate.

  A bias voltage that operates in a Geiger mode is applied to both ends of an APD (avalanche photodiode) included in each light detection unit via first and second bump electrodes. Carriers generated in a plurality of APDs by the incidence of light (energy rays) flow to the common electrode on the semiconductor substrate through the respective quenching resistors, and pass from the common electrode through the through electrode and the first bump electrode. It reaches the wiring board and is taken out to the outside.

  Since the APD having this structure has a carrier transmission path shortening structure using a through electrode or the like, the wiring resistance is reduced. Therefore, the transmission speed of the carrier from the APD, that is, the time resolution is improved. When a plurality of photons are incident on a single semiconductor chip having a plurality of APDs, the time resolution is improved, so that more accurate photon detection can be performed. In addition, in another semiconductor chip, due to causes such as manufacturing variation error, it is not guaranteed that the same time resolution is achieved, but at the time of assembly, select a semiconductor chip with a product characteristic within a certain range, Bonding to the wiring board via the bump electrodes reduces the characteristic variation for each semiconductor chip.

  Since the two-dimensionally arranged semiconductor chips are separated from each other, the light incident on a specific semiconductor chip leaks to other semiconductor chips and the influence of crosstalk is suppressed. The gap can alleviate the influence of the warpage of the wiring board caused by the expansion / contraction of the wiring board on the semiconductor chip. That is, characteristics such as time resolution, crosstalk, and resistance to temperature change as a whole detector are remarkably improved.

  In the detector according to the above-described embodiment, each of the light detection units includes a surface electrode that is electrically connected to the second semiconductor region and surrounds the second semiconductor region along an outer edge thereof. ing.

  In the detector according to the above-described embodiment, carriers generated in response to the incidence of light on the first and second semiconductor regions sequentially pass through the surface electrode, quenching resistor, and readout wiring from the second semiconductor region. To the common electrode. The surface electrode can generate a constant electric field at the outer edge of the second semiconductor region, and can improve the output stability of the APD.

  In the detector according to the above-described embodiment, when the plane including the surface of the second semiconductor region is a reference plane, the distance from the reference plane to the readout wiring is from the reference plane to the surface electrode. It is larger than the distance, and the readout wiring is located between the adjacent APDs. Since the readout wiring is formed in an upper layer than the surface electrode, the spatial restriction by the surface electrode is released, and the width and the like can be widened. Therefore, the time constant is reduced and the signal readout speed is increased. Can be improved.

  In the detector according to the above-described embodiment, the first contact electrode that contacts the second semiconductor region and a material different from the first contact electrode are disposed at a position overlapping the first contact electrode, A second contact electrode in contact with the first contact electrode, and the quenching resistance is continuous with the second contact electrode. Carriers generated in the pn junction by the incidence of photons flow to the quenching resistance via the first contact electrode and the second contact electrode, and via the readout wiring, common electrode, and through electrode connected to the quenching resistance, It reaches the wiring board.

  Further, in the detector according to the above-described embodiment, the space required for connecting the quenching resistor and the first contact electrode can be minimized by arranging the second contact electrode at a position overlapping the first contact electrode. it can. Of course, the first contact electrode and the second contact electrode are inevitably not on the same plane but have different height positions, and the quenching resistance continuously extends from the second contact electrode. As a result, wiring in the light detection unit can be omitted, and the aperture ratio of the light detection unit can be significantly increased.

  In the detector according to the above-described embodiment, it is preferable that the second contact electrode and the quenching resistor include SiCr. Since SiCr has a high light transmittance, even if a quenching resistance exists in the light detection unit, an incident photon passes through the quenching resistance, so that an effective aperture ratio can be increased.

  DESCRIPTION OF SYMBOLS 1Na, 1Nb ... Main surface, 12 ... 1st semiconductor region, 14 (13) ... 2nd semiconductor region, BE, B2 ... Bump electrode, E3 ... Common electrode, PDA ... Photodiode array, R1 ... Quenching resistance, TE ... Through electrode, 20 ... wiring board.

Claims (5)

A detector comprising first and second bump electrodes disposed between a semiconductor chip and a wiring board,
The semiconductor chip is
A semiconductor substrate having a plurality of photodetectors arranged two-dimensionally;
An insulating layer formed on the surface of the semiconductor substrate;
With
Each of the light detection units includes a quenching resistor,
The quenching resistor is disposed on the insulating layer;
The quenching resistor is electrically connected to the through electrode extending on the back surface of the semiconductor substrate through the through hole of the semiconductor substrate,
Each of the light detection units is
A first conductivity type first semiconductor region, and an APD that forms a pn junction with the first semiconductor region and includes a second conductivity type second semiconductor region that outputs carriers, and operates in Geiger mode ;
The quenching resistor electrically connected in series to the second semiconductor region of the APD;
With
The first bump electrode electrically connects the through electrode and the wiring board,
The second bump electrode electrically connects the first semiconductor region of the APD and the wiring board,
The quenching resistor comprises SiCr;
A detector characterized by that.   The detector according to claim 1, wherein a scintillator is positioned on the surface of the semiconductor chip via an insulator.   The said photodetection part is provided with the surface electrode which is electrically connected to the said 2nd semiconductor region, and surrounds the said 2nd semiconductor region along the outer edge. The detector described. A cradle,
A gantry having an opening in which the cradle is located,
A PET apparatus comprising a plurality of the detectors according to claim 1 arranged so as to surround an opening of the gantry. A cradle,
A gantry having an opening in which the cradle is located and having an X-ray source for emitting X-rays in the opening;
With
An X-ray CT apparatus comprising a plurality of detectors according to any one of claims 1 to 3 arranged at a position where X-rays from the X-ray source are incident.