JP6123150B2 - Method for evaluating silicon wafer processing amount and method for manufacturing silicon wafer - Google Patents

Description

  The present invention relates to a silicon wafer processing amount evaluation method and an evaluation silicon wafer, and in particular, a silicon wafer processing amount evaluation method for highly accurately evaluating a processing amount in processing for reducing the thickness of a silicon wafer, and an evaluation provided for this method. The present invention relates to a silicon wafer for industrial use.

  In general, for silicon wafers, single crystal silicon is grown by the Czochralski method (CZ method), etc., the silicon single crystal is cut into blocks, and then sliced thinly, and then surface grinding (lapping), etching, and mirror polishing. (Polishing) It is obtained by final cleaning after the process. After that, various quality inspections are performed and if no abnormality is confirmed, the product is shipped as a product.

  In recent years, the diameter of a silicon wafer has been increased and the devices formed on the silicon wafer have been miniaturized, and the demand for high flatness of the wafer surface has become increasingly severe. Therefore, for large-diameter silicon wafers having a diameter exceeding 200 mm, the wafer is sandwiched between upper and lower surface plates to which a polishing cloth is applied as a rough polishing process in the polishing step described above. It is common to perform double-side polishing (DSP) processing that performs polishing at the same time, and development of a polishing processing technique that enables such high flatness of the wafer surface is being promoted.

  With the development of such polishing technology, it has become important to establish a method that can accurately evaluate the amount of polishing in the polishing process. In Patent Document 1, in order to evaluate the polishing amount in the double-side polishing process, a recess for etching is formed on the front and back surfaces of the silicon wafer to produce an evaluation wafer, and from the depth change of the recess before and after the double-side polishing process. A technique for evaluating the polishing amount in the double-side polishing process has been proposed.

JP 2009-266896 A

However, in the technique of Patent Document 1, it is difficult to uniformly form recesses having the same depth in the surface of the silicon wafer by the etching process, and as a result, variation in the measurement result of the polishing amount increases.
In general, the wafer thickness after the polishing process is measured by a capacitance type flatness measuring device (WaferSight) or the like, but it is difficult to accurately evaluate the polishing amount with an accuracy of 1 μm or less. It is.
Furthermore, since a recess that does not exist in the actual product wafer is formed on the surface of the evaluation wafer, the polishing pressure applied to the evaluation wafer surface when performing double-side polishing is different from that of the product wafer. Since the evaluation result of the wafer polishing amount obtained using the evaluation wafer is different from that of the actual product, it cannot be reflected in the double-side polishing process in the wafer manufacturing process.

  Accordingly, an object of the present invention is to provide a silicon wafer processing amount evaluation method capable of highly accurately evaluating a processing amount in processing for reducing the thickness of a wafer (hereinafter referred to as “thickening processing”), and an evaluation for use in this method. It is to provide a silicon wafer.

  As a result of intensive studies on how to solve the above problems, the inventors have utilized an optical thickness measuring means capable of measuring the thickness of a measurement object with high accuracy, and silicon capable of measuring the thickness by the optical thickness measuring means. A silicon wafer for evaluation in which a layer is formed on the silicon wafer, and the thickness before and after the thickness reduction processing applied to the silicon layer of the silicon wafer for evaluation is measured by the optical thickness measuring means, Based on the thickness measurement result, it was found that the amount of processing in the thickness reduction processing can be evaluated with high accuracy, and the present invention has been completed.

That is, the gist configuration of the present invention is as follows.
(1) In evaluating the amount of processing in the thickness reduction processing applied to the silicon wafer, an evaluation silicon wafer in which a silicon layer capable of measuring the thickness by an optical thickness measuring means is formed on the front and back surfaces of the silicon wafer, Next, after the thickness of the silicon layer of the silicon wafer for evaluation is measured by the optical thickness measuring means, the thickness reduction processing is performed on the silicon layer, and then the thickness of the silicon layer after the thickness reduction processing is performed. was measured by the optical thickness measuring unit, to evaluate the processing amount in processing the reduced thickness reduction process based on the thickness measurement results before and after with respect to the silicon layer, the silicon layer is Ri epitaxial layer der, the silicon measurements of thickness of the layer, and carrying out separately for each of the front and back surfaces of the evaluation silicon wafer sheet Evaluation method of con wafer processing amount.

(2) The silicon wafer processing amount evaluation method according to (1) , wherein the processing process is a polishing process or an etching process.

(3) The method for evaluating a processing amount of a silicon wafer according to either (1) or (2) , wherein the processing is a double-side polishing process.

(4) the optical thickness measuring unit is an FTIR method or the spectroscopic ellipsometer method, wherein (1) to (3) any method of evaluating a silicon wafer processing amount according to one of.

(5) the thickness of the reduced thickness reduction pretreatment of the silicon layer is larger than the processing amount, the (1) to (4) any method of evaluating a silicon wafer processing amount according to one of.

(6) Evaluation of silicon wafer processing amount as described in any one of said (1)- (5) whose dopant concentration in the silicon wafer of the said silicon wafer for evaluation is higher than the dopant concentration in the said silicon layer. Method.

(7) The dopant concentration in the silicon wafer of the silicon wafer for evaluation is adjusted to a range of 1 × 10 ¹⁸ atoms / cm ³ or more, and the dopant concentration in the silicon layer is in a range of 1 × 10 ¹⁷ atoms / cm ³ or less. The method for evaluating the amount of silicon wafer processing according to any one of (1) to (6) , wherein

(8) The processing amount of the silicon layer on the front surface and the back surface of the silicon wafer for evaluation is evaluated by the method for evaluating the processing amount of the silicon wafer described in the above (1) to (7). If there is a difference in the processing amount, the processing conditions of the thickness reduction processing are adjusted, and the thickness reduction processing is performed on the surface of the silicon wafer under the processing conditions that offset the difference. A method for producing a silicon wafer.

According to the present invention, since the thickness of the silicon layer before and after processing in the silicon wafer for evaluation can be determined with high accuracy, in the thickness reduction processing based on the thickness measurement result of the silicon layer before and after the thickness reduction processing. The processing amount can be obtained with high accuracy.
In addition, since the evaluation silicon wafer has a silicon layer similar to the surface layer of the actual product wafer, the environment where the surface of the evaluation silicon wafer is placed in the thickness reduction processing is almost the same as that of the actual product wafer. Be the same. As a result, it is possible to accurately and easily perform the processing amount evaluation corresponding to each thickness reduction processing type, and the evaluation result of the wafer processing amount obtained using the evaluation silicon wafer is reduced in the actual wafer manufacturing process. It can be reflected in the processing step.
Furthermore, by producing and using an evaluation silicon wafer having a silicon layer on the front and back surfaces of the silicon wafer, the polishing amount in the double-side polishing process can be individually evaluated for each of the front surface and the back surface.

It is a figure which shows the silicon wafer for evaluation by this invention. It is a figure explaining the thickness measurement principle of FTIR (Fourier Transform Infrared Spectroscopy) method. It is a flowchart of the evaluation method of the silicon wafer processing amount by this invention. It is a figure which shows an example of a double-side polish apparatus. It is a figure which shows (a) thickness of the epitaxial layer before and behind single-side polishing process, and (b) polish amount. It is a figure which shows the thickness of the epitaxial layer of the (a) surface before and behind double-sided grinding | polishing process, (b) the thickness of the epitaxial layer of a back surface, (c) polishing amount in the surface, and (d) polishing amount in the back surface.

(Evaluation silicon wafer)
Embodiments of the present invention will be described below with reference to the drawings. In describing the evaluation method of the processing amount of the silicon wafer of the present invention, first, the evaluation silicon wafer used in the evaluation method of the present invention will be described. FIG. 1A shows a silicon wafer for evaluation according to the present invention. This evaluation silicon wafer 1 is for evaluating a processing amount in a thinning process performed on a silicon wafer, and has a thickness larger than the above processing amount on the surface of the silicon wafer 11, and is an optical type. It is important to have the silicon layer 12 capable of measuring the thickness by the thickness measuring means.

In the present invention, the “thinning process” means all processes that mechanically or chemically reduce the thickness of the wafer, such as polishing processes such as double-sided polishing processes, etching processes, and cleaning processes in the manufacturing process of silicon wafers. “Processing amount” means a thickness reduction by these thickness reduction processing.
“Optical thickness measuring means” means a means that allows light to be incident on a silicon surface and measure the thickness based on information of the reflected light. Specifically, Fourier transform infrared spectroscopy is used. (Fourier Transform Infrared Spectroscopy, FTIR) method or spectroscopic ellipsometer method.

  FIG. 2 shows the principle of measuring the thickness of the silicon layer 12 by the FTIR method. In the FTIR method, the surface S2 of the silicon layer 12 of the evaluation silicon wafer 1 is irradiated with incident light L1 that is infrared light, and reflected by the surface S2 of the silicon layer 12, and the silicon wafer 11 and the silicon layer 12 are reflected. The thickness of the silicon layer 12 is measured by causing the reflected light L3 reflected at the interface (ie, the surface of the silicon wafer 11) S1 to enter a detector (not shown) and measuring the optical path difference between the reflected lights L2 and L3. Can be obtained.

  On the other hand, in the spectroscopic ellipsometer method, incident light with a known polarization state is irradiated obliquely onto the surface of the film to be measured, and the polarization state of the reflected polarized light reflected / interfered within the film surface or in the film is acquired and subjected to polarization analysis. This is a method for measuring the thickness of the measurement target film. In the semiconductor field, it is mainly used for measuring the thickness of thin films such as oxide films, nitride films, and photoresist films, and is suitable for measuring thicknesses of 1 μm or less. Therefore, the spectroscopic ellipsometer method is suitable for evaluation when an SOI wafer having a silicon active layer thickness of 1 μm or less is used as an evaluation wafer. In addition, when the thickness of the active layer exceeds 5 μm, measurement error may be caused.

  By using these measurement methods, the thickness of the measurement object can be measured with high accuracy in a non-contact and non-destructive manner based on the optical principle. Therefore, by using the measurement object as the silicon layer 12, It becomes possible to evaluate the processing amount in the thickness reduction processing applied to the silicon layer 12 with high accuracy.

  Here, an epitaxial wafer or an SOI wafer is used as the evaluation silicon wafer 1, and the epitaxial layer in the epitaxial wafer or the SOI layer in the SOI wafer corresponds to the silicon layer 12. Since the FTIR method can measure a thickness of about several tens of micrometers, it is suitable when an epitaxial wafer is used as an evaluation silicon wafer. The spectroscopic ellipsometer method is suitable when an SOI wafer having an SOI layer thickness of 1 μm or less is used as the evaluation silicon wafer 1 because a measurement error may be caused when the thickness of the measurement object exceeds 5 μm. By applying the optical thickness measuring means in this way, the thickness of the epitaxial layer or the SOI layer can be accurately grasped, and the processing amount in the thickness reduction processing applied to the silicon layer 12 can be accurately measured.

  Further, the evaluation silicon wafer 1 shown in FIG. 1A has the silicon layer 12 only on the surface, but the silicon layer 12 is formed on the front and back surfaces of the silicon wafer 11 as shown in FIG. It can also be set as the evaluation silicon wafer 2 formed in the above. By using this silicon wafer for evaluation 2, the polishing amount in the above-described double-side polishing process can be individually evaluated for each of the front surface and the back surface. As the silicon 2 for evaluation, an epitaxial wafer in which an epitaxial layer is formed on the front and back surfaces of a silicon wafer, or an SOI wafer in which an SOI layer is formed on the front and back surfaces of the silicon wafer by the SIMOX method can be used.

  In addition, when using an epitaxial wafer as the silicon wafer for evaluation 2, if the difference in resistivity between the silicon wafer 11 and the silicon layer 12 is small, it becomes difficult to measure the thickness of the silicon layer 12 as an epitaxial layer by the FTIR method. It is effective to make the dopant concentration of the silicon wafer 11 higher than that of the silicon layer 12. Hereinafter, each configuration of the evaluation silicon wafer 1 (and 2) will be described.

  The silicon wafer 11 is used as a substrate for the evaluation silicon wafer 1 (or 2). For example, a silicon single crystal grown by the CZ method or the like is sliced, and finally polished through a lapping process, an etching process, and a polishing process. A wafer. The silicon wafer 11 is preferably polished at least on the surface on which the silicon layer 12 is formed. When it is desired to evaluate the polishing amount of the front and back surfaces in the double-side polishing processing, the front and back surfaces of the wafer are mirror-polished. A polished wafer to which is applied can be used.

  The silicon layer 12 is formed on the surface of the silicon wafer 11 and is a layer that is subjected to processing in the thickness reduction processing. As this silicon layer 12, an epitaxial layer formed on a polished wafer or an SOI layer in an SOI (Silicon On Insulator) wafer formed by a bonding method or a SIMOX (Separation by IMplanted Oxygen) method is suitable.

As described above, in order to be able to measure the thickness of the silicon layer 12, a part of the light incident on the surface of the silicon layer 12 is reflected by the surface of the silicon layer 12, and the remaining incident light is reflected by the silicon layer 12. It is necessary to reflect the incident light L1 at the interface between the silicon wafer 11 and the silicon layer 12, and in order to satisfy this requirement, a dopant is added to the silicon wafer 11 and the silicon layer 12, and the silicon wafer 11 It is effective to increase the dopant concentration of the silicon layer 12 higher than that of the silicon layer 12.
Therefore, a dopant can be added to the silicon wafer 11 and the silicon layer 12. The kind of the dopant is not particularly limited, and boron, phosphorus, arsenic, antimony, or the like can be used.

Here, it is preferable that the dopant concentration of the silicon wafer 11 is adjusted to a range of 1 × 10 ¹⁸ atoms / cm ³ or more. Thereby, the light transmitted through the silicon layer 12 can be effectively reflected at the interface S1 between the silicon wafer 11 and the silicon layer 12. More preferably, it is 1 × 10 ¹⁸ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less.

On the other hand, the dopant concentration of the silicon layer 12 needs to be lower than that of the silicon wafer 11 and is preferably adjusted to a range of 1 × 10 ¹⁷ atoms / cm ³ or less. As a result, it is possible to effectively reflect the remainder of the incident light L1 on the surface S2 of the silicon layer 12 while transmitting a part of the incident light L1 into the silicon layer 12. More preferably, it is 1 × 10 ¹⁵ atoms / cm ³ or more and 1 × 10 ¹⁷ atoms / cm ³ or less.

  Moreover, since the evaluation of the processing amount in the thickness reduction processing is performed based on the thickness measurement result of the silicon layer 12 before and after the thickness reduction processing, the thickness of the silicon layer 12 is larger than the processing amount in the thickness reduction processing. is necessary. Since the processing amount in the actual thickness reduction processing is about 0.5 μm or more and 20 μm or less, the thickness of the silicon layer 12 is preferably 0.5 μm or more and 20 μm or less.

  Further, when the silicon wafer for evaluation is considered to be recycled as a product silicon wafer, the silicon wafer 11 used as the substrate is polished only by removing the silicon layer 12 formed on the evaluation wafer 1 or 2. A polished wafer can be obtained by performing the etching process and the polishing process on the silicon wafer 11 that has been recycled as a material of the wafer and processed after the thickness reduction process.

Using the silicon wafer for evaluation described above, the silicon layer of the silicon wafer for evaluation can be subjected to thickness reduction processing, and the thickness of the silicon layer before and after processing can be measured with high accuracy by optical thickness means. Based on the thickness measurement results of the silicon layer before and after the thickness reduction processing, the processing amount in the thickness reduction processing can be evaluated with high accuracy.
In addition, since the evaluation silicon wafer has a silicon layer similar to the surface layer of the actual product wafer, the environment where the surface of the evaluation silicon wafer is placed in the thickness reduction processing is almost the same as that of the actual product wafer. Be the same. As a result, it is possible to accurately and easily perform the processing amount evaluation corresponding to each thickness reduction processing type, and the evaluation result of the wafer processing amount obtained using the evaluation silicon wafer is reduced in the actual wafer manufacturing process. It can be reflected in the processing step.
Furthermore, by producing and using an evaluation silicon wafer having a silicon layer on the front and back surfaces of the silicon wafer, the polishing amount in the double-side polishing process can be individually evaluated for each of the front surface and the back surface.

(Method for evaluating the amount of silicon wafer processing)
Next, the silicon wafer processing amount evaluation method according to the present invention will be described. FIG. 3 is a flowchart of the silicon wafer processing amount evaluation method according to the present invention. The silicon wafer processing amount evaluation method according to the present invention produces an evaluation silicon wafer 1 in which a silicon layer 12 capable of thickness measurement by an optical thickness measuring means is formed on the surface of a silicon wafer 11 (step S1). Next, after the thickness of the silicon layer 12 of the evaluation silicon wafer 1 is measured by the optical thickness measuring means (step S2), the silicon layer 12 is subjected to a thickness reduction process (step S3), and then the thickness reduction process is performed. The thickness of the subsequent silicon layer 12 is measured by optical thickness measuring means (step S4), and the processing amount in the thickness reduction processing is evaluated based on the thickness measurement results before and after the processing on the silicon layer 12 (step S5). Hereinafter, each of the above steps will be described.

  First, in step S1, an evaluation silicon wafer 1 (or 2) is produced. As described above, the silicon wafer for evaluation 1 has the silicon layer 12 on the silicon wafer 11 that can be measured for thickness by optical thickness measuring means. The evaluation silicon wafer 1 can be an epitaxial wafer having a silicon epitaxial layer on the silicon wafer, or an SOI wafer in which an insulating oxide film and an SOI layer are sequentially provided on the silicon wafer. Hereinafter, a method for manufacturing an epitaxial wafer and an SOI wafer will be briefly described.

  Here, when an epitaxial wafer is used as the silicon wafer 1 for evaluation, for example, the silicon wafer 11 is introduced into a single-phase epitaxial growth furnace, the silicon wafer 11 is heated to about 1200 ° C., trichlorosilane, Diborane as a dopant gas is supplied onto the silicon wafer 11 together with hydrogen gas as a carrier gas for a predetermined time. Thereby, an epitaxial layer is formed on the silicon wafer 11, and an epitaxial wafer can be obtained. The epitaxial wafer thus obtained is used as an evaluation silicon wafer 1.

The kind of dopant is not particularly limited, and boron, phosphorus, arsenic, antimony, or the like can be used. As the dopant gas, for example, diborane (B ₂ H ₆ ) or phosphine (PH ₃ ) containing these atoms can be used. Can be used.

Here, in order to enable measurement of the thickness of the epitaxial layer by the FTIR method or the spectroscopic ellipsometer method, it is necessary to adjust the dopant gas concentration and flow rate so that the dopant concentration of the epitaxial layer is smaller than that of the silicon wafer 11. It is preferable to adjust to 10 ¹⁸ atoms / cm ³ or more. Thereby, the light transmitted through the silicon layer 12 is reliably reflected at the interface S1 between the silicon wafer 11 and the silicon layer 12. More preferably, it is 1 × 10 ¹⁸ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less.

The dopant concentration of the epitaxial layer is preferably 1 × 10 ¹⁷ atoms / cm ³ or less, more preferably 1 × 10 ¹⁵ atoms / cm ³ or more and 1 × 10 ¹⁷ atoms / cm ³ or less. As a result, a part of the incident light L1 is transmitted through the silicon layer 12, and the remaining incident light L1 is reliably reflected by the surface S2 of the silicon layer 12.

  Furthermore, since the processing amount in the thickness reduction processing in the actual wafer manufacturing process is about 0.5 μm or more and 20 μm or less, the thickness of the epitaxial layer to be grown is preferably 0.5 μm or more and 20 μm or less.

  Furthermore, when evaluating the polishing amount in the double-side polishing process, after forming an epitaxial layer on the surface of the silicon wafer 11, the wafer 11 is turned upside down to form an epitaxial layer on the back surface of the wafer 11. An evaluation silicon wafer 2 can be obtained.

  Thus, an epitaxial wafer as an evaluation silicon wafer can be produced.

  On the other hand, an SOI wafer can also be used as the silicon wafer for evaluation. As a method for manufacturing this SOI wafer, there are a bonding method and a SIMOX (Separation by IM planted Oxygen) method. In the bonding method, the surface-oxidized silicon support substrate is bonded to the active substrate for manufacturing the device, and heat treatment is performed at a high temperature of about 1200 ° C. to bond the oxide film of the support substrate and the silicon of the active substrate. An SOI wafer is obtained.

On the other hand, in the SIMOX method, oxygen ions are implanted into a predetermined depth of the silicon wafer 11 by an ion implanter, and then an oxide layer is formed by high-temperature heat treatment, and the crystallinity of the SOI layer formed on the oxide layer is measured. By recovering the above, an SOI wafer can be obtained.
In this way, an SOI wafer as a silicon wafer for evaluation can be manufactured.

  Further, instead of using the evaluation silicon wafer intentionally produced as described above, an epitaxial wafer or SOI wafer manufactured as a product wafer and becoming a non-standard product can also be used as the evaluation silicon wafer.

Next, in step S2, measured by the optical thickness measuring unit and the thickness T _i of the previous thickness reduction processing of the silicon layer 12. In the present invention, FTIR method or spectroscopic ellipsometer method is used as the optical thickness measuring means. By using these measurement methods according to the above-described principle, the thickness of the silicon layer 12 of the evaluation silicon wafer 1 can be measured with high accuracy. The thickness measurement of the silicon layer 12 is performed at a predetermined position of the evaluation silicon wafer 1 or 2, but by measuring the thickness over the entire wafer surface, the thickness of the silicon layer 12 and the processing amount within the wafer surface are measured. Can be obtained.

  Subsequently, in step S3, the silicon layer 12 is subjected to thickness reduction processing. Here, the thickness reduction processing means all processes for reducing the thickness of the wafer, such as a polishing process such as a double-sided polishing process in an actual wafer manufacturing process, an etching process, and a cleaning process. Hereinafter, a case where a double-side polishing process and an etching process are performed will be described as an example of the polishing process.

  FIG. 4 is a diagram illustrating an example of the double-side polishing apparatus 100. First, the evaluation silicon wafer 2 fitted in the small hole 25 of the carrier 26 is sandwiched between the upper surface plate 21 to which the upper polishing cloth 23 is fixed and the lower surface plate 22 to which the lower polishing cloth 24 is fixed. The lower surface plate 22 is rotated in directions opposite to each other, and the carrier 26 is rotated in the direction of the arrow using the center gear 27. In this way, both surfaces of the evaluation silicon wafer 2 can be polished simultaneously. When performing double-side polishing, the polishing amount is set, and the polishing pressure, the polishing time, the rotation speed of the surface plate, the shape of the carrier plate, etc. are adjusted so that the polishing amount is achieved.

  Further, the evaluation silicon wafer 2 can be applied to the evaluation of the etching amount performed for the purpose of removing the processing strain after the lapping process, the evaluation of the etching amount by the cleaning performed for the purpose of removing the particles after the final polishing, and the like.

The etching process includes acid etching or alkali etching, and may be appropriately selected according to the purpose. Acid etching does not have selective etching properties with respect to a silicon wafer, has a small surface roughness, improves micro shape accuracy, and has an advantage of high etching efficiency. As an etching solution for this acid etching, an etching solution using a ternary element obtained by diluting a mixed acid of hydrofluoric acid (HF) and nitric acid (HNO ₃ ) with water (H ₂ O) or acetic acid (CH ₃ COOH) is mainly used. Yes.

On the other hand, the alkali etching is improved excellent macro shape precision flatness, and less metal contamination, there is a harmful by-product of the problems and handling also no benefit risk, such as of the NO _x in the acid etching. An aqueous solution of potassium hydroxide (KOH) or sodium hydroxide (NaOH) is used as an etching solution for this alkaline etching.

  When performing these etching processes, the etching amount is set, and the selection of the etching solution, the concentration of the etching solution, the processing time, and the like are adjusted so that the etching amount is achieved.

Subsequently, the thickness _Tf of the silicon layer 12 after the thickness reduction processing is measured by an optical thickness measuring unit. This measurement is performed at the same position where the thickness is measured in step S2, and when measurement is performed at a plurality of positions within the wafer surface in step S2, measurement is performed at each position.

Finally, the processing amount in the thickness reduction processing is evaluated based on the thickness measurement results of the silicon layer 12 before and after the thickness reduction processing. In steps S2 and S4 described above, since the thicknesses T _i and T _f of the silicon layer 12 before and after the thickness reduction processing are measured, the amount of processing at the measurement position can be determined by obtaining the difference T _f −T _i. Can be evaluated. Here, in the case where the thickness measurement in steps S2 and S4 is performed over the entire area within the wafer surface, a processing surface in-wafer surface profile can be obtained.

  Further, since the evaluation silicon wafer 1 (or 2) has a silicon layer 12 similar to the surface layer of the actual product wafer, the surface of the evaluation silicon wafer 1 (or 2) is placed in the thickness reduction processing. The environment is almost the same as the actual product wafer. Thereby, the processing amount evaluation corresponding to each thickness reduction processing type can be performed accurately and simply, and the evaluation result of the wafer processing amount obtained using the evaluation silicon wafer 1 (or 2) is obtained as an actual wafer. This can be reflected in the thickness reduction processing step of the manufacturing process.

  Furthermore, the processing accuracy can be improved by feeding back the evaluation of the processing amount thus obtained to the processing conditions of the thickness reduction processing for the silicon layer 12 in step S3. For example, the double-side polishing process is performed in step S3, and if there is a difference between the set polishing amount and the polishing amount evaluated in step S5, the difference is offset by adjusting the polishing conditions of the double-side polishing process. be able to. Specifically, when the thickness is uniformly adjusted in the wafer surface, the polishing pressure and the polishing time are adjusted, and the polishing amount in the wafer surface is partially adjusted, such as the wafer center portion and the peripheral portion. What is necessary is just to adjust the rotation speed of a surface plate and to change the shape of a carrier plate.

  Thus, the thickness of the silicon layer of the evaluation silicon wafer is reduced, and the thickness of the silicon layer before and after the processing can be measured with high accuracy by the optical thickness means. Based on the thickness measurement result of the silicon layer, the processing amount in the thickness reduction processing can be evaluated with high accuracy.

(Invention Example 1)
Examples of the present invention will be described below.
The amount of wafer processing was evaluated for a single-side polishing apparatus that performed 10 batches of single-side polishing. First, an epitaxial wafer was used as the silicon wafer 1 for evaluation, a single-side polishing process was adopted as the processing process, and the polishing amount of the silicon wafer was evaluated according to steps S1 to S5 shown in FIG. First, as a base wafer for an epitaxial wafer, a silicon wafer 11 containing 300 mm in diameter and 1.3 × 10 ¹⁹ atoms / cm ³ of boron as a dopant and having mirror-polished front and back surfaces was prepared. This silicon wafer 11 was introduced into a single wafer epitaxial growth furnace, and a silicon epitaxial layer as a silicon layer 12 containing 1.008 × 10 ¹⁶ atoms / cm ³ of boron as a dopant was formed on the silicon wafer 11. The silicon wafer for evaluation 1 shown in (a) was produced (step S1). Next, the thickness of the epitaxial layer of the silicon wafer for evaluation 1 was measured by the FTIR method. This measurement was performed at 21 points along the wafer radial direction from one point on the peripheral edge of the wafer to another point on the peripheral edge (step S2). Subsequently, the evaluation silicon wafer 1 was introduced into a single-side polishing apparatus, and single-side polishing processing as finish polishing was performed on the epitaxial layer of the evaluation silicon wafer 1 (step S3). That is, the wafer back side is attached to and supported by the lower surface of the polishing head (upper surface plate), and then the polishing head and lower surface plate are rotated in opposite directions to push the wafer surface side against the suede polishing cloth attached to the lower surface plate. Then, the polishing time was adjusted so that the amount of polishing removal at the center of the wafer was 0.2 μm. At that time, a polishing liquid was supplied to the polishing cloth, and an alkaline aqueous solution mainly composed of KOH containing fine colloidal silica as abrasive grains was used as the polishing liquid. Thereafter, the thickness of the epitaxial layer after the single-side polishing treatment was measured by the FTIR method (step S4). At that time, the thickness was measured at 21 points along the wafer radial direction from one point on the peripheral edge of the wafer to another point on the peripheral edge. FIG. 5A shows the thickness of the epitaxial layer in the wafer surface before and after the single-side polishing treatment. Finally, the amount of polishing in the wafer surface was determined from the change in the thickness of the epitaxial layer before and after the single-side polishing treatment. The obtained polishing amount is shown in FIG.

  FIG. 5A shows that the thickness of the epitaxial layer is about 2.95 μm before the single-side polishing treatment, whereas the thickness is reduced to about 2.7 μm after the single-side polishing treatment. Looking at the polishing amount obtained from the thickness of the epitaxial layer before and after the single-side polishing treatment, as shown in FIG. 5B, the polishing amount in the single-side polishing processing is larger at the peripheral portion than at the center portion of the wafer. I understand. From this result, when performing single-side polishing to produce a product wafer using the single-side polishing apparatus, the polishing conditions (pressure, surface plate rotation speed, etc.) are reduced so as to reduce the polishing amount of the wafer peripheral portion. It can be seen that the adjustment should be made.

(Invention Example 2)
The wafer processing amount was evaluated with respect to a double-side polishing apparatus that performed 10 batches of single-side polishing. As an evaluation silicon wafer 2, except that an epitaxial film was formed on the front and back surfaces, an epitaxial wafer having the same conditions as in Invention Example 1 was used, and a double-sided polishing process was adopted as a processing treatment. The silicon wafer polishing amount was evaluated according to the indicated steps S1 to S5. Here, the thickness measurement of the epitaxial layer in steps S2 and S4 and the evaluation of the polishing amount in step S5 were performed on the front and back surfaces of the wafer 2. In step S2, the measurement was performed at 11 points along the wafer radial direction from one point on the peripheral edge of the wafer to another point on the peripheral edge. Furthermore, the double-side polishing process in step S3 was performed as follows using a sun gear type double-side polishing apparatus. That is, first, the silicon wafer 2 for evaluation is loaded in the carrier plate, the wafer is sandwiched between the upper and lower surface plates to which the polyurethane polishing cloth is affixed, and the upper and lower surface plates are rotated in opposite directions to remove the polishing at the center of the wafer. The polishing time was adjusted so that the allowance was 0.2 μm, and the front and back surfaces of the wafer 2 were simultaneously polished. Here, a polishing liquid was supplied to the polishing cloth, and as the polishing liquid, an alkaline aqueous solution mainly composed of KOH containing fine colloidal silica as abrasive grains was used. The other processing is the same as that of Invention Example 1. The thickness of the epitaxial layer before and after the double-side polishing treatment is shown in FIGS. 6 (a) and 6 (b). Here, (a) is the result on the front side, and (b) is the result on the back side. The polishing amount in the double-side polishing process is shown in FIGS. 6 (c) and 6 (d). Here, (c) is the result on the front side, and (d) is the result on the back side.

6A and 6B, the polishing amount on the surface is about 0.25 to 0.30 μm, and a polishing amount close to the set value is achieved, but the polishing amount on the back surface is 0.04 to 0. .10, which is considerably smaller than the set value, and it can be seen that the polishing amount is greatly different between the front surface and the back surface. Further, from FIGS. 6C and 6D, it can be seen that the polishing amount of the peripheral portion is larger than the central portion of the wafer on both the front surface and the back surface. From this result, it is sufficient to reduce the polishing amount on the front surface or increase the polishing amount on the back surface so that the polishing amount on the front surface and the back surface of the wafer are equal. Adjustment is effective. In addition, since the polishing amount of the peripheral portion is large on both the front and back surfaces, it is effective to adjust the rotation speed of the surface plate and the carrier plate.
Thus, it can be seen that the polishing amount in the double-side polishing treatment can be individually evaluated for each of the front surface and the back surface by using the evaluation silicon wafer having the epitaxial layer on the front and back surfaces of the silicon wafer.

1, 2 Silicon wafer for evaluation 11 Silicon wafer 12 Silicon layer 21 Upper surface plate 22 Lower surface plate 23 Upper polishing cloth 24 Lower polishing cloth 25 Small hole 26 Carrier 27 Central gear 100 Double-side polishing apparatus S1 Silicon wafer surface S2 Silicon layer surface L1 Incident light L2, L3 Reflected light

Claims (8)

In evaluating the processing amount in the thickness reduction processing applied to silicon wafers,
On the front and back surfaces of the silicon wafer, a silicon wafer for evaluation in which a silicon layer capable of measuring the thickness by an optical thickness measuring unit is formed,
Next, after measuring the thickness of the silicon layer of the silicon wafer for evaluation by the optical thickness measuring means, the thickness reduction processing is performed on the silicon layer,
Subsequently, the thickness of the silicon layer after the thickness reduction processing is measured by the optical thickness measuring means,
Evaluating the amount of processing in the thickness reduction processing based on the thickness measurement results before and after processing for the silicon layer,
The silicon layer is an epitaxial layer;
The method for evaluating the amount of silicon wafer processing, wherein the measurement of the thickness of the silicon layer is performed individually for each of the front surface and the back surface of the evaluation silicon wafer.   The silicon wafer processing amount evaluation method according to claim 1, wherein the processing processing is polishing processing or etching processing.   The silicon wafer processing amount evaluation method according to claim 1, wherein the processing process is a double-side polishing process.   The said optical thickness measurement means is an evaluation method of the silicon wafer processing amount as described in any one of Claims 1-3 which is a FTIR method or a spectroscopic ellipsometer method.   The silicon wafer processing amount evaluation method according to any one of claims 1 to 4, wherein a thickness of the silicon layer before the thickness reduction processing is larger than the processing amount.   The silicon wafer processing amount evaluation method according to any one of claims 1 to 5, wherein a dopant concentration in the silicon wafer of the evaluation silicon wafer is higher than a dopant concentration in the silicon layer. The dopant concentration in the silicon wafer of the silicon wafer for evaluation is adjusted to a range of 1 × 10 ¹⁸ atoms / cm ³ or more, and the dopant concentration in the silicon layer is adjusted to a range of 1 × 10 ¹⁷ atoms / cm ³ or less. The evaluation method of the silicon wafer processing amount as described in any one of Claims 1-6.   The processing amount of the silicon layer on the front surface and the back surface of the silicon wafer for evaluation is evaluated by the method for evaluating the processing amount of the silicon wafer according to claim 1, and there is a difference in the processing amount of the evaluated front surface and back surface In the case of performing the thickness reduction processing, the thickness reduction processing is performed on the surface of the silicon wafer under the processing conditions in which the difference is offset by adjusting the processing conditions of the thickness reduction processing. Wafer manufacturing method.

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