JP6107472B2 - Nonvolatile memory cell and nonvolatile memory including the nonvolatile memory cell - Google Patents

Description

  The present invention relates to a nonvolatile memory cell using a resistance variable element and a nonvolatile memory including the nonvolatile memory cell.

  In recent years, a resistance change type memory for storing data using a resistance change type element has attracted attention as a next-generation non-volatile memory in place of a flash memory or a DRAM that has become limited in miniaturization. Examples of the resistance change element include MRAM (Magnetoretic Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistance Random Access Memory). The thing that is. A memory using such a resistance variable element does not require a complicated process like a flash memory, is compatible with a standard logic process, is suitable for miniaturization, and operates at a low voltage. The future is promising.

  The element configuration, characteristics, and array configuration of a memory using this type of variable resistance element are disclosed in Non-Patent Document 1, for example. This non-patent document 1 relates to an MRAM, but discloses a memory cell having a simple configuration including one transistor and one resistance variable element. According to Non-Patent Document 1, this memory cell can be written and read at a low voltage of 1.2 V, the write current is 49 μA, and the memory cell from the high resistance state in which data “1” is stored. The read current is 10 μA, and the read current from the memory cell in the low resistance state in which data “0” is stored is 15 μA. Thus, low power consumption can be realized. Further, according to FIG. 1 of Non-Patent Document 1, it is likely that the write voltage to the memory cell can be lowered to about ± 0.6V.

  FIG. 16A and FIG. 16B are diagrams showing the configuration and operation of a memory cell using a typical MTJ (Magnetic Tunnel Junction) element as a resistance variable element. As shown in FIG. 16, the MTJ element includes a pinned layer having a constant magnetic direction, a tunnel barrier film, and a free layer whose magnetic direction changes. As shown in FIG. 16A, when a current in the direction from the free layer to the pinned layer is passed, the magnetization direction of the free layer becomes the same as that of the pinned layer, the MTJ element has a low resistance, and data “0” is stored. It becomes a state. Conversely, as shown in FIG. 16B, when a current in the direction from the pinned layer toward the free layer is passed, the magnetization direction of the free layer is opposite to that of the pinned layer, the MTJ element becomes high resistance, and data “1” "Is stored. When a memory cell is configured with such an MTJ element, a transistor Ts is connected in series with the MTJ element as a switch for selecting the MTJ element, as illustrated in FIGS. 16 (a) and 16 (b). Is done. FIG. 17 is a diagram showing an equivalent circuit of a memory cell constituted by MTJ elements. In FIG. 17, the pin layer side and the free layer side of the resistance variable element are indicated by arrows parallel to the resistance variable element (MTJ element) R1. More specifically, in FIG. 17, the original side of the arrow parallel to the resistance variable element R1 corresponds to the pinned layer side, and the tip side of the arrow corresponds to the free layer side.

  FIG. 18 is a diagram illustrating a cross-sectional structure of a memory array including memory cells as shown in FIGS. 16 (a) and 16 (b). In the example shown in FIG. 18, the selection transistor Ts shown in FIGS. 16A and 16B is formed on a semiconductor substrate. A selection voltage WL is applied to the gate of each transistor Ts. The source of the transistor Ts is connected to the second layer metal wiring 2M for supplying the write voltage BL via the through hole and the first layer metal wiring 1M. The drain of the transistor Ts is connected to the pin layer of the MTJ element through a through hole, and the free layer of the MTJ element is connected to the second layer metal wiring 2M for supplying the source voltage SL through the through hole. Has been.

  Patent Document 1 discloses a rewritable nonvolatile RAM using a resistance variable element. In the nonvolatile RAM of Patent Document 1, a phase change memory element is used as a resistance change element.

  FIG. 19 is a circuit diagram showing a configuration of a memory cell of the nonvolatile RAM disclosed in FIG. In FIG. 19, a flip-flop is constituted by an inverter composed of a P-channel transistor P0 and an N-channel transistor N0 and an inverter composed of a P-channel transistor P1 and an N-channel transistor N1. An output node S0 of the inverter composed of the P channel transistor P0 and the N channel transistor N0 is connected to the bit line BL0 via the N channel transistor Na0. The output node S1 of the inverter composed of the P channel transistor P1 and the N channel transistor N1 is connected to the bit line BL1 via the N channel transistor Na1. The selection voltage WL is applied to the N channel transistors Na0 and Na1. The above circuit is a normal SRAM memory cell. In the memory cell shown in FIG. 19, phase change memory elements Rr and Rm and an N-channel transistor Ns are added to the SRAM memory cell. Here, phase change memory element Rr is interposed between the source of P channel transistor P0 and power supply line PWR, and phase change memory element Rm is interposed between the source of P channel transistor P1 and power supply line PWR. N-channel transistor Ns is interposed between the connection point of P-channel transistor P1 and phase change memory element Rm and store line STR, and the voltage of node S0 is applied to its gate.

According to Patent Document 1, one of the phase change memory elements (Rr) is a reference (reference) resistance, and the other one of the phase change memory (logic storage resistance Rm) changes with a high resistance (logic value 1) and a low resistance. A resistance value between (logical value 0) is set in advance. The logic memory resistor Rm is applied with a current causing a phase change by the power supply line PWR, the switching element (transistor Ns), and the store line STR. At the time of reading, the SRAM circuit portion indicated by the dotted line is operated as a normal SRAM. The logical storage resistance Rm during this operation is set to a low resistance value. Then, before the power is turned off, the voltage of the store line STR is changed, and a current is passed through the logic storage resistor Rm by the transistor Ns, thereby transferring the logic value stored in the SRAM circuit portion (store). When the power is turned on, the stored contents transferred to the phase change memory element Rm are returned to the SRAM circuit section (recall). In this way, when the power is turned off and on, the memory contents are moved and returned by the logical storage resistor Rm of the phase change memory and the SRAM circuit unit, thereby operating as a non-volatile memory (see Patent Documents above). 1 paragraphs 0012 and 0013).
Patent Document 2 and Patent Document 3 disclose a so-called cross-point type memory. In the resistance change type memories disclosed in Patent Document 2 and Patent Document 3, a memory cell is configured by only one resistance element, and its formation is realized in a post-process (BEOL: Back End Of Line) after metal wiring. The

Japanese Patent No. 3845734 JP 2002-8369 A Japanese Patent Publication No. 2007-5366680

IEICE IEICE technical report ICEC Technical Report ICD2010-7 p35-p40

The nonvolatile RAM of Patent Document 1 described above has several problems. First, in the nonvolatile RAM of Patent Document 1, a phase change memory element is used as a resistance change type element. This phase change memory element is a so-called monopolar type resistance change element, and data “1” is stored. It is necessary to pass current in the same direction when writing data or when writing data “0”. This complicates the control for writing data. In addition, the phase change memory element cannot be rewritten at high speed because the write characteristic and the erase characteristic are greatly different. Further, as shown in FIG. 19, in the nonvolatile RAM of Patent Document 1, phase change memory elements (Rr and Rm) whose resistance values change are inserted on the power supply current paths of the two inverters constituting the flip-flop. Has been. For this reason, the flip-flop becomes unbalanced, and has a great adverse effect on the SNM (Static Noise Margin), which is the most important characteristic of the SRAM.
Hereinafter, this adverse effect on the SNM will be described.

  FIG. 20 is a circuit diagram showing a configuration of a general SRAM memory cell. In the illustrated example, one memory cell is constituted by P-channel transistors P1 and P2 and N-channel transistors N1, N2, Ta1, and Ta2.

  21A to 21D illustrate the SNM characteristics of the memory cell shown in FIG. 21A to 21D, the horizontal axis represents the voltage V0 at the common connection point of the transistors P1 and N1, and the vertical axis represents the voltage V1 at the common connection point of the transistors P2 and N2.

  In FIGS. 21A to 21D, the dashed curve and the solid curve are each called a butterfly curve. These two butterfly curves cross each other on the way, and the positional relationship between the top and bottom and the left and right is switched. In each of FIGS. 21 (a) to 21 (d), two squares are respectively drawn that fall within two regions sandwiched between a broken butterfly curve and a solid butterfly curve. The size of this square is the size of the SNM. More specifically, the square between the two butterfly curves in the region where the broken butterfly curve is at the upper right and the solid butterfly curve is at the lower left is a noise that increases the voltage V0 at the connection point of the drains of the transistors P1 and N1. When this occurs, it is an SNM (hereinafter referred to as a first SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell. The square between the two butterfly curves in the region where the solid butterfly curve is at the upper right and the broken butterfly curve is at the lower left is when noise that raises the voltage V1 at the connection point of the drains of the transistors P2 and N2 occurs. , An SNM (hereinafter referred to as a second SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell.

  FIGS. 21A and 21C illustrate the SNM characteristics when the power supply voltage VDD of the SRAM is 1.0 V, respectively. In the example shown in FIG. 21A, the beta value β and the threshold voltage Vt of each transistor constituting the memory cell are balanced, the first SNM and the second SNM are approximately the same, and Is also large enough. Therefore, in this memory cell, stable write access and read access are possible.

  However, the butterfly curve depends on the balance of the beta values and the threshold voltage of each of the transistors P1, N1, P2, and N2. For example, in FIG. 21A, when the beta ratio βp / βn between the beta value βp of the transistor P2 and the beta value βn of the transistor N2 becomes high, the broken butterfly curve projects in the upper right direction. Conversely, when the beta ratio βp / βn decreases, the broken butterfly curve retreats in the lower left direction. Further, when the threshold voltage Vtn of the transistor N2 increases and the threshold voltage Vtp of the transistor P2 decreases, the voltage V0 at which the broken butterfly curve suddenly falls increases. Conversely, when the threshold voltage Vtn of the transistor N2 decreases and the threshold voltage Vtp of the transistor P2 increases, the voltage V0 at which the broken butterfly curve suddenly falls decreases.

  Further, in the process of increasing the voltage V0 from 0V to VDD, when the transistor N2 is turned on, a current flows into the transistor N2 via the transistor Ta2. Therefore, the voltage V1 does not fall down to the VSS level (0V), but the VSS level. Float from. If the current flowing through the transistor Ta2 is constant, the floating of the voltage V1 from the VSS level at this time increases as the threshold voltage Vtn of the transistor N2 is higher or the beta value βn of the transistor N2 is lower.

  Thus, the broken butterfly curve is affected by changes in threshold voltages and beta values of the transistors P2 and N2. On the other hand, the solid butterfly curve is mainly affected by changes in the balance of the beta values and the balance of the threshold voltages of the transistors P1 and N1. Thus, since the butterfly curve is affected by changes in the threshold voltage and beta value of each transistor, the first and second SNMs are also affected by changes in the threshold voltage and beta value of each transistor.

  In the example shown in FIG. 21C, an imbalance occurs between the threshold voltage Vt or the beta value of each transistor constituting the memory cell, and the first SNM is sufficiently large, but the second SNM Is slightly smaller.

  As described above, when the characteristics (specifically, the threshold voltage Vt and the beta value) of the transistors constituting the memory cell vary, the sizes of the first and second SNMs vary.

  Further, when the power supply voltage VDD of the SRAM is reduced, the degree of influence on the first and second SNMs of the characteristic variation of each transistor constituting the memory cell is increased. FIGS. 21B and 21D show examples thereof. In the examples of FIGS. 21B and 21D, the power supply voltage VDD of the SRAM is 0.5V. In the example shown in FIG. 21B, since the power supply voltage VDD is 0.5 V, the first and second SNMs are considerably small. However, the characteristics of the transistors constituting the memory cell are balanced. Therefore, the first and second SNMs are sized to enable normal write access and read access. However, in the example shown in FIG. 21 (d), there is a slight imbalance in the characteristics of the transistors constituting the memory cell, and the second SNM is almost eliminated due to the influence. As described above, when the operation margin is insufficient, the write access and the read access are hindered.

  When an imbalance occurs in the characteristics of the transistors constituting the memory cell in this way, the SNM of the SRAM is adversely affected, particularly when the power supply voltage VDD is low.

  However, in the technique of Patent Document 1, phase change memory elements whose resistance values change are respectively inserted in power supply current paths of two inverters constituting such SRAM memory cells. When such a phase change memory element is interposed, the transistors P0 and N0 that constitute one inverter and the transistors P1 and N1 (see FIG. 19) that constitute the other inverter cause an imbalance in bias conditions. As a result, the characteristics of the transistors constituting each inverter are unbalanced, and the SNM of the memory cell is greatly deteriorated. The above is the analysis of the static operation of the SRAM. In addition, considering the dynamic operation, the gate capacitance of the transistor Ns is added to the node S0, and the capacitance is unbalanced between the node S0 and the node S1. This capacity imbalance reduces the dynamic operating margin. In the cross-point type memory disclosed in Patent Document 2, an unnecessary sneak current is generated as shown in FIGS. 3A, 3B, and 3C of Patent Document 2. There is a problem that power consumption increases. Further, the cross-point type memory disclosed in Patent Document 2 has a problem that a bipolar type writing method that allows a bidirectional current to flow cannot be adopted as a data writing method. The cross-point type memory disclosed in Patent Document 3 has a 1R2D type configuration and cannot be applied to a resistance variable element having bidirectional characteristics such as MRAM.

  The present invention has been made in view of the circumstances described above, and a first object thereof is to rewrite the stored data in the volatile storage unit and to store the stored data in the nonvolatile storage unit without impairing the function as the SRAM. It is an object of the present invention to provide a non-volatile memory cell and a non-volatile memory that can easily perform a store operation for writing data and a recall operation for writing data from a non-volatile storage unit to a volatile storage unit. A second object of the present invention is to provide a non-volatile memory cell and a non-volatile memory that are resistant to variations in characteristics of elements constituting the cell. A third object of the present invention is to provide a nonvolatile memory cell and a nonvolatile memory that can operate at high speed with a small number of elements (small area).

In order to solve the above-described problems, the present invention includes a volatile storage unit and a nonvolatile storage unit, and the volatile storage unit uses first and second output signals as input signals to each other. A flip-flop interposed between a first power supply node to which a high-potential-side power supply voltage is applied and a second power-supply node to which a low-potential-side power supply voltage is applied, and an inverter of the first and second inverters When each of the output nodes is inserted between two bit lines and data is written to the flip-flop via the two bit lines, or from the flip-flop, the two First and second switches that are turned on when data is read through the bit line, and the nonvolatile memory unit includes the output node of the first inverter and the second switch. A first resistance variable element, a threshold element, and a second resistance variable element inserted in series between output nodes of the inverter; a common connection point of the first resistance variable element and the threshold element; A common connection point between the first capacitor interposed between the first power supply node and one of the second power supply nodes, the second resistance variable element, and the threshold element And a second capacitor interposed between the one power supply node and passing a current from the output node of the first inverter to the output node of the second inverter, One of the first and second variable resistance elements changes in resistance in a first direction, and the other changes in resistance in a second direction opposite to the first direction. The first input from the output node of the inverter When the current toward the output node of the data is passed, the resistance value of the one resistance change element changes in the second direction, and the resistance value of the other resistance change element changes in the first direction. A non-volatile memory cell characterized by changing is provided.

  As the first and second resistance change elements in the nonvolatile memory cell, an MTJ element or an element that generates an electric field induced giant resistance change such as MRAM or ReRAM can be used. For example, in the case where MTJ elements are used as the first and second variable resistance elements, the free layer side (or pinned layer side) of each of these two variable resistance elements is connected to a threshold element to form a nonvolatile memory What is necessary is just to comprise a cell. As the threshold element, a mode using a third switch such as a transistor can be considered. Further, as the threshold element, an element that allows a current to flow in a direction corresponding to the potential difference between the output node of the first inverter and the output node of the second inverter (for example, two diodes connected in antiparallel to each other, or a Zener diode) ) May be used. For example, in the aspect using the third switch as the threshold element, the first and second switches are turned off when storing the data stored in the flip-flop of the volatile storage unit in the nonvolatile storage unit. And turning on the third switch. In a state where the first and second switches are turned off and the third switch is turned on, the magnitude relationship of the potentials of the output nodes of the first and second inverters (that is, stored in the volatile storage unit) The first current path such as the first variable resistance element → the third switch → the second variable resistance element, depending on whether the data is “0” or “1”), or A current flows along one of the second current paths such as the second variable resistance element → the third switch → the first variable resistance element. As described above, since each of the first and second variable resistance elements has the same kind of layer connected to the third switch, the first and second resistance change elements are arranged along any of the first current path and the second current path. Even if current flows, the resistance values of the first and second variable resistance elements change in different directions, thereby realizing the storage of data stored in the volatile storage unit. That is, the magnitude relationship between the resistance values of the first and second variable resistance elements represents the data stored in the nonvolatile storage unit.

  When recalling the data stored in the non-volatile storage unit to the flip-flop, the voltage applied to the first power supply node by turning off the first, second and third switches is changed from 0 to the high potential side power supply. What is necessary is just to make it raise to a voltage. When the first, second, and third switches are turned off to increase the voltage applied to the first power supply node from 0 to the high potential side power supply voltage, the first capacitor is connected to the first capacitor via the first resistance variable element. While the charging current flows, the charging current flows to the second capacitor via the second resistance variable element, and the magnitude of both charging currents depends on the resistance state of the first and second resistance variable elements. A difference occurs, and a difference occurs between the potential of the output node of the first inverter and the potential of the output node of the second inverter. Thereby, writing back (recall) of the data stored in the nonvolatile storage unit to the volatile storage unit is realized.

  As described above, the nonvolatile memory portion of the nonvolatile memory cell according to the present invention includes a small number of elements (two resistance change elements, two capacitors, and one switch (transistor)). If MTJ elements are used as the first and second variable resistance elements, the inter-element voltage required for changing the resistance state of the first and second variable resistance elements is 0. The current flowing through these elements is about 49 μA. As described above, according to the present invention, less current flows through the resistance variable element at the time of storing or recalling, so that it is possible to realize an inexpensive nonvolatile memory chip with a small area. If the volatile storage unit has a 6Tr configuration, the data write operation and read operation to the volatile storage unit are the same as those in a normal SRAM, and the data write operation and read operation can be performed at high speed. In addition, a wide static noise margin can be ensured.

It is a circuit diagram showing an example of composition of memory cell 10A of nonvolatile RAM of a 1st embodiment of the present invention. It is a figure which shows the operating conditions of the non-volatile memory cell 10A. It is a circuit diagram which shows the structural example of the memory cell 10B of the non-volatile RAM of 2nd Embodiment of this invention. It is a figure which shows the operating conditions of the non-volatile memory cell 10B. It is a whole block diagram of the non-volatile RAM of 3rd Embodiment of this invention. It is a figure which shows the structural example of the non-volatile memory cell array 100 of the non-volatile RAM. It is a circuit diagram which shows the structural example of row selection circuit 200-k which comprises the row decoder 200 of the same non-volatile RAM. It is a time chart which shows the operation | movement at the time of the storage of the non-volatile RAM. It is a time chart which shows the operation | movement at the time of recall of the non-volatile RAM. It is a block diagram which shows the structural example of the non-volatile RAM which is 4th Embodiment of this invention. It is a circuit diagram which shows the structural example of row selection circuit 220-k of the 4th Embodiment. It is a time chart which shows the operation | movement at the time of recall of the non-volatile RAM of the 4th embodiment. It is a block diagram which shows the structure of a part of non-volatile RAM which is 5th Embodiment of this invention. It is a block diagram which shows the structure of a part of non-volatile RAM which is 6th Embodiment of this invention. It is a block diagram which shows the structure of a part of non-volatile RAM which is 7th Embodiment of this invention. It is a figure which shows the structure and operation | movement of an MTJ element. It is a figure which shows the equivalent circuit of the memory cell using the MTJ element. It is a figure which shows the cross-section of the memory cell using the same MTJ element. It is a circuit diagram which shows the structural example of the conventional non-volatile memory cell. 1 is a circuit diagram showing a general SRAM memory cell; FIG. It is a figure which illustrates the static noise margin of the memory cell. It is a figure which shows the equivalent circuit of the memory cell of 8th Embodiment of this invention. It is a figure which shows the voltage-current characteristic between the node N and the node SL in the memory cell. It is a figure which shows the operating condition of the memory cell. It is a figure which shows the other equivalent circuit example of the same memory cell. It is a figure which shows the structural example of the memory cell. It is a figure which shows the operating condition of the memory cell. It is a figure which shows the structural example of the memory cell of 9th Embodiment of this invention. It is a figure which shows the operating condition of the memory cell. It is a whole block diagram of the non-volatile RAM of 10th Embodiment of this invention. It is a figure which shows the structural example of the non-volatile RAM. It is a figure which shows the structural example of row selection circuit 2000-k in the non-volatile RAM. It is a time chart which shows the operation | movement at the time of the storage of the non-volatile RAM. It is a time chart which shows the operation | movement at the time of recall of the non-volatile RAM. It is a time chart for demonstrating the recall operation | movement of the non-volatile RAM of 11th Embodiment of this invention. It is a figure which shows an example of the circuit which raises VDC for every column in the non-volatile RAM. It is a figure which shows the structural example of the non-volatile RAM of 12th Embodiment of this invention. It is a figure which shows the structural example of row selection circuit 2200-k contained in the non-volatile RAM. It is a figure which shows the structure of the principal part of the non-volatile RAM of 13th Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(A: 1st Embodiment)
FIG. 1 is a circuit diagram showing a configuration example of a nonvolatile memory cell 10A of the nonvolatile RAM according to the first embodiment of the present invention. The nonvolatile memory cell 10A includes a volatile storage unit 11 and a nonvolatile storage unit 12A. The volatile storage unit 11 has the same configuration as that used as a volatile memory cell in a normal SRAM. More specifically, the volatile memory unit 11 includes an inverter INV1 including a P-channel field effect transistor (hereinafter, “field effect transistor” is simply abbreviated as “transistor”) P1 and an N-channel transistor N1, and a P-channel transistor. It has an inverter INV2 composed of P2 and an N-channel transistor N2, and N-channel transistors Ta1 and Ta2 as transfer gates. Here, the inverters INV1 and INV2 use the output signals of the other party as input signals for each other, and constitute a flip-flop. This flip-flop supplies a first power supply node for supplying a high potential side voltage VDC and a low potential side power supply voltage VSS as a dedicated power supply voltage (hereinafter referred to as a memory cell voltage) of the volatile storage unit 11. It is inserted between the second power supply node. The N channel transistor Ta1 is interposed between the output node V1 of the inverter INV1 and the bit line BL. The N-channel transistor Ta2 is interposed between the output node V2 of the inverter INV2 and the bit line BLB. The gates of N channel transistors Ta1 and Ta2 are connected to row select line WL. The N-channel transistors Ta1 and Ta2 are turned on when the row selection line WL is in a selected state (a state where a voltage of a selection level (1.2 V in this embodiment) is applied to the row selection line WL). As a result, data can be written to the flip-flop of the volatile storage unit 11 via the bit lines BL and BLB, and data can be read from the flip-flop of the volatile storage unit 11 to the bit lines BL and BLB.

  The nonvolatile memory unit 12A includes an N-channel transistor Tw as a switch, variable resistance elements R1 and R2, and capacitors C1 and C2. The variable resistance element R1, the N-channel transistor Tw, and the variable resistance element R2 are interposed in series between the output node V1 and the output node V2. The resistance variable elements R1 and R2 are the MTJ elements described above. The pin layer side of the resistance variable element R1 is connected to the output node V1 of the inverter INV1, and the free layer side is connected to the N-channel transistor Tw. The pin layer side of the resistance variable element R2 is connected to the output node V2 of the inverter INV2, and the free layer side is connected to the N-channel transistor Tw. A capacitor C1 is interposed between the common connection point between the resistance variable element R1 and the N channel transistor Tw and the second power supply node, and the resistance variable element R2 and the N channel transistor Tw are connected to each other. A capacitor C2 is interposed between the common connection point and the second power supply node. Then, a store enable signal STE that is at a selection level when data is stored (stored) in resistance change elements R1 and R2 is applied to the gate of N channel transistor Tw.

  The outline of the operation of the nonvolatile memory cell 10A is as follows. At normal times, the store enable signal STE is at the non-selection level (0 V), and the N-channel transistor Tw is OFF. Since the N-channel transistor Tw is OFF, the resistance change elements R1 and R2 are disconnected, and the nonvolatile memory cell 10A operates as an SRAM. On the other hand, when the power is turned off, it is necessary to save the data stored in the flip-flop of the volatile storage unit 11 to the nonvolatile storage unit 12A. Therefore, when the power is turned off, first, the store enable signal STE is set to the selection level (1.2 V), the N-channel transistor Tw is turned on, and the data stored in the flip-flop of the volatile storage unit 11 is stored. The power supply is shut off after saving to the nonvolatile storage unit 12A. This is defined as a store. When the power is turned on, the store enable signal STE is set to the non-selection level (0 V), and the data stored in the nonvolatile storage unit 12A is transferred to the flip-flop of the volatile storage unit 11 when the memory cell voltage VDC rises. . This is defined as recall. After the recall is completed, the nonvolatile memory cell 10A operates as a normal SRAM. As described above, the nonvolatile memory cell 10A according to this embodiment operates as a nonvolatile memory by storing when the power is turned off and recalling when the power is turned on.

  FIG. 2 is a diagram showing operating conditions of the nonvolatile memory cell 10A when the power supply voltage VDD of the chip is 1.2V. Hereinafter, the operation of the nonvolatile memory cell 10A will be described with reference to FIG. When the data stored in the flip-flop of the volatile storage unit 11 is stored in the nonvolatile storage unit 12A, as shown in FIG. 2, the row selection line WL is set to the non-selected state (0 V) and the store enable is performed. The signal STE is set to the selection level (1.2V). At this time, the bit line BL and the inverted bit line BLB may be in either a selected state or a non-selected state (indicated as “−” meaning “Don't care” in FIG. 2). For example, if data “1” is held in the flip-flop of the volatile storage unit 11, the voltage at the node V1 is 1.2V, and the voltage at the node V2 is 0V. In this state, when the row selection line WL is set to the non-selected state (0 V) and the store enable signal STE is set to the selection level (1.2 V), the N-channel transistors Ta1 and Ta2 are turned off and the N-channel transistor Tw is turned on. A current flows from the node V1 (1.2 V) to the node V2 (0 V) along a current path such as the resistance variable element R1 → the N-channel transistor Tw → the resistance variable element R2. In the resistance variable element R1, since a current flows from the pin layer to the free layer, the resistance variable element R1 enters a high resistance state, and in the resistance variable element R2, a current flows from the free layer to the pin layer. R2 enters a low resistance state. The resistance states of the resistance variable elements R1 and R2 are maintained even after the power is turned off. As a result, the data “1” is stored in the nonvolatile storage unit 12A.

  When data “0” is held in the flip-flop of the volatile storage unit 11, the node V 1 is 0 V and the node V 2 is 1.2 V. Therefore, the row selection line WL is not selected (0 V). And the store enable signal STE is set to the selected level, the current flows from the node V2 (1.2 V) to the node V1 (0 V) along the current path of the resistance variable element R2 → the N channel transistor Tw → the resistance variable element R1. Flows. At this time, since a current flows from the free layer to the pinned layer in the resistance variable element R1, the resistance variable element R1 enters a low resistance state, and in the variable resistance element R2, a current flows from the pinned layer to the free layer. The mold element R2 enters a high resistance state. As a result, the data “0” is stored in the nonvolatile storage unit 12A.

  Next, a recall operation for storing the data stored in the nonvolatile storage unit 12A in the flip-flop of the volatile storage unit 11 will be described. In this recall operation, the row selection line WL is set to the non-selected state (0V), the store enable signal STE is set to the non-selected level (0V), and the memory cell voltage VDC is raised from 0V to 1.2V. In the process in which the memory cell voltage VDC rises from 0V to 1.2V, the voltages at the nodes V1 and V2 both rise from 0V to 1.2V. A resistance variable element R1 and a capacitor C1 are inserted in series between the second power supply node to which the low-potential-side power supply voltage VSS is supplied and the node V1, and between the second power supply node and the node V2. A resistance variable element R2 and a capacitor C2 are inserted in series. Therefore, a charging current flows from the node V1 to the capacitor C1 via the resistance variable element R1, and a charging current flows from the node V2 to the capacitor C2 via the resistance variable element R2.

  If the resistance variable element R1 is in the high resistance state and the resistance variable element R2 is in the resistance state (that is, the state where the data “1” is stored in the nonvolatile memory unit 12A), the charging current of the capacitor C2 Becomes larger than the charging current of the capacitor C1, and a difference occurs between the potential of the node V1 and the potential of the node V2. In accordance with this potential difference, the node V1 of the flip-flop of the volatile storage unit 11 is set to High (1.2V), and the node V2 is set to Low (0V). Thereby, the recall of the data “1” stored in the nonvolatile storage unit 12A to the flip-flop of the volatile storage unit 11 is completed. When the resistance variable element R1 is in the low resistance state and the resistance variable element R2 is in the high resistance state (that is, the state where the data “0” is stored in the nonvolatile memory unit 12), the charging current of the capacitor C1 Is larger than the charging current of the capacitor C2, the node V1 is latched to Low (0V) and the node V2 is latched to High (1.2V), and the recall ends.

  It should be noted here that attention must be paid to how to raise the memory cell voltage VDC. In the recall operation of the present embodiment, since a minute difference (transient current) that charges the capacitor through the resistance variable element is used, if the rise of the memory cell voltage VDC is too gradual, the node V1 This is because the difference between the potential and the potential of the node V2 is unlikely to occur, and the recall may fail. The rise time of the memory cell voltage VDC is preferably determined in consideration of the time constant between the resistance variable element and the capacitor. To increase the time constant, the capacitance of the capacitor may be increased. However, since the layout area increases when the capacitance of the capacitor is increased, for example, the rise time of the memory cell voltage VDC is preferably set to about 10 ns to 1 μs.

  The data read operation from the nonvolatile memory cell 10A (more precisely, the volatile storage unit 11) is the same as the data read operation in a normal SRAM. In this case, the nonvolatile memory cell 10A operates as an SRAM having a configuration including six transistors (hereinafter abbreviated as 6Tr configuration), and thus operates as an SRAM having a wide static noise margin. In addition, since data writing to the nonvolatile memory cell 10A is exactly the same as a normal RAM, detailed description is omitted here.

  As described above, the nonvolatile memory unit 12A of the nonvolatile memory cell 10A of the present embodiment is configured with a small number of elements such as two resistance change elements, two capacitors, and one switch (transistor). Yes. Further, since the MTJ elements are used as the resistance change elements R1 and R2, the inter-element voltage required for changing the resistance state of these resistance change elements is about 0.6 V, and the current flowing through these elements is 49 μA. Degree. As described above, according to the present embodiment, since a small amount of current flows through the resistance variable element at the time of storing or recalling, it is possible to realize an inexpensive nonvolatile memory chip with a small area. Further, the data read operation and write operation from the nonvolatile memory cell 10A are the same as those in a normal SRAM, and the data write operation and read operation can be performed at a high speed and a wide static noise margin is ensured. Can do.

(B: Second embodiment)
FIG. 3 is a circuit diagram showing a configuration example of the nonvolatile memory cell 10B according to the second embodiment of the present invention.
In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals. As apparent from a comparison between FIG. 3 and FIG. 1, the configuration of the nonvolatile memory cell 10B is different from the configuration of the nonvolatile memory cell 10A in that a nonvolatile memory unit 12B is provided instead of the nonvolatile memory unit 12A. . In the nonvolatile memory unit 12B of this embodiment, the resistance variable element R1 and the capacitor C1 are inserted in series between the node V1 and the power supply node to which the memory cell voltage VDC is applied, and the resistance variable Unlike the nonvolatile memory unit 12A, the element R2 and the capacitor C2 are inserted in series between the node V2 and the same power supply node, and the free layer side of the resistance variable element R1 is connected to the node V1. The point that the free layer side of the resistance variable element R2 is connected to the node V2 is also different from the nonvolatile memory unit 12A of FIG.

  FIG. 4 is a diagram showing operating conditions of the nonvolatile memory cell 10B. Hereinafter, the operation of the nonvolatile memory cell 10B will be described with reference to FIG. When the data stored in the flip-flop of the volatile storage unit 11 is stored in the nonvolatile storage unit 12B, the row selection line WL is set to the non-selected state (0 V) as in the first embodiment, The store enable signal STE is set to the selection level (1.2 V). If data “1” is held in the flip-flop of the volatile storage unit 11, the voltage of the node V1 is 1.2V, and the voltage of the node V2 is 0V. In this state, when the row selection line WL is set to the non-selected state (0 V) and the store enable signal STE is set to the selection level (1.2 V), the N-channel transistors Ta1 and Ta2 are turned off and the N-channel transistor Tw is turned on. Become. Therefore, a current flows from the node V1 (1.2 V) to the node V2 (0 V) along the current path of the resistance variable element R1 → the N channel transistor Tw → the resistance variable element R2. In the resistance variable element R1, since a current flows from the free layer to the pin layer, the resistance variable element R1 enters a low resistance state, and in the resistance variable element R2, a current flows from the pin layer to the free layer. R2 enters a high resistance state. As a result, the data “1” is stored in the nonvolatile storage unit 12B.

When data “0” is held in the flip-flop of the volatile storage unit 11, the node V 1 is 0 V and the node V 2 is 1.2 V. Therefore, the row selection line WL is not selected (0 V). And the store enable signal STE is at the selection level (1.2 V), the node V2 (1.2 V) to the node V1 along the current path of the resistance variable element R2 → N-channel transistor Tw → resistance variable element R1. Current flows at (0V). At this time, since a current flows from the pinned layer to the free layer in the resistance variable element R1, the resistance variable element R1 enters a high resistance state, and in the resistance variable element R2, a current flows from the free layer to the pinned layer. Element R2 is in a low resistance state. Thus, data "0" is stored in the nonvolatile memory unit 12 B.

  Next, a recall operation for storing the data stored in the nonvolatile storage unit 12B in the flip-flop of the volatile storage unit 11 will be described. In this recall operation, the memory cell voltage VDC is raised from 0V to 1.2V with the row selection line WL set to the non-selected state (0V) and the store enable signal STE set to the non-selected level (0V). In the process in which the memory cell voltage VDC rises from 0V to 1.2V, the voltages at the nodes V1 and V2 both rise from 0V to 1.2V. A capacitor C1 and a resistance variable element R1 are interposed in series between a power supply node to which the memory cell voltage VDC is applied and the node V1, and a capacitor C2 and a resistance variable element are interposed between the power supply node and the node V2. R2 is inserted in series. For this reason, the potential of the node V1 rises toward the potential of the power supply node by the action of the capacitor C1 and the resistance variable element R1, and the potential of the node V2 also increases by the action of the capacitor C2 and the resistance variable element R2. It rises toward the potential.

If the resistance variable element R1 is in the low resistance state and the resistance variable element R2 is in the high resistance state (that is, the state where the data “1” is stored in the nonvolatile storage unit 12B), the potential of the node V1 Is more likely to rise than the potential of the node V2, and a difference occurs between the potential of the node V1 and the potential of the node V2, and the node V1 of the flip-flop of the volatile storage unit 11 is set to High (1.2 V), and the node V2 Is set to Low (0 V). Thereby, the recall of the data “1” stored in the nonvolatile storage unit 12 B to the flip-flop of the volatile storage unit 11 is completed. When the resistance variable element R1 is in the low resistance state and the resistance variable element R2 is in the high resistance state (that is, the state where the data “0” is stored in the nonvolatile storage unit 12), the potential of the node V2 This is more likely to rise than the potential of the node V1, and the node V1 is latched low (0V) and the node V2 is latched high (1.2V), and the recall ends.

  In the present embodiment as well, recall is realized by utilizing the difference in a minute current (transient current) that charges the capacitor via the resistance variable element, so that the power supply voltage VDC of the nonvolatile memory cell is raised. It is the same as in the first embodiment that attention should be paid to the above. Further, the data read operation from the nonvolatile memory cell 10B (more precisely, the volatile storage unit 11) is the same as the normal SRAM operation, as in the nonvolatile memory cell 10A of the first embodiment. The non-volatile memory cell 10B operates as an SRAM having a wide static noise margin because it operates as a 6Tr configuration SRAM, and is the same as in the first embodiment. Further, since data writing to the nonvolatile memory cell 10B is exactly the same as a normal SRAM as in the first embodiment, detailed description thereof is omitted.

  Also in this embodiment, the data read operation and write operation from the nonvolatile memory cell 10B are the same as those in a normal SRAM, and the data write operation and read operation can be performed at a high speed, and a wide static noise margin is provided. Can be secured. Further, the point that an inexpensive non-volatile memory chip can be realized is the same as in the first embodiment.

(C: Third embodiment)
FIG. 5 is a block diagram showing an overall configuration of a nonvolatile RAM according to the third embodiment of the present invention. In FIG. 5, a nonvolatile memory cell array 100 is configured by arranging the nonvolatile memory cells 10A of the first embodiment in a matrix. In this example, the memory capacity of the nonvolatile memory cell array 100 is 64M bits (4M × 16 bits).

  The control circuit 500 is a circuit that controls each part in the nonvolatile RAM in accordance with a chip enable signal CEB, a store signal STR, a recall signal RCL, and an output permission signal OEB given from the outside. Here, the chip enable signal CEB and the output permission signal OEB are control signals used in a normal SRAM. The store signal STR and the recall signal RCL are control signals unique to this embodiment. The store signal STR is a control signal that is set to H level (1.2 V in this example) when storing data in the nonvolatile RAM, and the recall signal RCL is set to H level when recalling data to the nonvolatile RAM. Control signal. Control circuit 500 generates control signals STRB, RCLB, RSTB in response to store signal STR and recall signal RCL, and provides them to row decoder 200. The control signal STRB is a signal obtained by logically inverting the store signal STR, and the control signal RCLB is a signal obtained by logically inverting the recall signal RCL. The control signal RSTB is a signal obtained by logically inverting the reset signal RST given from the outside to the control circuit 500.

  The address input circuit 950 is a circuit that receives and holds addresses A0 to A23 that specify access destinations in the nonvolatile memory cell array 100 under the control of the control circuit 500. In the nonvolatile memory cell array 100, the addresses A0 to A23 are divided into a row address that specifies the row to which the access destination belongs and a column address that specifies the column to which the access destination belongs.

  The row decoder 200 decodes the row address and selects one of the rows of the nonvolatile memory cell array 100 according to the decoding result. The column decoder 300 decodes the column address and selects one of the columns of the nonvolatile memory cell array 100 according to the decoding result. The column gate 400 connects the data input circuit 800 at the time of write access and the sense amplifier 600 at the time of read access to the bit line of the column selected by the column decoder 300. The sense amplifier 600 is a circuit that amplifies the voltage on the bit line supplied through the column gate 400 at the time of read access and outputs the amplified voltage to the input / output buffer 700. The data input circuit 800 is a circuit that supplies the column gate 400 with a data voltage corresponding to write data supplied via the input / output buffer 700 during write access. Input / output buffer 700 receives 16-bit write data from the outside, supplies it to data input circuit 800, and outputs 16-bit read data to the outside based on the output signal of sense amplifier 600. An output circuit is used.

  The row decoder 200 is provided with a function specific to the present embodiment in addition to the function of a normal SRAM row decoder. That is, the row decoder 200 in this embodiment selects a desired nonvolatile memory cell 10A in the nonvolatile memory cell array 100 in units of rows, turns off the N-channel transistors Ta1 and Ta2 of the nonvolatile memory cell, and turns off the N-channel transistor Tw. Is turned ON, store control means for storing data from the volatile storage unit 11 of the nonvolatile memory cell 10A to the nonvolatile storage unit 12A, and a desired nonvolatile memory cell 10A in the nonvolatile memory cell array 100 in units of rows The N-channel transistors Ta1, Ta2 and Tw of the nonvolatile memory cell 10A are turned off, and the memory cell voltage VDC for the nonvolatile memory cell 10A is further raised, whereby the nonvolatile memory cell 10A Volcano It has a function as a recall control means for causing the recall of writing data from the sexual storage unit 12A to the volatile storage unit 11. The VDC circuit 900 is a circuit that generates a memory cell voltage VDC. In the present embodiment, a VDC circuit 900 common to all the nonvolatile memory cells is provided in order to recall all the nonvolatile memory cells at the time of recall. The VDD detection circuit 960 is provided to cope with an unexpected power shutdown. The VDD detection circuit 960 detects the rise of the power supply voltage VDD, outputs a pulse of the power-on signal PON to the control circuit 500, and outputs a LowVDD signal to the control circuit 500 when detecting that the power supply voltage VDD has decreased.

  FIG. 6 is a block diagram showing a specific configuration example of the nonvolatile RAM according to the present embodiment. In FIG. 6, only the configuration related to storage and input / output of 1-bit data is shown in order to prevent the drawing from becoming complicated. The actual nonvolatile RAM has a configuration in which the nonvolatile memory cell array 100 and the column gate 400 shown in FIG.

  In FIG. 6, the nonvolatile memory cell array 100 uses the nonvolatile memory cells 10A of the first embodiment (FIG. 1) as nonvolatile memory cells Mkj, and the nonvolatile memory cells Mkj are arranged in a matrix of m + 1 rows and n + 1 columns. It is an arrangement. Although the minimum unit of the non-volatile memory cell array 100 depends on the high speed and the scale of the memory capacity, generally, for example, m = 1024 and n = 512 are divided into 512K bits. In this example, since the memory capacity is 64 Mbits, 128 minimum memory arrays are provided.

  In the nonvolatile memory cell array 100, a pair of bit lines BITj and BITjB are wired along each column j of nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) arranged in a matrix. Has been. Here, the sources of the N-channel transistors Ta1 of m + 1 nonvolatile memory cells Mkj (k = 0 to m) belonging to the column j are connected to the bit line BITj, respectively, and the bit line BITjB belongs to the column j. The sources of N-channel transistors Ta2 of m + 1 nonvolatile memory cells Mkj (k = 0 to m) are connected to each other.

  In the nonvolatile memory cell array 100, a signal line for supplying a row selection voltage WLk along each row k of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) arranged in a matrix. A signal line for supplying the store enable signal STEk is wired. Row selection voltage WLk is supplied to the gates of N channel transistors Ta1 and Ta2 (see FIG. 1) of n + 1 nonvolatile memory cells Mkj (j = 0 to n) belonging to row k. The store enable signal STEk is supplied to each gate of the N-channel transistor Tw (see FIG. 1) of the n + 1 nonvolatile memory cells Mkj (j = 0 to n) belonging to the row k. The memory cell voltage VDC is supplied from the VDC circuit 900 to the connection node between the sources of the P-channel transistors P1 and P2 in each of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n). The low potential side power supply voltage VSS is supplied to the connection node between the sources of the N channel transistors N1 and N2.

  The column gate 400 includes n + 1 sets of N-channel column selection transistors CGj (j = 0 to n) and CGjB (j = 0 to 0) associated with the respective columns j (j = 0 to n) of the nonvolatile memory cell array 100. n). Column selection transistors CGj and CGjB corresponding to column j are turned on when column selection voltage COLj becomes H level, and bit lines BITj and BITjB are connected to data input circuit 800 and sense amplifier 600.

  The column selection circuit 300-j (j = 0 to n) is provided in association with each column j (j = 0 to n) of the nonvolatile memory cell array 100. The column decoder 300 in FIG. 5 includes these n + 1 column selection circuits 300-j (j = 0 to n). The column selection circuit 300-j corresponding to the column j includes a column address match detection unit 301 that outputs an L level (0V) signal when the column address indicates the column j, and an output of the column address match detection unit 301. When the signal is at the L level, the inverter 302 outputs an H level row selection voltage COLj and turns on the column gate transistors CGj and CGjB corresponding to the column j.

  The row selection circuit 200-k (k = 0 to m) is provided in association with each row k (k = 0 to m) of the nonvolatile memory cell array 100. The row decoder 200 in FIG. 5 includes these m + 1 row selection circuits 200-k. In an operation mode as a normal SRAM, the row selection circuit 200-k corresponding to the row k sets the row selection voltage WLk to the H level when the row address indicates the row k, and n + 1 pieces belonging to the row k. The N-channel transistors Ta1 and Ta2 (see FIG. 1) of the nonvolatile memory cell Mkj (j = 0 to n) are turned on. In addition, the row selection circuit 200-k corresponding to the row k controls the output of the store enable signal STEk to be supplied to the n + 1 nonvolatile memory cells Mkj (j = 0 to n) belonging to the row k.

FIG. 7 is a circuit diagram illustrating a configuration example of the row selection circuit 200-k (k = 0 to m).
As illustrated in FIG. 7, the row selection circuit 200-k includes an address match detection unit 201, a NAND circuit 202, a NOR circuit 203, an inverter 204, and a NOR circuit 205. The address match detection unit 201 is given a row address ADDX. When the row address ADDX indicates a row k, the output of the address match detection unit 201 is L level. Conversely, when the row address ADDX does not indicate the row k, the output of the address match detection unit 201 is H level. It becomes. As shown in FIG. 7, the output of the address match detection unit 201 is given to the NOR circuit 203 and the NOR circuit 205.

  The NAND circuit 202 is supplied with the control signal STRB and the control signal RCLB, and the output of the NAND circuit 202 is supplied to the NOR circuit 203. As shown in FIG. 7, in the present embodiment, the output of the NOR circuit 203 is the row selection signal WLk. The output of the NAND circuit 202 is given to the NOR circuit 205 through logic inversion by the inverter 204. The NOR circuit 205 is further supplied with a control signal RSTB, and the output of the NOR circuit 205 becomes a store enable signal STEk.

  In the operation mode for storing, the control signal STRB is at L level, the control signal RCLB is at H level, and the control signal RSTB is at L level. For this reason, the output of the NAND circuit 202 becomes H level, and the output of the NOR circuit 203 (that is, the row selection signal WLk) becomes L level. At this time, if the row address ADDX indicates row k, the output of the address match detection unit 201 becomes L level, and the output of the NOR circuit 205 (that is, the store enable signal STEk) becomes H level.

  In the operation mode in which the recall is performed, the control signal STRB becomes H level and the control signal RCLB becomes L level. In this case, the control signal RSTB is set to the L level only during the reset operation, and is set to the H level at other times. Further, all the bits constituting the row address ADDX are set to “1” by a predecoder of the row address (not shown). Therefore, the output of the NAND circuit 201 is always at the L level. The output of the NAND circuit 202 becomes H level, the output of the NOR circuit 203 (that is, the row selection signal WLk) is L level, and the output of the NOR circuit 205 (that is, the store signal STEk) is when the control signal RSTB is L level. Only becomes H level, otherwise it becomes L level. When the nonvolatile RAM of this embodiment is operated as a normal SRAM, the control signals STRB and RCLB are both at the H level, and the output of the NAND circuit 202 is always at the L level. Therefore, if the row address ADDX indicates the row k, the row selection circuit 200-k outputs the H level row selection signal WLk, and if the row address ADDX does not indicate the row k, the L level row. A selection signal WLk is output. Regardless of whether or not the row address ADDX indicates row k, the row selection circuit 200-k outputs an L level store enable signal STEk.

  FIG. 8 is a time chart showing the operation during storage of the nonvolatile RAM according to the present embodiment. In this example, the nonvolatile RAM operates under the operating conditions shown in FIG. In this example, an example is shown in which data is simultaneously stored in a non-volatile memory cell connected to one row line. When the store signal STR is at L level (period t1 in FIG. 8), the nonvolatile RAM operates as a normal SRAM. When the supply of the power supply voltage VDD to the nonvolatile RAM is cut off, the store signal STR is raised prior to that. When the STR signal becomes H level, the control signals STRB and RSTB output from the control circuit 500 become L level, and the nonvolatile RAM starts the operation for storing as follows.

  When the control signal STRB becomes L level, the output of each NAND circuit 202 of the row selection circuit 200-k (k = 0 to m) becomes H level, and the output of the NOR circuit 203 (that is, the row selection signal WLk) is always set. L level. Therefore, the bit line BLj and the inverted bit line BLBj are don't care. In a period t2 starting from a point in time when a predetermined time has elapsed after the store signal STR becomes H level, from the address AX0 corresponding to the first row k = 0 to the address AXm corresponding to the last row k = m A process of setting each of the m + 1 row addresses to the row address ADDX over the period Δt1 is executed, and the volatile storage unit 11 in each of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n). To the nonvolatile storage unit 12A is performed in units of rows.

  For example, during the period in which the address AX0 is set as the row address ADDX, the output of the address match detection unit 201 of the row selection circuit 200-0 is L level, and the row selection circuit 200-k (k = 1 to m) The output of the address match detection unit 201 becomes H level. As described above, in each of the row selection circuits 200-k (k = 0 to m), since the output of the NAND circuit 202 is at the H level, the output of the inverter 204 is at the L level. Since the control signal RSTB applied to each of the row selection circuits 200-k (k = 0 to m) is at the L level, the output of the NOR circuit 205 of the row selection circuit 200-0 (that is, the store enable signal for the 0th row) Only STE0) becomes H level (1.2V), and the output of the NOR circuit 205 of the row selection circuit 200-k (k = 1 to m) (that is, the store signal STEk for the kth row) becomes L level (0V). Become. For this reason, in each of the nonvolatile memory cells M0j (j = 1 to n) in the 0th row, the storage data of the volatile storage unit 11 is written to the nonvolatile storage unit 12A.

  Similarly, during a period in which AXk (k = 1 to m) is set as the row address ADDX, each of the nonvolatile memory cells Mkj (j = 1 to n) in the k-th row stores the volatile storage unit 11. The stored data is written into the nonvolatile storage unit 12A. When the storage for all the rows is completed, the supply of the power supply voltage VDD to the nonvolatile RAM is interrupted in the subsequent period t3.

  In the above operation, assuming that the current required for storing one nonvolatile memory cell is 49 μA, the number of nonvolatile memory cells per row is 512, so storing one row (= 512) at once. Thus, the current consumption required for this is 25 mA. When the current consumption required to store one row at a time is not within the allowable range, one row is divided into a plurality of blocks in the row direction, and the block is stored all at once. Just do it. Further, if the power consumption is within the allowable range even if the storage for a plurality of rows is performed at once, the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) are stored for the plurality of rows. Of course, you can select and store one by one.

  FIG. 9 is a time chart showing the operation at the time of recall of the nonvolatile RAM according to the present embodiment. In this example, the recall is performed according to the operating conditions of FIG. In the power supply startup period t1, the power supply voltage VDD for the nonvolatile RAM is raised to 1.2V. In this process, the VDD detection circuit 960 detects the rise of the power supply voltage VDD and outputs a power-on signal PON in pulses. The control circuit 500 resets (initializes) the nodes V0 and V1 of the volatile storage unit 11 in each of the non-volatile memory cells Mkj (k = 0 to m, j = 0 to n) upon reception of the power-on signal PON. ) In the following manner.

  First, when the recall signal RCL becomes H level, all the bits constituting the row address ADDX are set to “1” (High Fix), and the control signal RSTB is set to L level over a period of time t2. Since the row address ADDX is high-fixed, it does not match the row address indicating any row from the 0th row to the m-th row, and the row selection signal WLk (k = 0 to m) becomes L level. Further, since the control signal RSTB is at the L level over the period of time t2, the store enable signal STEk (k = 0 to m) is at the H level (1.2 V) only during the period t2, and the nonvolatile memory cell N-channel transistors Tw included in each of Mkj (k = 0 to m, j = 0 to n) are turned on. As a result, the node V0 and the node V1 of the volatile storage unit 11 in each of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) are short-circuited and reset to the same potential.

  Thereafter, the control circuit 500 returns the control signal RSTB to the H level. As a result, the store enable signal STEk (k = 0 to m) becomes L level, and the N-channel transistor Tw included in each of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) is turned OFF. . In this state, the memory cell voltage VDC is raised from 0 V to 1.2 V by the VDC circuit 900, and the memory of the nonvolatile memory unit 12 is stored in each of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n). Data is written back to the volatile storage unit 11 (period t3 in FIG. 9). Thereafter, when the recall signal RCL becomes L level, the recall operation is terminated, and thereafter, the nonvolatile RAM operates as a normal SRAM (FIG. 9: period t4).

(D: 4th Embodiment)
FIG. 10 is a diagram showing a configuration example of a nonvolatile RAM according to the fourth embodiment of the present invention. 10, the same components as those in FIG. 6 are denoted by the same reference numerals. The nonvolatile RAM of the present embodiment has a feature that the memory cell voltage VDC applied to each nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n) constituting the nonvolatile memory cell array 100 is controlled for each row. Unlike the nonvolatile RAM of the third embodiment, in order to realize such control, a control circuit 520 is provided instead of the control circuit 500, and a row selection circuit 200-k (k = 0 to m) is provided. Instead, a row selection circuit 220-k (k = 0 to m) is provided, which is different from the nonvolatile RAM (see FIG. 6) of the third embodiment.

  FIG. 11 is a circuit diagram showing a configuration example of the row selection circuit 220-k. Each of address match detection unit 221, NAND circuit 230, inverter 231, NOR circuits 232 and 233 in FIG. 11 corresponds to each of address match detection unit 201, NAND circuit 202, inverter 204, and NOR circuits 203 and 205 in FIG. To do. In the row selection circuit 220-k shown in FIG. 11, the output of the address coincidence detection unit 201 is given to each of the NOR circuits 232 and 233, and after being inverted by the inverter 222, is given to the latch L1 as the address match detection signal ADTk.

  The latch L1 is configured by a P-channel transistor 223, N-channel transistors 224 and 226, and an inverter 225. The P-channel transistor 223 and the N-channel transistor 224 are interposed in series between the high potential side power supply VDD and the low potential side power supply VSS. Address match detection signal ADTk is applied to the gate of N channel transistor 224. Inverter 225 inverts and outputs a signal generated at the connection node between the drains of P channel transistor 223 and N channel transistor 224. The output signal of the inverter 225 becomes the output signal of the latch L1. The output signal of the inverter 225 is supplied to the gate of the P channel transistor 223. The N-channel transistor 226 is interposed between the output node of the inverter 225 and the low potential side power source VSS. A power-on signal PON is supplied to the gate of the N-channel transistor 226. The above is the configuration of the latch L1.

The delay circuit 227 delays the output signal of the latch L1 by a predetermined time Δt1. The inverter 228 inverts the output signal of the delay circuit 227 and outputs it. The level shifter 229 is supplied with the memory cell voltage VDC output from the VDC circuit 900 as the high potential side power supply voltage. The level shifter 229 inverts the output signal of the inverter 228. If the inverted result is “0”, the level shifter 229 outputs 0V, and if it is “1”, the voltage VDC output from the VDC circuit 900 corresponds to the row k. Output as voltage VDCk.
The above is the configuration of the row selection circuit 220-k.

Next, the operation of the row selection circuit 220-k will be described with reference to FIG.
FIG. 12 is a time chart showing the operation at the time of recall of the nonvolatile RAM according to the present embodiment. Since the operation at the time of storing is the same as that of the third embodiment described above, description thereof is omitted. As is clear from comparison between FIG. 12 and FIG. 9, in the operation at the time of recall of the nonvolatile RAM according to the present embodiment, the memory cell voltage with respect to the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n). The difference from the third embodiment is that VDCk is selectively raised sequentially for each row.

  More specifically, when power is turned on and supply of the power supply voltage VDD to the nonvolatile RAM is started, a power-on signal PON is output from the VDD detection circuit 960 (not shown in FIG. 12), and the row selection circuit Each N-channel transistor 226 of 220-k (k = 0 to m) is turned on, and the output NN2 of the latch circuit L1 is reset to 0V. As a result, the output voltage VDCk of each level shifter 229 of the row selection circuit 220-k (k = 0 to m) becomes 0V. This is the initial state.

  Next, the recall signal RCL becomes H level, and the recall operation is started. When the address AX0 indicating the 0th row is set as the row address ADDX, in the row selection circuit 220-0, the output NN1 of the address match detection unit 221 becomes L level and the output NN2 of the latch circuit L1 becomes H level. Further, the control signal RSTB is set to the L level by the control circuit 520 over the period Δt1 from the setting of the address AX0, and the store enable signal STE0 is set to the H level over the period Δt1. Thereafter, the delay circuit 227 delays Δt1 and the output of the inverter 228 becomes L level, and the memory cell voltage VDC0 for the k-th row becomes 1.2V. Thereafter, when the period Δt2 elapses and the row address ADDX is switched to the address AX1 indicating the first row, the same processing is executed in the row selection circuit 220-1. Thereafter, the row address ADDX is switched to the addresses AX2, AX3... AXm, and the recall is executed in all the nonvolatile memory cells Mkj. When the recall of all the nonvolatile memory cells Mkj is completed, the recall signal RCL is set to L level, and the nonvolatile RAM of this embodiment operates as a normal SRAM.

  Note that the latch of the nonvolatile memory cell Mkj to the flip-flop of the volatile memory unit 11 is very fast, and this cycle can be performed in 10 ns or less (that is, Δt1 + Δt2 <10 ns). Therefore, to recall the nonvolatile memory cell array 100 with m = 1024 and n = 512, 10 ns × 1024 rows = 10.2 μs. In the case of a 64 Mbit memory, since there are 128 memory arrays, all memories can be recalled in 10.2 μs × 128 blocks = 1.3 ms. In the present embodiment, the nonvolatile memory cells Mkj are selected and recalled one row at a time, and the volatile memory unit 11 of the recalled nonvolatile memory cells Mkj is reset prior to the recall. Of course, as shown by a dotted line in FIG. 12, the volatile memory portions 11 of all the nonvolatile memory cells Mkj may be reset at once.

(E: 5th Embodiment)
FIG. 13 is a block diagram showing a partial configuration of a nonvolatile RAM according to the fifth embodiment of the present invention. This embodiment is a modification of the fourth embodiment. In the fourth embodiment described above, the reference power supply voltage VDCk supplied to the nonvolatile memory cells Mkj (j = 0 to n) in the k-th row is controlled by the row selection circuit 220-k. On the other hand, in the nonvolatile memory cell array of FIG. 13, a row selection circuit 240-k is provided instead of the row selection circuit 220-k, and the low-potential-side power supply voltage VSCk is applied to each row by the row selection circuit 240-k. It is different that it was made to supply. In the operation at the time of recall of the present embodiment, when the power supply voltage VDD rises, all the low-potential-side power supply voltages VSCk are once charged to the VDD level by each of the row selection circuits 240-k (k = 0 to m). The Thereafter, for each row specified by the row address ADDX, the low potential side power supply voltage VSCk is sequentially set to 0 V by the row selection circuit 240-k, and the nonvolatile memory cells Mkj (j = 0 to n) in the k-th row are set. In each case, the data stored in the nonvolatile storage unit 12A is written into the volatile storage unit 11.

(F: Sixth embodiment)
FIG. 14 is a block diagram showing a partial configuration of a nonvolatile RAM according to the sixth embodiment of the present invention. This embodiment is a modification of the fourth embodiment. In the fourth embodiment described above, the memory cell voltage VDCk supplied to the non-volatile memory cell Mkj (j = 0 to n) in the kth row is controlled by the row selection circuit 220-k. On the other hand, in this embodiment, a P-channel transistor Ts is provided between the power supply line to which the output voltage VDC of the VDC circuit 900 is applied and the high-potential-side power supply node of the nonvolatile memory cell Mkj. The fifth embodiment is different from the fifth embodiment in that a row selection circuit 250-k that outputs a recall selection signal RCSBk for controlling ON / OFF of Ts is provided instead of the row selection circuit 220-k. That is, in this embodiment, at the time of recall, the recall selection signal RCsk is sequentially selected (set to L level) by the row address ADDX, and the recall is performed for each row.

  According to this embodiment, although there is a defect that the number of elements of the nonvolatile memory cell is increased as compared with the fourth embodiment described above, there are the following advantages. That is, since the P-channel transistor Ts is provided for each nonvolatile memory cell Mkj, wiring for supplying the voltages VDC and VSS can be wired in the vertical direction of FIG. 14 (that is, the column direction in the nonvolatile memory cell array). it can. For this reason, it is sufficient to consider only one bit as a current flowing in one power supply line at the time of writing to the resistance variable element or at the time of recall, and the voltage drop due to the power supply line resistance can be reduced.

(G: 7th embodiment)
FIG. 15 is a block diagram showing a partial configuration of a nonvolatile RAM according to the seventh embodiment of the present invention. The nonvolatile RAM of the present embodiment is different from the nonvolatile RAM of the sixth embodiment in that a nonvolatile memory cell array is configured using the nonvolatile memory cell 10B instead of the nonvolatile memory cell 10A. Needless to say, the operating conditions shown in FIG. 4 may be adopted as operating conditions at the time of storing or recalling in the nonvolatile RAM of the present embodiment. Similarly, in the nonvolatile RAM of the third embodiment (see FIG. 6), the nonvolatile RAM of the fourth embodiment (FIG. 10), and the nonvolatile RAM of the fifth embodiment, the nonvolatile memory cell 10A is replaced by a nonvolatile memory. The non-volatile memory cell array may be configured by arranging the volatile memory cells 10B in a matrix, and the operating conditions shown in FIG. 4 may be adopted as the operating conditions at the time of storing or recalling.

(H: Eighth Embodiment)
FIG. 22 is a diagram showing an equivalent circuit of the memory cell according to the eighth embodiment of the present invention. As shown in FIG. 22, this memory cell has a configuration in which a resistance variable element R such as an MTJ element and a threshold element THD are connected in series. In this embodiment, the threshold element THD includes a diode D1, The diode D2 is connected in parallel to the diode D1 in the reverse direction.

  FIG. 23 is a diagram showing a voltage-current characteristic between the node N (common connection point of the resistance variable element R and the threshold element THD) and the node SL (the other end of the threshold element THD) in the memory cell of FIG. is there. As shown in FIG. 22, in this memory cell, diodes D1 and D2 are connected in opposite directions between node N and node SL. Hereinafter, the voltage at the node N is VN, and the voltage at the node SL is VSL. When a positive voltage is applied between the node N and the node SL (that is, VN−VSL> 0), the diode D2 becomes forward, and the voltage exceeds the threshold voltage VF (for example, 0.5 V) of the diode D2. The on-state current suddenly flows. On the other hand, when a negative voltage is applied between the node N and the node SL, an on-current suddenly flows when the magnitude of the voltage exceeds the threshold voltage VF of the diode D1.

  That is, in the memory cell whose equivalent circuit configuration is represented by FIG. 22, when a positive voltage or a negative voltage is applied between the node BL (the other end of the resistance variable element R) and the node SL, the voltage is When the threshold voltage VF of the diode is exceeded, a large current flows in the forward direction or the reverse direction.

  FIG. 24 shows operating conditions of the memory cell shown in FIG. As shown in FIG. 24, when a voltage of 1.0 V is applied to the node BL of this memory cell and a voltage of 0 V is applied to the node SL, the diode D2 is turned on, and is substantially between the node N and the node SL. A voltage of 0.5V is applied. As a result, a forward current flows through the resistance variable element R, and changes to a low resistance state storing “0”. That is, in order to store data “0” in the memory cell in FIG. 22, a voltage of 1.0 V may be applied to the node BL and a voltage of 0 V may be applied to the node SL. In this embodiment, the resistance of the diode D1 or D2 is sufficiently smaller than the resistance of the resistance variable element R, and there is almost no potential drop due to these diodes.

  On the other hand, when data “1” is stored in the memory cell of FIG. 22, a voltage of 0 V may be applied to the node BL and a voltage of 1.0 V may be applied to the node SL. As a result, the diode D1 is turned ON, a voltage of about −0.5 V is applied between the node N and the node SL, and a voltage between the node BL and the node N (that is, the resistance variable element R) is about −. A voltage of 0.5V is applied. As a result, a current in the reverse direction flows through the resistance variable element R, and changes to the high resistance state storing “1”. As shown in FIG. 25, the memory cell may be configured by using the Zener diode Dz as the threshold element THD instead of the diodes D1 and D2, and the breakdown voltage of the Zener diode Dz is about 0.5V. If so, the same voltage-current characteristics as in FIG. 23 can be obtained.

  FIG. 26 is a diagram illustrating a configuration example of the nonvolatile memory cell 10C of the nonvolatile RAM according to the present embodiment. In FIG. 26, the same components as those in FIG. 1 are denoted by the same reference numerals. As apparent from the comparison between FIG. 26 and FIG. 1, the configuration of the nonvolatile memory cell 10C of the present embodiment is that the nonvolatile memory unit 12C is provided instead of the nonvolatile memory unit 12A. Different from the configuration of the nonvolatile memory cell 10A. The configuration of the nonvolatile memory unit 12C is different from the configuration of the nonvolatile memory unit 12A in that diodes Da and Db connected in opposite directions are provided as threshold elements instead of the N-channel transistor Tw.

  In this embodiment, the normal memory cell voltage VDC is 0.5V. In this case, both the diodes Da and Db are turned off, and the resistance variable elements R1 and R2 are disconnected from the volatile storage unit 11. For this reason, the non-volatile memory cell 10C of the present embodiment operates as an SRAM in a normal state, similarly to the non-volatile memory cell 10A of the first embodiment. When the power is turned off, it is necessary to store the data stored in the volatile storage unit 11 in the nonvolatile storage unit 12C. For this reason, when the power is turned off, the memory cell voltage VDC is set to a high voltage of about 1.5V. Then, a current flows between the output nodes V1 and V2, and one resistance of the resistance variable elements R1 and R2 becomes a resistance and the other becomes a high resistance. Data is stored. When the power is turned on, the voltage stored between the memory cell voltage VDC and the reference voltage VSS is applied to incline the flip-flop of the volatile storage unit 11 in a certain direction, and the data stored in the nonvolatile storage unit 12C. Is recalled to the flip-flop. Thus, after the data is recalled from the nonvolatile storage unit 12C to the volatile storage unit 11, the nonvolatile memory cell 10C operates as an SRAM.

  FIG. 27 is a diagram showing operating conditions of the nonvolatile memory cell 10C. When the data stored in the flip-flop of the volatile storage unit 11 is stored in the nonvolatile storage unit 12C, the row selection line WL is set to the non-selected state (0V) as shown in FIG. Set VDC to 1.5V. At this time, the bit line BL and the inverted bit line BLB may be in either a selected state or a non-selected state (in FIG. 27, expressed as “−” meaning “Don't care”). The reason why the memory cell voltage VDC is set to 1.5 V is that a voltage of about 1.5 V is applied to both ends of the threshold element and the resistance variable element connected in series.

  For example, if data “1” is held in the flip-flop of the volatile storage unit 11, the voltage at the node V1 is 1.5V and the voltage at the node V2 is 0V. Since the row selection line WL is in the non-selected state (0 V), the N-channel transistors Ta1 and Ta2 are turned off, and the node V1 (1) along the current path of the resistance variable element R1 → the diode Da → the resistance variable element R2. .5V) to node V2 (0V). In the resistance variable element R1, since a current flows from the pin layer to the free layer, the resistance variable element R1 enters a high resistance state, and in the resistance variable element R2, a current flows from the free layer to the pin layer. R2 enters a low resistance state. The resistance states of the resistance variable elements R1 and R2 are maintained even after the power is turned off. As a result, the data “1” is stored in the nonvolatile storage unit 12C.

  When data “0” is held in the flip-flop of the volatile storage unit 11, the node V1 is 0V and the node V2 is 1.5V. Since the row selection line WL is in the non-selected state (0 V), the N-channel transistors Ta1 and Ta2 are turned off, and the node V2 (1) along the current path of the resistance variable element R2 → the diode Db → the resistance variable element R1. .5V) to node V1 (0V). At this time, since a current flows from the free layer to the pinned layer in the resistance variable element R1, the resistance variable element R1 enters a low resistance state, and in the variable resistance element R2, a current flows from the pinned layer to the free layer. The mold element R2 enters a high resistance state. As a result, the data “0” is stored in the nonvolatile storage unit 12C.

  Next, a recall operation for storing the data stored in the nonvolatile storage unit 12C in the flip-flop of the volatile storage unit 11 will be described. In this recall operation, the row selection line WL is set to a non-selected state (0V), and the memory cell voltage VDC is raised from 0V to 0.5V. In the process in which the memory cell voltage VDC rises from 0V to 0.5V, the voltages at the nodes V1 and V2 both rise from 0V to 0.5V. A resistance variable element R1 and a capacitor C1 are inserted in series between the second power supply node to which the low-potential-side power supply voltage VSS is supplied and the node V1, and between the second power supply node and the node V2. A resistance variable element R2 and a capacitor C2 are inserted in series. Therefore, a charging current flows from the node V1 to the capacitor C1 via the resistance variable element R1, and a charging current flows from the node V2 to the capacitor C2 via the resistance variable element R2.

  If the resistance variable element R1 is in the high resistance state and the resistance variable element R2 is in the resistance state (that is, the state where the data “1” is stored in the nonvolatile memory unit 12C), the charging current of the capacitor C2 Becomes larger than the charging current of the capacitor C1, and a difference occurs between the potential of the node V1 and the potential of the node V2. In accordance with this potential difference, the node V1 of the flip-flop of the volatile storage unit 11 is set to High (0.5V), and the node V2 is set to Low (0V). Thereby, the recall of the data “1” stored in the nonvolatile storage unit 12C to the flip-flop of the volatile storage unit 11 is completed. When the resistance variable element R1 is in the low resistance state and the resistance variable element R2 is in the high resistance state (that is, the state where the data “0” is stored in the nonvolatile storage unit 12C), the charging current of the capacitor C1 Is larger than the charging current of the capacitor C2, the node V1 is latched to Low (0V) and the node V2 is latched to High (0.5V), and the recall is completed.

  As described above, the nonvolatile memory portion 12C of the nonvolatile memory cell 10C of the present embodiment is configured with a small number of elements such as two resistance change elements, two capacitors, and two diodes. Further, since the MTJ elements are used as the resistance change elements R1 and R2, the inter-element voltage required for changing the resistance state of these resistance change elements is about 0.6 V, and the current flowing through these elements is 49 μA. Degree. As described above, according to the present embodiment, since a small amount of current flows through the resistance variable element at the time of storing or recalling, it is possible to realize an inexpensive nonvolatile memory chip with a small area. Further, the data read operation and write operation from the nonvolatile memory cell 10C are the same as those in a normal SRAM, and the data write operation and read operation can be performed at a high speed and a wide static noise margin is ensured. Can do. However, also in this embodiment, it is necessary to pay attention to how to raise the memory cell voltage VDC, as in the first embodiment.

(I: Ninth embodiment)
FIG. 28 is a circuit diagram showing a configuration example of the nonvolatile memory cell 10D according to the ninth embodiment of the present invention. In FIG. 28, the same components as those in FIG. 26 are denoted by the same reference numerals. As is clear from comparison between FIG. 28 and FIG. 26, the configuration of the nonvolatile memory cell 10D is different from the configuration of the nonvolatile memory cell 10C in that a nonvolatile memory unit 12D is provided instead of the nonvolatile memory unit 12C. . In the nonvolatile memory unit 12D of this embodiment, the resistance variable element R1 and the capacitor C1 are inserted in series between the node V1 and the power supply node to which the memory cell voltage VDC is applied, and the resistance variable type Unlike the nonvolatile memory unit 12C, the element R2 and the capacitor C2 are inserted in series between the node V2 and the same power supply node. Further, the free layer side of the resistance variable element R1 is connected to the node V1. The point that the free layer side of the resistance variable element R2 is connected to the node V2 is also different from the nonvolatile memory unit 12C of FIG.

  FIG. 29 is a diagram illustrating operating conditions of the nonvolatile memory cell 10D. Hereinafter, the operation of the nonvolatile memory cell 10D will be described with reference to FIG. When the data stored in the flip-flop of the volatile storage unit 11 is stored in the nonvolatile storage unit 12D, the row selection line WL is set to the non-selected state (0 V) as in the case of the eighth embodiment. And the memory cell voltage VDC is set to 1.5V. If data “1” is held in the flip-flop of the volatile storage unit 11, the voltage of the node V1 is 1.5V and the voltage of the node V2 is 0V. In this state, when the row selection line WL is set to the non-selected state (0 V), the N-channel transistors Ta1 and Ta2 are turned off. Therefore, a current flows from the node V1 (1.5 V) to the node V2 (0 V) along a current path such as the resistance variable element R1 → the diode Da → the resistance variable element R2. In the resistance variable element R1, since a current flows from the free layer to the pin layer, the resistance variable element R1 enters a low resistance state, and in the resistance variable element R2, a current flows from the pin layer to the free layer. R2 enters a high resistance state. As a result, the data “1” is stored in the nonvolatile storage unit 12D.

  When data “0” is held in the flip-flop of the volatile storage unit 11, the node V1 is 0V and the node V2 is 1.5V. Therefore, when the row selection line WL is set to the non-selected state (0V). Then, a current flows from the node V2 (1.5 V) to the node V1 (0 V) along the current path of the resistance variable element R2 → the diode Db → the resistance variable element R1. At this time, since a current flows from the pinned layer to the free layer in the resistance variable element R1, the resistance variable element R1 enters a high resistance state, and in the resistance variable element R2, a current flows from the free layer to the pinned layer. Element R2 is in a low resistance state. As a result, data “0” is stored in the nonvolatile storage unit 12D.

  Next, a recall operation for storing the data stored in the nonvolatile storage unit 12D in the flip-flop of the volatile storage unit 11 will be described. In this recall operation, the row selection line WL is set to a non-selected state (0V), and the memory cell voltage VDC is raised from 0V to 0.5V. In the process in which the memory cell voltage VDC rises from 0V to 0.5V, the voltages at the nodes V1 and V2 both rise from 0V to 0.5V. A capacitor C1 and a resistance variable element R1 are interposed in series between a power supply node to which the memory cell voltage VDC is applied and the node V1, and a capacitor C2 and a resistance variable element are interposed between the power supply node and the node V2. R2 is inserted in series. For this reason, the potential of the node V1 rises toward the potential of the power supply node by the action of the capacitor C1 and the resistance variable element R1, and the potential of the node V2 also increases by the action of the capacitor C2 and the resistance variable element R2. It rises toward the potential.

  If the resistance variable element R1 is in the low resistance state and the resistance variable element R2 is in the high resistance state (that is, the state where the data “1” is stored in the nonvolatile storage unit 12D), the potential of the node V1 Is more likely to rise than the potential of the node V2, and a difference occurs between the potential of the node V1 and the potential of the node V2, and the node V1 of the flip-flop of the volatile storage unit 11 is set to High (0.5 V), and the node V2 Is set to Low (0 V). Thereby, the recall of the data “1” stored in the nonvolatile storage unit 12D to the flip-flop of the volatile storage unit 11 is completed. When the resistance variable element R1 is in the high resistance state and the resistance variable element R2 is in the low resistance state (that is, the state where the data “0” is stored in the nonvolatile storage unit 12D), the potential of the node V2 This is more likely to rise than the potential of the node V1, and the node V1 is latched low (0V) and the node V2 is latched high (0.5V), and the recall ends.

  In the present embodiment as well, recall is realized by utilizing the difference in a minute current (transient current) that charges the capacitor via the resistance variable element, so that the power supply voltage VDC of the nonvolatile memory cell is raised. As in the eighth embodiment, it is necessary to pay attention to the above. In addition, the data read operation from the volatile memory unit 11 of the nonvolatile memory cell 10D is the same as the normal SRAM operation, which is the same as the nonvolatile memory cell 10C of the eighth embodiment, and has a wide static noise margin. The point of operating as an SRAM is the same as in the eighth embodiment. Further, since data writing to the nonvolatile memory cell 10D is exactly the same as a normal SRAM as in the eighth embodiment, detailed description thereof is omitted.

  Also in this embodiment, the data read operation and write operation from the nonvolatile memory cell 10D are the same as those in a normal SRAM, and the data write operation and read operation can be performed at a high speed, and a wide static noise margin is provided. Can be secured. Further, it is the same as in the eighth embodiment in that an inexpensive nonvolatile memory chip having a small area can be realized.

(J: 10th embodiment)
FIG. 30 is a block diagram showing the entire configuration of the nonvolatile RAM according to the tenth embodiment of the present invention. In FIG. 30, the same components as those in FIG. 5 are denoted by the same reference numerals. As is clear from comparison between FIG. 30 and FIG. 5, the configuration of the nonvolatile RAM of the present embodiment is that a nonvolatile memory cell array 1000 is provided instead of the nonvolatile memory cell array 100, and a row decoder is substituted for the row decoder 200. The configuration of the non-volatile RAM of FIG. 5 (the non-volatile RAM of the third embodiment) is different from that of FIG. 5 in that 2000 is provided and the column gate 4000 is provided instead of the column gate 400. Hereinafter, the nonvolatile memory cell array 1000, the row decoder 2000, and the column gate 4000, which are different from the nonvolatile RAM of the third embodiment, will be described with reference to FIG.

FIG. 31 is a diagram illustrating a specific configuration example of the nonvolatile RAM according to the present embodiment.
The nonvolatile memory cell array 1000 is configured by arranging the nonvolatile memory cells 10C of the eighth embodiment in a matrix. A symbol Mij (i = 0 to m, j = 0 to n) in FIG. 31 indicates each of m × n nonvolatile memory cells 10C arranged in a matrix. The memory capacity of the nonvolatile memory cell array 1000 is 64 Mbits (4M × 16 bits), similar to the nonvolatile memory cell array 100 of the third embodiment.

  The row decoder 2000 decodes the row address and selects one of the rows of the nonvolatile memory cell array 1000 according to the decoding result. The row decoder 2000 includes a row selection circuit 2000-k (k = 0 to m) shown in FIG. FIG. 32 is a circuit diagram showing a configuration example of the row selection circuit 2000-k in the k-th row. As illustrated in FIG. 32, the row selection circuit 2000-k includes an address match detection unit 2010, a NAND circuit 2020, and an inverter 2030. The address match detection unit 2010 is given a row address ADDX. When the row address ADDX indicates the kth row, the output of the address match detection unit 2010 is L level. Conversely, when the row address ADDX does not indicate the kth row, the output of the address match detection unit 2010 is H level. It becomes. As shown in FIG. 32, the output of the address match detection unit 2010 is given to the NAND circuit 2020.

  In addition to the output signal of the address match detection unit 2010, the NAND circuit 2020 is supplied with a control signal STRB and a control signal RCLB. The output signal of the NAND circuit 2020 becomes L level only when the output signal of the address match detection unit 2010, the control signal STRB and the control signal RCLB are all at H level, and becomes H level in other cases. The output signal of NAND circuit 2020 is applied to inverter 2030, and the output of inverter 2030 becomes row selection signal WLk. At the time of store and recall, control signal STRB or control signal RCLB is set to L level. In this case, the row selection signal WLk becomes L level (a value indicating a non-selected state) regardless of whether the output signal of the address match detection unit 2010 is H level or L level. On the other hand, in the normal SRAM operation, both the control signal STRB and the control signal RCLB are set to the H level, so that the row selection signal WLk is set to the L level or the H level according to the output of the address match detection unit 2010. Become.

  The column gate 4000 includes n + 1 sets of N-channel column selection transistors CGj (j = 0 to n) and CGjB (j = 0 to 0) associated with the respective columns j (j = 0 to n) of the nonvolatile memory cell array 1000. n). The column selection transistors CGj and CGjB corresponding to the j-th column are turned on when the column selection voltage COLj becomes H level, and connect the bit lines BITj and BITjB to the data input circuit 800 and the sense amplifier 600. In addition, the column gate 4000 includes a voltage switching circuit that switches a memory cell voltage supplied to each of the non-volatile memory cells Mij (i = 0 to m) in the jth (j = 0 to n) column. As shown in FIG. 31, the voltage switching circuit in the j-th column has a level shifter 401-j and N-channel transistors 402-j and 403-j for each column.

  More specifically, the sources of the N-channel transistor 402-j and the N-channel transistor 403-j are commonly connected, and this common connection point is a high-potential-side power supply node for each nonvolatile memory belonging to the kth column. It has become. The drain of the N-channel transistor 402-j is connected to the power supply VDD (high-potential-side power supply sharing the operating voltage with the nonvolatile RAM of the present embodiment), and the drain of the N-channel transistor 403-j is the power supply VDC (memory cell). Connected to a high-potential side power source for supplying voltage) A column selection voltage COLj that has undergone a level shift by the level shifter 401-j is applied to the gate of the N-channel transistor 402-j, and a column selection voltage COLj is applied to the gate of the N-channel transistor 403-j.

  FIG. 33 is a time chart showing an operation at the time of storing the nonvolatile RAM according to the present embodiment. The nonvolatile RAM of the present embodiment is an extremely low voltage memory operating at 0.5 V and operates under the operating conditions shown in FIG. In the present embodiment, storing is performed collectively for each column of the nonvolatile memory cell array 1000. In the period t1 in FIG. 33, the nonvolatile RAM operates as a normal SRAM, and the memory cell voltage VDC is 0.5V. When the supply of the power supply voltage VDD to the nonvolatile RAM is cut off, first, the store signal STR is raised. When the STR signal becomes H level, all the row selection signals WLk (k = 0 to m) become L level, and the memory cell voltage VDC rises from 0.5V to 1.5V. Here, when the column address ADDY is set to the first address AY0 and the column selection circuit 300-0 is selected, the column selection signal COL0 = H level, the N channel transistor 402-0 is turned OFF, and the N channel transistor 403- 0 turns ON. Therefore, in the period Δt1 in which the address AY0 is set to the column address ADDY, the memory cell voltage VD0 supplied to the nonvolatile memory cells in the 0th column is 1.5V.

  In this state, for example, when data “1” is held in the flip-flop of the volatile storage unit 11 of the nonvolatile memory cell M00, the voltage of the node V1 becomes 1.5 V in the nonvolatile memory cell M00, and the voltage of the node V2 Since the voltage is 0.5 V, the store condition shown in FIG. 27 is satisfied, and data “1” is stored in the nonvolatile storage unit 12C of the nonvolatile memory cell M00. Hereinafter, similarly, the data held in the volatile storage units 11 of the nonvolatile memory cells M10 to Mm0 are stored in the respective nonvolatile storage units 12C.

  Next, when the column address ADDY is set to the address AY1 and the column selection circuit 300-1 is selected, the memory cell voltage VD0 supplied to the nonvolatile memory cells in the first column becomes 1.5V, and the nonvolatile memory cell M01. The data held in each of the volatile storage units 11 to Mm1 is stored in each of the nonvolatile storage units 12C. Thereafter, the store operation in all the nonvolatile memory cells is completed by advancing the column address ADDY to the addresses AY2... AYN.

  When the store operation for the nth column (that is, the last column) is completed, the store signal STR becomes L level as shown in FIG. 33, and thereafter, the memory cell voltage VDC is set to 0V in the period t3 when the store signal STR is L level. Power off. In preparation for a sudden power failure due to an unexpected power failure, etc., a voltage drop detection circuit and a capacitor (storage battery) are provided to detect a drop in the power supply voltage. When detected, the store operation may be performed by the electric power stored in the capacitor. Further, in the present embodiment, the case where the storage is performed collectively for each column has been described, but the store current increases as the number of nonvolatile memory cells selected simultaneously increases. For example, when the store current per nonvolatile memory cell is 49 μA, if 128 bits are stored simultaneously, the total store current is 128 × 49 μA = 6.3 mA. Therefore, a divided store may be performed in which the column lines are divided and the number of nonvolatile memories selected at the same time is limited.

  FIG. 34 is a time chart showing the operation at the time of recall of the nonvolatile RAM according to the present embodiment. In the present embodiment, data is recalled in accordance with the operating conditions of FIG. 27 simultaneously in all the nonvolatile memory cells. In the power supply startup period t1, the power supply voltage VDD for the nonvolatile RAM is raised to 0.5V. In this process, the VDD detection circuit 960 detects the rise of the power supply voltage VDD and outputs a power-on signal PON in pulses. The internal circuit is reset (initialized) by the power-on signal PON.

  Next, when the recall signal RCL becomes H level, all the row selection lines WLk are not selected, and the memory cell voltages VDCj (j = 0 to n) of all the columns rise from 0V to 0.5V in the period t2. . In each of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n), the nonvolatile memory cell Mkj is nonvolatile depending on the operation condition shown in FIG. 27 (that is, the magnitude relationship between the voltage of the node V1 and the voltage of the node V2). Data stored in the storage unit 12C is written back to the volatile storage unit 11. Thereafter, when the recall signal RCL becomes L level, the recall operation is terminated, and thereafter, the nonvolatile RAM operates as a normal SRAM (period t3 in FIG. 34).

(K: 11th embodiment)
In the tenth embodiment, the case where all the nonvolatile memory cells included in the nonvolatile RAM are recalled at once has been described. However, as shown in FIG. 35, the memory cell voltage VDCj of each column is set for each column. It is also possible to start up and recall for each column. Specifically, after the power-on signal PON is output in a pulse and the recall signal RCL is set to H level, the memory cell voltage VDC0 is changed from 0V to 0.5V after a period Δt1 from the time when the column address AY0 is set. Launch. During the period Δt2 after the rise of the memory cell voltage VDC0 and before the column address is switched to the address AY1, the nonvolatile memory cells belonging to the 0th column are recalled. Note that once the memory cell voltage VDC0 rises to 0.5V, the memory cell voltage VDC0 is maintained at 0.5V until the power is turned off. After that, when the column addresses are sequentially set as addresses AY1... AYn and the recall of all the nonvolatile memory cells is completed, the recall signal RCL becomes L level, and the normal SRAM operation is started in the subsequent period t3.

  In order to raise the memory cell voltage VDCj of each column for each column and perform the recall for each column, a circuit corresponding to each column of the column gate 4000 may be configured as shown in FIG. A column gate 4000 shown in FIG. 36 is different from the column gate 4000 of FIG. 32 in that it includes a power supply latch circuit 410j (j = 0 to n). The power supply latch circuit 410j includes an address latch circuit L1, a delay circuit 415, an inverter 416, and a level shifter 417. Delay circuit 415 delays the output signal of address latch circuit L1 by Δt1 and provides the delayed signal to inverter 416. The output signal of inverter 416 is applied to level shifter 417. Level shifter 417 selectively outputs output voltage VDC of the internal power supply as memory cell voltage VDC * j (j = 0 to n).

  Address latch circuit L1 includes a P-channel transistor 411, N-channel transistors 412 and 414, and an inverter 413. The P-channel transistor 411 and the N-channel transistor 412 are inserted in series between the power supply VDD and the power supply VSS. An N-channel transistor 414 is interposed between the gate of the P-channel transistor 411 and the power supply VSS. A power-on signal PON is supplied to the gate of the N-channel transistor 414, and this N-channel transistor 414 serves as a reset transistor. Column select signal COLj is applied to the gate of N channel transistor 412. An inverter 413 is connected between the common connection point of the drain of the P-channel transistor 411 and the drain of the N-channel transistor 412 and the common connection point of the gate of the P-channel transistor 411 and the drain of the N-channel transistor 414 (FIG. 36: node N2). The node N2 is an output node of the address latch circuit L1.

  When the power-on signal PON is output as a pulse when the power is turned on, the N-channel transistor 414 is turned on. When the N channel transistor 414 is turned on, the node N2 becomes L level, the address latch circuit L1 is reset, and the memory cell voltage VDC * j becomes 0V. Next, when the column address AYj is selected, the column selection signal COLj becomes H level. When the column selection signal COLj becomes H level, the address latch circuit L1 is set and its output signal becomes H level. The output signal of address latch circuit L1 is applied to inverter 416 through a delay of Δt1 by delay circuit 415, and output as memory cell voltage VDC * j (0.5 V) through logic inversion by inverter 416 and level shift by level shifter 417. Is done. On the other hand, since the column selection signal COLj is at the H level, the N-channel transistor 402-j is turned OFF and the N-channel transistor 403-j is turned ON. As a result, the memory cell voltage VDCj is 0V during the period Δt1 and 0.5V during the next period Δt2, and the operation of the timing waveform of FIG. 35 is realized.

(L: 12th embodiment)
In the eleventh embodiment, the recall is performed for each column. However, the nonvolatile RAM of the present embodiment is different in that the recall is performed for each row. FIG. 37 is a diagram showing a specific configuration example of the nonvolatile RAM of the present embodiment. In FIG. 37, the same components as those in FIG. 31 are denoted by the same reference numerals. As is clear from a comparison between FIG. 37 and FIG. 31, the nonvolatile RAM of the present embodiment includes a row selection circuit 2200-k instead of the row selection circuit 2000-k, and a column gate 4000. Instead, the column gate 4200 is different from the nonvolatile RAM of FIG.

  The column gate 4200 has a configuration in which the inverter 401-j (j = 0 to n) and the N-channel transistors 402-j (j = 0 to n) and 403-j (j = 0 to n) are deleted from the column gate 4000. It has become. The row selection circuit 2200-k selectively outputs a memory cell voltage VDCk and a row selection signal WLk applied to the nonvolatile memory cells in the kth row. FIG. 38 is a diagram illustrating a configuration example of the row selection circuit 2200-k. In this row selection circuit 2200-k, NAND circuit 221 and inverter 222 constitute a row address decoder, and P channel transistor 223, N channel transistors 224 and 226, and inverter 225 constitute latch circuit L1. The delay circuit 227 is a delay circuit that generates a delay Δt1, and the output signal of the delay circuit 227 is applied to the level shifter 229 through logic inversion by the inverter 228, and the output signal of the level shifter 229 is a memory for the non-volatile memory cell in the k-th row. The cell voltage becomes VDCk. The row selection circuit 2200-k performs the same operation as that of the power supply latch circuit 410 in FIG. The operation timing waveform at the time of storing and the operation timing waveform at the time of recall are not shown in detail because the column address AYj in FIGS. 33 and 35 may be replaced with the row address AXk.

(M: 13th Embodiment)
This embodiment is a modification of the twelfth embodiment (that is, an embodiment in which the memory cell voltage VDC is supplied for each row). In the present embodiment, as shown in FIG. 39, the power source that supplies the memory cell voltage VDC and each nonvolatile memory cell are connected via the P-channel transistor SW, and the P-channel transistor SW in the k-th row is turned on / off. The difference from the twelfth embodiment is that the row selection circuit 2300-k is controlled. As shown in FIG. 39, in this embodiment, the row power supply selection signal SELBk is supplied from the row selection circuit 2300-k to the gate of the P-channel transistor SW in the k-th row. For example, when the row selection circuit 2300-k is selected, the row power supply selection signal SELBk becomes L level, and the nonvolatile memory cells Mk0 to MKn are connected to the power supply that supplies the memory cell voltage VDC. According to such an aspect, the power supply line that connects the power supply that supplies the memory cell voltage VDC and each nonvolatile memory cell (more precisely, the P-channel transistor SW corresponding to each nonvolatile memory cell) is connected to the nonvolatile memory. It is possible to perform wiring along at least one of the column direction and the row direction of the cell (that is, along the column direction, or along the row direction, or in a mesh-like manner in the row direction and the column direction). It becomes possible to strengthen the power supply line through which a current flows.

(N: deformation)
Although the first to tenth embodiments of the present invention have been described above, the following modifications may of course be added to these embodiments.
(1) In the nonvolatile memory unit 12A of the nonvolatile memory cell 10A of the first embodiment, the free layer side of the resistance change element R1 is connected to the N-channel transistor Tw, and the free layer side of the resistance change element R2 is It was connected to the N channel transistor Tw. However, the nonvolatile memory unit may be configured by connecting the pin layer side of the resistance variable element R1 to the N channel transistor Tw and connecting the pin layer side of the resistance variable element R2 to the N channel transistor Tw. In the nonvolatile memory unit having such a configuration, when data “1” is stored, the resistance variable element R1 is in a low resistance state and the resistance variable element R2 is in a high resistance state. When data “0” is stored, the resistance variable element R1 enters a high resistance state, and the resistance variable element R2 enters a low resistance state. Similarly, in the nonvolatile memory cell 10B of the second embodiment, the pin layer side of the resistance change element R1 is connected to the N channel transistor Tw, and the pin layer side of the resistance change element R2 is connected to the N channel transistor Tw. All the non-volatile storage units 12B may be configured. The point is that the same type of two types of layers of each of the resistance variable elements R1 and R2 may be connected to the N-channel transistor Tw. The same applies to the nonvolatile memory unit 12C of the nonvolatile memory cell 10C of the eighth embodiment and the nonvolatile memory unit 12D of the nonvolatile memory cell 10D of the ninth embodiment.

(2) In each of the embodiments described above, all the nonvolatile memory cells are configured by nonvolatile memory cells including a volatile storage unit and a nonvolatile storage unit. However, instead of doing so, a part of the non-volatile memory cell array may be constituted by non-volatile memory cells, and the remaining area may be constituted by ordinary SRAM memory cells. That is, only a part of the entire memory space of the SRAM is made an area that can be stored and recalled.

(3) In the nonvolatile memory cell 10A of the first embodiment, the capacitor C1 is interposed between the common connection point between the N-channel transistor Tw and the resistance variable element R1 and the low potential side power supply node. The capacitor C2 is interposed between the common connection point between the N-channel transistor Tw and the resistance variable element R2 and the low potential side power supply node. However, the capacitors C1 and C2 may be omitted, and the role of both may be assigned to the parasitic capacitance or metal wiring capacitance of the N-channel transistor Tw. Similarly, in the nonvolatile memory cells in each of the second to tenth embodiments, the capacitors C1 and C2 may be omitted, and the role of both may be assigned to the parasitic capacitance or the metal wiring capacitance of the N-channel transistor Tw.

10A, 10B, 10C, 10D ... non-volatile memory cell, 11 ... volatile memory unit, 12A, 12B, 12C, 12D ... non-volatile memory unit, INV1, INV2 ... inverter, V1, V2 ... output node, P1, P2 ... P channel transistor, N1, N2, Ta1, Ta2 ... N channel transistor, 100, 1000 ... non-volatile memory cell array, 200, 2000 ... row decoder, 200-k, 220-k, 240-k, 250-k ... row selection Circuit 300, column decoder 300-j column selection circuit 400, 4000 column gate 500 control circuit 600 sense amplifier 700 input / output buffer 800 data input circuit 900 VDC circuit 950 ... Address input circuit, 960 ... VDD detection circuit.

Claims (19)

A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
The first and second inverters, each having an output signal of the other party as an input signal, each of the first power supply node to which the high potential side power supply voltage is applied and the second power supply node to which the low potential side power supply voltage is applied A flip-flop interposed between them,
When writing data to the flip-flop via the two bit lines, which are respectively inserted between the output nodes of the first and second inverters and the two bit lines, Or first and second switches that are turned on when data is read from the flip-flops via the two bit lines,
The nonvolatile storage unit is
A first resistance variable element, a threshold element, and a second resistance variable element inserted in series between an output node of the first inverter and an output node of the second inverter;
A first capacitor interposed between a common connection point of the first variable resistance element and the threshold element and one of the first and second power supply nodes;
A second capacitor interposed between a common connection point of the second variable resistance element and the threshold element and the one power supply node;
When a current from the output node of the first inverter to the output node of the second inverter is passed, the resistance value of one of the first and second variable resistance elements changes in the first direction. On the other hand, when the resistance value changes in a second direction opposite to the first direction and a current from the output node of the second inverter to the output node of the first inverter is passed, A nonvolatile memory cell, wherein one resistance change element changes a resistance value in the second direction, and the other resistance change element changes a resistance value in the first direction.   2. The nonvolatile memory cell according to claim 1, wherein the first and second resistance change elements are a magnetic tunnel junction element or a resistance element in which an electric field induced giant resistance change occurs.   The threshold element is a third switch. When the data stored in the flip-flop is stored in the nonvolatile storage unit, the first switch and the second switch are turned off and the third switch is turned on. When the data stored in the nonvolatile storage unit is stored in the flip-flop, the voltage of the first power supply node is set with the first, second, and third switches turned off. 3. The nonvolatile memory cell according to claim 1, wherein the non-volatile memory cell rises from the low potential side power supply voltage to the high potential side power supply voltage.   4. The nonvolatile memory cell according to claim 1, wherein the threshold element is a field effect transistor, and the first and second capacitors are parasitic capacitances of the field effect transistor. 5. .   The threshold element is an element that causes a current to flow in a direction corresponding to a potential difference between the output node of the first inverter and the output node of the second inverter, and the data stored in the flip-flop is stored in the nonvolatile storage unit. When storing, the first and second switches are turned OFF, the voltage of the first power supply node is raised to a predetermined voltage higher than the high-potential-side power supply voltage, and stored in the nonvolatile storage unit When storing the processed data in the flip-flop, the voltage of the first power supply node is changed from the low-potential-side power supply voltage to the high-potential-side power-supply voltage with the first and second switches turned off. The non-volatile memory cell according to claim 1, wherein the non-volatile memory cell is started up to a maximum.   The nonvolatile memory cell according to claim 5, wherein the threshold element is two diodes connected in antiparallel or a Zener diode. A nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix;
Control means for controlling the operation of each nonvolatile memory cell in the nonvolatile memory cell array,
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
The first and second inverters, each having an output signal of the other party as an input signal, each of the first power supply node to which the high potential side power supply voltage is applied and the second power supply node to which the low potential side power supply voltage is applied A flip-flop interposed between them,
When writing data to the flip-flop via the two bit lines, which are respectively inserted between the output nodes of the first and second inverters and the two bit lines, Or first and second switches that are turned on when data is read from the flip-flops via the two bit lines,
The nonvolatile storage unit is
A first variable resistance element, a third switch, and a second variable resistance element interposed in series between an output node of the first inverter and an output node of the second inverter;
A first capacitor interposed between a common connection point of the first variable resistance element and the third switch and one of the first and second power supply nodes;
A second capacitor interposed between a common connection point of the second variable resistance element and the third switch and the one power supply node;
When a current from the output node of the first inverter to the output node of the second inverter is passed, the resistance value of one of the first and second variable resistance elements changes in the first direction. On the other hand, when the resistance value changes in a second direction opposite to the first direction and a current from the output node of the second inverter to the output node of the first inverter is passed, One resistance change element changes its resistance value in the second direction, and the other resistance change element changes its resistance value in the first direction,
The control means includes
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected, the first and second switches of the nonvolatile memory cell are turned off, and the third switch is turned on to turn on the flip-flop of the nonvolatile memory cell. Store control means for executing a store process for storing the data stored in the nonvolatile memory cell of the nonvolatile memory cell;
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected, and the voltage of the first power supply node is set to the low potential with the first, second, and third switches of the nonvolatile memory cell turned off. Recall control means for executing a recall process in which the data stored in the nonvolatile memory cell of the nonvolatile memory cell is stored in the flip-flop of the nonvolatile memory cell by rising from the side power supply voltage to the high potential power supply voltage And a non-volatile memory.   The store control means selects nonvolatile memory cells in a row unit and executes the store process, and the recall control means selects all the nonvolatile memory cells included in the nonvolatile memory cell array at a time. The nonvolatile memory according to claim 7, wherein the recall process is executed. A nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix;
Control means for controlling the operation of each nonvolatile memory cell in the nonvolatile memory cell array,
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
The first and second inverters, each having an output signal of the other party as an input signal, each of the first power supply node to which the high potential side power supply voltage is applied and the second power supply node to which the low potential side power supply voltage is applied A flip-flop interposed between them,
When writing data to the flip-flop via the two bit lines, which are respectively inserted between the output nodes of the first and second inverters and the two bit lines, Or first and second switches that are turned on when data is read from the flip-flops via the two bit lines,
The nonvolatile storage unit is
A first variable resistance element, a third switch, and a second variable resistance element interposed in series between an output node of the first inverter and an output node of the second inverter;
A first node interposed between a common connection point of the first variable resistance element and the third switch and one of the first power supply node and the second power supply node; A capacitor;
A second capacitor interposed between a common connection point of the second variable resistance element and the third switch and the one power supply node;
When a current from the output node of the first inverter to the output node of the second inverter is passed, the resistance value of one of the first and second variable resistance elements changes in the first direction. On the other hand, when the resistance value changes in a second direction opposite to the first direction and a current from the output node of the second inverter to the output node of the first inverter is passed, One resistance change element changes its resistance value in the second direction, and the other resistance change element changes its resistance value in the first direction,
The control means includes
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected, the first and second switches of the nonvolatile memory cell are turned off, and the third switch is turned on to turn on the flip-flop of the nonvolatile memory cell. Store control means for executing a store process for storing the data stored in the nonvolatile memory cell of the nonvolatile memory cell;
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected in units of one or more rows, and the nonvolatile memory cell is in a state where the first, second and third switches of the nonvolatile memory cell are turned off. The voltage of the first power supply node is raised from the low-potential-side power supply voltage to the high-potential-side power supply voltage, and the data stored in the nonvolatile storage portion of the nonvolatile memory cell is transferred to the flip-flop of the nonvolatile memory cell. And a recall control means for executing a recall process stored in the memory.   10. The recall control means collectively initializes flip-flops of all nonvolatile memory cells included in the nonvolatile memory cell array prior to selection of a row to be recalled. Nonvolatile memory as described in 1.   10. The nonvolatile memory according to claim 9, wherein the recall control unit initializes a flip-flop of the nonvolatile memory cell in the selected row prior to execution of the recall. A nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix;
Control means for controlling the operation of each nonvolatile memory cell in the nonvolatile memory cell array,
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
The first and second inverters, each having an output signal of the other party as an input signal, each of the first power supply node to which the high potential side power supply voltage is applied and the second power supply node to which the low potential side power supply voltage is applied A flip-flop interposed between them,
When writing data to the flip-flop via the two bit lines, which are respectively inserted between the output nodes of the first and second inverters and the two bit lines, Or first and second switches that are turned on when data is read from the flip-flops via the two bit lines,
The nonvolatile storage unit is
A first variable resistance element, a third switch, and a second variable resistance element interposed in series between an output node of the first inverter and an output node of the second inverter;
A first node interposed between a common connection point of the first variable resistance element and the third switch and one of the first power supply node and the second power supply node; A capacitor;
A second capacitor interposed between a common connection point of the second variable resistance element and the third switch and the one power supply node;
When a current from the output node of the first inverter to the output node of the second inverter is passed, the resistance value of one of the first and second variable resistance elements changes in the first direction. On the other hand, when the resistance value changes in a second direction opposite to the first direction and a current from the output node of the second inverter to the output node of the first inverter is passed, One resistance change element changes its resistance value in the second direction, and the other resistance change element changes its resistance value in the first direction,
The control means includes
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected in units of rows, the first and second switches of the nonvolatile memory cell are turned OFF, and the third switch is turned ON to turn the nonvolatile memory cell Store control means for executing store processing for storing the data stored in the flip-flop in the nonvolatile memory portion of the nonvolatile memory cell;
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected in units of rows, and the voltage of the second power supply node is set with the first, second, and third switches of the nonvolatile memory cell turned off. Recall processing for storing the data stored in the nonvolatile memory portion of the nonvolatile memory cell in the flip-flop of the nonvolatile memory cell by charging to the high potential power supply voltage and then falling to the low potential power supply voltage A non-volatile memory comprising recall control means for executing A non-volatile memory cell array in which non-volatile memory cells are arranged in a matrix, and a power supply line to which a high-potential-side power supply voltage is applied for each column of the non-volatile memory cell is wired along the column,
Control means for controlling the operation of each nonvolatile memory cell in the nonvolatile memory cell array,
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
A first power supply node comprising first and second inverters each having a counterpart output signal as an input signal to each other, and connected via a selection switch to a power supply line corresponding to a column to which the nonvolatile memory cell belongs; A flip-flop interposed between the second power supply nodes to which the low potential side power supply voltage is applied;
When writing data to the flip-flop via the two bit lines, which are respectively inserted between the output nodes of the first and second inverters and the two bit lines, Or first and second switches that are turned on when data is read from the flip-flops via the two bit lines,
The nonvolatile storage unit is
A first variable resistance element, a third switch, and a second variable resistance element interposed in series between an output node of the first inverter and an output node of the second inverter;
A first node interposed between a common connection point of the first variable resistance element and the third switch and one of the first power supply node and the second power supply node; A capacitor;
A second capacitor interposed between a common connection point of the second variable resistance element and the third switch and the one power supply node;
When a current from the output node of the first inverter to the output node of the second inverter is passed, the resistance value of one of the first and second variable resistance elements changes in the first direction. On the other hand, when the resistance value changes in a second direction opposite to the first direction and a current from the output node of the second inverter to the output node of the first inverter is passed, One resistance change element changes its resistance value in the second direction, and the other resistance change element changes its resistance value in the first direction,
The control means includes
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected in units of rows, the first and second switches of the nonvolatile memory cell are turned OFF, and the third switch is turned ON to turn the nonvolatile memory cell Store control means for executing store processing for storing the data stored in the flip-flop in the nonvolatile memory portion of the nonvolatile memory cell;
A desired non-volatile memory cell in the non-volatile memory cell array is selected in units of rows, and the selection switch of the non-volatile memory cell is turned on with the first, second and third switches of the non-volatile memory cell being turned off. ON, the voltage of the connected power line is raised from the low-potential-side power supply voltage to the high-potential-side power supply voltage, and the data stored in the nonvolatile storage portion of the nonvolatile memory cell is transferred to the nonvolatile memory cell And a recall control means for executing a recall process stored in the flip-flop. A nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix;
Control means for controlling the operation of each nonvolatile memory cell in the nonvolatile memory cell array,
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
The first and second inverters, each having an output signal of the other party as an input signal, each of the first power supply node to which the high potential side power supply voltage is applied and the second power supply node to which the low potential side power supply voltage is applied A flip-flop interposed between them,
When writing data to the flip-flop via the two bit lines, which are respectively inserted between the output nodes of the first and second inverters and the two bit lines, Or first and second switches that are turned on when data is read from the flip-flops via the two bit lines,
The nonvolatile storage unit is
A first resistance variable element, a threshold element, and a second resistance variable element inserted in series between an output node of the first inverter and an output node of the second inverter;
A first capacitor interposed between a common connection point of the first variable resistance element and the threshold element and one of the first and second power supply nodes;
A second capacitor interposed between a common connection point of the second variable resistance element and the threshold element and the one power supply node;
The threshold element is an element that allows a current to flow in a direction according to a potential difference between an output node of the first inverter and an output node of the second inverter;
When a current from the output node of the first inverter to the output node of the second inverter is passed, the resistance value of one of the first and second variable resistance elements changes in the first direction. On the other hand, when the resistance value changes in a second direction opposite to the first direction and a current from the output node of the second inverter to the output node of the first inverter is passed, One resistance change element changes its resistance value in the second direction, and the other resistance change element changes its resistance value in the first direction,
The control means includes
A desired non-volatile memory cell in the non-volatile memory cell array is selected, the first and second switches of the non-volatile memory cell are turned OFF, and the voltage of the first power supply node of the non-volatile memory cell is increased. Store control means for executing a store process for raising the data to a predetermined voltage higher than the potential-side power supply voltage and storing the data stored in the flip-flop of the nonvolatile memory cell in the nonvolatile memory unit of the nonvolatile memory cell;
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected, and the voltage of the first power supply node is set to the low-potential-side power supply voltage in a state where the first and second switches of the nonvolatile memory cell are turned off. Recall control means for executing a recall process for starting up from the high-potential-side power supply voltage and storing the data stored in the nonvolatile memory portion of the nonvolatile memory cell in the flip-flop of the nonvolatile memory cell; A non-volatile memory comprising:   The nonvolatile memory according to claim 14, wherein the store control unit selects the nonvolatile memory cells in units of columns and executes the store process.   16. The nonvolatile memory according to claim 14, wherein the recall control unit selects the nonvolatile memory cells included in the nonvolatile memory cell array in units of columns and executes the recall process. A nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix;
A voltage generating circuit that is provided for each row of the nonvolatile memory cell array and supplies an operating voltage to the nonvolatile memory cells in the corresponding row;
Control means for controlling the operation of each nonvolatile memory cell in the nonvolatile memory cell array,
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
The first and second inverters, each having an output signal of the other party as an input signal, each of the first power supply node to which the high potential side power supply voltage is applied and the second power supply node to which the low potential side power supply voltage is applied A flip-flop interposed between them,
When writing data to the flip-flop via the two bit lines, which are respectively inserted between the output nodes of the first and second inverters and the two bit lines, Or first and second switches that are turned on when data is read from the flip-flops via the two bit lines,
The nonvolatile storage unit is
A first resistance variable element, a threshold element, and a second resistance variable element inserted in series between an output node of the first inverter and an output node of the second inverter;
A first capacitor interposed between a common connection point of the first variable resistance element and the threshold element and one of the first and second power supply nodes;
A second capacitor interposed between a common connection point of the second variable resistance element and the threshold element and the one power supply node;
The threshold element is an element that allows a current to flow in a direction according to a potential difference between an output node of the first inverter and an output node of the second inverter;
When a current from the output node of the first inverter to the output node of the second inverter is passed, the resistance value of one of the first and second variable resistance elements changes in the first direction. On the other hand, when the resistance value changes in a second direction opposite to the first direction and a current from the output node of the second inverter to the output node of the first inverter is passed, One resistance change element changes its resistance value in the second direction, and the other resistance change element changes its resistance value in the first direction,
The control means includes
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected in units of rows, the first and second switches of the volatile memory cells belonging to the selected row are turned OFF, and the first nonvolatile memory cell Data stored in the flip-flop of the nonvolatile memory cell is controlled by controlling the voltage generation circuit corresponding to the selected row so that a predetermined voltage higher than the high-potential-side power supply voltage is applied to the power supply node. Store control means for executing store processing to be stored in the nonvolatile storage unit of the nonvolatile memory cell;
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected in units of rows, and applied to the first power supply node in a state where the first and second switches of the nonvolatile memory cells belonging to the selected row are turned off. Data stored in the nonvolatile memory portion of the nonvolatile memory cell is controlled by controlling the voltage generation circuit corresponding to the selected row so that the generated voltage rises from the low potential power supply voltage to the high potential power supply voltage. Recall control means for executing a recall process stored in the flip-flop of the nonvolatile memory cell. A nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix;
A selection switch that is provided for each of the non-volatile memory cells and that switches whether to connect to a voltage generation circuit that supplies an operating voltage to the non-volatile memory cells;
Control means for controlling the operation of each nonvolatile memory cell in the nonvolatile memory cell array,
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
The first and second inverters, each having an output signal of the other party as an input signal, each of the first power supply node to which the high potential side power supply voltage is applied and the second power supply node to which the low potential side power supply voltage is applied A flip-flop interposed between them,
When writing data to the flip-flop via the two bit lines, which are respectively inserted between the output nodes of the first and second inverters and the two bit lines, Or first and second switches that are turned on when data is read from the flip-flops via the two bit lines,
The nonvolatile storage unit is
A first resistance variable element, a threshold element, and a second resistance variable element inserted in series between an output node of the first inverter and an output node of the second inverter;
A first capacitor interposed between a common connection point of the first variable resistance element and the threshold element and one of the first and second power supply nodes;
A second capacitor interposed between a common connection point of the second variable resistance element and the threshold element and the one power supply node;
The threshold element is an element that allows a current to flow in a direction according to a potential difference between an output node of the first inverter and an output node of the second inverter;
When a current from the output node of the first inverter to the output node of the second inverter is passed, the resistance value of one of the first and second variable resistance elements changes in the first direction. On the other hand, when the resistance value changes in a second direction opposite to the first direction and a current from the output node of the second inverter to the output node of the first inverter is passed, One resistance change element changes its resistance value in the second direction, and the other resistance change element changes its resistance value in the first direction,
The control means includes
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected, the first and second switches of the volatile memory cell are turned off, and the high potential side is connected to the first power supply node of the nonvolatile memory cell. The selection switch corresponding to the selected nonvolatile memory cell is controlled so that a predetermined voltage higher than the power supply voltage is applied, and the data stored in the flip-flop of the nonvolatile memory cell is transferred to the nonvolatile memory cell. Store control means for executing store processing to be stored in the nonvolatile storage unit;
When a desired nonvolatile memory cell in the nonvolatile memory cell array is selected and the first and second switches of the nonvolatile memory cell are turned off, the voltage applied to the first power supply node is the low potential side. Control the selection switch corresponding to the selected nonvolatile memory cell so as to rise from the power supply voltage to the high-potential-side power supply voltage, and the data stored in the nonvolatile memory portion of the nonvolatile memory cell is transferred to the nonvolatile memory cell. And a recall control means for executing a recall process stored in the flip-flop.   19. The nonvolatile memory according to claim 18, wherein a power supply line connecting the voltage generation circuit and each selection switch is wired along at least one of a column direction and a row direction in the nonvolatile memory cell. Sex memory.

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