JP6100854B2 - Semiconductor device manufacturing method, substrate processing apparatus, gas supply system, and program - Google Patents

Description

  The present invention relates to a three-dimensional flash memory, a dynamic random access memory, a semiconductor device, a semiconductor device manufacturing method, a substrate processing apparatus, a gas supply system, and a program.

  As a process of manufacturing a semiconductor device (device), a film forming process may be performed in which a silicon film (Si film) is formed on a substrate with an insulating film exposed on at least a part of the surface.

  An object of the present invention is to provide a technique capable of improving the quality of a Si film to be formed when the Si film is formed on a substrate having an insulating film exposed on at least a part of the surface.

According to one aspect of the invention,
A substrate made of single crystal silicon;
An insulating film formed on the surface of the substrate;
A first silicon film formed by homoepitaxial growth on the single crystal silicon using the single crystal silicon as a base; and
A second silicon film formed on the insulating film and having a crystal structure different from that of the first silicon film;
A technique is provided.

  According to the present invention, it is possible to improve the quality of the Si film formed on the substrate where the single crystal Si and the insulating film are exposed.

It is a schematic block diagram of the vertical processing furnace of the substrate processing apparatus used suitably by one Embodiment of this invention, and is a figure which shows a processing furnace part with a longitudinal cross-sectional view. It is a schematic block diagram of the vertical processing furnace of the substrate processing apparatus used suitably by one Embodiment of this invention, and is a figure which shows a processing furnace part with the sectional view on the AA line of FIG. It is a schematic block diagram of the controller of the substrate processing apparatus used suitably by one Embodiment of this invention, and is a figure which shows the control system of a controller with a block diagram. It is a figure which shows the timing of the gas supply in the film-forming sequence of one Embodiment of this invention. (A) shows the surface structure of the wafer before the start of the parallel seed step, (b) shows the surface structure of the wafer after the DCS gas supply is in progress, and (c) shows the parallel seed step in progress. (D) shows the surface structure of the wafer after completion of the parallel seed step, (e) shows the surface structure of the wafer during the CVD film forming step, and (f) shows the CVD. (G) is a diagram showing the surface structure of the wafer after completion of the annealing step. It is a figure which shows the modification 1 of the timing of the gas supply in the film-forming sequence of one Embodiment of this invention. It is a figure which shows the modification 2 of the timing of the gas supply in the film-forming sequence of one Embodiment of this invention. It is a figure which shows the modification 3 of the timing of the gas supply in the film-forming sequence of one Embodiment of this invention. It is a figure which shows the modification 4 of the timing of the gas supply in the film-forming sequence of one Embodiment of this invention. It is a figure which shows the modification 5 of the timing of the gas supply in the film-forming sequence of one Embodiment of this invention. It is a figure which shows the modification 6 of the timing of the gas supply in the film-forming sequence of one Embodiment of this invention. (A) is a surface structure example 1 on the wafer to be processed, (b) is a surface structure example 2 on the wafer to be processed, (c) is a surface structure example 3 on the wafer to be processed, and (d) is a process. It is a figure which shows the surface structure example 4 in the wafer of object. (A) is the TEM image which shows the cross-sectional structure of the surface in the sample 1 which performed the parallel seed process when forming Si film, (b) The sample which did not perform the parallel seed process when forming Si film 2 is a TEM image showing a cross-sectional structure of a surface in 2. (A) is a schematic block diagram of the processing furnace of the substrate processing apparatus used suitably by other embodiment of this invention, and is a figure which shows a processing furnace part with a longitudinal cross-sectional view, (b) is other of this invention It is a schematic block diagram of the processing furnace of the substrate processing apparatus used suitably by this embodiment, and is a figure which shows a processing furnace part with a longitudinal cross-sectional view. (A) is a process of a dynamic random access memory (DRAM) manufacturing process, (b) is a process of a DRAM manufacturing process, (c) is a process of a DRAM manufacturing process, and (d) is a DRAM process. (E) is a process of the DRAM manufacturing process, (f) is a process of the DRAM manufacturing process, (g) is a process of the DRAM manufacturing process, (h) FIG. 8 is a diagram showing a process of manufacturing a DRAM. (A) is a process of the DRAM manufacturing process, (b) is a process of the DRAM manufacturing process, (c) is a process of the DRAM manufacturing process, and (d) is a process of the DRAM manufacturing process. (E) is a diagram showing a process of the DRAM manufacturing process, (f) is a process of the DRAM manufacturing process, and (g) is a diagram showing a process of the DRAM manufacturing process. (A) shows one step of the manufacturing process of the three-dimensional NAND flash memory (3DNAND), (b) shows one step of the manufacturing process of 3DNAND, (c) shows one step of the manufacturing process of 3DNAND, (d) (E) shows one step of the 3DNAND manufacturing process, (f) shows one step of the 3DNAND manufacturing process, (g) shows one step of the 3DNAND manufacturing process, h) is a diagram showing one process of manufacturing 3D NAND.

<One Embodiment of the Present Invention>
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

(1) Configuration of Substrate Processing Apparatus As shown in FIG. 1, the processing furnace 202 has a heater 207 as heating means (heating mechanism). The heater 207 has a cylindrical shape and is vertically installed by being supported by a heater base (not shown) as a holding plate. As will be described later, the heater 207 also functions as an activation mechanism (excitation unit) that activates (excites) gas with heat.

Inside the heater 207, a reaction tube 203 constituting a reaction vessel (processing vessel) concentrically with the heater 207 is disposed. The reaction tube 203 is made of a heat-resistant material such as quartz (SiO ₂ ) or silicon carbide (SiC), and is formed in a cylindrical shape with the upper end closed and the lower end opened. A processing chamber 201 is formed in the cylindrical hollow portion of the reaction tube 203. The processing chamber 201 is configured to be able to accommodate wafers 200 as substrates in a state where they are aligned in multiple stages in a vertical posture in a horizontal posture by a boat 217 described later.

  In the processing chamber 201, nozzles 249 a and 249 b are provided so as to penetrate the lower side wall of the reaction tube 203. The nozzles 249a and 249b are made of a heat resistant material such as quartz or SiC. Gas supply pipes 232a and 232b are connected to the nozzles 249a and 249b, respectively. A gas supply pipe 232c is connected to the gas supply pipe 232b. As described above, the reaction tube 203 is provided with the two nozzles 249a and 249b and the three gas supply tubes 232a to 232c, and can supply a plurality of types of gases into the processing chamber 201. It has become.

  However, the processing furnace 202 of this embodiment is not limited to the above-mentioned form. For example, a metal manifold that supports the reaction tube 203 may be provided below the reaction tube 203, and each nozzle may be provided so as to penetrate the side wall of the manifold. In this case, an exhaust pipe 231 described later may be further provided in the manifold. Even in this case, the exhaust pipe 231 may be provided below the reaction pipe 203 instead of the manifold. As described above, the furnace port of the processing furnace 202 may be made of metal, and a nozzle or the like may be attached to the metal furnace port.

  In the gas supply pipes 232a to 232c, a mass flow controller (MFC) 241a to 241c that is a flow rate controller (flow rate control unit) and valves 243a to 243c that are on-off valves are provided in order from the upstream direction. Gas supply pipes 232d and 232e for supplying an inert gas are connected to the downstream sides of the valves 243a and 243b of the gas supply pipes 232a and 232b, respectively. The gas supply pipes 232d and 232e are provided with MFCs 241d and 241e as flow rate controllers (flow rate control units) and valves 243d and 243e as opening / closing valves, respectively, in order from the upstream direction.

  Nozzles 249a and 249b are connected to the distal ends of the gas supply pipes 232a and 232b, respectively. As shown in FIG. 2, the nozzles 249 a and 249 b are arranged in an annular space in plan view between the inner wall of the reaction tube 203 and the wafer 200, along the upper portion from the lower portion of the inner wall of the reaction tube 203. Each is provided so as to rise upward in the arrangement direction. That is, the nozzles 249a and 249b are respectively provided along the wafer arrangement area in the area horizontally surrounding the wafer arrangement area on the side of the wafer arrangement area where the wafers 200 are arranged. In other words, the nozzles 249a and 249b are respectively provided perpendicular to the surface (flat surface) of the wafer 200 on the side of the end (periphery) of the wafer 200 carried into the processing chamber 201. The nozzles 249a and 249b are each configured as an L-shaped long nozzle, and each horizontal portion thereof is provided so as to penetrate the lower side wall of the reaction tube 203, and each vertical portion thereof is at least arranged in a wafer array. It is provided so as to rise from one end side of the region toward the other end side. Gas supply holes 250a and 250b for supplying gas are provided on the side surfaces of the nozzles 249a and 249b, respectively. The gas supply holes 250 a and 250 b are opened so as to face the center of the reaction tube 203, and gas can be supplied toward the wafer 200. A plurality of gas supply holes 250a and 250b are provided from the lower part to the upper part of the reaction tube 203, each having the same opening area, and further provided at the same opening pitch.

  Thus, in the present embodiment, an annular shape in a plan view defined by the inner wall of the side wall of the reaction tube 203 and the ends (peripheral portions) of the plurality of wafers 200 arranged in the reaction tube 203 is provided. Gas is conveyed through nozzles 249a and 249b arranged in a vertically long space, that is, in a cylindrical space. Then, gas is first ejected into the reaction tube 203 from the gas supply holes 250a and 250b opened in the nozzles 249a and 249b, respectively, in the vicinity of the wafer 200. The main flow of gas in the reaction tube 203 is a direction parallel to the surface of the wafer 200, that is, a horizontal direction. With such a configuration, it is possible to supply gas uniformly to each wafer 200 and improve the film thickness uniformity of the thin film formed on each wafer 200. The gas flowing on the surface of the wafer 200, that is, the residual gas after the reaction, flows toward the exhaust port, that is, the direction of the exhaust pipe 231 described later. However, the direction of the remaining gas flow is appropriately specified depending on the position of the exhaust port, and is not limited to the vertical direction.

  A gas containing silicon (Si) and a halogen element, that is, a halosilane source gas, is supplied from the gas supply pipe 232a into the processing chamber 201 through the MFC 241a, the valve 243a, and the nozzle 249a as the first processing gas. The

  The halosilane raw material gas is a gaseous halosilane raw material, for example, a gas obtained by vaporizing a halosilane raw material in a liquid state at normal temperature and normal pressure, a halosilane raw material in a gaseous state at normal temperature and normal pressure, or the like. The halosilane raw material is a silane raw material having a halogen group. The halogen group includes chloro group, fluoro group, bromo group, iodo group and the like. That is, the halogen group includes halogen elements such as chlorine (Cl), fluorine (F), bromine (Br), iodine (I) and the like. It can be said that the halosilane raw material is a kind of halide. In the present specification, when the term “raw material” is used, it means “a raw material in a liquid state”, “a raw material in a gas state (raw material gas)”, or both of them. There is a case.

As the first processing gas, for example, a halosilane source gas containing Si and Cl, that is, a chlorosilane source gas containing silane chloride (a chlorine compound of silicon) can be used. As the chlorosilane source gas, for example, dichlorosilane (SiH ₂ Cl ₂ , abbreviation: DCS) gas containing one Si atom, two Cl atoms, and two hydrogen (H) atoms in one molecule (in the molecular structure). Can be used.

Further, from the gas supply pipe 232a, a gas containing an impurity (dopant) added to the finally formed Si film as a dopant gas enters the processing chamber 201 through the MFC 241a, the valve 243a, and the nozzle 249a. Supplied. As the dopant gas, a gas containing any one of Group III elements and Group V elements can be used. For example, a phosphine containing one phosphorus (P) atom and three H atoms in one molecule ( PH ₃ (abbreviation: PH) gas can be used.

From the gas supply pipe 232b, a silane source gas containing Si and not containing a halogen element is supplied into the processing chamber 201 as the second processing gas through the MFC 241b, the valve 243b, and the nozzle 249b. As the second processing gas, hydrogenated silane (silicon hydride), that is, a hydrogenated silane source gas containing a hydrogen compound of silicon can be used, for example, two Si atoms and six H atoms in one molecule. Disilane (Si ₂ H ₆ , abbreviation: DS) gas containing atoms and not containing a halogen element can be used.

From the gas supply pipe 232c, a silane source gas containing Si as a third processing gas is supplied into the processing chamber 201 via the MFC 241c, the valve 243c, the gas supply pipe 232b, and the nozzle 249b. As the third processing gas, hydrogenated silane (silicon hydride), that is, a hydrogenated silane source gas containing a hydrogen compound of silicon can be used, for example, one Si atom and four H atoms in one molecule. A monosilane (SiH ₄ , abbreviation: MS) gas that contains atoms and does not contain a halogen element can be used.

From the gas supply pipes 232d and 232e, for example, nitrogen (N ₂ ) gas is used as an inert gas via the MFCs 241d and 241e, valves 243d and 243e, gas supply pipes 232a and 232b, and nozzles 249a and 249b, respectively. Supplied into 201.

  When the first processing gas is supplied from the gas supply pipe 232a, the first processing gas supply system is mainly configured by the gas supply pipe 232a, the MFC 241a, and the valve 243a. The nozzle 249a may be included in the first processing gas supply system. The first processing gas supply system can also be referred to as a first raw material gas supply system or a first raw material supply system. When supplying the halosilane source gas from the gas supply pipe 232a, the first processing gas supply system may be referred to as a halosilane source gas supply system or a halosilane source supply system.

  When supplying dopant gas from the gas supply pipe 232a, a dopant gas supply system is mainly configured by the gas supply pipe 232a, the MFC 241a, and the valve 243a. The nozzle 249a may be included in the dopant gas supply system. The dopant gas supply system can also be referred to as a dopant supply system.

  When the second processing gas is supplied from the gas supply pipe 232b, the second processing gas supply system is mainly configured by the gas supply pipe 232b, the MFC 241b, and the valve 243b. The nozzle 249b may be included in the second processing gas supply system. The second processing gas supply system can also be referred to as a second raw material gas supply system or a second raw material supply system. When the hydrogenated silane raw material gas is supplied from the gas supply pipe 232b, the second processing gas supply system may be referred to as a hydrogenated silane raw material gas supply system or a hydrogenated silane raw material supply system.

  When the third processing gas is supplied from the gas supply pipe 232c, the third processing gas supply system is mainly configured by the gas supply pipe 232c, the MFC 241c, and the valve 243c. The nozzle 249b may be included in the third processing gas supply system on the downstream side of the connection portion of the gas supply pipe 232b with the gas supply pipe 232c. The third processing gas supply system can also be referred to as a third raw material gas supply system or a third raw material supply system. When the hydrogenated silane source gas is supplied from the gas supply pipe 232c, the third processing gas supply system can also be referred to as a hydrogenated silane source gas supply system or a hydrogenated silane source supply system.

  Any or all of the first to third process gas supply systems may be referred to as a process gas supply system or a film formation gas supply system. The dopant gas supply system can be considered to be included in the film forming gas supply system (processing gas supply system).

  Further, an inert gas supply system is mainly configured by the gas supply pipes 232d and 232e, the MFCs 241d and 241e, and the valves 243d and 243e. The inert gas supply system can also be referred to as a purge gas supply system, a dilution gas supply system, or a carrier gas supply system.

  Any or all of the various gas supply systems described above may be configured as an integrated gas supply system 248 in which valves 243a to 243e, MFCs 241a to 241e, and the like are integrated. The integrated gas supply system 248 is connected to each of the gas supply pipes 232a to 232e, and supplies various gases into the gas supply pipes 232a to 232e, that is, opens and closes the valves 243a to 243e and MFCs 241a to 241e. The flow rate adjusting operation or the like is controlled by a controller 121 described later. The integrated gas supply system 248 is configured as an integral or divided type integrated unit, and can be attached to and detached from the gas supply pipes 232a to 232e in units of integrated units, and maintenance of the gas supply system. , Replacement, expansion, etc. can be performed in units of integrated units. The various gas supply systems described above can also be referred to as a gas supply unit, a gas supply system, and a gas supply unit, respectively.

  The reaction tube 203 is provided with an exhaust pipe 231 for exhausting the atmosphere in the processing chamber 201. The exhaust pipe 231 is connected via a pressure sensor 245 as a pressure detector (pressure detection unit) for detecting the pressure in the processing chamber 201 and an APC (Auto Pressure Controller) valve 244 as a pressure regulator (pressure adjustment unit). A vacuum pump 246 as a vacuum exhaust device is connected. The APC valve 244 can open and close the vacuum pump 246 while the vacuum pump 246 is in operation, thereby evacuating and stopping the vacuum exhaust in the processing chamber 201. Further, with the vacuum pump 246 in an operating state, The valve is configured such that the pressure in the processing chamber 201 can be adjusted by adjusting the valve opening based on the pressure information detected by the pressure sensor 245. An exhaust system (exhaust system) is mainly configured by the exhaust pipe 231, the APC valve 244, and the pressure sensor 245. The vacuum pump 246 may be included in the exhaust system.

  Below the reaction tube 203, a seal cap 219 is provided as a furnace opening lid capable of airtightly closing the lower end opening of the reaction tube 203. The seal cap 219 is configured to contact the lower end of the reaction tube 203 from the lower side in the vertical direction. The seal cap 219 is made of a metal such as SUS and is formed in a disk shape. On the upper surface of the seal cap 219, an O-ring 220 is provided as a seal member that comes into contact with the lower end of the reaction tube 203. On the opposite side of the seal cap 219 from the processing chamber 201, a rotation mechanism 267 for rotating a boat 217 described later is installed. A rotation shaft 255 of the rotation mechanism 267 passes through the seal cap 219 and is connected to the boat 217. The rotation mechanism 267 is configured to rotate the wafer 200 by rotating the boat 217. The seal cap 219 is configured to be lifted and lowered in the vertical direction by a boat elevator 115 as a lifting mechanism vertically installed outside the reaction tube 203. The boat elevator 115 is configured so that the boat 217 can be carried in and out of the processing chamber 201 by moving the seal cap 219 up and down. That is, the boat elevator 115 is configured as a transfer device (transfer mechanism) that transfers the boat 217, that is, the wafers 200 into and out of the processing chamber 201.

  The boat 217 as a substrate support is configured to support a plurality of, for example, 25 to 200 wafers 200 in a horizontal posture and in a multi-stage by aligning them in the vertical direction with their centers aligned. It is configured to arrange at intervals. The boat 217 is made of a heat-resistant material such as quartz or SiC. Under the boat 217, heat insulating plates 218 made of a heat-resistant material such as quartz or SiC are supported in multiple stages in a horizontal posture. With this configuration, heat from the heater 207 is not easily transmitted to the seal cap 219 side. However, this embodiment is not limited to the above-mentioned form. For example, instead of providing the heat insulating plate 218 in the lower portion of the boat 217, a heat insulating cylinder configured as a cylindrical member made of a heat resistant material such as quartz or SiC may be provided.

  A temperature sensor 263 is installed in the reaction tube 203 as a temperature detector. By adjusting the power supply to the heater 207 based on the temperature information detected by the temperature sensor 263, the temperature in the processing chamber 201 becomes a desired temperature distribution. The temperature sensor 263 is configured in an L shape similarly to the nozzles 249a and 249b, and is provided along the inner wall of the reaction tube 203.

  As shown in FIG. 3, the controller 121, which is a control unit (control means), is configured as a computer including a CPU (Central Processing Unit) 121a, a RAM (Random Access Memory) 121b, a storage device 121c, and an I / O port 121d. Has been. The RAM 121b, the storage device 121c, and the I / O port 121d are configured to exchange data with the CPU 121a via the internal bus 121e. For example, an input / output device 122 configured as a touch panel or the like is connected to the controller 121.

  The storage device 121c is configured by, for example, a flash memory, an HDD (Hard Disk Drive), or the like. In the storage device 121c, a control program that controls the operation of the substrate processing apparatus, a process recipe that describes the procedure and conditions of the substrate processing described later, and the like are stored in a readable manner. The process recipe is a combination of the controller 121 that allows the controller 121 to execute each procedure in the substrate processing process described later and obtain a predetermined result, and functions as a program. Hereinafter, the process recipe, the control program, and the like are collectively referred to simply as a program. The process recipe is also simply called a recipe. When the term “program” is used in this specification, it may include only a recipe, only a control program, or both. The RAM 121b is configured as a memory area (work area) in which programs, data, and the like read by the CPU 121a are temporarily stored.

  The I / O port 121d is connected to the above-described MFCs 241a to 241e, valves 243a to 243e, pressure sensor 245, APC valve 244, vacuum pump 246, heater 207, temperature sensor 263, rotating mechanism 267, boat elevator 115, and the like. .

  The CPU 121a is configured to read and execute a control program from the storage device 121c and to read a recipe from the storage device 121c in response to an operation command input from the input / output device 122 or the like. The CPU 121a adjusts the flow rate of various gases by the MFCs 241a to 241e, the opening / closing operation of the valves 243a to 243e, the opening / closing operation of the APC valve 244, and the pressure adjustment by the APC valve 244 based on the pressure sensor 245 so as to follow the contents of the read recipe. Operation, start and stop of the vacuum pump 246, temperature adjustment operation of the heater 207 based on the temperature sensor 263, rotation and rotation speed adjustment operation of the boat 217 by the rotation mechanism 267, lifting and lowering operation of the boat 217 by the boat elevator 115, etc. It is configured.

  The controller 121 is stored in an external storage device 123 (for example, a magnetic tape, a magnetic disk such as a flexible disk or a hard disk, an optical disk such as a CD or a DVD, a magneto-optical disk such as an MO, or a semiconductor memory such as a USB memory or a memory card). The above-mentioned program can be configured by installing it in a computer. The storage device 121c and the external storage device 123 are configured as computer-readable recording media. Hereinafter, these are collectively referred to simply as a recording medium. When the term “recording medium” is used in this specification, it may include only the storage device 121c alone, may include only the external storage device 123 alone, or may include both of them. The program may be provided to the computer using a communication means such as the Internet or a dedicated line without using the external storage device 123.

(2) Substrate Processing Step As an example of a semiconductor device (device) manufacturing process using the above-described substrate processing apparatus, a sequence example in which a Si film is formed on a substrate and the Si film is heat-treated is shown in FIG. This will be described with reference to FIGS. In the following description, the operation of each part constituting the substrate processing apparatus is controlled by the controller 121.

In the film forming sequence shown in FIG.
Step 1 of supplying a DCS gas as a first processing gas to a wafer 200 as a substrate having exposed single crystal Si and an insulating film 200a on the surface, and DS as a second processing gas to the wafer 200 A step of alternately supplying gas 2 and a step of performing a parallel seed step (parallel seed step);
Supplying MS gas as a third processing gas to the wafer 200 (CVD film forming step);
Thus, the first Si film 200e is homoepitaxially grown on the single crystal Si, and the second Si film 200g having a crystal structure different from that of the first Si film 200e is grown on the insulating film 200a. That is, in the film forming sequence shown in FIG. 4, the second Si film 200g is formed on the first Si film 200e on the single crystal Si by using three kinds of silane source gases (triple Si source). A laminated structure (laminated film) is formed. Hereinafter, this laminated film is also simply referred to as a Si film.

  Thereafter, the Si film in which the second Si film 200g is formed on the first Si film 200e is heat-treated (annealed), whereby the first Si film 200e (homoepitaxial Si) in the second Si film 200g. A step (annealing step) of homoepitaxializing the portion in contact with the film) is performed.

  In this specification, the above-described film forming sequence may be indicated as follows for convenience. Annealing may also be referred to as ANL.

[(DCS → DS) × n → MS] → ANL ⇒ Si

  In this specification, when the term “wafer” is used, it means “wafer itself” or “a laminate (aggregate) of a wafer and a predetermined layer or film formed on the surface”. In other words, it may be called a wafer including a predetermined layer or film formed on the surface. In addition, when the term “wafer surface” is used in this specification, it means “the surface of the wafer itself (exposed surface)” or “the surface of a predetermined layer or film formed on the wafer”. That is, it may mean “the outermost surface of the wafer as a laminated body”.

  Therefore, in the present specification, the phrase “supplying a predetermined gas to the wafer” means “supplying a predetermined gas directly to the surface (exposed surface) of the wafer itself”. , It may mean that “a predetermined gas is supplied to a layer, a film, or the like formed on the wafer, that is, to the outermost surface of the wafer as a laminated body”. Further, in this specification, when “describe a predetermined layer (or film) on the wafer” is described, “determine a predetermined layer (or film) directly on the surface (exposed surface) of the wafer itself”. This means that a predetermined layer (or film) is formed on a layer or film formed on the wafer, that is, on the outermost surface of the wafer as a laminate. There is a case.

  In this specification, the term “substrate” is also synonymous with the term “wafer”.

(Wafer charge and boat load)
A plurality of wafers 200 are loaded into the boat 217 (wafer charge). Thereafter, as shown in FIG. 1, the boat 217 that supports the plurality of wafers 200 is lifted by the boat elevator 115 and loaded into the processing chamber 201 (boat loading). In this state, the seal cap 219 seals the lower end of the reaction tube 203 via the O-ring 220.

As the wafer 200, for example, a Si substrate made of single crystal Si or a substrate having a single crystal Si film formed on the surface can be used. As shown in the partially enlarged view of FIG. 12A, an insulating film 200a such as a silicon oxide film (SiO ₂ film, hereinafter also referred to as SiO film) is formed on a part of the surface of the wafer 200 in advance. ing. That is, the surface of the wafer 200 is in a state where the single crystal Si and the insulating film 200a are exposed. In addition to the SiO film, the insulating film 200a includes a silicon nitride film (SiN film), a silicon carbide film (SiC film), a silicon carbonitride film (SiCN film), a silicon oxynitride film (SiON film), and a silicon oxycarbide film (SiOC). Film), silicon oxycarbonitride film (SiOCN film), silicon boronitride film (SiBN film), silicon borocarbonitride film (SiBCN film), etc., silicon oxide film, aluminum oxide film (AlO film), hafnium oxide film It may be a metal insulating film such as (HfO film), zirconium oxide film (ZrO film), titanium oxide film (TiO film). That is, the insulating film 200a may be a high-k film (high dielectric constant insulating film) such as a HfO film or a ZrO film, and a low-k film such as a SiOCN film, a SiOC film, a SiBN film, or a SiBCN film. (Low dielectric constant insulating film) may be used.

  5 (a) to 5 (g) show a case where the wafer 200 having the surface structure shown in FIG. 12 (a) is processed, that is, the surface is provided with a recess, and the bottom of the recess is made of single crystal Si. A case is shown in which a wafer 200 is processed, in which side portions and upper portions of the recesses are formed of an insulating film (SiO film) 200a. 5A to 5G are views in which the surface of the wafer 200 is partially enlarged for convenience. Before the wafer 200 is carried into the processing chamber 201, the surface of the wafer 200 is previously cleaned with hydrogen fluoride (HF) or the like. However, the surface of the wafer 200 is temporarily exposed to the atmosphere after the cleaning process and before being carried into the processing chamber 201. Therefore, as shown in FIG. 5A, a natural oxide film (SiO film) 200b is formed on at least a part of the surface of the wafer 200 carried into the processing chamber 201. The natural oxide film 200b may be formed so as to cover the bottom of the concave portion, that is, a part of the exposed single crystal Si sparsely (in an island shape), or continuously over the entire exposed single crystal Si. It may be formed so as to cover (non-island shape).

(Pressure adjustment and temperature adjustment)
Vacuum exhaust (reduced pressure) is performed by the vacuum pump 246 so that the processing chamber 201, that is, the space where the wafer 200 exists, has a desired pressure (degree of vacuum). At this time, the pressure in the processing chamber 201 is measured by the pressure sensor 245, and the APC valve 244 is feedback-controlled based on the measured pressure information. The vacuum pump 246 maintains a state in which it is always operated until at least the processing on the wafer 200 is completed. Further, the wafer 200 in the processing chamber 201 is heated by the heater 207 so as to reach a desired temperature. At this time, the power supply to the heater 207 is feedback-controlled based on the temperature information detected by the temperature sensor 263 so that the inside of the processing chamber 201 has a desired temperature distribution. Heating of the processing chamber 201 by the heater 207 is continuously performed at least until the processing on the wafer 200 is completed. Further, the rotation of the boat 217 and the wafers 200 by the rotation mechanism 267 is started. The rotation of the boat 217 and the wafer 200 by the rotation mechanism 267 is continuously performed at least until the processing on the wafer 200 is completed.

(Parallel seed step)
Thereafter, the next two steps, that is, steps 1 and 2 are sequentially executed.

[Step 1]
(DCS gas supply)
In this step, DCS gas is supplied to the wafer 200 in the processing chamber 201.

The valve 243a is opened and DCS gas is allowed to flow into the gas supply pipe 232a. The flow rate of the DCS gas is adjusted by the MFC 241a, supplied into the processing chamber 201 through the nozzle 249a, and exhausted from the exhaust pipe 231. At this time, DCS gas is supplied to the wafer 200. At the same time, the valve 243d is opened and N ₂ gas is allowed to flow into the gas supply pipe 232d. The flow rate of the N ₂ gas is adjusted by the MFC 241d, supplied into the processing chamber 201 together with the DCS gas, and exhausted from the exhaust pipe 231. Further, in order to prevent DCS gas from entering the nozzle 249b, the valve 243e is opened, and N ₂ gas is allowed to flow into the gas supply pipe 232e. The N ₂ gas is supplied into the processing chamber 201 through the gas supply pipe 232b and the nozzle 249b, and is exhausted from the exhaust pipe 231.

  By supplying the DCS gas to the wafer 200, the following processing can be performed to change the surface state of the wafer 200 to the state shown in FIG.

  First, oxygen (O) in the natural oxide film 200b formed on the surface of the single crystal Si is supplied by supplying DCS containing halogen (Cl) having a large electronegativity at the bottom of the recess, that is, on the single crystal Si. ) And Cl in DCS attract each other, and the Si—O bond contained in the natural oxide film 200b can be cut. Thereby, the Si bond on the surface of the single crystal Si becomes free. In other words, Si dangling bonds (unbonded hands) can be generated on the surface of single crystal Si. As a result, an environment in which homoepitaxial growth, which will be described later, easily proceeds, is prepared. In addition, in the bottom part of a recessed part, the above-mentioned reaction advances and the natural oxide film 200b formed in the surface will be removed. That is, the DCS gas acts as a cleaning gas (cleaning gas) for removing the natural oxide film 200b from the surface of the single crystal Si.

  Further, on the side and upper part of the recess, that is, on the insulating film (SiO film) 200a, by supplying DCS containing halogen (Cl) having a high electronegativity, O and DCS on the surface of the insulating film 200a are supplied. Cl is attracted to the Si—O bond contained in the insulating film 200a. Thereby, Si dangling bonds, that is, Si adsorption sites can be formed on the surface of the insulating film 200a. Note that, on the insulating film 200a such as an SiO film, Si dangling bonds originally do not exist, or even if there are few. Therefore, in this state, even if Step 2 (to be described later) for supplying DS gas to the wafer 200 is performed, Si nuclei do not grow on the surface of the insulating film 200a, or even if grown, random growth (island) Growth).

(Residual gas removal)
When an environment in which homoepitaxial growth is likely to proceed at the bottom of the recess is ready, and Si adsorption sites are formed at the side and top of the recess, the valve 243a is closed and the supply of DCS gas is stopped. At this time, the APC valve 244 is kept open, the inside of the processing chamber 201 is evacuated by the vacuum pump 246, and the unreacted gas remaining in the processing chamber 201 or the gas after contributing to the above-mentioned reaction is sent from the processing chamber 201. Exclude. At this time, the valves 243d and 243e remain open, and the supply of N ₂ gas into the processing chamber 201 is maintained. The N ₂ gas acts as a purge gas, which can enhance the effect of removing the gas remaining in the processing chamber 201 from the processing chamber 201.

At this time, the gas remaining in the processing chamber 201 may not be completely removed, and the inside of the processing chamber 201 may not be completely purged. If the amount of gas remaining in the processing chamber 201 is very small, there will be no adverse effect in the subsequent step 2. The flow rate of the N ₂ gas supplied into the processing chamber 201 does not need to be a large flow rate. For example, by supplying an amount of N ₂ gas equivalent to the volume of the reaction tube 203 (processing chamber 201), step 2 is performed. Purging can be performed to such an extent that no adverse effect is caused. Thus, by not completely purging the inside of the processing chamber 201, the purge time can be shortened and the throughput can be improved. The consumption of N ₂ gas can be suppressed to the minimum necessary.

[Step 2]
(DS gas supply)
After step 1 is completed, DS gas is supplied to the wafer 200 in the processing chamber 201.

  In this step, the opening / closing control of the valves 243b, 243d, 243e is performed in the same procedure as the opening / closing control of the valves 243a, 243d, 243e in Step 1. The DS gas flowing through the gas supply pipe 232b is adjusted in flow rate by the MFC 241b, supplied into the processing chamber 201 through the nozzle 249b, and exhausted from the exhaust pipe 231. At this time, DS gas is supplied to the wafer 200.

  By supplying the DS gas to the wafer 200, the following processing is performed, and the surface state of the wafer 200 is changed to the state shown in FIG. 5C, that is, two seeds are formed in parallel. And can be migrated.

  First, at the bottom of the recess, that is, on single crystal Si, Si contained in DS is bonded to the Si dangling bonds formed by performing Step 1, and Si crystal is epitaxially grown on single crystal Si ( Vapor phase epitaxial growth). Since the crystal serving as the base and the crystal growing on the crystal are the same material (Si), this growth is homoepitaxial growth. In homoepitaxial growth, a crystal having the same lattice constant as this crystal and made of the same material grows on the underlying crystal in the same crystal orientation. Therefore, in homoepitaxial growth, it is possible to obtain a high-quality crystal with fewer defects compared to heteroepitaxial growth in which the underlying crystal and the crystal grown on this crystal are different materials. The nucleus (or film) formed at this time can be considered as a seed (first seed) 200c of a first Si film (epitaxial Si film) 200e described later.

  Further, Si contained in the DS can be adsorbed on the adsorbing sites formed by performing Step 1 on the side and upper portions of the recesses, that is, on the insulating film 200a. The crystal structure of the nucleus formed by the adsorption of Si at the adsorption site is amorphous (amorphous), poly (polycrystalline), or a mixed crystal of amorphous and poly. The nucleus formed at this time can be considered as a seed (second seed) 200d of a second Si film 200g described later.

(Residual gas removal)
When the formation of the first seed 200c and the second seed 200d, that is, the formation of two kinds of seeds (parallel seed processing) is completed, the valve 243b is closed and the supply of the DS gas is stopped. Then, by the same processing procedure as in Step 1, unreacted gas remaining in the processing chamber 201 or after having contributed to the above reaction and reaction by-products are removed from the processing chamber 201. At this time, it is the same as in step 1 that the gas remaining in the processing chamber 201 does not have to be completely removed.

[Perform a specified number of times]
In the parallel seed step, a cycle in which Steps 1 and 2 described above are performed alternately, that is, non-simultaneously without being synchronized is performed a predetermined number of times (one or more times). By performing the parallel seed step, the following processing can be advanced to shift the surface state of the wafer 200 to the state shown in FIG.

  First, the first Si film 200e can be formed on the bottom of the recess, that is, on the single crystal Si. The first Si film 200e is formed by homoepitaxial growth of the Si crystal using the first seed 200c formed on the single crystal Si as a nucleus. The crystal structure of the first Si film 200e is a single crystal that inherits the crystallinity of the base. That is, the first Si film 200e is a single crystal Si film (epitaxial Si film) made of the same material as the underlying single crystal Si and having the same lattice constant and the same crystal orientation. The first Si film 200e formed by the parallel seed step can also be considered as a seed layer. In this case, the seed layer is composed of an epitaxial Si layer. The seed layer composed of this epitaxial Si layer can also be referred to as a first seed layer.

  Further, a seed layer 200f can be formed on the side and upper part of the recess, that is, on the insulating film 200a. The seed layer 200f is formed by growing the second seed 200d at a high density on the insulating film 200a, and becomes a layer that densely covers the surface of the insulating film 200a. The crystal structure of the seed layer 200f is amorphous, poly, or a mixed crystal of amorphous and poly. That is, the seed layer 200f is an amorphous Si layer, a poly Si layer, or a mixed crystal Si layer of amorphous and poly. The seed layer 200f can also be referred to as a second seed layer.

  Thus, in the parallel seed step, the first seed layer (epitaxial Si layer) and the second seed layer (amorphous Si layer, poly-Si layer, or amorphous and poly-layer are formed on the single crystal Si and the insulating film 200a. The mixed crystal Si layers) are formed in parallel. That is, in the parallel seed step, two types of Si seed layers having different crystal structures are formed in parallel. This is why this step is called a parallel seed step.

[Parallel seed step processing conditions]
In step 1, the supply flow rate of the DCS gas controlled by the MFC 241a is, for example, 10 to 1000 sccm, preferably 10 to 500 sccm. The time for supplying the DCS gas to the wafer 200, that is, the gas supply time (irradiation time) is, for example, 0.5 to 10 minutes, preferably 1 to 5 minutes.

  In step 2, the supply flow rate of the DS gas controlled by the MFC 241b is, for example, 10 to 1000 sccm, preferably 10 to 500 sccm. The time for supplying the DS gas to the wafer 200, that is, the gas supply time (irradiation time) is, for example, 0.5 to 10 minutes, preferably 1 to 5 minutes.

In steps 1 and 2, the supply flow rate of the N ₂ gas controlled by the MFCs 241d and 241e is set to a flow rate in the range of 100 to 10,000 sccm, for example.

  The pressure in the processing chamber 201 in steps 1 and 2 is, for example, 1 to 1000 Pa, preferably 1 to 100 Pa.

  The temperature of the heater 207 in steps 1 and 2 is set such that the temperature of the wafer 200 becomes a temperature (first temperature) within a range of 350 to 450 ° C., preferably 370 to 390 ° C., for example.

  When the temperature of the wafer 200 is less than 350 ° C., the DS supplied in Step 2 is difficult to be decomposed, and the formation of the first seed 200c and the second seed 200d on the wafer 200, that is, the first Si film 200e. Or the seed layer 200f may be difficult to form. By setting the temperature of the wafer 200 to 350 ° C. or higher, the above-described problems can be solved. By setting the temperature of the wafer 200 to 370 ° C. or higher, the decomposition of the DS supplied in Step 2 can be promoted, and the above-described Si—O bond breaking reaction by the DCS supplied in Step 1 is reliably advanced. It becomes possible to make it. That is, it is possible to reliably prepare an environment in which homoepitaxial growth is likely to proceed at the bottom of the recess, to reliably form Si adsorption sites at the side and top of the recess, and to form the first on the wafer 200. It is possible to reliably form the seed 200c and the second seed 200d, that is, the first Si film 200e and the seed layer 200f.

  When the temperature of the wafer 200 exceeds 450 ° C., Si included in the DCS supplied in Step 1 may be deposited on the wafer 200. In this case, Si is deposited before the natural oxide film is removed from the surface of the single crystal Si. Therefore, homoepitaxial growth does not proceed on single crystal Si (natural oxide film), and an amorphous Si film or a poly Si film grows. In addition, when the temperature of the wafer 200 exceeds 450 ° C., it may be difficult to advance the above-described Si—O bond breaking reaction by DCS. This may make it difficult to form the first seed 200c and the second seed 200d on the wafer 200, that is, to form the first Si film 200e and the seed layer 200f. By setting the temperature of the wafer 200 to 450 ° C. or less, the above-described problems can be solved. By setting the temperature of the wafer 200 to 390 ° C. or less, the above-described Si—O bond cleavage reaction by the DCS can be reliably advanced while reliably suppressing the deposition of Si contained in the DCS on the wafer 200. It becomes possible. In other words, it is possible to reliably prepare an environment in which homoepitaxial growth is likely to proceed at the bottom of the recess, and to reliably form Si adsorption sites at the side and top of the recess. This makes it possible to reliably form the first seed 200c and the second seed 200d on the wafer 200, that is, the formation of the first Si film 200e and the seed layer 200f.

  Therefore, the temperature of the wafer 200 is, for example, 350 to 450 ° C., preferably 370 to 390 ° C.

  The number of executions of the cycle in which Steps 1 and 2 are alternately performed is, for example, 1 to 20 times, preferably 1 to 10 times. The thickness of the first Si film 200e formed thereby and the thickness of the seed layer 200f are, for example, 1 to 50 mm, preferably 5 to 20 mm, respectively.

As the first processing gas, in addition to DCS gas, monochlorosilane (SiH ₃ Cl, abbreviation: MCS) gas, tetrachlorosilane, that is, silicon tetrachloride (SiCl ₄ , abbreviation: STC) gas, trichlorosilane (SiHCl ₃ , abbreviation: A chlorosilane source gas such as TCS) gas or hexachlorodisilane (Si ₂ Cl ₆ , abbreviation: HCDS) gas can be used. In step 1, in order to promote the above-described Si—O bond breaking reaction while suppressing the deposition of Si on the wafer 200, the number of Si contained in one molecule as the first processing gas. Therefore, it is preferable to use a halosilane source gas having a small number of halogen elements (such as Cl) contained in one molecule. Further, in Step 1, it is preferable to use a halosilane source gas having a small number of halogen elements (Cl or the like) contained in one molecule in order to appropriately suppress the above-described Si—O bond cleavage reaction.

As the second processing gas, a halogen element-free silane source gas such as MS gas, trisilane (Si ₃ H ₈ , abbreviation: TS) gas, or the like can be used in addition to the DS gas.

As the inert gas, for example, a rare gas such as Ar gas, He gas, Ne gas, and Xe gas can be used in addition to N ₂ gas.

(CVD deposition step)
After forming the first Si film 200e and the seed layer 200f, MS gas and PH gas are supplied to the wafer 200 in the processing chamber 201.

  In this step, the opening / closing control of the valves 243c, 243d, 243e is performed in the same procedure as the opening / closing control of the valves 243a, 243d, 243e in Step 1. The MS gas flowing in the gas supply pipe 232c is controlled in flow rate by the MFC 241c, supplied into the processing chamber 201 through the gas supply pipe 232b and the nozzle 249b, and exhausted from the exhaust pipe 231. At this time, the valve 243a is opened and PH gas is caused to flow into the gas supply pipe 232a. The pH of the PH gas is adjusted by the MFC 241a, supplied into the processing chamber 201 through the nozzle 249a, and exhausted from the exhaust pipe 231. At this time, the MS gas and the PH gas are supplied to the wafer 200 together and simultaneously.

  By supplying MS gas and PH gas to the wafer 200, the following processing can be performed to sequentially shift the surface of the wafer 200 to the state shown in FIGS. 5E and 5F. it can.

  First, as shown in FIG. 5E, on the bottom of the recess, that is, on the single crystal Si, the first Si film 200e formed by performing the parallel seed step is further homoepitaxially grown (vapor phase epitaxial growth). ). That is, an epitaxial Si film having the same crystal structure as that of the first Si film 200e can be further grown on the first Si film 200e in FIG. By supplying the PH gas together with the MS gas, a P component as a dopant can be added to the first Si film 200e.

  Further, as shown in FIG. 5E, on the side and upper part of the recess, that is, on the insulating film 200a, the second Si film 200g is formed on the seed layer 200f formed by performing the parallel seed step. Can be formed. The crystal structure of the second Si film 200g is amorphous, poly, or a mixed crystal of amorphous and poly. That is, the second Si film 200g is an amorphous Si film, a poly Si film, or a mixed crystal Si film of amorphous and poly. Since the seed layer 200f is very thin and the crystal structure and material are the same as those of the second Si film 200g, the seed layer 200f can be considered to be included in the second Si film 200g. By supplying the PH gas together with the MS gas, the P component as a dopant can be added also to the second Si film 200g.

  By continuing the above processing, the growth of the first Si film 200e can be stopped by the growth of the second Si film 200g. That is, as shown in FIG. 5F, the first Si film 200e is homoepitaxially grown by covering the upper part of the first Si film 200e with the second Si film 200g grown from the side of the recess. Can be stopped. In this state, a laminated structure (laminated film) in which the second Si film 200g is laminated on the first Si film 200e is formed in the recess, that is, on the wafer 200. The concave portion is closed by the laminated film, that is, embedded. As described above, in this specification, this laminated film may be simply referred to as a Si film.

  After the stacked film is formed, the valves 243c and 243a are closed, and the supply of MS gas and PH gas into the processing chamber 201 is stopped. Then, the unreacted gas remaining in the processing chamber 201 or the gas or reaction by-product that has contributed to the above reaction is removed from the processing chamber 201 by the same processing procedure as in Step 1 described above. At this time, it is the same as in step 1 that the gas remaining in the processing chamber 201 does not have to be completely removed.

[Processing conditions for CVD film formation step]
The supply flow rate of the MS gas controlled by the MFC 241c is, for example, a flow rate in the range of 10 to 2000 sccm, preferably 500 to 1000 sccm. The time for supplying the MS gas to the wafer 200, that is, the gas supply time (irradiation time) can be appropriately determined depending on the film thickness of the Si film formed on the wafer 200.

  The supply flow rate of the PH gas controlled by the MFC 241a is appropriately determined depending on the specifications of the device formed on the wafer 200, and is, for example, 0.1 to 500 sccm, preferably 1 to 100 sccm. The time for supplying the PH gas to the wafer 200, that is, the gas supply time (irradiation time) can be appropriately determined according to the specifications of the device formed on the wafer 200.

The supply flow rate of the N ₂ gas controlled by the MFCs 241d and 241e is, for example, a flow rate in the range of 100 to 10000 sccm.

  The pressure in the processing chamber 201 is, for example, 1 to 1000 Pa, preferably 1 to 100 Pa.

  The temperature of the heater 207 is set to a temperature at which the temperature of the wafer 200 becomes equal to or higher than the above-described first temperature (second temperature). Specifically, the temperature of the heater 207 is set to such a temperature that the temperature of the wafer 200 becomes a temperature (second temperature) in the range of 350 to 650 ° C., preferably 400 to 550 ° C., for example.

  When the temperature of the wafer 200 is lower than 350 ° C., the gas is difficult to be decomposed depending on the type of the third processing gas, and as a result, homoepitaxial growth of the first Si film 200e and formation processing of the second Si film 200g are performed. (Hereinafter, these processes are also referred to as a CVD film forming process) may be difficult to proceed. For example, when DS gas is used as the third processing gas, when the temperature of the wafer 200 is less than 350 ° C., DS is difficult to decompose and it is difficult to proceed with the above-described CVD film forming process. This can be eliminated by setting the temperature of the wafer 200 to 350 ° C. or higher. Further, when the temperature of the wafer 200 is set to 400 ° C. or higher, the above-described CVD film forming process can be facilitated. For example, when DS gas is used as the third processing gas, by making the temperature of the wafer 200 400 ° C. or higher, DS can be easily decomposed, and the above-described CVD film forming process can be reliably advanced. It becomes. In addition, when MS gas is used as the third processing gas, the temperature of the wafer 200 is set to 450 ° C. or more, so that MS can be easily decomposed and the above-described CVD film forming process can be progressed reliably. It becomes.

  When the temperature of the wafer 200 exceeds 650 ° C., the CVD reaction becomes too strong (excess gas phase reaction occurs), so that the film thickness uniformity tends to be deteriorated and the control becomes difficult. Further, there is a concern that particles may be generated in the processing chamber 201, and the film quality of the laminated film formed on the wafer 200 may be deteriorated. By setting the temperature of the wafer 200 to 650 ° C. or lower, an appropriate gas phase reaction can be caused, so that deterioration in film thickness uniformity can be suppressed and control thereof is possible. In addition, generation of particles in the processing chamber 201 can be suppressed. In particular, by setting the temperature of the wafer 200 to 550 ° C. or less, it becomes easy to ensure film thickness uniformity and control thereof becomes easy.

  Therefore, the temperature of the wafer 200 is, for example, 350 to 650 ° C., preferably 400 to 550 ° C. (second temperature). When the temperature of the wafer 200 is set to a temperature within the range of 350 to 520 ° C., the second Si film 200g tends to be an amorphous Si film. Further, when the temperature of the wafer 200 is set to a temperature in the range of 520 to 530 ° C., the second Si film 200g is more likely to be a mixed crystal Si film of amorphous and poly. Further, when the temperature of the wafer 200 is set to a temperature within the range of 530 to 650 ° C., the second Si film 200g tends to be a poly-Si film. In either case, the first Si film 200e is an epitaxial Si film.

  The thickness of the first Si film 200e grown in the CVD film forming step and the thickness of the second Si film 200g are determined as appropriate depending on the specifications of the device formed on the wafer 200. It can be 1 to 5000 mm.

  As the third processing gas, in addition to the MS gas, the above-described halogen element-free hydrogenated silane source gas and the above-described halosilane source gas can be suitably used. From the viewpoint of suppressing the remaining of the halogen element in the first Si film 200e and the second Si film 200g, it is preferable to use a hydrogenated silane source gas containing no halogen element as the third processing gas. . From the viewpoint of improving the deposition rate of the first Si film 200e and the second Si film 200g, it is preferable to use a highly reactive halosilane source gas as the third processing gas.

As the dopant gas, a gas containing a group V element (P, As, etc.) such as an arsine (AsH ₃ ) gas in addition to the PH gas can be used. Further, as the dopant gas, in addition to a gas containing a group V element, a gas containing a group III element (such as B) such as diborane (B ₂ H ₆ ) gas or trichloroborane (BCl ₃ ) gas can be used. .

As the inert gas, for example, a rare gas such as Ar gas, He gas, Ne gas, and Xe gas can be used in addition to N ₂ gas.

(Annealing step)
After the formation of the first Si film 200e and the second Si film 200g is completed, the temperature of the heater 207 is appropriately adjusted to form the first Si film 200e and the second Si film 200g formed on the wafer 200. Each is heat-treated.

This step may be performed while the valves 243d and 243e are opened and the N ₂ gas is supplied into the processing chamber 201, and the valves 243d and 243e are closed and the supply of the N ₂ gas to the processing chamber 201 is stopped. You may carry out in a state. In any case, this step is performed with the valves 243a to 243c closed and the supply of the silane source gas into the processing chamber 201 stopped.

  By performing the annealing step, the laminated film of the first Si film 200e and the second Si film 200g formed on the wafer 200 can be changed to the film shown in FIG. That is, the portion of the second Si film 200g (amorphous Si film, poly Si film, amorphous and poly mixed crystal Si film) that contacts the first Si film 200e (homoepitaxial Si film) is homoepitaxially formed. (Solid phase epitaxial growth) can be altered (modified) into a homoepitaxial Si film. In other words, a part of the crystal state of the second Si film 200g can be changed to the same crystal state as that of the first Si film 200e. This homoepitaxial region can be considered as a part of the first Si film 200e. That is, by performing the annealing step, the region occupied by the first Si film 200e in the laminated film can be expanded.

[Annealing step processing conditions]
The supply flow rate of the N ₂ gas controlled by the MFCs 241d and 241e is set to a flow rate in the range of 0 to 10,000 sccm, for example.

  The pressure in the processing chamber 201 is preferably set to a pressure less than atmospheric pressure. For example, the pressure in the range of 1 to 1000 Pa, preferably 1 to 100 Pa, is the same as when performing a parallel seed step or a CVD film forming step. To do.

  The temperature of the heater 207 is set to a temperature at which the temperature of the wafer 200 becomes equal to or higher than the above-described second temperature (third temperature). Specifically, the temperature of the heater 207 is set to such a temperature that the temperature of the wafer 200 becomes a temperature (third temperature) in the range of 500 to 700 ° C., preferably 550 to 600 ° C., for example.

  When the temperature of the wafer 200 is less than 500 ° C., solid phase epitaxial growth is difficult to proceed, and it may be difficult to homoepitaxialize the portion of the second Si film 200g that contacts the first Si film 200e. is there. This can be eliminated by setting the temperature of the wafer 200 to 500 ° C. or higher. By setting the temperature of the wafer 200 to 550 ° C. or higher, the growth efficiency of the solid phase epitaxial growth can be increased, and the portion of the second Si film 200g that contacts the first Si film 200e is efficiently homoepitaxially formed. It becomes possible to make it.

  When the temperature of the wafer 200 exceeds 700 ° C., the portion of the second Si film 200g that contacts the first Si film 200e may be polycrystallized without homoepitaxialization. This can be solved by setting the temperature of the wafer 200 to 700 ° C. or lower. By setting the temperature of the wafer 200 to 600 ° C. or less, it becomes easy to perform solid-phase epitaxial growth and homoepitaxial growth of the portion of the second Si film 200g that contacts the first Si film 200e.

  Therefore, the temperature of the wafer 200 is, for example, 500 to 700 ° C., preferably 550 to 600 ° C. (third temperature). In the above temperature range, the temperature of the wafer 200 is set to a temperature close to a low temperature, that is, the heat treatment slowly at a temperature close to the low temperature allows the solid phase epitaxial growth to proceed more appropriately. .

As the inert gas, an inexpensive and highly safe gas can be suitably used. In addition to the N ₂ gas, for example, a rare gas such as H ₂ gas, Ar gas, He gas, Ne gas, or Xe gas can be used. Gas can be used.

(Purge and return to atmospheric pressure)
When the heat treatment is completed, the valves 243d and 243e are opened, N ₂ gas is supplied from the gas supply pipes 232d and 232e into the processing chamber 201, and the exhaust pipe 231 is exhausted. N ₂ gas acts as a purge gas. Thereby, the inside of the processing chamber 201 is purged with the inert gas, and the gas and reaction by-products remaining in the processing chamber 201 are removed from the processing chamber 201 (purging). Thereafter, the atmosphere in the processing chamber 201 is replaced with an inert gas (inert gas replacement), and the pressure in the processing chamber 201 is returned to normal pressure (return to atmospheric pressure).

(Boat unload and wafer discharge)
The seal cap 219 is lowered by the boat elevator 115 and the lower end of the reaction tube 203 is opened. Then, the processed wafer 200 is carried out from the lower end of the reaction tube 203 to the outside of the reaction tube 203 (boat unloading) while being supported by the boat 217. The processed wafer 200 is taken out from the boat 217 (wafer discharge).

(3) Effects According to the Present Embodiment According to the present embodiment, one or more effects shown below can be obtained.

(A) In the parallel seed step, the natural oxide film 200b formed on the surface of the single crystal Si is performed by performing step 1 of supplying a DCS gas containing a halogen element to the wafer 200 on which the single crystal Si is exposed. In addition, it is possible to generate Si dangling bonds on the surface of the single crystal Si. As a result, an epitaxial Si film (first Si film 200e) can be grown on the single crystal Si. As a result, a film in which the second Si film 200g is stacked on the first Si film 200e on the surface (single crystal Si) of the wafer 200, that is, a stacked film including an epitaxial Si film on the lower layer side. It becomes possible to form. Since this laminated film includes an epitaxial Si film on the lower layer side, the contact resistance with respect to the wafer 200 or the like is higher than that of an Si single film composed only of amorphous Si, poly Si, or mixed crystal Si of amorphous and poly. It is a low-quality film with excellent electrical characteristics. When a silane source gas not containing a halogen element such as a hydrogenated silane source gas or an aminosilane source gas containing an amino group in one molecule is used instead of the DCS gas, the epitaxial layer is formed on the single crystal Si. It becomes difficult for the Si film to grow, and it becomes difficult to obtain the above-described effect.

(B) In the parallel seed step, Si adsorption sites are formed on the surface of the insulating film 200a by performing step 1 of supplying a DCS gas containing a halogen element to the wafer 200 with the insulating film 200a exposed on the surface. It becomes possible to do. This makes it possible to reliably form the second seed 200d on the insulating film 200a, that is, form the seed layer 200f. As a result, when the concave portion is provided on the surface of the wafer 200 and the side portion of the concave portion is constituted by the insulating film 200a, the second Si film 200g is formed in the concave portion, that is, into the concave portion. The Si film can be reliably embedded. The laminated film (Si film) formed on the wafer 200 can be a dense film without pinholes, and can be a film highly resistant to hydrogen fluoride (HF).

(C) In the parallel seed step, by performing Step 1, an environment in which homoepitaxial growth is likely to proceed is prepared at the bottom of the recess, and Si adsorption sites can be formed at the side and top of the recess. Thereby, the formation of the first Si film 200e and the seed layer 200f on the wafer 200 can be started without delay. As a result, it is possible to shorten the incubation time (growth delay) of the laminated film (Si film) and improve the productivity of the film formation process.

(D) In the parallel seed step, the density of the first seed 200c and the second seed 200d is increased by alternately supplying the DCS gas and the DS gas, and the first Si film 200e and the seed are supplied. It is possible to avoid the layer 200f from growing in an island shape. Thereby, the step coverage of the first Si film 200e and the seed layer 200f can be improved. As a result, the Si film formed on the wafer 200 can be a dense film without pinholes, and can be a film highly resistant to HF.

(E) In the parallel seed step, the supply of DCS gas and the supply of DS gas are alternately performed, so that an undesirable excessive gas phase reaction in the processing chamber 201 can be suppressed and generated in the processing chamber 201. The amount of particles to be reduced can be reduced.

(F) Film formation of a laminated film finally formed by using silane source gases having different molecular structures (chemical structures), that is, silane source gases having different materials, in the parallel seed step and the CVD film formation step. It is possible to achieve both efficiency and characteristics such as film thickness uniformity.

  For example, in the parallel seed step, the second processing gas has two Si atoms in one molecule, and has a lower thermal decomposition temperature (easily decomposed) than the MS gas used in the CVD film forming step, and has an adsorption efficiency of By using a high DS gas, the generation efficiency of the first seed 200c and the second seed 200d can be increased. Thereby, the formation efficiency of the first Si film 200e and the seed layer 200f can be increased. That is, by using DS gas as the second processing gas and MS gas as the third processing gas, the stack formed on the wafer 200 is more than when MS gas is used as the second and third processing gases. The film formation efficiency can be increased.

  Further, for example, in the CVD film forming step, the third processing gas has one Si atom in one molecule, and has a higher thermal decomposition temperature (difficult to decompose) than the DS gas used in the parallel seed step, and the adsorption efficiency. By using a low MS gas, it is possible to appropriately control the deposition rates of the first Si film 200e and the second Si film 200g. Thereby, it is possible to improve the in-plane film thickness uniformity and the step coverage of the first Si film 200e and the second Si film 200g, respectively. That is, by using a DS gas as the second processing gas and an MS gas as the third processing gas, a stack formed on the wafer 200 as compared with the case where the DS gas is used as the second and third processing gases. It is possible to improve characteristics such as in-plane film thickness uniformity and step coverage.

(G) By performing the annealing step, the film quality of the laminated film formed on the wafer 200 can be further improved. For example, a portion of the second Si film 200g that is in contact with the first Si film 200e is homoepitaxially (solid phase epitaxial growth), and a region occupied by the first Si film 200e (homoepitaxial Si film) in the stacked film By enlarging this, it becomes possible to further reduce the contact resistance of the laminated film. In addition, for example, by performing an annealing step, the laminated film can be further densified to obtain a film having higher HF resistance.

(H) The above-described effects are obtained when a halosilane gas other than the DCS gas is used as the first processing gas, a hydrogenated silane gas other than the DS gas is used as the second processing gas, or the MS is used as the third processing gas. The same can be obtained when a hydrogenated silane gas other than the gas is used, or when a dopant gas other than the PH gas is used as the dopant gas.

(4) Modification The film forming sequence in the present embodiment is not limited to the above-described embodiment, and can be changed as in the following modification.

(Modification 1)
As in the film forming sequence shown in FIG. 6 and the following, in the parallel seed step, a step (pre-cleaning step) of supplying DCS gas to the wafer 200 is started before starting a cycle in which steps 1 and 2 are alternately performed. You may make it perform. Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. Further, the above-described operation by supplying the DCS gas to the wafer 200 can be obtained more reliably. In particular, by making the DCS gas supply time in the pre-cleaning step longer than the DCS gas supply time in Step 1, the above-described operation by supplying the DCS gas to the wafer 200 can be obtained more reliably. Can do.

[DCS → (DCS → DS) × n → MS] → ANL ⇒ Si

(Modification 2)
As in the film formation sequence shown in FIG. 7, in the parallel seed step, when the cycle in which steps 1 and 2 are alternately performed is performed a predetermined number of times, the DCS gas supply time in step 1 of the first cycle is set to the subsequent cycle. The DCS gas supply time in step 1 may be longer than that. Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. Further, the above-described operation by supplying the DCS gas to the wafer 200 can be obtained more reliably.

(Modification 3)
As in the film formation sequence shown in FIG. 8, in the parallel seed step, when the cycle in which steps 1 and 2 are alternately performed is performed a predetermined number of times, the DCS gas supply flow rate in step 1 of the first cycle is changed to the subsequent cycle. The supply flow rate of DCS gas in step 1 may be increased. Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. Further, the above-described operation by supplying the DCS gas to the wafer 200 can be obtained more reliably.

(Modification 4)
As in the film forming sequence shown in FIG. 9, in the parallel seed step, when a cycle in which steps 1 and 2 are alternately performed is performed a predetermined number of times, the supply flow rate of DCS gas in step 1 is gradually decreased every time the cycle is performed. You may do it. In the parallel seed step, when the cycle in which steps 1 and 2 are alternately performed is performed a predetermined number of times, the DCS gas supply time in step 1 may be gradually shortened each time the cycle is performed. Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 and the modifications 1-3 is acquired. In addition, by reducing the supply flow rate and supply time of the DCS gas from the middle of the parallel seed step, the amount of DCS gas used can be reduced and the film formation cost can be reduced.

(Modification 5)
As shown in FIG. 10 and the film forming sequence shown below, in the parallel seed step, after step 1 is performed, step 2 may be intermittently performed a plurality of times. Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. Further, by not supplying DCS gas in the middle of the parallel seed step, it is possible to reduce the amount of DCS gas used and to reduce the film formation cost. Note that the DCS gas is supplied to the wafer 200 by setting the DCS gas supply time in Step 1 of the present modification longer than the DCS gas supply time in Step 1 of the film forming sequence shown in FIG. The above-mentioned action can be obtained with certainty. Further, the DCS gas is supplied to the wafer 200 by increasing the supply flow rate of the DCS gas in step 1 of this modification to the supply flow rate of DCS gas in step 1 of the film forming sequence shown in FIG. The above-mentioned action can be obtained with certainty.

[DCS → DS × n → MS] → ANL ⇒ Si

(Modification 6)
As in the film forming sequence shown in FIG. 11 and the following, silane source gases having the same molecular structure, that is, silane source gases having the same material may be used as the second and third processing gases. FIG. 11 shows a case where DS gas is used as the second and third processing gases. Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. Further, when a DS gas having a lower thermal decomposition temperature than MS gas (high adsorptivity) is used as the second and third processing gases, the deposition rate of the Si film formed on the wafer 200 is improved, and It is also possible to improve the productivity of the membrane treatment. Further, when MS gas having a higher thermal decomposition temperature (lower adsorbability) than DS gas is used as the second and third process gases, the step coverage and film thickness uniformity of the Si film formed on the wafer 200 It is also possible to improve.

[(DCS → DS) × n → DS] → ANL ⇒ Si

(Modification 7)
A chlorosilane source gas other than DCS gas may be used as the first processing gas. Hereinafter, a film forming sequence using HCDS gas and MCS gas as the first processing gas will be exemplified.

[(HCDS → DS) × n → MS] → ANL ⇒ Si

[(MCS → DS) × n → MS] → ANL ⇒ Si

  Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. Note that by using an HCDS gas having a larger number of Cl atoms contained in one molecule than a DCS gas as the first processing gas, the first processing gas is more sensitive to the wafer 200 than the film formation sequence shown in FIG. It becomes possible to further enhance the above-described action by supplying the processing gas. Further, by using an MCS gas having a smaller number of Cl atoms contained in one molecule than a DCS gas as the first processing gas, the first processing gas can be applied to the wafer 200 more than in the film forming sequence shown in FIG. It becomes possible to appropriately suppress the above-described action caused by supplying the processing gas.

(Modification 8)
As the first processing gas, a silane source gas containing C, that is, a silane source gas that also functions as a C source may be used instead of a silane source gas not containing carbon (C). Hereinafter, 1,1,2,2-tetrachloro-1,2-dimethyldisilane ((CH ₃ ) ₂ Si ₂ Cl ₄ , abbreviation: TCMDDS) gas, bis (trichlorosilyl) methane ( A film forming sequence using (SiCl ₃ ) ₂ CH ₂ (abbreviation: BTCSM) gas is illustrated.

[(TCDMDS → DS) × n → MS] → ANL ⇒ Si

[(BTCSM → DS) × n → MS] → ANL ⇒ Si

  Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. In addition, according to this modification, it is possible to add a small amount of C into the first Si film 200e and the seed layer 200f formed by the parallel seed step. By adding C to the first Si film 200e, it becomes easy to suppress the polycrystallization of the first Si film 200e and to make this film an epitaxial Si film. Further, by adding C to the seed layer 200f, the grain size of the crystal grains constituting the seed layer 200f can be reduced, and the seed layer 200f can be easily formed into a dense layer. However, depending on the specifications of the device formed on the wafer 200, it may be desired to avoid the addition of C into the first Si film 200e or the seed layer 200f. In this case, it is preferable to use a C-free hydrogenated silane source gas as the first processing gas as in the film forming sequence shown in FIG.

(Modification 9)
As the first processing gas, a halosilane source gas containing a halogen group other than Cl (chloro group), for example, a halosilane source gas containing F (fluoro group), Br (bromo group), I (iodo group) or the like is used. Also good. For example, as the first processing gas, monofluorosilane (SiH ₃ F, abbreviation: MFS) gas, tetrafluorosilane, that is, silicon tetrafluoride (SiF ₄ , abbreviation: STF) gas, trifluorosilane (SiHF ₃ , abbreviation: Fluorosilane source gas such as TFS) gas, hexafluorodisilane (Si ₂ F ₆ , abbreviation: HFDS) gas, monobromosilane (SiH ₃ Br, abbreviation: MBS) gas, tetrabromosilane, that is, silicon tetrabromide (SiBr ₄₎ , Abbreviation: STB) gas, tribromosilane (SiHBr ₃ , abbreviation: TBS) gas, bromosilane source gas such as hexabromodisilane (Si ₂ Br ₆ , abbreviation: HBDS) gas, monoiodosilane (SiH ₃ I, abbreviation) : MIS) gas, tetraiodosilane Using iodosilane source gas such as silicon tetraiodide (SiI ₄ , abbreviation: STI) gas, triiodosilane (SiHI ₃ , abbreviation: TIS) gas, hexaiododisilane (Si ₂ I ₆ , abbreviation: HIDS) gas, etc. Also good. Hereinafter, a film forming sequence using STF gas, STB gas, and STI gas as the first processing gas will be exemplified.

[(STF → DS) × n → MS] → ANL ⇒ Si

[(STB → DS) × n → MS] → ANL ⇒ Si

[(STI → DS) × n → MS] → ANL ⇒ Si

  Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. However, in the case where a gas containing F is used as the first processing gas, a film formation base (a surface of the single crystal Si or a surface of the insulating film 200a) may be pre-etched. In order to suppress pre-etching, it is preferable to use a halosilane source gas containing a halogen group other than F as the first processing gas.

(Modification 10)
As the first processing gas, a chloro-based gas containing a Si-free chloro group may be used. Alternatively, a halogen-based gas containing a halogen group other than Si-free Cl may be used. Hereinafter, a film forming sequence using hydrogen chloride (HCl) gas, chlorine (Cl ₂ ) gas, BCl ₃ gas, and chlorine fluoride (ClF ₃ ) gas as the first processing gas will be exemplified.

[(HCl → DS) × n → MS] → ANL ⇒ Si

[(Cl ₂ → DS) × n → MS] → ANL ⇒ Si

[(BCl ₃ → DS) × n → MS] → ANL ⇒ Si

[(ClF ₃ → DS) × n → MS] → ANL ⇒ Si

  Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. However, when a Si-free halogen-based gas is used as the first processing gas, a film formation base (a surface of the single crystal Si or a surface of the insulating film 200a) may be pre-etched. In order to suppress pre-etching, it is preferable to use a halogen-based gas containing Si, such as a chlorosilane source gas, as the first processing gas.

(Modification 11)
As the second processing gas, not only C and nitrogen (N) -free silane raw material gas, but also silane raw material gas containing C and N, that is, silane raw material gas acting as C source and also acting as N source. May be used. For example, as the second processing gas, monoaminosilane (SiH ₃ R) gas, diaminosilane (SiH ₂ RR ′) gas, triaminosilane (SiHRR′R ″) gas, tetraaminosilane (SiRR′R ″ R ″). ') Aminosilane source gas such as gas may be used. Each of R, R ′, R ″, and R ′ ″ represents a ligand (ligand). Examples of the aminosilane source gas include butylaminosilane (BAS) gas, bisthal butylaminosilane (BTBAS) gas, dimethylaminosilane (DMAS) gas, bisdimethylaminosilane (BDMAS) gas, tridimethylaminosilane (3DMAS) gas, and diethylaminosilane (3DMAS) gas. DEAS) gas, bisdiethylaminosilane (BDEAS) gas, dipropylaminosilane (DPAS) gas, diisopropylaminosilane (DIPAS) gas, or the like can be used. Hereinafter, a film forming sequence using BTBAS gas, 3DMAS gas, and DIPAS gas as the second processing gas will be exemplified.

[(HCDS → BTBAS) × n → MS] → ANL ⇒ Si

[(HCDS → 3DMAS) × n → MS] → ANL ⇒ Si

[(HCDS → DIPAS) × n → MS] → ANL ⇒ Si

  Also by this modification, the same effect as the film-forming sequence shown in FIG. 4 is acquired. Further, according to the present modification, as in Modification 8, it is possible to add a small amount of C or the like into the first Si film 200e or the seed layer 200f formed by the parallel seed step. This facilitates homoepitaxial growth of the first Si film 200e and densification of the seed layer 200f. However, depending on the specifications of the device formed on the wafer 200, it may be desired to avoid the addition of C or N into the first Si film 200e or the seed layer 200f. In this case, it is preferable to use a C- and N-free hydrogenated silane source gas as the second processing gas as in the film forming sequence shown in FIG.

<Other Embodiments of the Present Invention>
The embodiment of the present invention has been specifically described above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

  For example, in the above-described embodiment, the case where the wafer 200 having the surface structure shown in FIG. 12A is processed has been described, but the present invention is not limited to such a mode.

  For example, as shown in FIG. 12B, when the recess is formed on the surface of the wafer 200 and the insulating film 200a is formed so as to surround the opening of the recess, that is, the bottom of the recess is made of single crystal Si. The present invention is preferably applicable even when the side portion of the recess is formed of single crystal Si and the insulating film 200a. Further, for example, as shown in FIG. 12C, the present invention is suitable even when a recess is formed on the surface of the wafer 200 and an insulating film 200a is formed so as to fill the recess. Applicable. Further, for example, as shown in FIG. 12D, the present invention is suitably applied even when a recess is formed on the surface of the wafer 200 and an insulating film 200a is formed on the side of the recess. Is possible.

  In any case, the first Si film 200e is homoepitaxially grown on the single crystal Si and the second film is formed on the insulating film 200a by performing the parallel seed step and the CVD film forming step shown in the above embodiment. 200 g of Si film can be grown. Thereby, a laminated structure (laminated film) in which the second Si film is formed on the first Si film can be formed on the single crystal Si. In addition, by performing the annealing step shown in the above embodiment, the region occupied by the first Si film in the laminated film can be expanded.

  For example, in the above-described embodiment, the case where the parallel seed step to the annealing step are performed in the same processing chamber (in-situ) has been described, but the present invention is not limited to such an aspect. For example, the parallel seed step, the CVD film forming step, and the annealing step can be performed in different processing chambers (ex-situ). If a series of steps are performed in-situ, the wafer 200 can be consistently processed while being kept under vacuum without being exposed to the air, and stable substrate processing can be performed. it can. If some steps are performed ex-situ, the temperature in each processing chamber can be set in advance to, for example, the processing temperature in each step or a temperature close thereto, reducing the time required for temperature adjustment and producing Efficiency can be increased.

  Further, for example, in the above-described embodiments and modifications, the example in which the annealing step is performed after forming the first Si film and the second Si film has been described, but the annealing step can be omitted. That is, according to the method of the above-described embodiment or modification, epitaxial Si is formed at the interface between the single crystal Si and the second Si film without performing an annealing step, that is, in an as-depo state. A film (first Si film) can be formed, and it is not always necessary to perform an annealing step to obtain this configuration (structure). However, even in this case, the region of the epitaxial film can be enlarged by performing the annealing step, and the contact resistance can be further reduced.

  The methods of the above-described embodiments and modifications can be applied to a manufacturing process of a dynamic random access memory (hereinafter also referred to as DRAM) which is a volatile semiconductor memory device (volatile memory). Hereinafter, the manufacturing process of the DRAM will be described with reference to FIGS. 15 (a) to 15 (h) and FIGS. 16 (a) to 16 (g).

  Here, for the sake of convenience, a part of the manufacturing process of the DRAM will be described, and description of other processes will be omitted. Here, for the sake of convenience, a part of the film and structure constituting the DRAM will be described, and description of the other film and structure will be omitted.

  First, as shown in FIG. 15A, the surface of a single crystal Si wafer is etched using an SiO film, an SiN film or the like as a hard mask to form a trench on the wafer surface. Thereafter, as shown in FIG. 15B, an SiO film or the like is formed as a liner film on the surface of the wafer in which the trench is formed. The SiO film can be formed by, for example, a CVD method or a thermal oxidation method. Thereafter, as shown in FIG. 15C, the trench with the liner film formed on the surface is filled with the SiO film. The SiO film can be formed by, for example, a CVD method.

  After filling the trench, as shown in FIG. 15D, the surface is flattened by CMP. After planarization, as shown in FIG. 15E, the SiO film, SiN film, etc. formed on the wafer are removed by dry etching or the like. Thereafter, the liner film is reattached as shown in FIG. That is, an SiO film or the like is formed again as a liner film on the surface of the trench. The SiO film can be formed by, for example, a CVD method.

  Thereafter, as shown in FIG. 15G, a tungsten (W) film for word lines is formed on the liner film (SiO film), and the trench is filled with the W film. The W film can be formed by, for example, a CVD method. After embedding the W film in the trench, a part (upper part) of the W film is removed by dry etching or the like. FIG. 15G shows a state in which a part of the W film embedded in the trench is removed. Thereafter, as shown in FIG. 15H, a SiN film is formed on the W film buried in the trench and partially removed. The SiN film can be formed by, for example, a CVD method. After the SiN film is formed, the surface is planarized by CMP. Thereby, a structure in which the W film and the SiN film are stacked in the trench can be formed. FIG. 15H shows a state after the surface is flattened after the SiN film is formed on the W film in the trench.

  Thereafter, as shown in FIG. 16A, an interlayer insulating film such as a SiO film or a SiN film is formed. These films can be formed by, for example, a CVD method. Thereafter, as shown in FIG. 16B, the SiN film on the SiO film is patterned by lithography, dry etching, or the like. Then, dry etching is performed on the SiO film using the SiN film as a hard mask. As a result, the SiO film on the SiN film formed in the trench is left, and the other part of the SiO film is removed. Note that after dry etching, the SiO film and the SiN film used as a hard mask when the SiO film is dry-etched remain on the SiN film formed in the trench. FIG. 16B shows a state after dry etching is performed on the SiO film. Thereafter, as shown in FIG. 16C, the SiN film used as a hard mask when the SiO film is dry etched is removed by dry etching.

  Thereafter, as shown in FIG. 16 (d), a parallel seed step similar to that of the above-described embodiment or modification is performed, so that the surface of the wafer is exposed, that is, a homoepitaxial Si layer is formed on single crystal Si. A first seed layer (first Si film) to be formed, and a second seed layer composed of an amorphous Si layer, a poly Si layer, or a mixed crystal Si layer of amorphous and poly on the SiO film Form. In FIG. 16D, a homoepitaxial Si (Epi-Si) layer is formed as a first seed layer on single crystal Si, and amorphous Si (a-Si) is formed as a second seed layer on the SiO film. The example which forms a layer is shown. In this case, the first seed layer can also be referred to as an epitaxial Si seed layer. The second seed layer can also be referred to as an amorphous Si seed layer.

  Thereafter, as shown in FIG. 16E, the first seed layer (first Si film) on the single crystal Si is obtained by performing the CVD film forming step similar to that of the above-described embodiment or modification. Further, homoepitaxial growth is performed (a homoepitaxial Si film is further grown on the first seed layer), and an amorphous Si film, a poly Si film, or a mixed crystal of amorphous and poly is formed on the second seed layer on the SiO film. A second Si film composed of the Si film is formed. As a result, the inside of the recess constituted by the adjacent SiO film and single crystal Si can be filled with the Si film. Note that a stacked structure in which a second Si film is stacked on a first Si film can be formed on the single crystal Si. That is, an epitaxial Si film can be formed at the interface between the single crystal Si and the second Si film. FIG. 16E shows an example in which an epitaxial Si film is formed as the first Si film and an amorphous Si film is formed as the second Si film. That is, FIG. 16E shows an example in which an epitaxial Si film is formed at the interface between single crystal Si and amorphous Si film. At this time, a dopant such as P, B, or As can be added to the Si film as in the above-described embodiment and modification. Thereafter, the region of the epitaxial Si film may be enlarged by performing an annealing step similar to that of the above-described embodiment or modification. In addition, according to the method of the above-mentioned embodiment and a modification, since an epitaxial Si film | membrane can be formed without performing an annealing step, ie, as-deposition (as-depo.), An annealing step is abbreviate | omitted. Can do. The first Si film and the second Si film serve as contact plugs.

  Thereafter, as shown in FIG. 16F, the surface is planarized by CMP. After planarization, as shown in FIG. 16G, a contact portion is formed, and then a capacitor portion is formed. In the lower part of FIG. 16 (g), a laminated structure including a capacitor part and a contact part is shown in a longitudinal sectional view, and in the upper part of FIG. 16 (g), a transverse sectional view of a part indicated by a broken line in the capacitor part. Is shown.

  In this way, the main part of the DRAM is formed.

  Even when the methods of the above-described embodiments and modifications are applied to the DRAM manufacturing process, the contact resistance can be greatly reduced, and the electrical characteristics can be greatly improved.

  The above-described embodiments and modifications can be applied to a manufacturing process of a flash memory that is a nonvolatile semiconductor memory device (nonvolatile memory). Hereinafter, a manufacturing process of a NAND flash memory which is a kind of flash memory, in particular, a three-dimensional NAND flash memory (hereinafter also referred to as 3D NAND) will be described with reference to FIGS. 17 (a) to 17 (h). . The three-dimensional NAND flash memory can also be simply referred to as a three-dimensional flash memory (three-dimensional nonvolatile semiconductor memory device).

  Here, for the sake of convenience, a part of the manufacturing process of the 3D NAND will be described, and description of other processes will be omitted. Here, for convenience, a part of the film and structure constituting the 3D NAND will be described, and description of the other film and structure will be omitted.

  First, as shown in FIG. 17A, a multilayer laminated film in which a plurality of SiN films and SiO films are alternately laminated on the surface of a single crystal Si wafer (hereinafter also simply referred to as a laminated film). Form. Here, an example is shown in which the lowermost layer and the uppermost layer are SiO films. These films can be formed by, for example, a CVD method. FIG. 17A shows an example in which the number of layers is nine for convenience, but the present invention is not limited to such a configuration. For example, the number of stacked layers may be 20 layers or more, 30 layers or more, and further 40 layers or more.

  Thereafter, as shown in FIG. 17B, a channel hole is formed in the laminated film by dry etching or the like, and an ONO film, that is, a SiO film / SiN film / SiO film is formed in the channel hole. An insulating film is formed. These films can be formed by, for example, a CVD method. FIG. 17B shows a state in which an ONO film is formed in a channel hole formed in the laminated film.

  In the state where the contact portion of the ONO film with the wafer is removed, as shown in FIG. 17C, a parallel seed step similar to that of the above-described embodiment or modification is performed. As a result, a first seed layer (first Si film) composed of a homoepitaxial Si layer is formed on the exposed surface of the wafer, that is, on the single crystal Si, and on the ONO film (more precisely, ONO). A second seed layer composed of an amorphous Si layer, a poly Si layer, or a mixed crystal Si layer of amorphous and poly is formed on the SiO film constituting the film. In FIG. 17C, a homoepitaxial Si (Epi-Si) layer is formed as a first seed layer on single crystal Si, and poly-Si (Poly-Si) is formed as a second seed layer on the SiO film. The example which forms a layer is shown. In this case, the first seed layer can also be referred to as an epitaxial Si seed layer. The second seed layer can also be referred to as a poly-Si seed layer.

  Thereafter, as shown in FIG. 17 (d), the same CVD film formation step as in the above-described embodiment or modification is performed, so that the first seed layer (first Si film) on the single crystal Si is formed. Further, homoepitaxial growth is performed (a further homoepitaxial Si film is grown on the first seed layer), and an amorphous Si film, a poly Si film, or a mixed crystal of amorphous and poly is formed on the second seed layer on the ONO film. A second Si film composed of the Si film is formed. FIG. 17D shows an example in which a homoepitaxial Si (Epi-Si) film is formed as the first Si film and a poly-Si (Poly-Si) film is formed as the second Si film. That is, FIG. 17D shows an example in which an epitaxial Si film is formed on single-crystal Si and a poly-Si film is formed on the ONO film. At this time, a dopant such as P, B, or As can be added to the Si film as in the above-described embodiment and modification. The film thickness of the Si film can be 10 nm or less, for example, 3 to 10 nm, and further can be 5 nm or less, for example, 3 to 5 nm. Thereafter, the region of the epitaxial Si film may be enlarged by performing an annealing step similar to that of the above-described embodiment or modification. In addition, according to the method of the above-mentioned embodiment and a modification, since an epitaxial Si film | membrane can be formed without performing an annealing step, ie, as-deposited, an annealing step can be skipped. The first Si film and the second Si film serve as channels. Hereinafter, the Si film functioning as the channel (first Si film, second Si film) is also referred to as channel Si.

  Thereafter, as shown in FIG. 17 (e), the remaining portion in the channel hole, that is, in the recess constituted by the first Si film (epitaxial Si film) and the second Si film (poly Si film). Is embedded with a SiO film. The SiO film can be formed by, for example, a CVD method.

  In this way, a channel portion is formed.

  Thereafter, as shown in FIG. 17F, trenches are formed in a multilayer laminated film (laminated film) in which a plurality of SiN films and SiO films are alternately laminated. The trench can be formed by dry etching or the like. Thereafter, the SiN film constituting the laminated film is removed by dry etching or the like. As a result, the SiO film constituting the laminated film is left. FIG. 17F shows a state after the SiN film is removed by dry etching or the like after the trench is formed in the laminated film.

  In this state, as shown in FIG. 17 (g), a portion of the SiN film removed, that is, a TiN film acting as a control gate, a metal film such as a W film, etc. is formed between the upper and lower adjacent SiO films. To do. These films can be formed by, for example, a CVD method. Thereafter, a TiN film, a metal film such as a W film formed in the trench at the time of film formation (extruded from between upper and lower adjacent SiO films), a W film, and the like are removed by dry etching or the like. As a result, the trench is re-formed. FIG. 17G shows a state after the trench is re-formed.

  In this way, a control gate portion in which the SiO film and the control gate (TiN film, W film, etc.) are laminated is formed.

  In this state, the trench is filled with a film such as a SiO film as shown in FIG. The SiO film can be formed by, for example, a CVD method. At this time, a film such as a SiO film is also formed on the control gate part and the channel part. Thereafter, a contact hole is formed in the upper portion of the channel portion by dry etching or the like, and a metal film acting as a contact is formed in the contact hole. FIG. 17H shows a state after the metal film is formed in the contact hole.

  In this way, the main part of the 3D NAND is formed.

  Even when the method of the above-described embodiment or modification is applied to the 3D NAND manufacturing process, the contact resistance between the Si wafer and the channel Si can be greatly reduced, and the electrical characteristics can be greatly improved. It becomes.

  Further, by applying the method of the above-described embodiment or modification to the manufacturing process of 3D NAND, a flat and dense seed layer (first seed layer, second seed layer) can be formed. In addition, since a flat and dense Si film (first Si film, second Si film) can be formed, the Si film can be a film without pinholes (pinhole-free film). Thereby, it is possible to prevent the base film of the Si film from being etched by a wet process using HF or the like performed after the Si film is formed. In addition, since a thin and flat Si film can be formed even if it is thin, it is possible to reduce the thickness of the second Si film (poly Si film), thereby reducing the charge trap density at the crystal grain boundary. It is possible to increase the electron mobility in the 3D NAND channel.

  Recipes used for substrate processing (programs that describe processing procedures, processing conditions, etc.) depend on the processing details (film type of film to be formed, composition ratio, film quality, film thickness, processing procedures, processing conditions, etc.) It is preferable to prepare them individually and store them in the storage device 121c via the telecommunication line or the external storage device 123. And when starting a process, it is preferable that CPU121a selects a suitable recipe suitably from the some recipe stored in the memory | storage device 121c according to the content of the board | substrate process. Accordingly, it is possible to form films having various film types, composition ratios, film qualities, and film thicknesses with a single substrate processing apparatus with good reproducibility. Further, it is possible to reduce the burden on the operator (such as an input burden on the processing procedure and processing conditions), and the processing can be started quickly while avoiding an operation error.

  The above-mentioned recipe is not limited to a case of newly creating, and for example, it may be prepared by changing an existing recipe that has already been installed in the substrate processing apparatus. When changing the recipe, the changed recipe may be installed in the substrate processing apparatus via an electric communication line or a recording medium on which the recipe is recorded. Further, an existing recipe that has already been installed in the substrate processing apparatus may be directly changed by operating the input / output device 122 provided in the existing substrate processing apparatus.

  In the above-described embodiment, an example in which a film is formed using a batch-type substrate processing apparatus that processes a plurality of substrates at one time has been described. The present invention is not limited to the above-described embodiment, and can be suitably applied to a case where a film is formed using, for example, a single-wafer type substrate processing apparatus that processes one or several substrates at a time. In the above-described embodiment, an example in which a film is formed using a substrate processing apparatus having a hot wall type processing furnace has been described. The present invention is not limited to the above-described embodiment, and can be suitably applied to a case where a film is formed using a substrate processing apparatus having a cold wall type processing furnace. Also in these cases, the processing procedure and processing conditions can be the same processing procedure and processing conditions as in the above-described embodiment, for example.

  For example, the present invention can be preferably applied to the case where a film is formed using a substrate processing apparatus including the processing furnace 302 shown in FIG. The processing furnace 302 includes a processing container 303 that forms the processing chamber 301, a shower head 303s as a gas supply unit that supplies gas into the processing chamber 301 in a shower shape, and one or several wafers 200 in a horizontal posture. A support base 317 for supporting, a rotating shaft 355 for supporting the support base 317 from below, and a heater 307 provided on the support base 317 are provided. Gas supply ports 332a and 332b are connected to the inlet (gas inlet) of the shower head 303s. The gas supply port 332a is connected to a gas supply system similar to the first processing gas supply system and the dopant gas supply system of the above-described embodiment. A gas supply system similar to the second processing gas supply system and the third processing gas supply system of the above-described embodiment is connected to the gas supply port 332b. At the outlet (gas outlet) of the shower head 303s, a gas dispersion plate that supplies gas into the processing chamber 301 in a shower shape is provided. The shower head 303 s is provided at a position facing (facing) the surface of the wafer 200 carried into the processing chamber 301. The processing vessel 303 is provided with an exhaust port 331 for exhausting the inside of the processing chamber 301. An exhaust system similar to the exhaust system of the above-described embodiment is connected to the exhaust port 331.

  Further, for example, the present invention can be suitably applied to the case where a film is formed using a substrate processing apparatus including the processing furnace 402 shown in FIG. The processing furnace 402 includes a processing container 403 that forms a processing chamber 401, a support base 417 that supports one or several wafers 200 in a horizontal position, a rotating shaft 455 that supports the support base 417 from below, and a processing container. A lamp heater 407 that irradiates light toward the wafer 200 in the 403 and a quartz window 403w that transmits light from the lamp heater 407 are provided. Gas supply ports 432 a and 432 b are connected to the processing container 403. The gas supply port 432a is connected to a gas supply system similar to the first processing gas supply system and the dopant gas supply system of the above-described embodiment. A gas supply system similar to the second process gas supply system and the third process gas supply system of the above-described embodiment is connected to the gas supply port 432b. The gas supply ports 432a and 432b are respectively provided on the side of the end portion of the wafer 200 loaded into the processing chamber 401, that is, at a position not facing the surface of the wafer 200 loaded into the processing chamber 401. The processing container 403 is provided with an exhaust port 431 for exhausting the inside of the processing chamber 401. An exhaust system similar to the exhaust system of the above-described embodiment is connected to the exhaust port 431.

  Even when these substrate processing apparatuses are used, film formation can be performed with the same sequence and processing conditions as in the above-described embodiments and modifications, and the same effects as in the above-described embodiments and modifications can be obtained.

  Moreover, the above-mentioned embodiment, a modification, etc. can be used in combination as appropriate. Further, the processing conditions at this time can be the same processing conditions as in the above-described embodiment, for example.

  Hereinafter, experimental results supporting the effects obtained in the above-described embodiments and modifications will be described.

As the sample 1, using the substrate processing apparatus in the above-described embodiment, the Si wafer with the single crystal Si (Si wafer surface) and the insulating film (SiO ₂ ) exposed on the surface by the film forming sequence shown in FIG. A Si film was formed on a Si wafer in which a recess was provided on the surface, the bottom of the recess was made of single crystal Si, and the side and upper portions of the recess were made of an insulating film. DCS gas was used as the first processing gas, DS gas was used as the second processing gas, and MS gas was used as the third processing gas. The temperature of the Si wafer in the parallel seed step was set to a temperature in the range of 370 to 390 ° C. The temperature of the Si wafer in the CVD film forming step was set to a temperature in the range of 400 to 500 ° C. The other processing conditions were those within the processing condition range described in the above embodiment.

As a sample 2, using the substrate processing apparatus in the above-described embodiment, on a Si wafer having a single crystal Si and an insulating film (SiO ₂ ) exposed on the surface by the same processing procedure as the CVD film forming step in the above-described embodiment Then, a Si film was formed. In sample 2, the parallel seed step was not performed. MS gas was used as the third processing gas. The processing conditions were the same as those in the CVD film forming step when sample 1 was prepared.

  Then, the cross-sectional structures of the Si films of Samples 1 and 2 were observed using TEM. FIG. 13A is a TEM image showing the cross-sectional structure of the Si film of Sample 1, and FIG. 13B is a TEM image showing the cross-sectional structure of the Si film of Sample 2.

  According to FIG. 13 (a), a laminated structure is formed in which an amorphous Si film (a-Si) is laminated on an epitaxial Si film (Epi-Si) on single crystal Si (in a recess). I understand that. This is presumably because the natural oxide film formed on the surface of the single crystal Si was removed by performing the parallel seed step when the sample 1 was produced. That is, it is considered that O was desorbed from the surface of the Si wafer (the surface of the single crystal Si) and the formation of the Si film was started after preparing an environment in which homoepitaxial growth was likely to proceed.

  Further, according to FIG. 13B, it can be seen that the epitaxial Si film is not grown on the single crystal Si (in the recess), and only the amorphous Si film (a-Si) is grown. This is because when the sample 2 is prepared, the parallel seed step is not performed, so the natural oxide film is not removed from the surface of the single crystal Si, and the surface of the Si wafer (single crystal Si) and the Si film This is presumably because O remained at the interface between and Si, and the environment for Si epitaxial growth was not established.

  When the electrical characteristics of the Si films formed in Samples 1 and 2 were evaluated, the Si film formed in Sample 1 had lower contact resistance and superior electrical characteristics than the Si film formed in Sample 2. It was confirmed that the film was of good quality. Further, when the Si film (laminated film) formed in Sample 1 is heat-treated with the same processing procedure and processing conditions as the annealing step shown in the above-described embodiment, the region occupied by the epitaxial Si film in the Si film (laminated film) is expanded. It was also confirmed that the electrical characteristics of the Si film can be further improved.

<Preferred embodiment of the present invention>
Hereinafter, preferred embodiments of the present invention will be additionally described.

(Appendix 1)
According to one aspect of the invention,
A substrate made of single crystal silicon, an insulating film formed on the surface of the substrate,
A first silicon film formed by homoepitaxial growth on the single crystal silicon using the single crystal silicon as a base; and
A second silicon film formed on the insulating film and having a crystal structure different from that of the first silicon film;
A three-dimensional flash memory, a dynamic random access memory, or a semiconductor device is provided.

(Appendix 2)
The three-dimensional flash memory, dynamic random access memory, or semiconductor device according to appendix 1, preferably,
A recess is provided on the surface of the substrate, the bottom of the recess is made of the single crystal silicon, and the side of the recess is made of the insulating film.

  Preferably, the first silicon film and the second silicon film in the three-dimensional flash memory function as a channel.

  Preferably, the first silicon film and the second silicon film in the dynamic random access memory function as contact plugs.

(Appendix 3)
The three-dimensional flash memory, dynamic random access memory, or semiconductor device according to appendix 1 or 2, preferably,
The first silicon film and the second silicon film are a first processing gas containing silicon and a halogen element with respect to the substrate in which the single crystal silicon and the insulating film are exposed on the surface. And a process of alternately supplying a second processing gas containing silicon and containing no halogen element to the substrate, and a third process containing silicon to the substrate. It is formed by performing the process which supplies process gas.

(Appendix 4)
According to another aspect of the invention,
Supplying a first processing gas containing silicon and a halogen element to a substrate having a surface on which the single crystal silicon and the insulating film are exposed; and a step of containing silicon and containing no halogen element to the substrate. And a step of alternately supplying the two processing gases;
Supplying a third processing gas containing silicon to the substrate;
Performing the process of homoepitaxially growing the first silicon film on the single crystal silicon and growing a second silicon film having a crystal structure different from that of the first silicon film on the insulating film. A semiconductor device manufacturing method or a substrate processing method is provided.

(Appendix 5)
The method according to appendix 4, preferably,
In the step of alternately performing the step of supplying the first processing gas and the step of supplying the second processing gas, the first silicon film is homoepitaxially grown on the single crystal silicon, and Forming a seed layer on the insulating film;
In the step of supplying the third processing gas, the first silicon film is further homoepitaxially grown and the second silicon film is grown on the seed layer.

(Appendix 6)
The method according to appendix 4 or 5, preferably,
A recess is provided on the surface of the substrate, the bottom of the recess is made of the single crystal silicon, and the side of the recess is made of the insulating film.

(Appendix 7)
The method according to appendix 6, preferably,
Homoepitaxial growth of the first silicon film is stopped by covering the upper part of the first silicon film with the second silicon film grown from the side of the recess.

(Appendix 8)
The method according to appendix 6 or 7, preferably,
The second silicon film grown from the side of the recess covers the upper portion of the first silicon film, and the second silicon film is laminated on the first silicon film. A laminated structure (laminated film) is formed.

(Appendix 9)
The method according to any one of appendices 4 to 8, preferably:
The crystal structure of the second silicon film is amorphous (amorphous), poly (polycrystalline), or a mixed crystal of amorphous and poly. That is, the second silicon film is an amorphous silicon film, a polysilicon film, or a mixed crystal silicon film of amorphous and poly.

(Appendix 10)
The method according to any one of appendices 4 to 9, preferably:
The first processing gas includes silane chloride (compound), the second processing gas includes hydrogenated silane (compound), and the third processing gas includes hydrogenated silane (compound).

(Appendix 11)
The method according to any one of appendices 4 to 10, preferably,
In the step of supplying the third processing gas, a dopant gas is supplied together with the third processing gas to the substrate.

(Appendix 12)
The method according to any one of appendices 4 to 11, preferably,
The second processing gas has a molecular structure (chemical structure) different from that of the third processing gas. That is, the second processing gas is a gas having a material different from that of the third processing gas.

(Appendix 13)
The method according to any one of appendices 4 to 12, preferably:
The thermal decomposition temperature of the second processing gas is lower than the thermal decomposition temperature of the third processing gas.

(Appendix 14)
The method according to any one of appendices 4 to 11, preferably,
The second processing gas has the same molecular structure (chemical structure) as the third processing gas. That is, the second processing gas is the same gas as the third processing gas.

(Appendix 15)
The method according to any one of appendices 4 to 14, preferably:
Furthermore, the method includes a step of heat-treating (annealing) the first silicon film and the second silicon film.

(Appendix 16)
The method according to appendix 15, preferably,
In the step of heat-treating the first silicon film and the second silicon film, a portion of the second silicon film that contacts the first silicon film (homoepitaxial silicon film) is homoepitaxially formed.

(Appendix 17)
The method according to appendix 15 or 16, preferably,
In the step of heat-treating the first silicon film and the second silicon film, a portion of the second silicon film that contacts the first silicon film (homoepitaxial silicon film) is transformed into a homoepitaxial silicon film. Let

(Appendix 18)
The method according to any one of appendices 15 to 17, preferably:
In the step of heat-treating the first silicon film and the second silicon film, a region occupied by the first silicon film is expanded.

(Appendix 19)
The method according to any one of appendices 4 to 18, preferably:
In the step of alternately performing the step of supplying the first processing gas and the step of supplying the second processing gas, the temperature of the substrate is set to the first temperature,
In the step of supplying the third processing gas, the temperature of the substrate is set to a second temperature that is equal to or higher than the first temperature.

(Appendix 20)
The method according to appendix 19, preferably,
In the step of heat-treating the first silicon film and the second silicon film, the temperature of the substrate is set to a third temperature that is equal to or higher than the second temperature.

(Appendix 21)
According to another aspect of the invention,
Supplying a first processing gas containing a halogen element to a substrate having a single crystal silicon and an insulating film exposed on the surface; and a second treatment containing silicon and containing no halogen element to the substrate. A step of alternately supplying a gas,
Supplying a third processing gas containing silicon to the substrate;
Performing the process of homoepitaxially growing the first silicon film on the single crystal silicon and growing a second silicon film having a crystal structure different from that of the first silicon film on the insulating film. A semiconductor device manufacturing method or a substrate processing method is provided.

(Appendix 22)
According to yet another aspect of the invention,
A processing chamber for accommodating the substrate;
A first processing gas supply system for supplying a first processing gas containing silicon and a halogen element to a substrate in the processing chamber;
A second processing gas supply system for supplying a second processing gas containing silicon and containing no halogen element to the substrate in the processing chamber;
A third processing gas supply system for supplying a third processing gas containing silicon to the substrate in the processing chamber;
A heater for heating the substrate in the processing chamber;
A process of supplying the first process gas to a substrate having a surface exposed with single crystal silicon and an insulating film in the process chamber; and the second process gas to the substrate in the process chamber And a process of alternately supplying a third process gas and a process of supplying the third process gas to the substrate in the process chamber. The first process gas supply system and the second process gas supply are formed so that a silicon film is homoepitaxially grown and a second silicon film having a crystal structure different from that of the first silicon film is grown on the insulating film. A control unit configured to control a system, the third process gas supply system, and the heater;
A substrate processing apparatus is provided.

(Appendix 23)
According to yet another aspect of the invention,
A first gas supply unit for supplying a first processing gas containing silicon and a halogen element to the substrate;
A second gas supply unit for supplying a second processing gas containing silicon and containing no halogen element to the substrate;
A third gas supply unit for supplying a third processing gas containing silicon to the substrate,
A process of supplying the first processing gas from the first gas supply unit to the substrate with the single crystal silicon and the insulating film exposed on the surface, and the substrate from the second gas supply unit to the substrate. By alternately performing a process of supplying a second process gas and a process of supplying the third process gas from the third gas supply unit to the substrate, A gas supply system controlled to homoepitaxially grow a first silicon film on single crystal silicon and to grow a second silicon film having a crystal structure different from that of the first silicon film on the insulating film. Provided.

(Appendix 24)
According to yet another aspect of the invention,
A step of supplying a first processing gas containing silicon and a halogen element to a substrate having a single crystal silicon and an insulating film exposed on the surface; and a step of containing silicon and containing no halogen element to the substrate. A procedure of alternately supplying the process gas of 2 and
Supplying a third processing gas containing silicon to the substrate;
The first silicon film is homoepitaxially grown on the single crystal silicon, and the second silicon film having a crystal structure different from that of the first silicon film is grown on the insulating film. A program to be executed by a computer or a computer-readable recording medium on which the program is recorded is provided.

121 Controller (control unit)
200 wafer (substrate)
200a Insulating film 200e First silicon film 200g Second silicon film 201 Processing chamber 202 Processing furnace 203 Reaction tube 207 Heater 231 Exhaust pipes 232a to 232e Gas supply pipe

Claims (24)

Supplying a first processing gas containing silicon and a halogen element to a substrate having a surface on which the single crystal silicon and the insulating film are exposed; and a step of containing silicon and containing no halogen element to the substrate. The step of supplying the second processing gas is alternately performed at a temperature at which silicon contained in the first processing gas is not deposited , so that the first silicon seed layer is homogenized on the single crystal silicon. Epitaxially growing and growing a second silicon seed layer having a crystal structure different from that of the first silicon seed layer on the insulating film;
By supplying a third processing gas containing silicon to the substrate , the first silicon film is homoepitaxially grown on the first silicon seed layer , and the second silicon seed layer is Growing a second silicon film having a crystal structure different from that of the first silicon film ;
A method for manufacturing a semiconductor device comprising: The method of manufacturing a semiconductor device according to claim 1, wherein the first silicon seed layer and the second silicon seed layer are grown in parallel. The method of manufacturing a semiconductor device according to claim 1, wherein the first silicon film and the second silicon film are grown in parallel. The surface of the said board | substrate is provided with the recessed part, The bottom part of the said recessed part is comprised with the said single crystal silicon, The side part of the said recessed part is comprised with the said insulating film , The any one of Claims 1-3. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. 5. The semiconductor device according to claim 4 , wherein homoepitaxial growth of the first silicon film is stopped by covering an upper portion of the first silicon film with the second silicon film grown from a side portion of the recess. Manufacturing method. The second silicon film grown from the side of the recess covers the upper portion of the first silicon film, and the second silicon film is laminated on the first silicon film. 6. The method of manufacturing a semiconductor device according to claim 4, wherein a stacked structure is formed. The method for manufacturing a semiconductor device according to claim 1 , wherein a crystal structure of the second silicon film is amorphous, poly, or a mixed crystal of amorphous and poly. The first process gas comprises a chloride silane, wherein the second process gas includes silane hydrides, the third process gas, any one of claims 1-7 comprising a silane hydride The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The method for manufacturing a semiconductor device according to claim 1 , wherein in the step of supplying the third processing gas, a dopant gas is supplied to the substrate together with the third processing gas. . Wherein the second process gas, a method of manufacturing a semiconductor device according to any one of claims 1-9 having the third process gas with different molecular structures. The method for manufacturing a semiconductor device according to claim 1 , wherein a thermal decomposition temperature of the second processing gas is lower than a thermal decomposition temperature of the third processing gas. The method for manufacturing a semiconductor device according to claim 1 , wherein the second processing gas has the same molecular structure as that of the third processing gas. Furthermore, the manufacturing method of the semiconductor device of any one of Claims 1-12 which has the process of heat-processing a said 1st silicon film and a said 2nd silicon film. In the first silicon film and heat-treating said second silicon film, wherein a portion in contact with the first silicon layer of the second silicon film in claim 13 for transformed into homoepitaxial silicon films Semiconductor device manufacturing method. 15. The method of manufacturing a semiconductor device according to claim 13 , wherein in the step of heat-treating the first silicon film and the second silicon film, a region occupied by the first silicon film is expanded. In the step of alternately performing the step of supplying the first processing gas and the step of supplying the second processing gas, the temperature of the substrate is set to the first temperature,
16. The semiconductor device according to claim 1 , wherein in the step of supplying the third processing gas, the temperature of the substrate is set to a second temperature that is equal to or higher than the first temperature. Manufacturing method. And a step of heat-treating the first silicon film and the second silicon film,
The semiconductor according to claim 16 , wherein in the step of heat-treating the first silicon film and the second silicon film, the temperature of the substrate is set to a third temperature that is equal to or higher than the second temperature. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 16, wherein the first temperature is 350 ° C. or higher and 450 ° C. or lower. The method of manufacturing a semiconductor device according to claim 18, wherein the second temperature is 350 ° C. or higher and 650 ° C. or lower. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is an oxide film. 21. The method of manufacturing a semiconductor device according to claim 1 , wherein the semiconductor device includes a three-dimensional flash memory or a dynamic random access memory. A processing chamber for accommodating the substrate;
A first processing gas supply system for supplying a first processing gas containing silicon and a halogen element to a substrate in the processing chamber;
A second processing gas supply system for supplying a second processing gas containing silicon and containing no halogen element to the substrate in the processing chamber;
A third processing gas supply system for supplying a third processing gas containing silicon to the substrate in the processing chamber;
A heater for heating the substrate in the processing chamber;
Supplied in the processing chamber, the substrate where the single crystal silicon and the insulating film is exposed to the surface, a process for supplying the first processing gas, for the previous SL substrate, the second process gas The first silicon seed layer is homoepitaxially grown on the single crystal silicon by alternately performing processing at a temperature at which silicon contained in the first processing gas is not deposited , and the insulating film A process of growing a second silicon seed layer having a crystal structure different from that of the first silicon seed layer and supplying the third processing gas to the substrate, thereby providing the first silicon a first silicon film causes homoepitaxially grown on the seed layer, growing a second silicon film crystal structure different from the first silicon layer to the second silicon seed layer A process of, so as to perform a first process gas supply system, the second process gas supply system, said third process gas supply system, and the configured control unit to control the heater,
A substrate processing apparatus. A first gas supply unit for supplying a first processing gas containing silicon and a halogen element to the substrate;
A second gas supply unit for supplying a second processing gas containing silicon and containing no halogen element to the substrate;
A third gas supply unit for supplying a third processing gas containing silicon to the substrate,
A process of supplying the first processing gas from the first gas supply unit to the substrate with the single crystal silicon and the insulating film exposed on the surface, and the substrate from the second gas supply unit to the substrate. The first silicon seed layer is formed on the single crystal silicon by alternately performing the process of supplying the second process gas at a temperature at which silicon contained in the first process gas is not deposited. A process of growing a second silicon seed layer having a crystal structure different from that of the first silicon seed layer on the insulating film, and growing the second silicon seed layer on the insulating film from the third gas supply unit. by supplying a third process gas, wherein the first silicon layer with homoepitaxially grown on the first silicon seed layer, the first silicon to the second silicon seed layer Gas supply system is controlled so as to perform a process of growing a second silicon film crystal structure is different from the. In the processing chamber of the substrate processing apparatus ,
A step of supplying a first processing gas containing silicon and a halogen element to a substrate having a single crystal silicon and an insulating film exposed on the surface; and a step of containing silicon and containing no halogen element to the substrate. The first silicon seed layer is homogenized on the single crystal silicon by alternately performing the steps of supplying the second processing gas at a temperature at which silicon contained in the first processing gas is not deposited. A step of epitaxially growing a second silicon seed layer having a crystal structure different from that of the first silicon seed layer on the insulating film;
Relative to the previous SL substrate by supplying a third process gas comprising silicon, a first silicon film causes homoepitaxially grown on the first silicon seed layer, the second silicon seed layer A procedure for growing a second silicon film having a crystal structure different from that of the first silicon film ;
For causing the substrate processing apparatus to execute the program.