JP6092540B2 - Crystal oscillator - Google Patents

Description

  The present invention relates to a crystal oscillator that detects the temperature of an atmosphere in which a crystal resonator is placed and controls a heating unit based on the temperature detection result to make the temperature of the atmosphere constant.

  When the crystal oscillator is incorporated in an application that requires extremely high frequency stability, an OCXO (Oven Control Crystal Oscillator) is generally used. The temperature control in OCXO is made up of discrete components such as operational amplifiers, resistors, and capacitors using a thermistor as a temperature detector. However, temperature control of ± 20m ° C, for example, due to individual variations and aging of analog components Could not do.

  However, base stations, relay stations, and the like are required to use clock signals with extremely high stability at low cost, and therefore, it is expected that conventional OCXO cannot cope with them.

2 and 3 of Patent Document 1 describe that two crystal resonators (quartz resonators) are configured by providing two pairs of electrodes on a common crystal piece. Paragraph 0018 describes that since a frequency difference appears between two crystal resonators according to a temperature change, measuring the frequency difference is the same as measuring the temperature. The relationship between the frequency difference Δf and the amount of frequency to be corrected is stored in the ROM, and the frequency correction amount is read based on Δf.
However, this technique relates to a TCXO (temperature compensated crystal oscillator) that corrects the oscillation frequency based on temperature detection, and is not related to OCXO.
Then, as described in paragraph 0019, the crystal resonator is adjusted so that the desired output frequency f0 and the respective frequencies f1 and f2 of the two crystal resonators are in the relationship of f0≈f1≈f2. Therefore, there is a problem that the manufacturing process of the crystal resonator is complicated and a high yield cannot be obtained. In addition, since the frequency signal from each crystal resonator is counted for a certain time and the difference (f1-f2) is obtained, the detection accuracy directly affects the detection time, and high-precision temperature compensation is difficult. is there.

JP 2001-292030 A

  The present invention has been made under such circumstances, and an object of the present invention is to detect the temperature of the atmosphere in which the crystal unit is placed and control the heating unit based on the temperature detection result to control the temperature of the atmosphere. It is an object of the present invention to provide a crystal oscillator that can obtain an oscillation output with high frequency stability in a crystal oscillator (OCXO) that keeps constant.

The present invention
An oscillator circuit for oscillator output connected to a crystal unit;
A heating unit for stabilizing the temperature of the atmosphere in which the crystal unit is placed;
A first crystal unit configured by providing a first electrode on a crystal piece;
A second crystal unit configured by providing a second electrode on a crystal piece;
A first oscillation circuit and a second oscillation circuit connected to the first crystal unit and the second crystal unit, respectively;
The oscillation frequency of the first oscillation circuit is f1, the oscillation frequency of the first oscillation circuit at the reference temperature is f1r, the oscillation frequency of the second oscillation circuit is f2, and the oscillation frequency of the second oscillation circuit at the reference temperature is f2r. Then, a frequency difference detection unit that obtains a value corresponding to {(f2-f2r) / f2r}-{(f1-f1r) / f1r} as a temperature detection value;
An adder for extracting a deviation between the temperature setting value of the temperature of the atmosphere in which the crystal unit is placed and the temperature detection value;
And a circuit unit that controls electric power supplied to the heating unit based on the deviation taken out by the adding unit.
Other inventions are:
(1) an oscillator circuit for outputting an oscillator connected to a crystal unit;
(2) a heating unit for stabilizing the temperature of the atmosphere in which the crystal unit is placed;
(3) a first crystal unit configured by providing a first electrode on a crystal piece;
(4) a second crystal unit configured by providing a second electrode on a crystal piece;
(5) a first oscillation circuit and a second oscillation circuit connected to the first crystal unit and the second crystal unit, respectively;
(6) The oscillation frequency of the first oscillation circuit is f1, the oscillation frequency of the first oscillation circuit at the reference temperature is f1r, the oscillation frequency of the second oscillation circuit is f2, and the oscillation frequency of the second oscillation circuit at the reference temperature Let f2r be
A pulse generating unit that generates a pulse having a frequency difference between f1 and f2, and a DDS circuit unit that outputs a frequency signal that repeatedly increases and decreases with time at a frequency according to the magnitude of the input DC voltage A latch circuit that latches the frequency signal output from the DDS circuit unit with the pulse generated by the pulse generation unit, and integrates the signal value latched by the latch circuit to detect the integrated value of the temperature A frequency difference detection comprising: a loop filter that outputs as a value; and an adder that extracts a difference between the output of the loop filter and a value corresponding to a difference between f1r and f2r and uses the difference as an input value of the DDS circuit unit And
(7) an adding unit for extracting a deviation between the temperature setting value of the atmosphere in which the crystal unit is placed and the temperature detection value;
(8), further comprising a circuit section for controlling the power supplied to the heating unit based on said deviations taken by the adding unit to take out the deviations of the temperature setting value and the detected temperature value It is characterized by.

The deviation taken out by the adding unit is integrated by, for example, an integrating circuit unit and output to the temperature control unit.
First oscillation circuit and the second oscillation circuit shall be the oscillation output of each overtone example.

The oscillation output of the crystal oscillator can be, for example, one of the first oscillation circuit and the second oscillation circuit, but the atmosphere is different from the first crystal oscillator and the second crystal oscillator. A third crystal oscillator placed on the third crystal oscillator may be provided, and the oscillation output from the third oscillation circuit connected to the third crystal oscillator may be used as the oscillation output of the crystal oscillator.
Another invention is an oscillating device comprising the crystal oscillator of the present invention and a main body circuit portion of an oscillating device including a PLL using the oscillation output of the crystal oscillator as a clock signal.

In the present invention, when the oscillation outputs of the first and second oscillation circuits are f1 and f2, and the oscillation frequencies of the first and second oscillation circuits at the reference temperature are f1r and f2r, respectively, {(f2-f2r) / A value corresponding to f2r}-{(f1-f1r) / f1r} is handled as the temperature at that time. Since the degree of correlation between this value and temperature is extremely high, the temperature of the atmosphere in which the crystal unit is placed is extremely stabilized by controlling the power supplied to the heating unit using the value as a temperature detection value. As a result, an oscillation output with high stability can be obtained.

It is a block diagram which shows the whole structure of embodiment of this invention. It is a block diagram which shows a part of embodiment of this invention. FIG. 3 is a waveform diagram of a part of outputs shown in FIG. 2. FIG. 3 is a waveform diagram of each part schematically showing a state where the loop including the DDS circuit part shown in FIG. 2 is not locked. FIG. 3 is a waveform diagram of each part schematically showing a locked state in a loop including a DDS circuit part shown in FIG. 2. It is a wave form diagram of each part in the loop about an actual device corresponding to the above-mentioned embodiment. FIG. 6 is a frequency-temperature characteristic diagram showing the relationship between the frequency f1 of the first oscillation circuit and the frequency f2 of the second oscillation circuit and the temperature. It is a frequency-temperature characteristic figure which shows the relationship between the value which normalized each of the change rate of f1, and the change rate of f2 with the value in reference | standard temperature, and temperature. It is a characteristic view which shows the relationship between the digital output value of a frequency difference detection part, and temperature. It is a circuit diagram which shows the control circuit of a heating part. It is a schematic longitudinal side view which shows the structure of the oscillation apparatus concerning the said embodiment. Relationship between the value obtained by normalizing the rate of change of f1 with the value of the reference temperature and the temperature, and the value obtained by normalizing the rate of change of f1 with the value of the reference temperature and the value obtained by normalizing the rate of change of f2 with the value of the reference temperature It is a frequency temperature characteristic figure which shows the relationship between difference (DELTA) F and temperature. FIG. 13 is a characteristic diagram showing a relationship between a value obtained by normalizing the vertical axis of FIG. 12 and a frequency correction value. It is a block diagram which shows a correction value calculating part. It is a block diagram which shows the whole structure of other embodiment of this invention. It is a lamp | ramp response figure which shows the frequency difference of two crystal oscillators when temperature is changed continuously. It is a step response figure which shows the output of a frequency difference detection part when temperature is changed 1 degreeC.

  FIG. 1 is a block diagram showing the entirety of an oscillation device configured by applying a crystal oscillator according to an embodiment of the present invention. The oscillation device is configured as a frequency synthesizer that outputs a frequency signal of a set frequency, and includes a voltage controlled oscillator 100 using a crystal resonator, a control circuit unit 200 that configures a PLL in the voltage controlled oscillator 100, and A crystal oscillator (not labeled) that generates a clock signal for operating the DDS 201 for generating a PLL reference signal, and the temperature of the atmosphere in which the crystal resonators 10 and 20 are placed in the crystal oscillator is adjusted. And a heater 5 which is a heating unit for the purpose. Therefore, the crystal oscillator is OCXO.

The oscillation device also includes a temperature compensation unit that performs temperature compensation of a reference clock input to the control circuit unit 200. The temperature compensation unit is not labeled, but corresponds to the left side of the control circuit unit 200 in FIG. 1 and is shared with the circuit unit for controlling the heater 5.
The control circuit unit 200 includes a reference (reference) clock output from a DDS (Direct Digital Synthesizer) circuit unit 201 and a phase of a clock obtained by dividing the output of the voltage controlled oscillator 100 by a frequency divider 204. The comparison is made at 205, and the phase difference as the comparison result is converted into an analog by the charge pump 204. The analog signal is input to the loop filter 206 and controlled so that a PLL (Phase locked loop) is stabilized. Therefore, it can be said that the control circuit unit 200 is a PLL unit. Here, the DDS circuit unit 201 uses a frequency signal output from the first oscillation circuit 1 described later as a reference clock, and is input with frequency data (digital value) for outputting a signal of a target frequency. .

  However, since the frequency of the reference clock has a temperature characteristic, an adder 60 adds a signal corresponding to a frequency correction value to be described later to the frequency data input to the DDS circuit unit 201 in order to cancel the temperature characteristic. ing. By correcting the frequency data input to the DDS circuit unit 201, the temperature variation of the output frequency of the DDS circuit unit 201 based on the temperature characteristic variation of the reference clock is canceled, and as a result, the reference clock is used for the temperature variation. Therefore, the output frequency from the voltage controlled oscillator 100 is stabilized.

  In this embodiment, as described below, the crystal oscillator that creates the reference clock is configured as an OCXO. Therefore, since the frequency of the reference clock is stable, the temperature characteristics of the reference clock cannot be seen. I can say that. However, when a malfunction of the heater or the like occurs, a highly reliable frequency synthesizer can be configured by compensating for the temperature variation of the output frequency of the DDS circuit unit 201 based on the temperature characteristic variation of the reference clock. There are advantages that can be configured.

  Next, the OCXO portion corresponding to the crystal oscillator of the present invention will be described. The crystal oscillator includes a first crystal resonator 10 and a second crystal resonator 20, and the first crystal resonator 10 and the second crystal resonator 20 use a common crystal piece Xb. Configured. That is, for example, the area of the strip-shaped crystal piece Xb is divided into two in the length direction, and excitation electrodes are provided on both the front and back surfaces of each divided area (vibration area). Accordingly, the first crystal resonator 10 is configured by one divided region and the pair of electrodes 11 and 12, and the second crystal resonator 20 is configured by the other divided region and the pair of electrodes 21 and 22. Therefore, it can be said that the first crystal unit 10 and the second crystal unit 20 are thermally coupled.

  A first oscillation circuit 1 and a second oscillation circuit 2 are connected to the first crystal unit 10 and the second crystal unit 20, respectively. The outputs of these oscillation circuits 1 and 2 may be the overtones (harmonics) of the crystal resonators 10 and 20 or the fundamental wave, for example. When obtaining an overtone output, for example, an overtone tuning circuit may be provided in an oscillation loop composed of a crystal resonator and an amplifier, and the oscillation loop may be oscillated with an overtone. Alternatively, the oscillation loop is oscillated with a fundamental wave, and a class C amplifier is provided after the oscillation stage, for example, after the amplifier that is a part of the Colpitts circuit. Further, a tuning circuit that tunes to the overtone may be provided, and as a result, for example, the oscillation frequency of the third overtone may be output from the oscillation circuits 1 and 2.

  Here, for convenience, it is assumed that a frequency signal having the frequency f1 is output from the first oscillation circuit 1 and a frequency signal having the frequency f2 is output from the second oscillation circuit 2, the frequency signal having the frequency f1 is Is supplied to the unit 200 as a reference clock. Reference numeral 3 denotes a frequency difference detection unit. In short, the frequency difference detection unit 3 is a circuit unit for extracting f2-f1-Δfr, which is a difference between f1 and f2, and a difference between Δfr. It is. Δfr is a difference between f1 (f1r) and f2 (f2r) at a reference temperature, for example, 25 ° C. An example of the difference between f1 and f2 is several MHz, for example. The present invention is realized by calculating ΔF which is a difference between a value corresponding to the difference between f1 and f2 and a value corresponding to the difference between f1 and f2 at a reference temperature, for example, 25 ° C., by the frequency difference detection unit 3. . In this embodiment, more specifically, the value obtained by the frequency difference detection unit 3 is {(f2-f1) / f1}-{(f2r-f1r) / f1r}. However, the display of the output of the frequency difference detection unit 3 is abbreviated in the drawing.

  FIG. 2 shows a specific example of the frequency difference detection unit 3. Reference numeral 31 denotes a flip-flop circuit (F / F circuit). A frequency signal having a frequency f1 from the first oscillation circuit 1 is input to one input terminal of the flip-flop circuit 31, and a second signal is input to the other input terminal. A frequency signal having the frequency f2 is input from the oscillation circuit 2, and the frequency signal having the frequency f2 from the second oscillation circuit 2 is latched by the frequency signal having the frequency f1 from the first oscillation circuit 1. In order to avoid redundancy described below, f1 and f2 are treated as representing frequencies or frequency signals themselves. The flip-flop circuit 31 outputs a signal having a frequency of (f2-f1) / f1, which is a value corresponding to the frequency difference between f1 and f2.

A one-shot circuit 32 is provided at the subsequent stage of the flip-flop circuit 31, and the one-shot circuit 32 outputs a one-shot pulse at the rising edge of the pulse signal obtained from the flip-flop circuit 31. 3A to 3D are time charts showing a series of signals so far.
A PLL (Phase Locked Loop) is provided at the subsequent stage of the one-shot circuit 32, and the PLL includes a latch circuit 33, a loop filter 34 having an integration function, an adder 35, and a DDS circuit 36. The latch circuit 33 is for latching the sawtooth wave output from the DDS circuit section 36 with the pulse output from the one-shot circuit 32. The output of the latch circuit 33 is the saw at the timing when the pulse is output. The signal level of the wave. The loop filter 34 integrates the DC voltage at the signal level, and the adding unit 35 adds the DC voltage and a DC voltage corresponding to Δfr (difference between f1 and f2 at a reference temperature, for example, 25 ° C.). DC voltage data corresponding to Δfr is stored in the memory 30 shown in FIG.

  In this example, the sign of the adder 35 is “+” on the input side of the DC voltage corresponding to Δfr, and “−” on the input side of the output voltage of the loop filter 34. The DDS circuit unit 36 receives a DC voltage calculated by the adding unit 35, that is, a voltage obtained by subtracting the output voltage of the loop filter 34 from a DC voltage corresponding to Δfr, and a sawtooth wave having a frequency corresponding to the voltage value. Is output. In order to facilitate the understanding of the operation of the PLL, FIG. 4 shows the state of the output of each part very schematically, and a very schematic explanation is given in order to make it intuitively understandable. When the apparatus is started up, a DC voltage corresponding to Δfr is input to the DDS circuit unit 36 through the adder 35. For example, if Δfr is 5 MHz, a sawtooth wave having a frequency corresponding to this frequency is output from the DDL 36.

  The sawtooth wave is latched with a pulse having a frequency corresponding to (f2-f1) by the latch circuit 33. If (f2-f1) is 6 MHz, for example, the period of the latching pulse is shorter than that of the sawtooth wave. Therefore, the sawtooth latch point gradually decreases as shown in FIG. 4A, and the output of the latch circuit 33 and the output of the loop filter 34 are − as shown in FIGS. 4B and 4C. Gradually go down to the side. Since the sign on the output side of the loop filter 34 in the adding unit 35 is “−”, the DC voltage input from the adding unit 35 to the DDS circuit unit 36 increases. For this reason, the frequency of the sawtooth wave output from the DDS circuit unit 36 becomes high, and when a DC voltage corresponding to 6 MHz is input to the DDS circuit unit 36, the frequency of the sawtooth wave becomes 6 MHz and FIG. The PLL is locked as shown in (c). At this time, the DC voltage output from the loop filter 34 has a value corresponding to Δfr− (f2−f1) = − 1 MHz. That is, it can be said that the integral value of the loop filter 34 corresponds to the integral value of the change of 1 MHz when the sawtooth wave changes from 5 MHz to 6 MHz.

  Contrary to this example, when Δfr is 6 MHz and (f2-f1) is 5 MHz, the latch pulse period is longer than that of the sawtooth, so the latch point shown in FIG. The output gradually increases, and accordingly, the output of the latch circuit 33 and the output of the loop filter 34 also increase. For this reason, since the value subtracted in the adding unit 35 becomes large, the frequency of the sawtooth wave gradually decreases and eventually the PLL is locked when it becomes 5 MHz which is the same as (f2-f1). At this time, the DC voltage output from the loop filter 34 has a value corresponding to Δfr− (f2−f1) = 1 MHz. FIG. 6 shows actual measurement data. In this example, the PLL is locked at time t0.

  As described above, the output of the frequency difference detection unit 3, that is, the output of the averaging circuit 37 shown in FIG. 2 is actually {(f2-f1) / f1}-{(f2r-f1r) / f1r}. This is a value expressed as a 34-bit digital value. The set of values from around −50 ° C. to around 100 ° C. is (f1−f1r) / f1 = OSC1 (unit is ppm or ppb), (f2−f2r) / f2r = OSC2 (unit is ppm or ppb). Then, the change with respect to temperature becomes substantially the same curve as OSC2-OSC1. Therefore, the output of the frequency difference detector 3 can be handled as OSC2−OSC1 = temperature data.

  In addition, since the operation of latching f2 by f1 in the flip-flop 31 is asynchronous, it is necessary to hold the input data for a certain time before and after the metastable (when the input data is latched at the clock edge). There is a possibility that an indefinite interval such as a state where the output becomes unstable due to the clock and input data changing almost simultaneously), and the output of the loop filter 34 may include an instantaneous error. For this reason, an averaging circuit 37 for obtaining a moving average of input values at a preset time is provided on the output side of the loop filter 34 so as to remove the instantaneous error. By providing the averaging circuit 37, the frequency shift information corresponding to the fluctuating temperature can be finally obtained with high accuracy, but the averaging circuit 37 may not be provided.

  Here, OSC2-OSC1 which is frequency shift information corresponding to the fluctuating temperature obtained by the loop filter 34 of the PLL will be described with reference to FIGS. FIG. 7 is a characteristic diagram showing the relationship between temperature and frequency by normalizing f1 and f2 with a reference temperature. Normalization here refers to, for example, setting 25 ° C. as a reference temperature, setting the frequency at the reference temperature to zero with respect to the relationship between temperature and frequency, and obtaining the relationship between the frequency deviation from the frequency at the reference temperature and the temperature. I mean. If the frequency at 25 ° C. in the first oscillation circuit 1 is f1r and the frequency at 25 ° C. in the second oscillation circuit 2 is f2r, that is, f1 and f2 at 25 ° C. are f1r and f2r, respectively. The values on the vertical axis in FIG. 7 are (f1-f1r) and (f2-f2r).

  FIG. 8 shows the rate of change with respect to the frequency at the reference temperature (25 ° C.) with respect to the frequency of each temperature shown in FIG. Therefore, the values on the vertical axis in FIG. 8 are (f1-f1r) / f1r and (f2-f2r) / f2r, that is, OSC1 and OSC2 as described above. The unit of the value on the vertical axis in FIG. 8 is ppm.

  FIG. 9 shows the relationship between OSC1 and temperature (the same as FIG. 8), and the relationship between (OSC2-OSC1) and temperature, and (OSC2-OSC1) has a linear relationship with temperature. I understand. Therefore, it can be seen that (OSC2-OSC1) corresponds to the temperature fluctuation deviation from the reference temperature.

Returning to FIG. 1, the output value of the frequency difference detection unit 3 is substantially (OSC2-OSC1), and this value is the temperature detection at which the crystal units 10 and 20 are placed as shown in FIG. It can be called a value. Therefore, an adder (deviation extraction circuit) 6 is provided in the subsequent stage of the frequency difference detection unit 3, and the temperature set value (34-bit digital value of OSC 2 -OSC 1 at the set temperature) as a digital signal and the output of the frequency difference detection unit 3 are provided. The difference from OSC2-OSC1 is extracted. As the temperature setting value, it is preferable to select a temperature at which the value of OSC1 corresponding to the first crystal resonator 10 for obtaining the output of the crystal oscillator is less likely to vary due to temperature change. As this temperature, for example, 50 ° C. corresponding to the bottom portion is selected in the relationship curve between OSC1 and temperature shown in FIG. In addition, 10 degrees may be set as the set temperature from the viewpoint of the temperature at which the value of OSC1 does not easily change due to a temperature change. In this case, the temperature may be lower than room temperature, so it is combined with a cooling unit such as a heating unit and a Peltier element. A temperature control unit will be provided.
A loop filter 61 corresponding to an integration circuit unit is provided after the adder 6.

Further, a PWM interpolation unit 62 is provided at the subsequent stage of the loop filter 61. PWM interpolation unit 62 performs a transform representing a pulse signal of a constant time 14-bit digital signal (2's complement ^{-2 13} to ^{+2 13).} For example, when the minimum H pulse width is 10 nsec, 2 ¹⁴ * 10 ⁻⁹ = 16.384 msec is set as a fixed time, and the pulse number digital signal during that period is expressed. Specifically, it is expressed as follows. 14 when the digital value of the bit is zero, H pulse number between 16.384msec is ^{2 13.} 14 when the digital value of the bit is ^{-2 13,} H pulse number between 16.384msec is zero. When the 14-bit digital value is 2 ¹³ −1, the number of H pulses during 16.384 msec is 2 ¹⁴ −1.

  A low-pass filter (LPF) 63 is provided at the subsequent stage of the PWM interpolation unit 62, and outputs a DC voltage corresponding to the number of pulses as the output by averaging the outputs from the PWM interpolation unit 62. That is, in this example, the PWM interpolation unit 62 and the low pass filter 63 are for converting a digital value into an analog value, and instead of using these, a digital / analog converter may be used.

  A heater circuit 5 corresponding to a heating unit is provided at the subsequent stage of the low-pass filter (LPF) 63. As shown in FIG. 10, the heater circuit 5 includes a transistor 64 having the output terminal of the low-pass filter 63 connected to the base and a voltage supplied from the power supply unit Vc to the collector, and between the emitter of the transistor 64 and the ground. The resistor 65 is connected. The relationship between the voltage supplied to the base of the transistor 64 and the total power of the power consumption of the transistor 64 and the power consumption of the resistor 65 is a linear relationship. Therefore, the temperature data and the temperature set value described above are The heat generation temperature is linearly controlled according to the difference between the two. In this example, since the transistor 64 is also a part of the heat generating portion, the expression “heater circuit 5, which serves as both a heater and a heater control circuit”, is used.

  FIG. 11 is a diagram showing a schematic structure of the oscillation device shown in FIG. Reference numeral 51 denotes a container, and 52 denotes a printed circuit board provided in the container 51. On the upper surface side of the printed circuit board 52, an integrated circuit unit 300 and a control circuit unit 200, in which circuits for performing digital processing including the crystal resonators 10 and 20, the oscillation circuits 1 and 2 and the frequency difference detection unit 3 are integrated into one chip. Etc. are provided. On the lower surface side of the printed circuit board 52, for example, a heater 5 is provided at a position facing the crystal resonators 10 and 20, and the crystal resonators 10 and 20 are maintained at a set temperature by the heat generated by the heater 5.

The oscillation device according to this embodiment also includes a temperature compensation unit that performs temperature compensation of the reference clock input to the control circuit unit 200 as described above. That is, the oscillation device of this example is a combination of OCXO and TCXO. However, the present invention does not have to combine TCXO. The temperature compensation unit includes crystal resonators 10 and 20, oscillation circuits 1 and 2, a frequency difference detection unit 3, and a correction value calculation unit 4. That is, the frequency difference detection unit 3 is a part of the temperature control unit for the heater 5, but is also a part of the temperature compensation unit.
The frequency deviation information corresponding to the fluctuating temperature obtained by the loop filter 34 of the PLL is input to the correction value calculation unit 4 which is a correction value acquisition unit shown in FIG. 1, and the frequency correction value is calculated here. The frequency shift information is as described above.

  FIG. 12 shows the relationship between OSC1 and temperature (the same as FIG. 8), and the relationship between (OSC2-OSC1) and temperature, and (OSC2-OSC1) has a linear relationship with temperature. I understand. Therefore, it can be seen that (OSC2-OSC1) corresponds to the temperature fluctuation deviation from the reference temperature. In general, it is said that the frequency temperature characteristic of the crystal resonator is expressed by a cubic function. Therefore, the relationship between the frequency correction value that cancels the frequency fluctuation due to this cubic function and (OSC2-OSC1). Is obtained, the frequency correction value is obtained based on the detected value of (OSC2-OSC1).

  As described above, the oscillation device of this embodiment uses the frequency signal (f1) obtained from the first oscillation circuit 1 as a reference clock of the control circuit unit 200 shown in FIG. Due to the existence of the characteristics, temperature correction is being performed with respect to the frequency of the reference clock. For this reason, first, a function indicating the relationship between the temperature and f1 normalized by the reference temperature is obtained in advance, and a function for canceling the frequency fluctuation of f1 by this function is obtained as shown in FIG. More specifically, f1 of the function is (f1−f1r) / f1r = OSC1 which is a frequency variation rate at the reference temperature. Therefore, the vertical axis in FIG. 13 is -OSC1. In this example, the function is defined as, for example, a ninth-order function in order to perform temperature correction with high accuracy.

  Since the temperature and (OSC2-OSC1) are in a linear relationship as described above, the horizontal axis in FIG. 13 is the value of (OSC2-OSC1), but if the value of (OSC2-OSC1) is used as it is, Since the amount of data for specifying this value increases, the value of (OSC2-OSC1) is normalized as follows. That is, an upper limit temperature and a lower limit temperature at which the oscillation device will actually be used are determined, the value of (OSC2-OSC1) at the upper limit temperature is +1, and the value of (OSC2-OSC1) at the lower limit temperature Is treated as -1. In this example, as shown in FIG. 13, -30 ppm is set to +1, and +30 ppm is set to -1.

  In this example, the frequency characteristic with respect to the temperature in the quartz resonator is handled as a ninth-order polynomial approximation. Specifically, the relationship between (OSC2-OSC1) and temperature is obtained by actual measurement at the time of crystal unit production, and the relationship between temperature and -OSC1 that cancels the frequency variation with respect to temperature is shown from the actual measurement data. A correction frequency curve is derived, and a ninth-order polynomial approximate expression coefficient is derived by the method of least squares. The polynomial approximate expression coefficients are stored in advance in the memory 30 (see FIG. 1), and the correction value calculation unit 4 performs calculation processing of the expression (1) using these polynomial approximate expression coefficients.

Y = P1 · X ⁹ + P2 · X ⁸ + P3 · X ⁷ + P4 · X ⁶ + P5 · X ⁵ + P6 · X ⁴ + P7 · X ³ + P8 · X ² + P9 · X (1)
In Equation (1), X is frequency difference detection information, Y is correction data, and P1 to P9 are polynomial approximate expression coefficients.

Here, X is a value obtained by the frequency difference detector 3 shown in FIG. 1, that is, a value (OSC2-OSC1) obtained by the averaging circuit 37 shown in FIG.
An example of a block diagram for executing the calculation in the correction value calculation unit 4 is shown in FIG. In FIG. 14, reference numerals 401 to 409 denote arithmetic units that perform arithmetic operations on the terms of the equation (1), 400 denotes an adder, and 410 denotes a circuit that performs rounding processing. The correction value calculation unit 4 uses, for example, one multiplication unit, obtains the value of the ninth power term by this multiplication unit, and then obtains the value of the eighth power term by the multiplication unit. In other words, the multiplication unit may be reused to finally add the values of the power terms. Further, the calculation formula of the correction value is not limited to using the ninth-order polynomial approximation formula, but an approximation formula of the order corresponding to the required accuracy may be used.

  Next, the overall operation of the above-described embodiment will be summarized. When attention is paid to the crystal oscillator of this oscillation device, the output of the crystal oscillator corresponds to the frequency signal output from the first oscillation circuit 1. The heater 5 is heated so that the atmosphere in which the crystal resonators 10 and 20 are placed becomes a set temperature. The first crystal unit 10 and the first oscillation circuit 1 generate a frequency signal that is an output of the crystal oscillator, and together with the second crystal unit 20 and the second oscillation circuit 2, a temperature detection unit. Have a role as. The value OSC2-OSC1 corresponding to the frequency difference between the frequency signals respectively obtained from the oscillation circuits 1 and 2 corresponds to the temperature as described above, and the temperature setting value (for example, the value of OSC2-OSC1 at 50 ° C.) is added by the adding unit. Difference) is taken out.

This difference is integrated by the loop filter 61, and then converted into a DC voltage to adjust the control power of the heater 5. As can be seen from the characteristic diagram shown in FIG. 9, when the value of OSC1 at 50 ° C. is −1.5 × 10 ⁵ , the output of the adder 6 is a positive value when the temperature is lower than 50 ° C. As the temperature decreases, it increases. Therefore, the control power of the heater 5 increases as the ambient temperature in which the crystal units 10 and 20 are placed is lower than 50 ° C. When the ambient temperature is higher than 50 ° C., the negative value is obtained, and the absolute value is increased as the temperature is increased. Therefore, as the temperature becomes higher than 50 ° C., the heater power is reduced. For this reason, the temperature of the atmosphere in which the crystal resonators 10 and 20 are placed tends to be maintained at the set temperature of 50 ° C., so that the output frequency from the first oscillator 1 that is the oscillation output is stabilized. As a result, in the control circuit unit 200 that uses the output from the first oscillator 1 as a clock signal, the frequency of the reference signal supplied to the phase comparison unit 205 is stabilized, so that the output of the oscillation device (frequency synthesizer) The output frequency from a certain voltage controlled oscillator 100 is also stabilized.

  On the other hand, the output (OSC2-OSC1) from the frequency difference detection unit 3 is input to the correction value calculation unit 4, and the calculation of the above-described equation (1) is executed to obtain the frequency correction data as temperature correction data. The calculation of equation (1) is a process for obtaining the value of the vertical axis of the correction frequency curve corresponding to the value obtained based on the output value of the frequency difference detection unit 3 in the characteristic diagram shown in FIG.

  As shown in FIG. 1, the first crystal unit 11 and the second crystal unit 12 are configured by using a common crystal piece Xb and are thermally coupled to each other. The frequency difference is a value that corresponds to the environmental temperature very accurately. Therefore, the output of the frequency difference detection unit 3 is temperature difference information between the environmental temperature and the reference temperature (25 ° C. in this example). Since the frequency signal f1 output from the first oscillation circuit 11 is used as the main clock of the control unit 200, the correction value obtained by the correction value calculation unit 4 is shifted from 25 ° C. This is used as a signal for compensating the operation of the control unit 200 in order to cancel the influence on the operation of the control unit 200 based on the frequency deviation of f1. As a result, the output frequency of the voltage controlled oscillator 100, which is the output of the oscillation device 1 of the present embodiment, becomes stable regardless of temperature fluctuations.

  As described above, according to the above-described embodiment, the difference between the values corresponding to the frequency difference between the frequency signals obtained from each of the crystal resonators 10 and 20 is used as the temperature detection value. The heater 5 that manages the ambient temperature is controlled based on the temperature detection value. For this reason, the ambient temperature can be maintained at the set temperature with high accuracy, and the output of the crystal oscillator (the output of the first oscillator 1) is stabilized.

Furthermore, in this embodiment, the output of the crystal oscillator is supplied as a clock signal to the control circuit unit 200 that generates the oscillation output of the frequency synthesizer that is the oscillation device, and the clock signal is corrected using a value corresponding to the frequency difference. ing. That is, the frequency synthesizer adds the correction value obtained by the correction value calculation unit 4 to the frequency setting value of the DDS 201, and performs temperature compensation of the main clock (f1) input to the DDS 201. Thus, the frequency synthesizer has the following advantages by having both functions of OCXO and TCXO. Although the manufacturer defines the operating temperature range of the frequency synthesizer, the output frequency is stable even when the user uses the frequency synthesizer in an environment outside the operating temperature range. In addition, when the temperature setting value by the heater is increased to increase the upper limit value of the operating temperature range, the power consumption of the heater increases and the scale of the heater circuit also increases, but by using the TCXO function, There is an advantage that the power consumption of the heater can be suppressed.
However, the frequency synthesizer may be configured not to include the correction value calculation unit 4 (not to have a TCXO function) as shown in FIG. Even in this case, the value corresponding to the difference between the value corresponding to the difference between f1 and f1r and the value corresponding to the difference between f2 and f2r is handled as the temperature at that time. Since the degree of correlation between this value and temperature is extremely high, the temperature of the atmosphere in which the crystal unit is placed is extremely stabilized by controlling the power supplied to the heating unit using the value as a temperature detection value. As a result, an oscillation output with high stability can be obtained.
Here, the loop filter 61 is a circuit for determining the loop gain and damping, and the coefficients of the loop gain and damping can be adjusted by digital values. Even if the heat transfer coefficient is changed by changing the structure by digitizing the loop coefficient, it is possible to easily adjust the coefficient for each structure.

  In the above example, the third overton of each of the crystal resonators 10 and 20 is extracted as the output frequency, and the frequency temperature characteristic of the overtone has a large temperature change, so the value corresponding to these differences is the temperature This is a preferred embodiment. However, each fundamental wave of the crystal resonators 10 and 20 may be taken out as an output frequency, and a value corresponding to these differences may be used as a temperature value. Alternatively, the fundamental wave and the overtone may be extracted from one and the other of the crystal resonators 10 and 20, respectively, and a value corresponding to the difference between them may be handled as a temperature value.

  Further, in order to obtain the frequency difference detection information, a pulse corresponding to the difference frequency between f1 and f2 is created, and the sawtooth signal output from the DDS circuit unit is latched by the latch circuit by the pulse, and the latched signal value And the integrated value is output as the frequency difference, and the difference between this output and the value corresponding to the difference between f1r and f2r is extracted and input to the DDS circuit unit to constitute the PLL. . When f1 and f2 are counted and the difference is acquired as in Patent Document 1, the count time directly affects the detection accuracy. However, in such a configuration, since there is no such problem, the detection accuracy is high. . Actually, both methods were compared by simulation, and in the method of counting the frequency, a count time of 200 ms was set. As a result, the detection accuracy of the method of this embodiment was about 50 times higher.

  The frequency difference detection unit 3 uses (f1−f1r) and (f2−f2r) as values corresponding to the difference value between the value corresponding to the difference between f1 and f1r and the value corresponding to the difference between f2 and f2r. ) May be used, and in this case, the temperature is obtained using the graph of FIG.

In the above embodiment, in the description of FIG. 8 to FIG. 10, the change in frequency is displayed in “ppm” units. However, in an actual digital circuit, all are handled in binary numbers. The frequency setting accuracy is calculated by the number of constituent bits, and is 34 bits, for example. As an example, when a clock frequency of 10 MHz is supplied to the DDS circuit unit 201 included in the control circuit unit 200 shown in FIG. 1, the variation frequency of this clock is 100 Hz [variation ratio calculation].
100Hz / 10MHz = 0.00001
[Ppm conversion]
0.00001 * 1e6 = 10 [ppm]
[DDS setting accuracy conversion]
0.00001 * 2 ^ 34≈171,799 [ratio-34 bit (provisional name)].

In the case of the above configuration, the frequency setting accuracy is expressed by the following equation (2).
1 × [ratio−34 bits] = 10 M [Hz] /2^34≈0.58 m [Hz / bit] (2)
Therefore, 100 [Hz] /0.58 m [Hz / bit] ≈171,799 [bit (ratio−34 bits)].
Moreover, 0.58 mHz can be calculated as in the following equation (3) with respect to 10 MHz.
0.58 m [Hz] / 10 M [Hz] * 1e9≈0.058 [ppb] (3)
Therefore, the relationship of the formula (4) is established from the formulas (2) and (3).

1e9 / 2 ^ 34 = 0.058 [ppb / ratio−34 bits] (4)
That is, the frequency processed by the DDS circuit 36 disappears, and only the number of bits is related.

  Furthermore, in the above-described example, the first crystal unit 10 and the second crystal unit 20 use the common crystal piece Xb, but the crystal piece Xb may not be shared. In this case, for example, an example in which the first crystal resonator 10 and the second crystal resonator 20 are arranged in a common housing can be given. According to such a configuration, the same effects can be obtained because they are placed under substantially the same temperature environment.

The output signal of the DDS circuit unit 36 of the frequency difference detection unit 3 is not limited to a sawtooth wave, but may be a frequency signal that repeatedly increases and decreases with time, and may be a sine wave, for example. The frequency difference detection unit 3 counts f1 and f2 with a counter, and subtracts a value corresponding to Δfr from the difference value between the count values, and outputs a value corresponding to the obtained count value. Also good.
In the above embodiment, the first crystal resonator 10 and the first oscillation circuit 1 have a role of taking out a temperature detection value and a role of creating an output of the crystal oscillator. That is, the oscillation circuit 1 shares an oscillation circuit for temperature detection and an oscillation circuit for output of the crystal oscillator. However, in the present invention, for example, three crystal oscillators and three oscillation circuits are prepared. For example, in the configuration of FIG. 1, a third crystal oscillator and a third oscillator circuit connected to the crystal oscillator are provided. The output of the third oscillation circuit is used as the output of the crystal oscillator, and the oscillation outputs of the remaining first oscillation circuit and second oscillation circuit are input to the frequency difference detection unit to obtain the temperature detection value. May be. In this case, if OCXO and TCXO are combined, the output of the third crystal oscillation circuit is used as the clock of DDS201.
The frequency synthesizer which is the oscillation device shown in FIG. 1 and FIG. 15 includes crystal resonators 10 and 20, oscillation circuits 1 and 2, frequency difference detection unit 3, addition unit 6 to heater circuit 5. The crystal oscillator according to the embodiment is used. However, the present invention is not limited to being configured as a frequency synthesizer, and may be configured such that the oscillation output of the first oscillation circuit 1 is the output of the crystal oscillator of the present invention, that is, the control circuit unit 200 is not used. .

  Two crystal resonators 10 when the temperature of the atmosphere in which the crystal resonators 10 and 20 are placed are continuously changed at an inclination of 1 ° C./1 minute using the circuit shown in the above-described embodiment. When the lamp response waveform showing the transition of the frequency difference of 20 was examined, the result shown in FIG. 16 was obtained. For both f1 and f2, a third-order overtone is used. One scale in FIG. 16 corresponds to 20 m ° C. (20 ° C./1000), and an offset equivalent to 20 m ° C. can be confirmed when the temperature gradient is 1 ° C./1 minute. The offset amount can be reduced by optimizing the coefficient of the loop filter 61. Can be reduced.

  Further, when the step response waveform showing the transition of the output of the frequency difference detection unit 3 when the ambient temperature was changed by 1 ° C. was examined, the result shown in FIG. 17 was obtained. From this result, it can be seen that the output (OSC2-OSC1) of the frequency difference detector 3 follows the temperature change. The overshoot portion of the response waveform can be improved by adjusting the coefficient of the loop filter 61.

DESCRIPTION OF SYMBOLS 1 1st oscillation circuit 2 2nd oscillation circuit 10 1st crystal oscillator 20 2nd crystal oscillator 3 Frequency difference detection part 31 Flip-flop circuit 32 One shot circuit 33 Latch circuit 34 Loop filter 35 Addition part 36 DDS Circuit unit 4 Correction value calculation unit (correction value acquisition unit)
5 Heater Circuit 6 Adder 100 Voltage Control Oscillator 200 Control Circuit

Claims (6)

An oscillator circuit for oscillator output connected to a crystal unit;
A heating unit for stabilizing the temperature of the atmosphere in which the crystal unit is placed;
A first crystal unit configured by providing a first electrode on a crystal piece;
A second crystal unit configured by providing a second electrode on a crystal piece;
A first oscillation circuit and a second oscillation circuit connected to the first crystal unit and the second crystal unit, respectively;
The oscillation frequency of the first oscillation circuit is f1, the oscillation frequency of the first oscillation circuit at the reference temperature is f1r, the oscillation frequency of the second oscillation circuit is f2, and the oscillation frequency of the second oscillation circuit at the reference temperature is f2r. Then, a frequency difference detection unit that obtains a value corresponding to {(f2-f2r) / f2r}-{(f1-f1r) / f1r} as a temperature detection value;
An adder for extracting a deviation between the temperature setting value of the temperature of the atmosphere in which the crystal unit is placed and the temperature detection value;
A crystal oscillator comprising: a circuit unit that controls electric power supplied to the heating unit based on a deviation taken out by the adding unit. (1) an oscillator circuit for outputting an oscillator connected to a crystal unit;
(2) a heating unit for stabilizing the temperature of the atmosphere in which the crystal unit is placed;
(3) a first crystal unit configured by providing a first electrode on a crystal piece;
(4) a second crystal unit configured by providing a second electrode on a crystal piece;
(5) a first oscillation circuit and a second oscillation circuit connected to the first crystal unit and the second crystal unit, respectively;
(6) The oscillation frequency of the first oscillation circuit is f1, the oscillation frequency of the first oscillation circuit at the reference temperature is f1r, the oscillation frequency of the second oscillation circuit is f2, and the oscillation frequency of the second oscillation circuit at the reference temperature Let f2r be
A pulse generating unit that generates a pulse having a frequency difference between f1 and f2, and a DDS circuit unit that outputs a frequency signal that repeatedly increases and decreases with time at a frequency according to the magnitude of the input DC voltage A latch circuit that latches the frequency signal output from the DDS circuit unit with the pulse generated by the pulse generation unit, and integrates the signal value latched by the latch circuit to detect the integrated value of the temperature A frequency difference detection comprising: a loop filter that outputs as a value; and an adder that extracts a difference between the output of the loop filter and a value corresponding to a difference between f1r and f2r and uses the difference as an input value of the DDS circuit unit And
(7) an adding unit for extracting a deviation between the temperature setting value of the atmosphere in which the crystal unit is placed and the temperature detection value;
(8), further comprising a circuit section for controlling the power supplied to the heating unit based on said deviations taken by the adding unit to take out the deviations of the temperature setting value and the detected temperature value Crystal oscillator characterized by   3. The crystal oscillator according to claim 1, further comprising an integration circuit unit that integrates the deviation extracted by the addition unit and outputs the integration to the circuit unit.   4. The crystal oscillator according to claim 1, wherein the oscillation circuit for outputting the oscillator and one of the first oscillation circuit and the second oscillation circuit are shared. 5. 3. The crystal oscillator according to claim 1, wherein each of the first oscillation circuit and the second oscillation circuit uses an overtone as an oscillation output. 3. An oscillating device comprising: the crystal oscillator according to claim 1; and a main body circuit unit of an oscillating device including a PLL using an oscillation output of the crystal oscillator as a clock signal.

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