JP6068388B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine called a pachinko machine.

2. Description of the Related Art Conventionally, a mechanism for forcibly resetting a reset signal by inputting a reset signal to a reset terminal of a CPU in which a malfunction or state abnormality has occurred, or a gaming machine having such a function is known.
For example, in Patent Document 1, when a period during which a clock signal (status signal) from a monitoring target CPU such as an effect control board or an audio control board is not input is a predetermined period or more, the control signal is changed from HIGH level to LOW as a reset level. A power supply board having a function of resetting a CPU (by outputting a reset signal) by fixing to a level (watchdog function) is disclosed.
Such a watchdog function can be performed not only between the power supply board and each control board but also between CPUs provided on a board such as a liquid crystal board (image control board) or a liquid crystal relay board.

JP 2006-101905 A

In either case, when transmitting / receiving a control signal between the substrates, there is a problem that noise is easily applied to the reset signal due to the wiring between the substrates.
The control signal is a signal fixed at HIGH or LOW at the reset level. When a waveform change occurs due to unnecessary noise on the control signal, the CPU that should be operating normally is reset. As a result, the game and production are hindered, and the player's interest must be cut off.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine capable of maintaining the interest of the player without causing unnecessary reset in the CPU.

The present invention has been made to solve the above-described problems, and can be realized by the following modes.
A gaming machine according to a first aspect includes a first microcomputer to be reset, a reset unit that resets the first microcomputer, and a second microcomputer that performs reset control of the first microcomputer, The first microcomputer supplies the second microcomputer with a first signal and a second signal which are independent of each other and indicate different states of the first microcomputer, and the second microcomputer Supply means for supplying intermittent pulse signals to the means, first receiving means for receiving the first signal, second receiving means for receiving the second signal, and the first microcomputer When the first signal is received and the second signal is received, the first microcontroller It determines not to reset the Yuta, wherein when at least one of the first signal and the second signal is not received from the first microcomputer, determining means and resetting said first microcomputer And when determining that the first microcomputer is to be reset by the determination unit, the supply of the pulse signal by the supply unit is stopped, and the supply of the pulse signal by the supply unit is stopped, When it is determined by the determination means that the first microcomputer is not reset, the supply of the pulse signal by the supply means is restarted, and the reset means supplies the pulse signal supplied from the second microcomputer within a predetermined period. Depending on the presence or absence of the first microcomputer And wherein the game machine to be set.

  A gaming machine capable of maintaining the interest of the player without causing unnecessary reset in the CPU can be realized.

The front view which showed the structural example of the pachinko machine as an example of the game machine which concerns on embodiment of this invention. The front view of the game board of the game machine concerning the embodiment of the present invention. The block diagram which showed the structure of the game control apparatus which performs game control of the game machine of this embodiment. The figure explaining an example of the reset mechanism in this embodiment. The conceptual diagram explaining the reset mechanism in the conventional game machine. The conceptual diagram explaining the reset mechanism in the conventional game machine. The conceptual diagram explaining the problem which the conventional reset mechanism had. The conceptual diagram explaining the reset mechanism which concerns on this embodiment (the 1). The conceptual diagram explaining the reset mechanism which concerns on this embodiment (the 2). The conceptual diagram explaining the reset mechanism which concerns on this embodiment (the 3). The figure explaining the effect by the reset mechanism which concerns on this embodiment. The flowchart explaining the state confirmation command transmission process which CPU of an image control board performs. The flowchart explaining the state confirmation control process which CPU of an image control board performs. 5 is a flowchart for explaining control signal transmission processing executed by a CPU of an image control board. The flowchart explaining the reset control process which WD-IC with which a liquid crystal relay board | substrate is provided performs.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
FIG. 1 is a front view showing a configuration example of a pachinko machine as an example of a gaming machine according to an embodiment of the present invention, and FIG. 2 is a front view of a gaming board of the gaming machine according to the embodiment of the present invention.

In FIG. 1, the pachinko machine 1 includes an outer frame 300 that is attached to an island facility of a game store, and a glass frame 310 that is rotatably supported by the outer frame 300. The outer frame 300 is provided with a game board 2 in which a game area 3 in which game balls flow down is formed.
The glass frame 310 supports a glass plate (not shown) that covers the game area 3 so as to be visible in front of the game board 2 (on the player side).
In addition, the glass frame 310 has an operation handle 311 for launching a game ball toward the game area 3 by being rotated, an audio output device (speaker) 312, and upper and lower effect lights having a plurality of lamps. Devices 313a and 313b, an effect button 314 for changing the effect mode by a pressing operation, and left and right effect movable illumination devices 320L and 320R are provided.
The effect movable illumination devices 320L and 320R are provided in the upper left corner and the upper right corner of the glass frame 310.
The stage movable illumination devices 320L and 320R include a movable illumination unit (not shown), and can automatically change from a state in which the movable illumination unit is housed (closed) to a state in which the movable illumination unit is opened (projected). It is configured as follows.

The audio output device 312 outputs BGM (background music), SE (sound effect), etc., and produces effects by sound. The lighting devices for production 313a and 313b change the light irradiation direction and the emission color of each lamp. Thus, the lighting is performed.
Further, a tray unit 315 is provided below the glass frame 310. The tray unit 315 is provided with a ball tray portion that stores a plurality of game balls. The ball tray portion has a downward inclination so that the game balls flow down toward the operation handle 311. . Then, when the player rotates the operation handle 311, the game ball is launched into the game area 3.
When the game ball launched as described above rises between the rails 5a and 5b and exceeds the ball return prevention piece 5c, it reaches the game area 3 and then falls in the game area 3. At this time, the game ball falls unpredictably by a plurality of nails and windmills provided in the game area 3.

Next, the configuration of the game area 3 of the game board 2 will be described.
1 and 2, an opening 3A is formed at the center of the game area 3, and a decorative member 6 that affects the flow of the game ball is provided along the periphery of the opening 3A. An image display device 7 composed of a liquid crystal display device or the like is provided on a substantially central portion (open portion) of the decorative member 6 and on the back side of the game board 2.
In addition, a first start port 13 and a second start port 14 that form a start region into which a game ball can enter are provided in a region below the center of the game region 3.
The second start port 14 has a second start port opening / closing door 14b, the first mode in which the second start port opening / closing door 14b is maintained in a closed state, and the second start port opening / closing door 14b in an open state. The second aspect is controlled to be movable. Therefore, when the second start port 14 is in the first mode, there is no opportunity for winning a game ball, and when it is in the second mode, the chance for winning a game ball is increased.

Here, the first start port 13 is provided with a first start port switch 13a (see FIG. 3) for detecting the entrance of a game ball, and the second start port 14 is a second for detecting the entrance of a game ball. A start port switch 14a (see FIG. 3) is provided. Then, when the first start port switch 13a or the second start port switch 14a detects the entry of a game ball, a special symbol determination random number or the like to be described later is acquired, and a special game such as a big hit game or a small hit game is executed. A lottery for rights acquisition (hereinafter referred to as “special game lottery”) is performed. When the first start port switch 13a or the second start port switch 14a detects the entry of a game ball, a predetermined prize ball (for example, three game balls) is paid out. In the pachinko machine 1 according to the present embodiment, when a game ball enters the first start port 13 or the second start port 14, for example, about three payouts are performed. It is not always necessary to perform a prize ball accompanying a ball entry.
Gates 15 are provided in the left and right regions of the decoration member 6, and further, a first grand prize winning port 16 and a second grand prize winning port 17, which are large winning areas, are provided in the right region of the decoration member 6. .
For this reason, if the operation ball 311 is not turned into a game ball that is driven by a strong force by rotating the operation handle 311 to the gate 15 on the right side of the decorative member 6, the first grand prize opening 16, and the second big prize opening 17, It is configured not to pass or win.

The gate 15 is provided with a gate switch 15a (see FIG. 3) for detecting the passage of the game ball. When the gate switch 15a detects the passage of the game ball, the gate 15 obtains a random number for determining auxiliary symbols, A symbol winning lottery is performed.
The first grand prize winning opening 16 is composed of an opening formed in the game board 2. A first big prize opening / closing door 16b that can project from the game board surface side to the glass plate side (front side) is provided at the lower part of the first big prize opening 16, and the first big prize opening opening / closing door 16b is provided. It is movably controlled between an open state protruding to the game board surface side and a closed state buried in the game board surface. When the first grand prize opening opening / closing door 16b protrudes from the game board surface, it functions as a tray for guiding the game ball into the first big prize opening 16, and the game ball can enter the first big prize opening 16. Become. The first big prize opening 16 is provided with a first big prize opening detection switch 16a. When the first big prize opening detection switch 16a detects the entry of a game ball, for example, 15 prize balls are set. Game balls).

The second grand prize opening 17 is normally maintained in a closed state by a second big prize opening opening / closing door (movable piece) 17b, and it is impossible to enter a game ball. On the other hand, when a predetermined special game is started, the second grand prize opening opening / closing door 17b is opened and the second big winning opening opening / closing door 17b guides the game ball into the second big winning opening 17. It functions as a taxiway, and a game ball can enter the second big prize opening 17. The second big prize opening 17 is provided with a second big prize opening switch 17a (see FIG. 3). When the second big prize opening switch 17a detects the entry of a game ball, a predetermined prize ball ( For example, 15 game balls) are paid out.
Further, the lowermost area of the game area 3 does not enter any of the general winning opening 18, the first starting opening 13, the second starting opening 14, the first major winning opening 16, and the second large winning opening 17. An out port 19 is provided for discharging the game balls.
When a game ball wins the general winning opening 18, a predetermined prize ball (for example, 10 game balls) is paid out.

On the lower left side of the game board 2, a first special symbol display device 20, a second special symbol display device 21, an auxiliary symbol display device 22, a first special symbol hold indicator 23, a second special symbol hold indicator 24, an auxiliary A display area 9 such as a symbol hold indicator 25 is provided.
The first special symbol display device 20 is the number of rounds of jackpots when the result of the special game lottery performed when the game ball enters the first start port 13 and the result of the special game lottery is a jackpot Is notified. The second special symbol display device 21 displays the number of rounds of the jackpot when the result of the special game lottery performed when the game ball enters the second start port 14 and the result of the special game lottery is a jackpot. It is for notification.

  Here, the “special game lottery” means that when a game ball enters the first start port 13 or the second start port 14, a special symbol determination random number value is acquired, and the acquired special symbol determination random value is acquired. Is a random number value corresponding to “big hit” or a random number value corresponding to “small hit”. The result of the special game lottery is not immediately notified to the player, and the first special symbol display device 20 or the second special symbol display device 21 performs a variable display such as blinking of a plurality of special symbol LEDs, When a predetermined fluctuation time has elapsed, the LEDs are stopped and displayed in a combination corresponding to the result of the special game lottery, and the player is notified of the lottery result and the number of jackpot rounds in the case of a big win.

  Further, in this embodiment, “big hit” means that a right to win a big hit game is acquired in a special game lottery performed on the condition that a game ball has entered the first start port 13 or the second start port 14. Say what you did. In the “hit game”, a round game in which the first big prize opening 16 or the second big prize opening 17 is opened is performed a predetermined number of rounds. For example, 2 times, 8 times, and 12 times. A predetermined time is set for the maximum opening time of the first grand prize port 16 or the second grand prize port 17 in each round game, and during this time, the first grand prize port 16 or the second grand prize port 17 is set. When a predetermined number of game balls (for example, nine) enter, one round game is completed. In other words, the “big hit game” is a game in which a game ball can enter the first grand prize winning opening 16 or the second big winning prize opening 17 and the player can acquire a winning ball according to the winning prize.

Further, the auxiliary symbol display device 22 is for notifying the lottery result of the auxiliary symbol that is performed when the game ball passes through the gate 15. When the winning symbol is won by the auxiliary symbol lottery, the auxiliary symbol display device 22 is turned on, and then the second start port 14 is controlled to the second mode for a predetermined time. That is, the second start port 14 is controlled from a closed state where it is difficult to win a game ball to an open state where a game ball is easy to win.
Here, the “auxiliary symbol lottery” is a random number value for auxiliary symbol determination when the game ball passes the gate 15, and the acquired random number value for auxiliary symbol determination is a random value corresponding to “win”. This is the process of determining whether or not there is.
As for the result of the auxiliary symbol lottery, the game ball passes through the gate 15 and the lottery result is not immediately notified. Instead, the auxiliary symbol display device 22 displays a variation such as blinking of the LED for the auxiliary symbol, When the predetermined fluctuation time has elapsed, the auxiliary symbol corresponding to the auxiliary symbol lottery result is stopped and the lottery result is notified to the player.

Furthermore, when the game ball enters the first start port 13 or the second start port 14 during the special symbol change display or the special game to be described later, the result notification of the special game lottery cannot be immediately performed. The lottery result of the special game lottery is put on hold under certain conditions. More specifically, the random number value for special symbol determination acquired when the game ball enters the first start port 13 is stored as the first hold, and when the game ball enters the second start port 14 The acquired special symbol determination random number value is stored as the second hold.
For both of these holds, the upper limit hold number is set to four, and the hold numbers are the first special symbol hold indicator 23 and the second special symbol hold indicator 24 in the display area 9 as the first hold display means. Is displayed.

The upper limit reserved number of auxiliary symbols is also set to four, and the number of reserved symbols is the auxiliary symbol hold indicator 25 in the same manner as the first special symbol hold indicator 23 and the second special symbol hold indicator 24. Is displayed.
On the upper surface of the tray unit 315, an effect button 314 generally called a chance button is arranged. The operation of the effect button 314 is provided with an effect button switch (SW) 314a (see FIG. 3). For example, guidance for prompting the operation of the effect button 314 is displayed on the image display device 7 in the case of a specific reach effect during the game. It is valid while

  On the image display device 7, for example, an effect symbol 31 corresponding to the first special symbol on which the variable display is performed in the first special symbol display device 20 is displayed. The effect symbol 31 is stopped and displayed in a specific combination (for example, 777), thereby notifying the jackpot or the like that is a special game.

FIG. 3 is a block diagram showing a configuration of a game control device that performs game control of the gaming machine of the present embodiment.
In the game control device shown in FIG. 3, a game control board 211 is provided as a main control board for controlling the progress of the game. Further, an effect control board 221, an image control board 231, a lamp control board 241, a payout control board 251 and the like are provided as sub-control boards.
The game control board 211 includes a CPU 212, a ROM 213, a RAM 214, and the like, and performs main control of the game machine.

  The game control board 211 has a first start port SW13a provided in the first start port 13, a second start port SW14a provided in the second start port 14, and a second start port opening / closing of the second start port 14. A second start opening solenoid (SOL) 14c for opening and closing the door 14b, a gate SW 15a provided in the gate 15, a first big winning opening SW 16a for detecting a game ball won in the first big winning opening 16, A first grand prize opening solenoid (SOL) 16c for opening and closing the first grand prize opening opening / closing door 16b, a second big prize opening SW17a for detecting a game ball won in the second big prize opening 17, and a second grand prize opening A second large prize opening solenoid (SOL) 17c for opening / closing the opening / closing door 17b, a general winning opening SW18a provided in the general winning opening 18 and the like are connected.

Also, on the game control board 211, a first special symbol display device 20 that performs variation and display of the first special symbol, a second special symbol display device 21 that performs variation and display of the second special symbol, and a variation and display of auxiliary symbols. An auxiliary symbol display device 22 is connected.
The first special symbol display device 20 and the second special symbol display device 21 display whether or not the special symbol is won in the big hit or the small hit by variably displaying the special symbol and stopping the variable display after a predetermined time has elapsed. To do. Further, the auxiliary symbol display device 22 displays the auxiliary symbol in a variable manner when the game ball passes through the gate SW 15a in the gate 15, and stops the variable symbol after a predetermined time has passed, so that the auxiliary symbol is won. Display whether or not.

Furthermore, the game control board 211 has a first special symbol hold indicator 23 for displaying the number of reserved rights (holding balls) for starting the variable display of the first special symbol, and a right for starting the variable display of the second special symbol. A second special symbol hold indicator 24 for displaying the number of reserves, the number of reserves of the right to start the change display of the auxiliary symbols obtained by passing when the game ball passes through the gate SW 15a in the gate 15 while the auxiliary symbols are changing Is connected to an auxiliary symbol hold indicator 25 or the like.
Note that the game control board 211 of the present embodiment preferentially digests the reserved ball of the second special symbol when the reserved ball of the first special symbol and the reserved ball of the second special symbol are both held. It is configured as follows.

Furthermore, the game control board 211 is connected to an effect control board 221, a payout control board 251, a board external information terminal board 260, and the like.
The effect control board 221 includes a CPU 222, a ROM 223, a RAM 224, an RTC (real time clock) 225, and the like, and controls the entire game effect.
Connected to the effect control board 221 are an image control board 231 that controls images and sounds, a lamp control board 241 that controls various lamps and effects, and an effect button switch 314a.

  The image control board 231 includes a CPU 232, a ROM 233, and a RAM 234, and performs image and sound control based on instructions from the effect control board 221. For this reason, the image display board 7 and the audio output device (speaker) 312 are connected to the image control board 231.

The lamp control board 241 includes a CPU 242, a ROM 243, a RAM 244, and the like, and controls the lighting device and the like based on an instruction from the effect control board 221. For this reason, the lamp control board 241 has an effect lighting device 313 (313a, 313b), various effect game lamps 316 provided on the game board 2 and not shown in FIG. A device 320 (320L, 320R) or the like is connected.
The lamp control board 241 also controls the movable accessory device and the like based on instructions from the effect control board 221. For this reason, although not shown in FIG. 1 and FIG. 2, when the effect movable accessory device 331 is provided on the game board 2, the effect movable accessory device 331 is also connected to the lamp control board 241.

The payout control board 251 includes a CPU 252, a ROM 253, a RAM 254, and the like, and controls the payout motor 255, the payout ball detection SW256, the ball presence detection SW257, and the full tank detection SW258 of the game ball payout device.
Further, a frame external information terminal board 270 is connected to the payout control board 251.
The board external information terminal board 260 is a terminal board for outputting various information of the game board to the outside. The frame external information terminal board 270 is a terminal board for outputting various information of the frame to the outside.

Hereinafter, characteristic embodiments of the present invention will be described.
FIG. 4 is a diagram illustrating an example of the reset mechanism in the present embodiment.
The image control board 231 shown in the block diagram of FIG. 3 is actually connected to the image display device (liquid crystal module) 7 via the liquid crystal relay board 400.
The liquid crystal relay substrate 400 is a substrate for relaying image data between the image control substrate 231 and the image display device 7.
In the gaming machine of this embodiment, the liquid crystal relay substrate 400 stores a CPU 401 as a reset control target, a WD-IC (watchdog IC) 402 (details will be described later) as a reset means, which is a feature of the present invention, and a control program. ROM 403, and a RAM 404 for expanding control programs and data.

5 to 7 are diagrams for explaining a reset mechanism in a conventional gaming machine. Prior to explaining the features of the present embodiment, the problems of the reset mechanism in the conventional gaming machine will be described with reference to these drawings. Outline.
5 and 6 are conceptual diagrams for explaining a reset mechanism in a conventional gaming machine, and FIG. 7 is a conceptual diagram for explaining a problem that the conventional reset mechanism has.

5 to 7, an example in which the image control board 231 performs reset control of the liquid crystal relay board 400 will be described as an example of a conventional reset mechanism.
As shown in FIG. 5, in a conventional gaming machine, a CPU 401 (hereinafter referred to as a controlled CPU) included in a liquid crystal relay substrate 400 on which reset control is performed is an image control board on the reset control side. A clock signal (pulse) as a status signal is always supplied to a CPU 232 (hereinafter referred to as a control-side CPU) included in the H.231.
While the clock signal is input from the controlled CPU 401, the controlling CPU 232 determines that the controlled CPU 401 is operating normally, and controls the reset terminal of the controlled CPU 401 to be at a HIGH level. The signal is continuously input (HIGH fixed output).

Thereafter, when a failure (such as a runaway due to heat) occurs in the controlled CPU 401 and the input of the status signal from the controlled CPU 401 to the controlling CPU 232 is interrupted (pulse stop), the controlling CPU 232 In order to reset the CPU 401 and recover from the malfunction, the control signal is changed to a LOW level as a reset level (LOW output).
The controlled CPU 401 to which the LOW level control signal is input resets and a normal pulse state signal is input to the control CPU 232 again as shown in FIG.
In response to this, the control-side CPU 232 starts to input a control signal whose HIGH level is fixed to the reset terminal of the controlled-side CPU 401 again.

With such a configuration, it is possible to immediately recover the CPU in which a problem has occurred and operate it normally, thereby minimizing the trouble with respect to the progress of the game.
However, as described above, the control signal is a signal composed of a HIGH level signal and a LOW level signal. Therefore, there is a problem that the waveform is easily affected by noise and the waveform is easily changed.
That is, as shown in FIG. 7, when noise is applied to the control signal at the HIGH level, the waveform is disturbed, for example, the signal level unintentionally falls to the LOW level, thereby causing the controlled CPU 401 to reset unintentionally. There is a problem that will be.

If a CPU that is actually operating normally is suddenly reset, naturally, the gaming machine cannot operate normally, resulting in a major obstacle to the progress of the game.
Conventionally, measures such as installing a noise filter near the reset terminal of the controlled CPU 401 have been taken. However, since gaming machines such as pachinko gaming machines are noisy, it has been difficult to completely prevent malfunctions.
The reset mechanism according to the present embodiment is intended to solve such problems.

[First Embodiment]
8, FIG. 9 and FIG. 10 are conceptual diagrams illustrating the reset mechanism according to the present embodiment.
FIG. 11 is a diagram for explaining the effect of the reset mechanism according to the present embodiment.
Similarly to the above, FIGS. 8 to 11 illustrate an example in which the image control board 231 performs reset control of the liquid crystal relay board 400 as an example of the reset mechanism according to the present embodiment.
As shown in FIG. 8, the CPU 401 (controlled CPU) included in the controlled liquid crystal relay substrate 400 sends a clock signal as a status signal to the CPU 232 (controlled CPU) included in the controlling image control substrate 231. (Pulse) is supplied. This is the same as the conventional configuration.

A difference from the prior art is that the control signal supplied from the CPU 232 (second microcomputer) of the image control board 231 on the control side to the liquid crystal relay board 400 on the controlled side is a pulse waveform signal. Is provided with a WD-IC 402 as reset means for resetting the controlled CPU 401.
The WD-IC 402 is configured to receive a control signal from the control-side CPU 232 (first microcomputer) of the image control board 231.

That is, the WD-IC 402 is a watchdog timer that forcibly resets the CPU (microcomputer) unless a clear pulse for periodically resetting the built-in timer is input.
The pulse included in the control signal sent out by the control CPU 232 is a clear pulse CP for resetting the built-in timer of the WD-IC 402.
Actually, the clear pulse CP is a signal that returns (relays) the state signal transmitted from the controlled CPU 401 to the controlled CPU 401 as it is, but is a signal used for reset control of the timer of the WD-IC 402. In the description, control signals and aliases will be described. In addition to these status signals and control signals, a status confirmation command and a response command are exchanged between the control CPU 232 and the controlled CPU 401. Is detailed below.

As shown in FIG. 8, the control-side CPU 232 supplies a control signal (clear pulse) having a pulse waveform to the WD-IC 402 during a period in which the state signal is received from the controlled-side CPU 401.
On the other hand, as shown in FIG. 9, when the supply of the status signal pulse is stopped, the control CPU 232 stops the supply of the control signal (clear pulse) to the WD-IC 402 (or LOW not including HIGH). A fixed control signal is supplied to the WD-IC 402).

On the other hand, the WD-IC 402 resets the built-in timer of the WD-IC 402 when a state where a control signal (clear pulse) is not input continues for a certain period as shown in FIG. Otherwise, a reset signal is input to the reset terminal of the controlled CPU 401 to reset the controlled CPU 401.
More specifically, the WD-IC 402 is configured to reset the timer each time one clear pulse CP having a period of time T (for example, 2 ms) is input.
The WD-IC 402 measures the period until the clear pulse after the timer reset is input by the built-in timer. If the clear pulse CP is not input within a predetermined period, the reset signal is sent to the reset terminal of the controlled CPU 401. To enter.
This predetermined period is a reset period of the WD-IC 402 (not a period for resetting the timer but a period for outputting a reset signal).

That is, the reset period is a period from when the timer reset is applied to the built-in timer of the WD-IC, until the WD-IC outputs a reset signal and resets the CPU when the clear pulse is not input for a certain period.
For example, the reset cycle of the WD-IC 402 is equivalent to one cycle T of the clear pulse, and when the clear pulse is not input for one cycle from the timer reset, a reset signal is input to the CPU.
As will be described below, the reset period of the WD-IC 402 is not limited to one clear pulse period, but is equal to the number of clear pulse periods (for example, three periods), or any other time instead of the clear pulse period unit. May be.

Also, as shown in FIGS. 8 and 9, the CPU 232 of the control-side image control board 231 periodically sends a status check command to the controlled-side CPU 401, separately from the control signal (clear pulse). Yes.
In response to this, the controlled CPU 401 transmits a response command to the controlling CPU 232.

As shown in FIG. 8, while the control side CPU 232 receives the response command, it supplies a clear pulse to the WD-IC to reset the timer. However, as shown in FIG. Even if a response command is not received, the supply of the control signal (clear pulse) is stopped and the WD-IC 402 is caused to reset the CPU 401.
The reason for performing such control is as follows. That is, even if the main processing system of the controlled CPU 401 operates normally and sends a status signal, only a part of functions, for example, communication registers used to exchange processing commands with other boards, stop functioning. In some cases, normal communication cannot be performed.

Therefore, whether the communication function is normal or abnormal is determined by whether or not a response command is returned to the status confirmation command from the control side CPU. If it is determined that there is an abnormality, supply of the clear pulse is stopped. Thus, the CPU 401 is reset by the WD-IC 402.
As a result, even with a CPU that appears to be operating normally on the surface by sending a status signal, it is possible to perform an appropriate reset by providing a system for determining the presence or absence of a separate system. Is possible.

The specific processing is as follows. The control side CPU 232 sends a state confirmation command to the controlled side CPU 401, and if there is a response command in response thereto, a state confirmation flag indicating that the controlled side CPU 401 is normal = 01 is set, and if a response command is not returned within a certain period, a state confirmation flag = 02 indicating that there is an abnormality in the controlled CPU 401 is set.
The control-side CPU 232 determines whether or not to supply a clear pulse by looking at the state of the state confirmation flag.
In view of the use of such a status confirmation command, it is desirable to set the cycle in which the control CPU 232 transmits the status confirmation command to be shorter than the reset cycle by the WD-IC 402.

If the transmission cycle of the status confirmation command is longer than the reset cycle by the WD-IC 402, once the malfunction occurs in the controlled CPU 401 and the status confirmation flag becomes 02, the status confirmation flag is 02 even after the controlled CPU 401 is reset. Then, after sending the status confirmation command, the controlled CPU 401 will continue to be reset until the response command is received from the controlled CPU 401 after the restart and the status confirmation flag is set to 01. .
On the other hand, if the transmission cycle of the status check command is shorter than the reset cycle by the WD-IC 402, the status check flag is sent by sending a status check command even if the status check flag after the restart of the controlled CPU is 02. Since the clear pulse can be transmitted in the next clear pulse cycle before reaching the reset cycle, unnecessary reset (reactivation) is not performed on the controlled CPU 401.
If the reset period is one clear pulse period, the status check command transmission period is shorter than that, and if the reset period is multiple clear pulse periods or any other period, it is longer than these periods. A status check command is sent in a short cycle.

By the way, in the gaming machine of this embodiment, the control signal transmitted from the control CPU to the WD-IC 402 is in a pulse format (reset pulse). Thereby, the following effects can be obtained.
That is, as shown in FIG. 11A, even if the WD-IC 402 has a noise on a control signal including a periodic clear pulse CP supplied from the control side CPU 232 and the waveform is temporarily disturbed, If the pulse waveform is recovered and pulses are continuously transmitted, only a few pulses having a period T ′ different from the period T are added to the clear pulse.
Therefore, the WD-IC 402 ignores this waveform disturbance and resets the timer in the same manner as when a normal pulse is input.
As a result, since no reset signal is input to the reset terminal of the controlled CPU 401, the controlled CPU 401 is not reset unnecessarily (regardless of whether a problem has occurred).

Only when the pulse is not input for a predetermined period (reset cycle), the WD-IC 402 inputs a reset signal to the reset terminal of the controlled CPU 402 without resetting the timer.
By adopting such a configuration, it is possible to prevent a trouble in the game from occurring without causing an unnecessary reset in the controlled CPU 401 even if a malfunction occurs in the control signal (clear pulse) due to noise. is there.

Further, as shown in FIG. 11B, even if the noise is applied and the waveform is temporarily disturbed when the control signal is at the reset level (fixed LOW), the WD-IC 402 ignores this and controls the controlled signal. Control is performed so as not to input a reset signal to the reset terminal of the side CPU 401.
By doing so, for example, the reset signal is not input again to the controlled CPU 401 during the reset operation, so that unnecessary reset can be prevented from occurring in the controlled CPU.

Hereinafter, processing by the control-side and controlled-side CPU for realizing the characteristic operation of the gaming machine of this embodiment shown in FIGS. 8 to 10 will be described.
Note that the processing shown in FIGS. 12 to 14 is processing that is sequentially executed in a predetermined cycle as interrupt processing for the main processing by the control-side CPU 232, but description of other processing included in the main processing is omitted here. .
FIG. 12 is a flowchart for explaining a state confirmation command transmission process executed by the CPU of the image control board.
In step S1001, the CPU 232 of the image control board that is the control side CPU (hereinafter referred to as the control side CPU 232) checks the state at a predetermined cycle with respect to the CPU 401 of the liquid crystal relay board that is the control side CPU (hereinafter referred to as the control side CPU 401). Send a command.

FIG. 13 is a flowchart for explaining state confirmation control processing executed by the CPU of the image control board.
In step 1101, the control side CPU 232 determines whether or not a response command has been received from the controlled side CPU 401.
If it is determined that a response command has been received (Yes in step S1101), the control-side CPU 232 sets a state confirmation flag = 01 indicating a normal response in the RAM 234 in step S1102, and ends the current state confirmation control process.
If it is determined in step S1101 that the response command has not been received, the control CPU 232 considers a command transmission delay due to some external or internal factor in step S1103, and a predetermined period has elapsed since the determination in step S1101. Determine whether or not.
If it is determined that the predetermined period has elapsed (Yes in step S1103), the control-side CPU 232 sets a state confirmation flag = 02 indicating an abnormal response (no response) in the RAM 234 and ends the current state confirmation control process. .

FIG. 14 is a flowchart illustrating control signal transmission processing executed by the CPU of the image control board.
In step S1201, the CPU 232 of the image control board that is the control side CPU determines whether or not a status signal is received from the CPU 401 of the liquid crystal relay board that is the controlled CPU.
If it is determined that the status signal has been received (there is a pulse) (Yes in step S1201), the control side CPU 232 further determines in step S1202 whether the status confirmation flag is 01 indicating a normal response.
If the status confirmation flag is 01 (Yes in step S1202), the CPU 232 sends a control signal including a clear pulse to the WD-IC 402 in step S1203.

If the state confirmation flag is not 01 (No in step S1202), the control-side CPU 232 determines in step S1204 that the state confirmation flag is 02 and stops sending the control signal including the clear pulse to the WD-IC 402. (Send a LOW fixed signal without a pulse) and finish the control signal transmission process.
If it is determined in step S1201 that the status signal has not been received (no pulse), the control CPU 232 ends the control signal transmission process.

FIG. 15 is a flowchart for explaining reset control processing executed by the WD-IC provided in the liquid crystal relay substrate.
In step S1301, the WD-IC 402 serving as a reset unit determines whether a control signal (clear pulse) is received from the control-side CPU 232 of the image control board 231.
If it is determined that the clear pulse has been received (there is a pulse) (Yes in step S1301), the WD-IC 402 resets the built-in timer in step S1302. Of course, in this case, no reset signal is input to the controlled CPU 401.

If it is determined in step S1011 that no pulse is received (no pulse) (No in step S1301), the WD-IC 402 resets the controlled CPU 401 in step S1303 (as described above, It is determined whether or not one period or a plurality of periods have been reached.
If the reset period has been reached (Yes in step S1303), in step S1304, a reset signal is input to the controlled CPU 401 to reset it.
If the reset period has not been reached (No in step S1303), the reset control process is terminated without doing anything.

By performing the control as described above, according to the present invention, even if a failure occurs in the control signal (clear pulse) due to noise, no unnecessary reset occurs in the controlled CPU 401 and no trouble occurs in the game. It is possible to do so.
In addition, it is possible to appropriately reset a CPU that appears to be operating normally on the surface by sending a status signal by providing a system for determining whether there is a different system. .

Note that various devices and switches are all connected via relay boards to the various control boards included in the gaming machine. The example of the liquid crystal relay substrate described above is only a part thereof, and the reset control of this embodiment can be applied to these other relay substrates.
In addition to the relay board and the control board, there are other main / sub relationships such as, for example, between the effect control board 221 and the image control board 231 and between the effect control board 221 and the lamp control board 241. Even between the control boards, the reset control of the present embodiment can be applied by providing the controlled board with the WD-IC.

[Second Embodiment]
In the first embodiment described above, the WD-IC 402 resets the built-in timer every clear pulse in one cycle to avoid unnecessary reset of the controlled CPU 401.
That is, it means that the reset period of the WD-IC 402 is a period of one pulse period T.
Accordingly, when the signal is fixed to LOW only during the period of the pulse of one cycle T (the control signal is not input), the reset signal is input to the controlled CPU assuming that the clear pulse is not input.
However, there may be a delay in the transmission of the status signal by the controlled CPU 401 and the transmission of the control signal by the control CPU 232 for some reason even if no state abnormality has occurred in the controlled CPU 401.
In that case, if the delay is a period of one pulse period, the timer of the WD-IC 402 is not reset, and the controlled CPU 401 is forcibly reset even though there is no problem in itself. It will be.
It goes without saying that frequent occurrence of such a situation has a serious impact on the progress of the game.

Therefore, in the second embodiment, the following measures are taken.
That is, unlike the first embodiment in which the reset period of the WD-IC 402 is one clear pulse period, a plurality of pulse periods, for example, three clear pulse periods are used.
This means that the timer reset is performed every cycle of the clear pulse, but the CPU is not reset immediately because the 1-cycle clear pulse is not input. This means that if the period is not received, the WD-IC 402 inputs a reset signal to the controlled CPU 401 to reset it.
By doing so, even if the clear pulse is somewhat delayed, the timer of the WD-IC 402 is normally reset and the controlled CPU 401 is not reset unnecessarily.
The control flow is the same as that of the first embodiment (FIGS. 12 to 15), and only the reset period determined in step S1303 of FIG. 15 is different.

Further, as shown in FIG. 11A, even if noise is added to the control signal (clear pulse), only the number of pulses in the reset period is increased from the WD-IC 402, and the WD-IC normally The timer is reset. Therefore, the WD-IC 402 does not unnecessarily reset the controlled CPU 401.
However, if the reset period of the WD-IC 402 is set too long, the status signal is interrupted due to a problem in the controlled CPU 401, and the control CPU 232 stops the control signal pulse in response to the interruption. Even in such a case, it is necessary to pay attention because the reset of the controlled CPU 401 is delayed.

[Other Embodiments]
In the above-described embodiment, a state confirmation command is transmitted from the control CPU 232 to the controlled CPU 401, and the state of the controlled CPU 401 is confirmed by a response command thereto.
On the other hand, without using a separate command as the status confirmation command, other commands used for effect control, such as a command for drawing instruction transmitted from the image control board 231 to the liquid crystal relay board 400, or the effect control board 221 to the image control board 231 Alternatively, the state of the controlled CPU may be checked using a control command transmitted to the lamp control board 241.
In that case, unlike the control shown in the flowchart of FIG. 13, the control CPU sets the status confirmation flag 01 when a response command is returned from the controlled CPU within a predetermined time after transmitting the control command. If the response command does not return within a predetermined time, processing such as setting the status confirmation flag 02 is performed.
With this configuration, the features of the present invention can be applied to existing well-known gaming machines.

Note that a liquid crystal display device, a rear projector, and other arbitrary display devices can be employed as the image display device used in the gaming machine of the present invention.
The gaming machine of the present invention can be applied not only to pachinko machines, but also to slot machines, other gaming machines having a display device, and game machines in general.

1 Pachinko machine, 2 Game board, 7 Image display device (LCD module), 13 Start port, 14 Start port, 15 Gate, 16 Grand prize port, 17 Grand prize port, 18 General prize port, 19 Out port, 20 Special design Display device, 21 Special symbol display device, 22 Auxiliary symbol display device, 23 Special symbol hold indicator, 24 Special symbol hold indicator, 25 Auxiliary symbol hold indicator, 31 Production symbol, 211 Game control board, 221 Production control board, 231 Image control board, 312 Audio output device, 314 Production button, 400 Liquid crystal relay board, 232, 401 CPU, 402 WD-IC

Claims (1)

A first microcomputer to be reset;
Resetting means for resetting the first microcomputer;
A second microcomputer for performing reset control of the first microcomputer,
The first microcomputer supplies the second microcomputer with a first signal and a second signal that are independent of each other and indicate different states of the first microcomputer;
The second microcomputer is
Supply means for supplying intermittent pulse signals to the reset means;
First receiving means for receiving the first signal;
Second receiving means for receiving the second signal;
When the first signal is received from the first microcomputer and the second signal is received, it is determined not to reset the first microcomputer, and the first microcomputer receives the first signal from the first microcomputer. Determination means for determining that the first microcomputer is reset when at least one of the second signal and the second signal is not received ,
If it is determined that resets the first microcomputer by the determining means, and stops the supply of the pulse signal by said supply means,
When it is determined not to reset the first microcomputer by the determination means after stopping the supply of the pulse signal by the supply means, the supply of the pulse signal by the supply means is resumed,
The gaming machine according to claim 1 , wherein the reset means resets the first microcomputer in accordance with the presence or absence of the pulse signal supplied from the second microcomputer within a predetermined period .

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