JP5954227B2 - Transmission equipment - Google Patents

Description

  The present invention relates to a transmission apparatus that transmits data, and more particularly to an SDH (Synchronous Digital Hierarchy) transmission apparatus.

  In the SDH transmission apparatus, each interface (600M, 150M, 6M, 1.5M, etc.) has a memory for transferring from the transmission path clock to the apparatus clock, and between the transmission path clock and the apparatus clock by this memory. The frequency fluctuation is allowed. However, when the frequency fluctuation between the transmission line clock and the device clock exceeds an allowable range, a phenomenon called “slip” that causes data destruction occurs.

JP-A-8-221331

  Conventionally, there is no means for grasping the relationship between the write phase to the memory and the read phase, and analysis or investigation has been performed after a field failure (slip or alarm caused by slip) has occurred. At the analysis stage, it was not possible to identify the suspected part even if it was estimated from the field event that it was due to the relative phase fluctuation (frequency fluctuation, etc.) between the transmission path clock and the device clock. For this reason, in order to identify the suspected part, a long-term investigation may be carried out in the field, and an enormous amount of time and labor have been spent on solving the problem.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a transmission apparatus that can easily analyze and investigate a field failure.

In one aspect, the transmission device, the data from the heat transmission path, and clock transfer memory for changing put on equipment clock from a transmission path clock, and writing phase of data into the clock crossover memory, from the clock crossover memory a phase difference detecting unit for periodically detecting a phase difference between the data read phase, when said phase difference detected by the phase difference detection unit is different from the phase difference detected last time, this time the detected phase difference it may comprise a storage portion for storing.
In another aspect, the transmission device receives data from the transmission line, and the data write phase and the data read phase to the clock transfer memory for transferring the data from the transmission line to the device clock from the transmission line clock. If there is one interface that accumulates the detected phase difference and one interface where the phase difference has changed over time, it is determined that the phase of the transmission path clock has changed over time. And a determination unit that determines that the phase of the device clock is temporally changing when there are a plurality of interfaces in which the phase difference changes with time, and the plurality of interfaces receive data from different transmission paths. May be received.

  It should be noted that any combination of the above-described constituent elements and a representation of the present invention converted between an apparatus, a method, a system, a program, a recording medium storing the program, and the like are also effective as an aspect of the present invention.

  According to the present invention, it is possible to provide a transmission apparatus that can easily analyze and investigate a field failure.

It is a figure for demonstrating the structure of the SDH transmission apparatus which concerns on this embodiment. FIGS. 2A and 2B are diagrams for explaining the occurrence of slip in clock transfer. 3A and 3B are diagrams for explaining the operation of the SDH transmission apparatus according to the present embodiment. It is a figure for demonstrating the automatic monitoring of the network state by an SDH transmission apparatus. It is a figure for demonstrating the automatic monitoring of the network state by an SDH transmission apparatus.

  Hereinafter, an SDH transmission apparatus according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram for explaining the configuration of the SDH transmission apparatus 100 according to the present embodiment. Here, of the functional blocks of the SDH transmission apparatus 100, only functional blocks related to clock transfer in the interface board that receives data from the transmission path are shown.

  Each block shown in the block diagram of the present specification can be realized in terms of hardware by an element such as a CPU of a computer or a mechanical device, and in terms of software, it can be realized by a computer program or the like. The functional block realized by those cooperation is drawn. Therefore, those skilled in the art will understand that these functional blocks can be realized in various forms by a combination of hardware and software.

  As shown in FIG. 1, the SDH transmission apparatus 100 supplies device clocks to the first transmission path interface boards 10_1 to 10_n that receive data from the transmission paths 102_1 to 102_n and the first transmission path interface boards 10_1 to 10_n. And a monitoring control board 14 for monitoring and controlling the first transmission path interface boards 10_1 to 10_n via the monitoring control bus. An external monitoring terminal 200 is connected to the monitoring control panel 14. A maintenance person of the SDH transmission apparatus 100 can monitor and control the SDH transmission apparatus 100 using the monitoring terminal 200.

  The configuration of the first transmission path interface boards 10_1 to 10_n is the same. Hereinafter, the first transmission path interface boards 10_1 to 10_n are collectively referred to as “transmission path interface board 10” as appropriate.

  As shown in FIG. 1, the transmission path interface board 10 includes a clock transfer memory 20, a clock extraction unit 22, a write frame pulse generation unit 24, a read frame pulse generation unit 28, a phase difference detection unit 30, A phase difference comparison unit 32, a storage unit 34, and a monitoring control panel interface 36 are provided.

  The clock extraction unit 22 extracts a clock (referred to as “transmission path clock”) from the data input from the transmission path 102 to the transmission path interface board 10. This transmission path clock is input to the clock transfer memory 20 as a write clock (Write CLK).

  The write frame pulse generator 24 generates a write frame pulse (Write FP) from the transmission path clock. This write frame pulse is a pulse signal that designates a phase (timing) for writing data from the transmission path 102 to the clock transfer memory 20. This write frame pulse is input to the clock transfer memory 20.

  The read frame pulse generator 28 generates a read frame pulse (Read FP) from the device clock output from the device clock supply source 12. This read frame pulse is a pulse signal that specifies the phase (timing) for reading data from the clock transfer memory 20. The read frame pulse is input to the clock transfer memory 20.

  The clock transfer memory 20 is a memory for transferring data from the transmission path 102 to the apparatus clock from the transmission path clock. Data from the transmission path 102 (write data (Write Data)), a write clock, and a write frame pulse are input to the write side of the clock transfer memory 20. Write data is written into the clock transfer memory 20 using the write clock and the write frame pulse. Further, a device clock (also referred to as a read clock (Read CLk)) and a read frame pulse from the device clock supply source 12 are input to the read side of the clock transfer memory 20. Data in the clock transfer memory 20 is read using the read clock and the read frame pulse. This read data (Read Data) is sent to the line setting processing board.

  The phase difference detection unit 30 periodically detects the phase difference between the data write phase to the clock transfer memory 20 and the data read phase from the clock transfer memory 20. More specifically, the write frame pulse from the write frame pulse generation unit 24 and the read frame pulse from the read frame pulse generation unit 28 are input to the phase difference detection unit 30, and the write frame pulse and the read frame pulse are input. Is measured using a sampling clock.

  The phase difference comparison unit 32 compares the current phase difference detected by the phase difference detection unit 30 with the previous phase difference, and stores the current phase difference information when the current phase difference and the previous phase difference are different. 34.

  The accumulation unit 34 accumulates the phase difference information input from the phase difference comparison unit 32. The accumulating unit 34 accumulates the date and time when the phase difference is detected together with the phase difference information.

  The monitoring control board interface 36 is an interface for communicating with the monitoring control board 14. The supervisory control board interface 36 is connected to the supervisory control board 14 via a supervisory control bus. A maintenance person of the SDH transmission apparatus 100 can access the phase difference information stored in the storage unit 34 via the monitoring control panel 14 and the monitoring control panel interface 36 by operating the monitoring terminal 200.

  FIGS. 2A and 2B are diagrams for explaining the occurrence of slip in clock transfer.

  FIG. 2A shows the relationship between the write phase and the read phase in the normal state. In clock transfer, first, data input from the transmission path 102 is written into the clock transfer memory 20 at an arbitrary phase (write phase). As shown in FIG. 2A, a write frame pulse is given from the write frame pulse generation unit 24 to the clock transfer memory 20 at an interval of 125 μs, which is the period of the SDH frame, and data is written starting from this write frame pulse. It is.

  Next, the data accumulated in the clock transfer memory 20 is read at the read phase. This read phase is a phase shifted by 180 ° from the write phase in order to avoid proximity to the write phase. That is, as shown in FIG. 2A, the read frame pulse from the read frame pulse generator 28 is delayed by 125 μs / 2 = 62.5 μs from the write frame pulse. Data is read from the clock transfer memory 20 starting from the read frame pulse.

  Ideally, it is desirable to always maintain a 180 ° phase relationship between the write phase and the read phase, but this phase relationship gradually collapses due to external factors (eg, frequency fluctuations in the network, etc.). There is a possibility that reading phases are close to each other.

  FIG. 2B shows a state where the writing phase and the reading phase are close (for example, coincident). As shown in FIG. 2B, when the writing phase and the reading phase are close to each other, a slip occurs and an error occurs in the data.

  3A and 3B are diagrams for explaining the operation of the SDH transmission apparatus according to the present embodiment. Phase relationship when writing and reading certain data (current data) (FIG. 3B) and phase relationship when writing and reading data immediately before (current data) this time ( FIG. 3 (a)) is shown. In the present embodiment, the phase difference detection unit 30 detects the phase difference between the writing phase and the reading phase. The phase difference detection unit 30 counts the number of sampling clocks from the writing frame pulse to the reading frame pulse using a sampling clock (for example, 26 MHz) generated by dividing the device clock, and calculates the number of the writing phase and the reading phase. Detect as phase difference.

  The phase difference comparison unit 32 compares the current sampling clock number detected by the phase difference detection unit 30 with the previous sampling clock number. The period of comparison may be 8 kHz, for example. Then, the phase difference comparison unit 32 outputs the current sampling clock number to the accumulation unit 34 when the current sampling clock number is different from the previous sampling clock number.

  Here, as shown in FIGS. 3A and 3B, it is assumed that the number of sampling clocks related to the previous data is 1620 and the number of sampling clocks related to the current data is 1617. As described above, when there is a change in the number of sampling clocks related to the previous data (previous phase difference) and the number of sampling clocks related to the current data (current phase difference), the phase difference comparison unit 32 stores the number of sampling clocks related to the current data in the storage unit 34. Output and accumulate. On the other hand, when there is no change in the number of sampling clocks related to the previous data (previous phase difference) and the number of sampling clocks related to the current data (current phase difference), the phase difference comparison unit 32 discards the current data and stores it in the storage unit 34. do not do.

  The fluctuation of the phase difference between the write phase and the read phase occurs over a very long period of time, for example, 1 year to 10 years. For this reason, it is assumed that the sampling clock number (phase difference) is accumulated for all data. , It becomes a huge amount of data. Since the amount of data can be greatly reduced by accumulating the number of sampling clocks only when there is a change in the number of sampling clocks between the previous data and the current data as in the present embodiment, it is necessary for the accumulating unit 34. Therefore, the storage capacity can be reduced and the cost can be reduced.

  A maintenance person of the SDH transmission apparatus 100 accesses the storage unit 34 using the monitoring terminal 200, so that the phase difference between the write phase and the read phase for each transmission path interface board 10 of the transmission path interface board 10, that is, sampling. The time change of the clock number can be monitored or investigated.

  For example, when a field failure such as slip occurs, the maintenance person of the SDH transmission apparatus 100 investigates the time variation of the number of sampling clocks for each transmission path interface board 10. Since the change in the number of sampling clocks is due to the relative phase fluctuation between the transmission line clock and the equipment clock, the following method is used to determine which fluctuation of the transmission line clock or the equipment clock is the cause of the field failure. Use.

  The SDH transmission apparatus 100 normally includes a plurality of transmission path interface boards 10, and the plurality of transmission path interface boards 10 are supplied with a device clock from a common device clock supply source 12. Therefore, when the time change of the sampling clock number is caused by the fluctuation of the device clock, the time change of the sampling clock number should occur in the plurality of transmission path interface boards 10. The maintenance person of the SDH transmission device 100 has a time change of the device clock when there are a plurality of transmission path interface boards 10 in which the time change of the number of sampling clocks is present, and the field failure is caused by the SDH transmission device side. It can be judged that it is a thing. On the other hand, when there is only one transmission path interface board 10 in which the number of sampling clocks has changed over time, the maintenance person has caused a time change in the transmission path clock, and the field failure is caused by the network side. It can be judged.

  As described above, the SDH transmission apparatus 100 according to the present embodiment is configured to accumulate phase difference information (the number of sampling clocks) between the write phase and the read phase. As a result, the maintenance person of the SDH transmission apparatus 100 can perform accurate analysis by accessing the storage unit 34 from the monitoring terminal 200 and collecting data when a field failure occurs, and identify the simulated part at an early stage. Can do. As described above, the variation in the phase difference between the write phase and the read phase occurs over a very long period of time, for example, 1 year to 10 years. Therefore, after the field failure occurs, the failure is reproduced and simulated. It is not easy to specify the location, and it takes a very long time. According to the present embodiment, when a field failure occurs, the past phase difference (the number of sampling clocks) already remains, so that the simulated part can be specified in a short time.

  Further, according to the SDH transmission apparatus 100, the state of the entire constructed network (whether there is a defect in the synchronization network, etc.) can be grasped by monitoring the temporal change of the phase difference between the write phase and the read phase. It becomes possible to deal with obstacles in advance.

  In the above, the maintenance person monitors the time change of the phase difference between the writing phase and the reading phase, and the maintenance person monitors the network state, but the SDH transmission apparatus 100 automatically monitors the network state, If there is an abnormality, the maintenance person may be notified.

  4 and 5 are diagrams for explaining automatic monitoring of the network state by the SDH transmission apparatus. 4 and 5, the vertical axis represents the number of sampling clocks, and the horizontal axis represents the date. 4 and FIG. 5, the broken line represents the time transition of the ideal sampling clock number (that is, the sampling clock number is constant at 1620). A solid line shows an example of a temporal change in the actual number of sampling clocks.

  The time change of the number of sampling clocks may change quantitatively as shown in FIG. 4 or may change suddenly as shown in FIG. As shown in FIGS. 4 and 5, the monitoring control panel 14 is configured to notify the monitoring terminal 200 of the information when the number of sampling clocks is equal to or less than a predetermined threshold (200 in FIGS. 4 and 5). May be. The maintenance person of the SDH transmission apparatus 100 can know the possibility of the occurrence of a field failure by these notifications, and can take measures such as investigation and analysis in advance.

  Further, in the above, the maintenance person determines whether the cause of the time change of the phase difference is caused by the transmission line clock (network side) or the equipment clock (SDH transmission apparatus 100 side). However, the SDH transmission apparatus 100 may automatically make this determination. In other words, the monitoring control board 14 of the SDH transmission apparatus 100 determines that the phase of the transmission path clock is temporally changing when there is one transmission path interface board 10 in which the phase difference changes with time. On the other hand, the monitoring control board 14 determines that the phase of the device clock is temporally changing when there are a plurality of transmission path interface boards 10 in which the phase difference changes with time. Thereby, the maintainer of the SDH transmission apparatus 100 can easily investigate or analyze the field failure.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications are possible depending on the combination of each component and each processing process, and such modifications are within the scope of the present invention. is there.

  10 transmission path interface board, 12 device clock supply source, 14 monitoring control board, 20 clock transfer memory, 22 clock extracting section, 24 writing frame pulse generating section, 28 reading frame pulse generating section, 30 phase difference detecting section, 32nd place Phase difference comparison unit, 34 storage unit, 36 monitoring control panel interface, 100 SDH transmission device, 102 transmission path, 200 monitoring terminal.

Claims (4)

The data from the heat transmission path, and clock transfer memory for changing put on equipment clock from line clock,
A phase difference detector that periodically detects a phase difference between a data writing phase to the clock transfer memory and a data read phase from the clock transfer memory;
When the phase difference detected by the phase difference detection unit is different from the phase difference detected last time, an accumulation unit that accumulates the phase difference detected this time is provided.
Transmission equipment, characterized in that. The transmission apparatus according to claim 1, wherein the accumulation unit accumulates the date and time when the phase difference is detected together with the phase difference information. Position if the phase difference is equal to or less than a predetermined threshold value, the transmission device according to claim 1 or claim 2, characterized by further comprising a notification unit for notifying the information to the monitoring terminal of the SDH transmission device. Receiving data from the heat transmission path, detects a phase difference between the data write phase and data read phases of the data from the transmission path to the clock transfer memory for transfer to equipment clock from line clock, the detected phase difference a plurality of interfaces for storing,
If there is one interface where the phase change has occurred over time, it is determined that the phase of the transmission path clock has changed over time, and if there are multiple interfaces where the phase change has occurred over time, the device clock A determination unit that determines that the phase is temporally changing ,
The plurality of interfaces receive data from different transmission paths;
Den feeding device characterized in that.

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