JP5920032B2 - Light control device - Google Patents

Description

  The present invention relates to a light control device that performs light control of an illuminator.

  It is widely practiced to dim an illuminator that is lit with the power of a commercial AC power source, for example, with a dimming device installed on the wall of a house. As one of such light control devices, there is known a triac light control device capable of connecting the light control device, an AC power source, and an illuminator with only two wires. In the triac method, the timing at which the triac transitions from the off state to the on state is controlled in each of the peaks and troughs of the AC waveform by the gate trigger signal (rank phase control). By controlling the timing, the power supplied to the illuminator is controlled, and light control is performed.

  By the way, in an illuminator, an illuminator using an LED (light emitting diode) having higher efficiency and longer life than an incandescent bulb has been widespread. An example of such an illuminator is an LED bulb having a bulb shape.

  The triac described above has a characteristic that a holding current of a certain degree must be continuously supplied in order to maintain the on state after the triac is once turned on. Since an LED has a smaller current flowing than an incandescent lamp and has a diode characteristic, it cannot maintain a holding current necessary for maintaining an ON state. Therefore, the triac is liable to malfunction. In order to cope with such a problem specific to the triac method, a circuit for constantly flowing a holding current necessary for normal operation of the triac is incorporated in an illuminator using an LED, in addition to the current flowing through the LED. Since the current of this circuit does not contribute to illumination, useless current consumption increases.

  Patent Document 1 discloses a two-wire antiphase control device that can be used for both LED bulbs and incandescent bulbs. This device includes a main current switching unit connected in reverse to the main current circuit and a control unit for controlling the main current. The control unit determines the positive / negative gate charge charging unit that charges the charge by energizing the gate of the switching element of the main current switching unit, the gate-off control unit that discharges the gate charge of the switching element at a predetermined timing, and the discharge timing A dimming variable pulse output unit, a full-wave rectification voltage dividing unit that generates a trigger input signal of the dimming variable pulse output unit, and a DC power source generation unit that generates a driving power source for the dimming variable pulse output unit. In this two-wire type anti-phase control device, the phase control is performed by repeating the operation of turning the switching element from the on state to the off state every half cycle of the alternating current, that is, each of the peak and valley of the alternating current waveform. This two-wire anti-phase control device controls the on / off period of the alternating current waveform by charging and discharging the gate of the switching element. Therefore, even when an LED bulb is used as an illuminator (load), the holding current is maintained. There is no need to provide a circuit for this. Therefore, the energy saving effect that the LED originally has can be sufficiently exhibited. The two-wire anti-phase control device performs anti-phase control that switches the switching element of the main current circuit from the ON state to the OFF state in the middle of each of the peaks and valleys in the AC waveform. For this reason, the choke coil for noise reduction and a large-sized capacitor which are required in the triac method of the order phase control are unnecessary.

JP 2011-238353 A

  Since the above antiphase control device performs phase control by switching the energized switching element from the on state to the off state, a surge is generated when an inductive load is erroneously connected. For example, when an inductive load is mistakenly connected, an outlet is connected to a wiring for a downlight arranged on a ceiling or a wall in an electrical wiring work of a house, for example, an electric drill, It is assumed that a ventilation fan, a dryer, and a fan are connected.

  If a surge voltage (kickback voltage) exceeding the withstand voltage of the switching element is generated by connecting the inductive load, the switching element may be broken. In order to protect the switching element, it is conceivable to connect the surge voltage absorbing elements in parallel. In general, the surge voltage absorption element is mainly composed of a gas tube arrester that uses the discharge phenomenon, a silicon surge absorber that uses the breakover voltage of the semiconductor, and zinc oxide as the main component. A varistor element used is known.

  However, these elements are originally elements for absorbing a single surge voltage such as a lightning surge. On the other hand, when an inductive load is connected to the antiphase control device, generation of a surge voltage is repeated every half cycle of the AC waveform. For this reason, the surge voltage absorbing element itself is overheated by the energy of the surge voltage to be absorbed, leading to malfunction and damage, and the switching element cannot be protected. For example, when gas, tube, and arrester are simply connected in parallel, a high temperature is reached in several tens of seconds, and the discharge stops and becomes an open state. In addition, when silicon surge absorbers and varistors are used, they are easily damaged and become semiconductive.

  An object of the present invention is to solve the above-described problems and to provide a light control device in which a failure is suppressed when an inductive load is erroneously connected.

The light control device of the present invention that achieves the above object is as follows.
In a current loop that returns from the commercial AC power source to the commercial AC power source via the illuminator, they are connected in series in opposite directions, each having a first terminal, a second terminal, and a gate terminal. A current flow path from the terminal to the second terminal is formed, and the current flow path is interrupted by the discharge of the gate, and the current flow from the second terminal to the first terminal regardless of charging and discharging of the gate. A switching circuit having a pair of switching elements formed with a path;
A charge / discharge circuit that alternately repeats charging for each gate of the pair of switching elements and discharging at a timing according to the operation for the pair of switching elements, and
A surge voltage detection circuit that detects a surge voltage generated between both ends of the switching circuit and generates a charge prohibition signal that lasts for a predetermined period longer than the cycle of the AC power supplied from the commercial AC power supply in response to the generation of the surge voltage When,
A charge prohibition circuit for prohibiting charging of the gate by the charge / discharge circuit during a period in which the charge prohibition signal is sustained after receiving the input of the charge prohibition signal;
A surge voltage absorbing element that is connected in parallel to the switching circuit and absorbs a surge voltage generated between both ends of the switching circuit is provided.

  The light control device of the present invention is a so-called two-wire light control device in which the switching element is connected in a current loop that returns from the commercial AC power source to the commercial AC power source via the illuminator. In addition, since the light control device of the present invention is an anti-phase light control device that discharges the gate of the switching element at a timing according to the operation, the power consumption of the LED illuminator can be suppressed, and noise can be reduced. Occurrence is also suppressed. Further, in the light control device according to the present invention, when a surge voltage is generated due to an inductive load being erroneously connected, switching of the switching element is stopped by a charge prohibition signal that lasts for a predetermined period. That is, no surge voltage is generated during the predetermined period. For this reason, the occurrence frequency of the surge voltage absorbed by the surge voltage absorption element is reduced, and overheating of the surge voltage absorption element is avoided. Therefore, the surge voltage absorbing performance of the surge voltage absorbing element is maintained, and failure can be suppressed even when an inductive load is connected to the dimmer.

  Here, in the light control device according to the present invention, the charge prohibition circuit may include a pair of transistors that form discharge paths for discharging the gates of the pair of switching elements while the charge prohibition signal is maintained. preferable.

  By discharging the gate of each switching element by the pair of transistors, it is possible to reliably inhibit the charging of the gate with a simple configuration with a small number of components.

In the light control device of the present invention,
The surge voltage detection circuit is
A surge detecting element for detecting a surge voltage across the switching circuit;
It is preferable to have an integration circuit that generates the charge prohibition signal by holding the surge detection signal obtained by the surge detection element for the predetermined period.

  The integration circuit can reliably hold the surge detection signal for a predetermined period with a simple configuration with few parts.

  As described above, according to the present invention, it is possible to realize a light control device in which a failure is suppressed when an inductive load is erroneously connected.

It is a circuit diagram which shows one Embodiment of the light modulation apparatus of this invention. It is a graph which shows the electric potential waveform and electric current waveform of each part of the light modulation apparatus shown in FIG. FIG. 2 is a circuit diagram illustrating a state in which an unauthorized load M is connected to the light control device illustrated in FIG. 1 instead of an illuminator. It is a graph which shows the example of the voltage waveform of the light control apparatus both ends in the circuit shown in FIG. 3, and the voltage waveform of both ends of load.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing an embodiment of the light control device of the present invention.

  The dimming device D shown in FIG. 1 is a dimming device that performs phase control of the AC power of the commercial AC power supply AC supplied to the illuminator LT.

  The commercial AC power source AC is a power source that supplies AC power having an effective voltage of 100 V and 50 Hz, for example. The illuminator LT is an illuminator that illuminates an LED (LD) by emitting light. The illuminator LT is, for example, a downlight illuminator that is installed on the ceiling of a room and illuminates directly below. The illuminator LT includes an LED array composed of a plurality of LEDs (LD). The illuminator LT may incorporate a power supply circuit (not shown). Instead of the illuminator LT, an incandescent bulb or a halogen lamp can be connected to the light control device D of the present embodiment.

  The light control device D is attached to a wiring fixture mounting frame (not shown) standardized by JIS, for example, and is installed on a wall of a room provided with the illuminator LT. The light control device D is a two-wire light control device, and is connected to the illuminator LT and the commercial AC power supply AC outside the light control device D by two wires. The light control device D has two terminals 0 and 1, one terminal 0 is connected to the illuminator LT, and the other terminal 1 is connected to the commercial AC power source AC. That is, the light control device D, the commercial AC power supply AC, and the illuminator LT are connected in series. In FIG. 1, a circuit connecting the commercial AC power supply AC, the illuminator LT, and the light control device D in a circuit is referred to as a main current loop (main current circuit).

  The light control device D is an anti-phase control device that crosses (zero-crosses) the midpoint potential (0 V) of the AC sine wave waveform supplied from the commercial AC power supply AC and then sets the midpoint potential (0 V). Phase control is performed to turn on from the vicinity of the zero cross in the half cycle until crossing and limit conduction in the second half. And electric power is controlled by changing the start timing of conduction | electrical_connection restriction | limiting according to operation.

  The light control device D includes a switching circuit 1, a charge / discharge circuit 2, a surge voltage detection circuit 3, a charge inhibition circuit 4, and a surge voltage absorption element 5. The light control device D is also provided with a switch 6, a fuse 7, and a power thermistor 8. The switch 6 is for bypassing the dimming circuit inside the dimming device D according to the operation, and supplying the electric power of the commercial AC power supply AC to the illuminator LT without control. The fuse 7 and the power thermistor 8 are for protecting the circuit from an excessive current and abnormal heat generation in the dimmer.

  The switching circuit 1 includes a pair of transistors Q1 and Q2. The pair of transistors Q1 and Q2 are connected in series in opposite directions in a current loop that returns from the commercial AC power supply AC to the commercial AC power supply AC via the illuminator LT. Each of the transistors Q1 and Q2 is an N-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), and has a drain terminal D, a source terminal S, and a gate terminal G. In each of the transistors Q1 and Q2, a current path from the drain terminal D to the source terminal S is formed by charging the gate terminal G, and the current path is interrupted by discharging the gate terminal G. Each of the transistors Q1 and Q2 incorporates flywheel diodes D1 and D2 (hereinafter also simply referred to as diodes D1 and D2) for reverse conduction between the source and drain. The flywheel diodes D1 and D2 have anodes connected to the source terminal S and cathodes connected to the drain terminal D. The flywheel diodes D1 and D2 form a current flow path from the source terminal S to the drain terminal D regardless of the charge and discharge of the gate G. The two flywheel diodes D1 and D2 are also connected in the opposite direction by the reverse connection of the transistors Q1 and Q2. A connection node common to the two transistors Q1 and Q2 is referred to as a GND node (simply a GND node) in the light control device D.

  Here, the pair of transistors Q1 and Q2 corresponds to an example of a pair of switching elements according to the present invention. The drain terminal D and the source terminal S correspond to examples of the first terminal and the second terminal, respectively. As the transistors Q1 and Q2, in addition to MOS transistors, for example, IGBTs (Insulated Gate Bipolar Transistors) can be employed.

  In the switching circuit 1, when a positive voltage having an AC waveform is applied to the drain terminal D connected to the terminal 0 in a state where a predetermined charge is stored in the gate terminal G of the transistor Q 1, the drain-source is turned on. The current I flows through the diode D2 of the transistor Q2 connected in the opposite direction to the transistor Q1. This current I is controlled by the gate potential of the transistor Q1. When the gate charge of the transistor Q1 is discharged while the current is flowing, the transistor Q1 is turned off and the energization is stopped. A similar operation is performed for the transistor Q2 connected in the opposite direction to the transistor Q1. That is, in a state where a predetermined charge is stored in the gate terminal G of the transistor Q2, an AC waveform positive voltage (a negative voltage having a reverse polarity when viewed from the transistor Q1) is applied to the drain terminal D connected to the terminal 1. When applied, the drain-source is turned on, and a current I (however, opposite to the arrow in the figure) flows through the diode D1 of the transistor Q1. This current is controlled by the gate potential of the transistor Q2. If the gate charge of the transistor Q2 is discharged while the current is flowing, the transistor Q2 is turned off and the energization is stopped.

  Here, in the period (half cycle) of the peaks and valleys repeated with the AC waveform, the period in which the positive voltage of the AC waveform is applied to the terminal 0, that is, the drain terminal D of the transistor Q1, is referred to as the positive phase period, and the period in which the negative voltage is applied. (A period in which a positive voltage is applied to the terminal 1, that is, the drain terminal D of the transistor Q2) is referred to as a negative phase period opposite to the positive phase period. In the circuit diagram shown in FIG. 1, the upper side of the GND node is referred to as a positive operation side for convenience, and the lower side is referred to as a negative operation side. In other words, the operation of the switching circuit 1 is such that the positive operation side transistor Q1 performs energization control according to the gate potential during the AC positive phase period, and the negative operation side transistor Q2 corresponds to the gate potential during the negative phase period. Energization control is performed.

  The charge / discharge circuit 2 is a circuit that causes the switching circuit 1 to perform phase control by controlling charge charge / discharge of the gate terminals G of the transistors Q1, Q2. The charge / discharge circuit 2 alternately repeats charging of the gates G of the pair of transistors Q1 and Q2 and discharging at a timing according to the operation for the pair of transistors Q1 and Q2. More specifically, the charging / discharging circuit 2 includes each of the phase periods (for example, the positive phase period) of the transistors Q1 and Q2 in a state where an alternating voltage that alternately repeats positive and negative is applied to the transistors Q1 and Q2. ), While charging the gate terminal G of the transistor (for example, Q2) on the opposite phase to the one transistor (for example, Q1) that can control the current during the phase period with the potential of the gate terminal G, the phase period ( The gate terminal of the one transistor (for example, Q1) is discharged at a predetermined off timing in the positive phase period).

  The charging / discharging circuit 2 includes a discharging circuit 21, a charging circuit 22, and a cutoff timing generation circuit 23. The discharge circuit 21 and the charging circuit 22 have a circuit configuration in which the positive operation side and the negative operation side are symmetrical.

  The discharge circuit 21 is a circuit that controls stop of energization of the main current T flowing through the switching circuit 1. The discharge circuit 21 receives the discharge signal Sd and discharges the gate terminals G of the pair of transistors Q1 and Q2. The discharge circuit 21 includes discharge transistors Q5 and Q6 and resistors R9 and R10. Transistor Q5 and resistor R9 form a positive operation side discharge circuit, and transistor Q6 and resistor R10 form a negative operation side discharge circuit. Transistors Q5 and Q6 are NPN type transistors. The discharge circuit 21 is also provided with zener diodes ZD1, ZD2 and resistors R7, R8 for limiting the potential applied to the gate terminals G of the transistors Q1, Q2.

  When the transistor Q5 of the positive operation side discharge circuit is turned on, the charge of the gate terminal G of the transistor Q1 is discharged through the resistor R9, and the energization of the switching circuit 1 is stopped. When the transistor Q6 of the negative operation side discharge circuit is turned on, the charge at the gate terminal G of the transistor Q2 on the negative operation side is discharged through the resistor R10, and the energization of the switching circuit 1 is stopped.

  The charging circuit 22 is a circuit that charges the main current in a certain phase period by energizing the gate terminal G of the switching element on the opposite phase side. The charging circuit 22 is energized by a voltage generated between both terminals of the transistors Q1 and Q2 when the transistor Q1 or the transistor Q2 is turned off. The charging circuit 22 charges the gate terminal G of the other transistor Q2 (Q1) with respect to the one transistor Q1 (Q2) from which the gate terminal G is discharged by the discharging circuit 21 among the pair of transistors Q1 and Q2.

  The charging circuit 22 has two diodes D3 and D4. The diode D3 constitutes a positive operation side charging circuit, and the diode D4 constitutes a negative operation side charging circuit. The diode D3 of the positive operation side charging circuit is energized by the voltage generated at the terminal 0, that is, the drain terminal D of the positive operation transistor Q1 in the switching circuit 1, and the charge of this voltage is supplied to the gate terminal G of the negative operation transistor Q2. Conducted to. More specifically, the diode D3 supplies a part of the main current to the gate terminal G of the transistor Q2 on the reverse polarity side when the main current supplied to the transistor Q1 is turned off at the timing of the discharge signal Sd. Charges up to the specified voltage of Q2. The diode D4 of the negative operation side charging circuit is energized by the voltage generated at the terminal 1, that is, the drain terminal D of the negative transistor Q2 in the switching circuit 1, and the charge of this voltage is supplied to the gate terminal G of the positive transistor Q1. Conducted to. More specifically, the diode D4 charges the gate of the transistor Q1 on the reverse polarity side to the specified voltage when the transistor Q2 is turned off.

  The cutoff timing generation circuit 23 is a circuit that determines the discharge timing of the gate terminals G of the transistors Q1 and Q2. The cutoff timing generation circuit 23 generates a discharge signal Sd and inputs it to the discharge circuit 21. The discharge signal Sd is generated at a timing according to the operation in synchronization with the AC power output from the commercial AC power supply AC.

  The cutoff timing generation circuit 23 includes diodes D5 and D6, inverter logic circuits IC1, IC2 and IC3, a variable resistor VR1, resistors R12, R13, R14, R15, R16 and R17, and capacitors C3, C4, C5 and C6. The AC voltage applied to both ends (that is, terminals 0 and 1) of the switching circuit 1 is full-wave rectified by the diodes D5, D6, D1, and D2. By full-wave rectification, a valley (negative voltage) portion in the waveform of the AC voltage is converted into a peak (positive voltage), and a pulsating current having a frequency twice that of the AC voltage is generated. The voltage of the pulsating current collectively represents the states of both ends (that is, terminals 0 and 1) of the switching circuit 1. A signal obtained by dividing the voltage of the pulsating current by the two resistors R13 and R14 is referred to as a switching state signal Si. Note that the pulsating voltage before voltage division by the resistors R13 and R14 is smoothed by the resistor R12 and the capacitor C3, and is used as the power supply voltage of the inverter logic circuits IC1, IC2, and IC3.

  The three inverter logic circuits IC1, IC2 and IC3, variable resistor VR1, resistors R15 and R16, and capacitor C5 constitute a delay circuit. Since three inverter logic circuits IC1, IC2, and IC3 are connected in series, the delay circuit output is a level-inverted output with respect to the input. The variable resistor VR1 is linked to an operation knob (not shown), and the delay amount of the delay circuit is changed by changing the resistance value by the operation. The switching state signal Si, that is, the pulsating signal divided by the resistors R13 and R14, is delayed by the delay circuit and the logic level is inverted, and is output as the discharge signal Sd. The discharge signal Sd represents the timing at which the gate terminals G of the transistors Q1 and Q2 are discharged.

  In the switching state signal Si, a state where the voltage is low (low level in the logic circuit IC1) represents a state where the switching circuit 1 is energizing the main current I, and a state where the voltage is high (high level in the logic circuit IC1). 1 represents a state in which one of the transistors Q1 and Q2 in FIG. Near the timing at which the AC voltage crosses the midpoint potential (0 V) (zero crossing), the switching state signal Si transitions from the high level to the low level. From this transition timing, the discharge signal Sd goes to a high level after a delay corresponding to the operation of the variable resistor VR1. That is, the cutoff timing generation circuit 23 outputs the high level of the discharge signal Sd at a timing delayed by a time corresponding to the operation from the timing at which the AC voltage crosses zero. The gate signal timing of the transistors Q1 and Q2 is controlled by the discharge signal Sd, and dimming is performed. The variable resistor VR1 is interlocked with the switch 6 via an operation knob (not shown). When the operation knob is at the maximum brightness position, the switch 6 is turned on, and all the electric power of the commercial AC power supply AC is supplied to the illuminator LT, and the operation of the circuit in the light control device D is stopped.

[Surge voltage detection circuit, charge prohibition circuit, and surge voltage absorption element]
The surge voltage detection circuit 3 is a circuit that detects a surge voltage generated between both ends of the switching circuit 1. The surge voltage detection circuit 3 includes surge detection elements SSA1, SSA2, resistors R1, R2, R3, R4, and capacitors C1, C2. Among these, the surge detection element SSA2, the resistors R3 and R4, and the capacitor C2 constitute a positive operation side surge voltage detection circuit, and the surge detection element SSA2, the resistors R3 and R4, and the capacitor C2 constitute a negative operation side surge voltage detection circuit. Is configured.

  Positive operation side surge detection element SSA1 and resistors R1, R2 are connected in series between the drain and source of transistor Q1. The capacitor C1 is connected in parallel with the resistor R2. The surge detection element SSA1 is an element that conducts by receiving a voltage larger than a threshold voltage, and is, for example, a silicon surge absorber. As the threshold voltage of surge detection element SSA1, a voltage that is larger than the voltage of commercial AC power supply AC and smaller than the breakdown voltage between the drain and source of transistor Q1 is selected. The resistor R2 and the capacitor C1 form an integrating circuit. As the time constant of the resistor R2 and the capacitor C1, a value longer than the cycle of the commercial AC power supply AC is selected. The time constant is, for example, a value that is about 2 to 100 times the AC cycle of the commercial AC power supply AC. The integrating circuit including the resistor R2 and the capacitor C1 generates the charge inhibition signal Sp by holding the surge detection signal obtained by the surge detection element SSA1 for a period corresponding to the time constant. In this way, the surge voltage detection circuit 3 generates the charge inhibition signal Sp that lasts for a period corresponding to the time constant in response to the occurrence of a surge voltage that is greater than the threshold voltage.

  The negative operation side surge voltage detection circuit including the surge detection element SSA2, resistors R3 and R4, and the capacitor C2 generates a charge inhibition signal Sp '. The circuit on the negative operation side has a symmetric configuration with the circuit on the positive operation side and performs the same operation as that on the positive operation side, so that the description is omitted.

  The transistor Q3 and the transistor Q4 of the charge prohibition circuit 4 prohibit charging of the gate terminals G of the transistors Q1 and Q2 by the charge circuit 22 during a period in which the charge prohibition signals Sp and Sp ′ are sustained in response to the input of the charge prohibition signal Sp. To do.

  The charge prohibition circuit 4 includes a transistor Q3 connected between the gate and the source of the transistor Q1, and a transistor Q4 connected between the gate and the source of the transistor Q2. Transistor Q3 constitutes a positive operation side charge inhibition circuit, and transistor Q4 constitutes a negative operation side charge inhibition circuit.

  The transistor Q3 of the positive operation side charge prohibition circuit is, for example, an N-channel MOSFET. The drain terminal D and the source terminal S of the transistor Q3 are connected to the gate terminal G and the source terminal S of the transistor Q1, respectively. The charge prohibition signal Sp is supplied from the surge voltage detection circuit 3 (positive operation side surge voltage detection circuit) to the gate terminal G of the transistor Q3. The transistor Q3 of the charge prohibition circuit 4 is turned on for the duration of the charge prohibition signal Sp and forms a discharge path for discharging the gate terminal G of the transistor Q1. As a result, charging of the gate terminal G of the transistor Q1 is prohibited. The negative operation side charge prohibition circuit composed of the transistor Q4 has a symmetric configuration with respect to the positive operation side, and is turned on while the charge prohibition signal Sp ′ continues, and discharges the gate terminal G of the transistor Q2. Form a road.

  In the present embodiment, each of the surge voltage detection circuit 3 and the charge prohibition circuit 4 operates independently on the positive operation side and the negative operation side.

  The surge voltage absorbing element 5 is connected in parallel with the switching circuit 1 and is an element that absorbs a surge voltage generated between both ends of the switching circuit 1. The surge voltage absorbing element 5 is, for example, a varistor. However, as the surge voltage absorbing element 5, a gas tube arrester or a silicon surge absorber can be used.

[Basic operation of the light control device]
FIG. 2 is a graph showing a potential waveform and a current waveform of each part of the light control device D shown in FIG. Part (A) of FIG. 2 is an output voltage of the commercial AC power supply AC. Part (B) is a switching state signal Si, and part (C) is a discharge signal Sd. Part (D) is the potential of the gate terminal G of the transistor Q1, and Part (E) is the potential of the drain terminal D of the transistor Q1. Part (F) shows the main current I flowing through the switching circuit 1 and the load. In FIG. 2, for easy understanding of the circuit operation, a waveform when the phase control of 90 ° is performed and the load is a forward resistance is shown.

  The basic operation of the light control device D will be described with reference to FIG. 1 and FIG. First, the operation in the positive phase period in the alternating current from the commercial AC power supply AC (see FIG. 1), that is, the operation in the period in which the terminal 0 is positive will be described from the state at the timing t1, which is the negative phase period immediately before.

  At the timing t1 of the negative phase period shown in FIG. 2, a positive voltage is applied to the terminal 1, that is, the drain terminal D of the transistor Q2 on the negative operation side in the switching circuit 1. However, at the timing t1, the transistor Q2 is in an off state, and the conduction of the main current I in the switching circuit 1 and the load is stopped (part (F) in FIG. 2). At this time, a voltage substantially equal to the voltage supplied from the commercial AC power supply AC is generated between the drain and source of the transistor Q2. The potential of the drain of the transistor Q2 is divided by the resistors R13 and R14 through the diode D6 in the cutoff timing generation circuit 23 and input to the inverter logic circuit IC1 as the switching state signal Si (part (B) in FIG. 2). .

  Further, the potential of the drain terminal D of the transistor Q2 charges the gate terminal G of the transistor Q1 on the positive operation side that controls the current in the positive phase period opposite to the negative phase period of the timing t1 through the diode D4 of the charging circuit 22. To do. That is, the gate of the transistor Q1 of the switching circuit 1 is charged by the charging circuit 22 with a potential having a phase period opposite to the polarity of the phase period controlled by the transistor Q1.

  Thereafter, at the timing t2 when the AC state supplied from the commercial AC power source AC shifts to the positive phase period, a positive voltage is applied to the drain terminal D of the transistor Q1 on the positive operation side in the switching circuit 1. Since the gate terminal G of the transistor Q1 is charged with the specified value voltage in the negative phase period immediately before this, the drain-source region of the transistor Q1 is turned on. Therefore, the main current I flows through the drain-source of the transistor Q1 and further through the diode D2 built in the transistor Q2 (part (F) of FIG. 2). That is, the current loop is energized. When the switching circuit 1 is turned on, the voltage generated at both ends of the switching circuit 1 is reduced, and charging of the gate terminal G of the transistor Q1 by the charging circuit 22 is stopped. Although the gate terminal G is gradually spontaneously discharged, the active state of the transistor Q1 continues because the active discharge is not performed.

  Further, the switching state signal Si (part (B) of FIG. 2) representing the state of the drain terminal D of the transistor Q2 via the diode D6 in the cutoff timing generation circuit 23 is the potential of the commercial AC power supply (part of FIG. 2). (A)) transitions from a high level to a low level at the timing of zero crossing. In response to this, the discharge signal Sd (part (C) of FIG. 2) in the interruption timing generation circuit 23 transitions from a low level to a high level indicating the discharge timing at a delay timing corresponding to an operation of an operation knob (not shown). .

  The discharge circuit 21 receives the discharge signal Sd and discharges the gate terminals G of the pair of transistors Q1 and Q2. More specifically, the bases of the transistors Q5 and Q6 in the discharge circuit 21 are set to the high level by the discharge signal Sd, and only the transistor on the side where the specified voltage (gate voltage) is applied to the collector side of the transistors Q5 and Q6 is turned on. become. The charges at the gate terminals G of the transistors Q1 and Q2, in particular, the charges at the gate terminal G of the transistor Q1, which have been charged here, are discharged through the transistor Q5 (part (D) in FIG. 2). As a result, the transistor Q1 is turned off.

  At timing t3 when the transistor Q1 is turned off, the conduction of the main current I in the switching circuit 1 and the load is stopped. At this time, a voltage substantially equal to the voltage supplied from the commercial AC power supply AC is applied between the drain and source of the transistor Q1. Therefore, this time, the potential of the drain terminal of the transistor Q1 charges the gate terminal G of the transistor Q2 on the negative operation side via the diode D3 of the charging circuit 22.

  Thereafter, when the AC state supplied from the commercial AC power supply AC shifts to the negative phase period, the above-described operation is repeated with the polarity changed.

  In this way, the AC power supplied from the commercial AC power supply AC is phase-controlled. Further, the timing at which the discharge signal Sd is output changes according to the operation of the variable resistor VR1, and the period during which the transistors Q1 and Q2 are turned on, that is, the phase control timing is controlled. In this way, dimming of the illuminator LT is performed.

  The dimming device D of the present embodiment performs phase control so as to turn on from the vicinity of the zero cross in each of the positive phase period and the negative phase period, which are half cycles of the AC waveform, and to limit conduction in the latter half part. For this reason, for example, high-frequency noise and audible noise are reduced compared to triac-type phase control in which conduction is performed at a steep rise after limiting conduction in the first half of the period. Large parts for noise suppression such as a low-pass filter are not required. Moreover, no countermeasure against a sudden inrush current is required. Further, the light control device D of the present embodiment does not require a holding current for maintaining the on-state, which is necessary for, for example, the phase control of the triac. Therefore, even when driving a non-forward resistance load such as an LED, a circuit for passing a current that is not used for illumination is unnecessary, and the overall power efficiency is improved.

[Surge voltage absorption operation]
FIG. 3 is a circuit diagram showing a state where an unauthorized load M is connected to the light control device shown in FIG. 1 instead of the illuminator.

  The load M illustrated in FIG. 3 is a load having a coil, such as an electric drill, a ventilation fan, a dryer, and a fan. These loads are mistakenly connected to the wiring for the illuminator. In addition, a low voltage halogen lamp with a step-down transformer can be connected to the light control device D of the present embodiment, but when the low voltage halogen lamp is blown (blow), the light control device D Is a state in which the primary coil of the step-down transformer is connected as an inductive load M.

  When the inductive load M is connected to the dimmer D, when the transistors Q1 and Q2 of the switching circuit 1 are turned off in response to the discharge signal Sd, an inductive surge is generated. Since the surge voltage absorbing element 5 absorbs the surge voltage, the surge voltage at both ends of the switching circuit 1 is lower than when the surge voltage absorbing element 5 is not provided, and can be suppressed lower than the breakdown voltage of the transistors Q1 and Q2. . The surge voltage absorbing element 5 does not completely eliminate the surge voltage.

  The surge detection element SSA1 of the surge voltage detection circuit 3 receives the generation of the surge voltage and generates a sustained charge prohibition signal Sp. The period during which this charge inhibition signal Sp lasts is longer than the cycle of the commercial AC power supply AC. The charge prohibition circuit 4 prohibits charging by the charging circuit 22 of the gate terminal G of the transistor Q1 during the period when the charge prohibition signal Sp is sustained. The switching of the transistor Q1 is stopped during the period in which the charge inhibition signal Sp is sustained. That is, no surge voltage is generated during this period. Therefore, the occurrence frequency of the surge voltage absorbed by the surge voltage absorbing element 5 is reduced, and overheating of the surge voltage absorbing element 5 can be avoided. As a result, the surge voltage absorption element 5 can maintain the surge voltage absorption performance, and failure can be prevented.

  FIG. 4 is a graph showing an example of the voltage waveform at both ends of the dimmer and the voltage waveform at both ends of the load in the circuit shown in FIG. Part (A) of FIG. 4 shows the voltages at both ends T1 and T2 of the light control device D, and Part (B) shows the voltage at both ends of the load. In this example, a waveform is shown when a ventilation fan with a power consumption of 43 W is connected as a load and AC power of 100 V 60 Hz is supplied from a commercial AC power supply AC.

  When a ventilation fan that is an inductive load is connected, charging of the gate terminal G of the transistor Q1 is prohibited for a period during which the charging prohibition signal Sp is sustained. Therefore, a voltage almost the same as the output voltage of the commercial AC power supply AC appears at both ends 0 and 1 of the light control device D. When the charge inhibition signal Sp is no longer sustained and released from the charge prohibited state, the transistor Q1 is charged and discharged. At this time, a pulsed surge (kickback) voltage is generated. Since a part of the surge voltage is absorbed by the surge voltage absorbing element 5, the peak value of the surge voltage at both ends 0 and 1 of the dimmer D is about 440V. This peak value is lower than the breakdown voltage of the transistor Q1. Further, as a result of the surge voltage being detected by the surge voltage detection circuit 3, charging of the gate terminal G of the transistor Q1 is prohibited. The charging of the gate terminal G is prohibited for a period corresponding to a plurality of periods of AC power. Since the occurrence frequency of the surge voltage is reduced, overheating of the surge voltage absorbing element 5 can be avoided and the absorption performance can be maintained. Therefore, the surge voltage generated in the transistor Q1 is suppressed to be lower than the breakdown voltage of the transistor Q1. Therefore, failure of the light control device D including the transistor Q1 can be suppressed. Further, in the dimming device D of the present embodiment, when the inductive load M is connected, the operation of the transistor Q1 is prohibited, so that almost no current flows through the inductive load M. Therefore, the load itself is protected.

  Here, the circuit on the positive operation side that controls charging / discharging of the transistor Q1 has been described, but these descriptions also apply to the operation of the circuit on the negative operation side that controls charging / discharging of the transistor Q2.

  When the surge voltage detection circuit 3 maintains the charge inhibition signal Sp, the frequency of occurrence of the surge voltage is reduced to less than half if the period of AC is about twice or more, thus reducing the heat generation of the surge voltage absorbing element 5. Effect. In addition, if the period to be maintained is about 100 times or less of the AC cycle, lighting by dimming will start in a short period of time within a few seconds at the longest when an erroneously connected load is removed and an illuminator is connected. To do.

  In the embodiment described above, a transistor that forms a discharge path for discharging the gate of the switching element is shown as an example of the charge prohibition circuit according to the present invention. However, the present invention is not limited to this. For example, the charging prohibition circuit may be a switching element that opens and closes a charging path, for example. However, by discharging the gate of the switching element, charging can be reliably prohibited with a simple configuration.

  In the embodiment described above, an integration circuit that holds a signal is shown as an example of the surge voltage detection circuit according to the present invention. In addition, the embodiment includes a cut-off timing generation circuit 23 that delays a signal for discharge by an inverter logic circuit and a capacitor as an example of a charge / discharge circuit that discharges at a timing according to an operation according to the present invention. A charge / discharge circuit 2 is shown. However, the present invention is not limited to this. For example, a circuit that holds a signal or a circuit that generates timing according to an operation is a digital processing circuit having a counter or a microcomputer that performs time counting processing. May be.

  In the above-described embodiment, as examples of the surge voltage detection circuit and the charge prohibition circuit according to the present invention, there are independent circuits on the positive operation side and the negative operation side, and the positive operation side and the negative operation side. The surge voltage detection circuit 3 and the charge prohibition circuit 4 that operate independently are shown. However, the present invention is not limited to this. For example, both the positive operation side and the negative operation side of the charge prohibition circuit are operated by detecting either the positive operation side or the negative operation side of the surge voltage detection circuit. It may be configured to.

  Moreover, the light control apparatus D installed in a wall etc. is shown by the embodiment mentioned above as an example of the light control apparatus said to this invention. However, the light control device of the present invention is not limited to this. For example, the light control device may be a portable type connected to an outlet, or may be built in the lighting device together with the light source.

DESCRIPTION OF SYMBOLS 1 Switching circuit 2 Charging / discharging circuit 21 Discharging circuit 22 Charging circuit 23 Cutoff timing generation circuit 3 Surge voltage detection circuit 4 Charge prohibition circuit 5 Surge voltage absorption element AC Commercial AC power supply LT Illuminator SSA1, SSA2 Surge detection element M Non-conformity load (induction Motor etc.)

Claims (3)

In a current loop that returns from the commercial AC power source to the commercial AC power source via the illuminator, they are connected in series in opposite directions, each having a first terminal, a second terminal, and a gate terminal, and the first is obtained by charging the gate. A current flow path from the terminal to the second terminal is formed, the current flow path is interrupted by the discharge of the gate, and a current flow from the second terminal to the first terminal irrespective of charging and discharging of the gate A switching circuit having a pair of switching elements formed with a path;
A charge / discharge circuit that alternately repeats charging for each gate of the pair of switching elements and discharging at a timing according to the operation for the pair of switching elements;
A surge voltage detection circuit that detects a surge voltage generated between both ends of the switching circuit and generates a charge prohibition signal that lasts for a predetermined period longer than the cycle of the AC power supplied from the commercial AC power supply in response to the generation of the surge voltage When,
A charge prohibition circuit for prohibiting charging of the gate by the charge / discharge circuit during a period in which the charge prohibition signal is sustained after receiving the input of the charge prohibition signal;
A light control device comprising: a surge voltage absorbing element that is connected in parallel with the switching circuit and absorbs a surge voltage generated between both ends of the switching circuit.   The light control device according to claim 1, wherein the charge prohibition circuit includes a pair of transistors that form a discharge path for discharging a gate of each of the pair of switching elements while the charge prohibition signal is sustained. The surge voltage detection circuit is
A surge detecting element for detecting a surge voltage across the switching circuit;
The light control device according to claim 1, further comprising an integration circuit that generates the charge inhibition signal by holding the surge detection signal obtained by the surge detection element for the predetermined period.

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