JP5907749B2

JP5907749B2 - Video signal multiplex transmission apparatus and imaging apparatus including the same

Info

Publication number: JP5907749B2
Application number: JP2012027048A
Authority: JP
Inventors: 忠義鳥居; 中村　和彦; 和彦中村
Original assignee: Hitachi Kokusai Electric Inc
Current assignee: Hitachi Kokusai Electric Inc
Priority date: 2011-02-17
Filing date: 2012-02-10
Publication date: 2016-04-26
Anticipated expiration: 2032-02-10
Also published as: CN103477622B; JP2012186800A; CN103477622A; WO2012111557A1

Description

本発明は、テレビジョンカメラ装置等の撮像装置に用いる映像信号多重伝送装置における伝送方法の改良に関するものである。 The present invention relates to an improvement in a transmission method in a video signal multiplex transmission apparatus used in an imaging apparatus such as a television camera apparatus.

従来、テレビジョンカメラシステムではカメラヘッドとカメラコントロールユニットの間で本線映像信号，送り返し映像信号，音声信号，コントロール用シリアルデータ信号，及び電源の伝送を３重同軸（トライアックス）ケーブル１本の伝送路で行なっている。簡易方法として伝送路に通常の同軸ケーブルも用いることもある。通常、これらの信号は周波数変調され周波数多重伝送するか、デジタルで時分割多重（双方向切換）伝送される。 Conventionally, in a television camera system, transmission of a main line video signal, a return video signal, an audio signal, a serial data signal for control, and a power supply between a camera head and a camera control unit is performed by a single triaxial cable. On the road. As a simple method, a normal coaxial cable may be used for the transmission line. Usually, these signals are frequency-modulated and frequency-multiplexed or digitally time-division multiplexed (bidirectional switching).

主な映像信号としてはＳＤＴＶとして有効走査線４８５本のＮＴＳＣと有効走査線５７５本のＰＡＬ、ＨＤＴＶとして有効走査線７２０本と有効走査線１０８０本、ＳＨＤＴＶとして有効走査線２１６０本、ＵＨＤＴＶとして有効走査線４３２０本がある。 Main video signals include NTSC with 485 effective scanning lines as SDTV and PAL with 575 effective scanning lines, 720 effective scanning lines and 1080 effective scanning lines as HDTV, 2160 effective scanning lines as SHDTV, and effective scanning as UHDTV. There are 4320 lines.

カメラ部から出力されたＮＴＳＣの１０ｂｉｔ４：２：２のデジタル化した映像信号、音声信号、制御信号を含む映像シリアルデジタルインタフェース（ＳＤＩ）信号は出力振幅０．８Ｖｐ−ｐで２７０Ｍｂｐｓのデータ量があり、送り返しの映像信号はデータ圧縮しても約５０Ｍｂｐｓのデータ量がある。時分割双方向伝送の場合、映像信号を時間圧縮し、約３６０Ｍｂｐｓの信号にして短い時間で間欠的にカメラヘッドからカメラ制御装置に伝送する。そして時間圧縮により空いた期間に、カメラ制御装置からカメラヘッドの方向に３６０Ｍｂｐｓに時間圧縮した送り返しの映像信号を短い時間で間欠的に伝送する。その処理を１秒間に数回の速度で入出力切換え器により切り替えを行なうことにより時分割多重（双方向切換）伝送を実現している（特許文献１）。ＨＤＴＶ用のＳＤＩ（ＨＤ−ＳＤＩ）信号は１５００Ｍｂｐｓのデータ量がある。３ＧのＳＤＩ信号は２９７０Ｍｂｐｓのデータ量がある。ＵＨＤＴＶ用のＳＤＩ信号は約２４０００Ｍｂｐｓのデータ量がある。 The NTSC 10-bit 4: 2: 2 digitized video signal, audio signal, and control signal output from the camera unit have a data amount of 270 Mbps with an output amplitude of 0.8 Vp-p. The sent back video signal has a data amount of about 50 Mbps even if the data is compressed. In the case of time-division bidirectional transmission, the video signal is time-compressed to be a signal of about 360 Mbps, and is intermittently transmitted from the camera head to the camera control device in a short time. Then, during a period freed by time compression, a video signal for sending back time-compressed to 360 Mbps in the direction of the camera head from the camera control device is intermittently transmitted in a short time. Time division multiplexing (bidirectional switching) transmission is realized by switching the processing at a rate of several times per second by an input / output switch (Patent Document 1). The SDI (HD-SDI) signal for HDTV has a data amount of 1500 Mbps. The 3G SDI signal has a data amount of 2970 Mbps. The SDI signal for UHDTV has a data amount of about 24000 Mbps.

パルス波形の再生を行うことを波形等化という。通常、直径８．６ｍｍのトライアックスケーブルの３００ＭＨｚの減衰量は１００ｍで１２ｄＢで１ｋｍで１２０ｄＢと大きく、現状の市販の波形等化器では、直径８．６ｍｍのトライアックスケーブルでは約５００ｍ程度しかカメラヘッドとカメラコントロールユニットの間は延長できない。中継ケーブルの挿入による延長には、伝送された基準信号に基づき、デジタル映像信号のケーブル周波数特性の劣化を予め補正する必要がある。ＳＤＩ映像信号に電源を重畳する監視用途の同軸重畳も提案されている（非特許文献１参照）。 Reproducing the pulse waveform is called waveform equalization. Usually, the attenuation of 300 MHz of a 8.6 mm diameter triax cable is as large as 120 dB at 1 dB and 12 dB at 100 dB, and the current commercially available waveform equalizer has a camera of only about 500 m with a 8.6 mm diameter triax cable. It cannot be extended between the head and the camera control unit. To extend by inserting a relay cable, it is necessary to correct in advance the deterioration of the cable frequency characteristic of the digital video signal based on the transmitted reference signal. Coaxial superimposition for monitoring that superimposes a power source on an SDI video signal has also been proposed (see Non-Patent Document 1).

ＳＤＩ信号は、アナログ信号処理回路において反転増幅器が多用されるため、信号の極性を常に留意していることが煩わしくなる。そこで、Ｇ（ｘ）＝（ｘ⁹ ＋ｘ⁴ ＋１）（ｘ＋１）という生成多項式による自己同期型スクランブルド（ＮｏｎＲｅｔｕｒｎＴｏＺｅｒｏ）ＮＲＺ−Ｉ符号を採用し、データの０／１を０→１，１→０の反転情報に置き換えることによって、極性フリーでスペクトルが均一に分布したＳＤＩ信号を実現している。こうした自己同期型スクランブルを掛けると、シリアル伝送路上に、１水平ラインに亘り、１ビットの１に続いて１９ビットの０が続くパターン（あるいはその反転パターン）の信号や、２０ビットの１が連続した後２０ビットの０が連続するパターン（あるいはその反転パターン）の信号が発生する場合がある。これらのパターンは、パソロジカルパターンと呼ばれている。したがって、パソロジカルパターンの最大長２０からＳＤＩ信号の基本クロック周波数の１／２０から３倍の高調波周波数を伝送すれば、誤りなくＳＤＩ信号を伝送できる（非特許文献２参照）。ＨＤ−ＳＤＩ信号も同様である。 Since the SDI signal uses an inverting amplifier frequently in the analog signal processing circuit, it is troublesome to always pay attention to the polarity of the signal. Therefore, a self-resonant scrambled (Non Return To Zero) NRZ-I code using a generator polynomial of G (x) = (x ⁹ + x ⁴ +1) (x + 1) is adopted, and 0/1 of the data is changed from 0 → 1, By replacing the inverted information with 1 → 0, an SDI signal having a spectrum distributed uniformly is realized. When such a self-synchronization type scramble is applied, a signal of a pattern (or its inverted pattern) in which a 19-bit zero follows a 1-bit 1 followed by a 1-bit 1 on a serial transmission line, or a 20-bit 1 continues. After that, a signal of a pattern in which 20 bits of 0s continue (or its inverted pattern) may be generated. These patterns are called pathological patterns. Therefore, if a harmonic frequency that is 1/20 to 3 times the basic clock frequency of the SDI signal is transmitted from the maximum length 20 of the pathological pattern, the SDI signal can be transmitted without error (see Non-Patent Document 2). The same applies to the HD-SDI signal.

送信回路と受信回路のインピーダンスがケーブルインピーダンス７５Ωから外れると反射が起こり伝送エラーが増加する。ＳＤＩ信号を長距離にケーブル伝送するには、送信回路と受信回路のインピーダンスを所要周波数内で、ケーブルインピーダンス７５Ωにできるだけ一致させるのが望ましい（非特許文献２参照）。 When the impedance of the transmission circuit and the reception circuit deviates from the cable impedance of 75Ω, reflection occurs and transmission errors increase. In order to transmit an SDI signal over a long distance, it is desirable to make the impedance of the transmission circuit and the reception circuit as close as possible to the cable impedance of 75Ω within the required frequency (see Non-Patent Document 2).

２９７０Ｍｂｐｓの３ＧのＳＤＩ信号受信で伝送同軸ケーブル長１００ｍから２００ｍに改良された波形等化器で波形等化しても、２７０ＭｂｐｓのＳＤＩ信号受信で伝送同軸ケーブル長は３５０ｍから４００ｍと少ししか伸びない（非特許文献３と非特許文献４参照）。波形等化器を含む受信器でも２７０ＭｂｐｓのＳＤＩ信号受信で伝送同軸ケーブル長は４８０ｍと少ししか伸びない（非特許文献５参照）。 Even if the waveform equalizer is improved by a waveform equalizer improved from a transmission coaxial cable length of 100 m to 200 m when receiving a 3G SDI signal of 2970 Mbps, the transmission coaxial cable length increases slightly from 350 m to 400 m when receiving a 270 Mbps SDI signal ( Non-Patent Document 3 and Non-Patent Document 4). Even with a receiver including a waveform equalizer, the length of the transmission coaxial cable is only slightly increased to 480 m by receiving an SDI signal of 270 Mbps (see Non-Patent Document 5).

電流帰還演算増幅器（Operational Amplifier: Op Amp）は０．２Ｖｐ−ｐの小振幅で増幅度１倍（０ｄＢ）なら１．８ＧＨｚ程度、増幅度２倍（＋６ｄＢ）なら１．２ＧＨｚ程度までの高周波数を増幅でき、２Ｖｐ−ｐの大振幅なら７５０ＭＨｚ程度までの高周波数を増幅でき、シャットダウン（ＳＤ）機能を有するものもある（非特許文献６参照）。
しかし、電流帰還演算増幅器内部の増幅トランジスタのエミッタが負入力端子に接続されており、負入力端子の接続インピーダンスは高周波数成分が抵抗成分でないと、高周波数で発振を起こしやすい。そのため、電流帰還演算増幅器の負入力端子を容量で接地し、高周波数成分を増強する増幅回路の実現は困難だった。 The operational amplifier (op amp) has a small amplitude of 0.2Vp-p and high frequency up to about 1.8GHz if the amplification is 1x (0dB), and about 2GHz if the amplification is 2x (+ 6dB). In the case of a large amplitude of 2 Vp-p, a high frequency up to about 750 MHz can be amplified, and some have a shutdown (SD) function (see Non-Patent Document 6).
However, the emitter of the amplification transistor inside the current feedback operational amplifier is connected to the negative input terminal, and the connection impedance of the negative input terminal tends to oscillate at a high frequency unless the high frequency component is a resistance component. Therefore, it has been difficult to realize an amplifier circuit that enhances the high frequency component by grounding the negative input terminal of the current feedback operational amplifier with a capacitor.

ところで、最近不要輻射低減用に、低い周波数では、低いインピーダンスで、特定周波数からインピーダンスが急激に高くなり、抵抗成分が大きいフェライトビーズが多様な種類で各社から量産されている。フェライトビーズの近似の等価回路はインダクタと容量と抵抗との並列接続したものと抵抗との直列接続したものである（非特許文献７参照）。フェライトビーズを用いたケーブル補正も提案されている（特許文献２参照）。 By the way, recently, various kinds of ferrite beads having a large resistance component have been mass-produced by various companies in order to reduce unnecessary radiation. An approximate equivalent circuit of a ferrite bead is one in which an inductor, a capacitor and a resistor are connected in parallel and a resistor is connected in series (see Non-Patent Document 7). Cable correction using ferrite beads has also been proposed (see Patent Document 2).

従来の一実施例の概要と動作を図２で説明する。図２は、従来の一実施例のトライアックスカメラシステムを示すブロック図である。図２において、トライアックスカメラシステムは撮像部１とトライアックスケーブル２と制御部３で構成している。 The outline and operation of a conventional embodiment will be described with reference to FIG. FIG. 2 is a block diagram showing a triax camera system of a conventional example. In FIG. 2, the triax camera system includes an imaging unit 1, a triax cable 2, and a control unit 3.

撮像部１の撮像素子１０２は、レンズ部１０１で結像された入射光を光電変換してデジタル映像信号処理部２０４に出力する。デジタル映像信号処理部２０４は、映像信号のレベル増幅や輪郭強調等の処理を施し出力する。伝送路２が長い場合、映像圧縮部１０５で映像圧縮を行い、短い場合はそのまま時分割双方向切換部２１０に出力される。時分割双方向切換部２１０では、デジタル映像信号とデジタル音声信号とを時分割多重化し、双方向伝送する。撮像部１より出力されたシリアルデジタル信号は、トライアックスケーブル２を介して制御部３に伝送される。制御部３に伝送されたシリアルデジタル信号は、時分割双方向切換部２１６で分解され、もとのデジタル映像信号とデジタル音声信号とに復調し、映像伸縮を行い、デジタル信号処理部２１７で信号処理後、D/Aコンバータ１２８でアナログ映像信号に変換され、映像信号を出力する。また、制御部３から入力し撮像部１から出力する外部映像信号も上記と同様に伝送される。 The imaging element 102 of the imaging unit 1 performs photoelectric conversion on incident light imaged by the lens unit 101 and outputs the converted light to the digital video signal processing unit 204. The digital video signal processing unit 204 performs processing such as level amplification and edge enhancement of the video signal and outputs the result. When the transmission path 2 is long, the video compression unit 105 compresses the video, and when the transmission path 2 is short, the video is directly output to the time division bidirectional switching unit 210. In the time division bidirectional switching unit 210, the digital video signal and the digital audio signal are time division multiplexed and bidirectionally transmitted. The serial digital signal output from the imaging unit 1 is transmitted to the control unit 3 via the triax cable 2. The serial digital signal transmitted to the control unit 3 is decomposed by the time-division bidirectional switching unit 216, demodulated into the original digital video signal and digital audio signal, expanded and contracted, and the digital signal processing unit 217 After processing, it is converted into an analog video signal by the D / A converter 128, and the video signal is output. An external video signal that is input from the control unit 3 and output from the imaging unit 1 is also transmitted in the same manner as described above.

時分割双方向切換部２１０と２１６とは、高速なＮＭＯＳ（N-channel Metal Oxidize Semiconductor Field Effect Transistor）バススイッチのＩＣを用いるが、ＮＭＯＳバススイッチのＩＣ内のＮＭＯＳのソースーゲート間電圧が約１Ｖ以上確保されないとＮＭＯＳバススイッチが導通されない。またＮＭＯＳバススイッチＩＣ内のＮＭＯＳのソースーゲート間電圧が約２ＶではＮＭＯＳバススイッチの導通抵抗Ｒｄが高い。またＮＭＯＳバススイッチＩＣ内のＮＭＯＳのソースーゲート間電圧が約２．５Ｖ以上確保されないとＮＭＯＳバススイッチの導通抵抗Ｒｄが下がりきらない。そのため、時分割双方向切換部を通過する信号は、ＮＭＯＳバススイッチＩＣの正電源電圧から約２．５Ｖ低い電圧以内が圧縮され、ＮＭＯＳバススイッチＩＣの正電源電圧から約２Ｖ低い電圧以内が強く圧縮され、ＮＭＯＳバススイッチＩＣの正電源電圧から約１Ｖ低い電圧以下に制限される。具体的なＮＭＯＳバススイッチＩＣの導通抵抗Ｒｄは、本発明の１実施例のＮＭＯＳバススイッチＩＣの導通抵抗特性の模式図の図８Ａのように、ＮＭＯＳバススイッチＩＣの正電源電圧から２．１Ｖで１０Ω、２．５Ｖで８Ω、２．９Ｖで７Ω、３．３Ｖで６Ω、３．７Ｖで５Ω、４．３Ｖで４Ωとなる（非特許文献８参照）。
つまり、時分割双方向切換を行う場合は、接地電位のＳＤＩ信号０．８Ｖｐ−ｐでの導通抵抗ＲｄがＮＭＯＳバススイッチで１０Ωから７Ωとなり、トライアックスケーブルまたは同軸ケーブルの伝送路の特性インピーダンスＲｚ＝７５Ωに対し５％以上と、無視できない抵抗値となり、インピーダンスミスマッチングが発生して反射による波形歪が発生する。さらにＳＤＩ信号の振幅値０．８Ｖｐ−ｐでの抵抗値変化がＮＭＯＳバススイッチＩＣでは３Ωと７５Ωに対し約４％と無視できない変化をし、上下非対称の波形歪が発生する。受信側で受信信号の高周波数成分を増幅させる等の周波数特性補正や２９７０Ｍｂｐｓの３ＧのＳＤＩ信号受信用に改良された等化器でも波形等化では、インピーダンスミスマッチングの反射による波形歪や上下非対称の波形歪による位相変化は残ってしまい補正できない。そのため、伝送ケーブル長を延長することが困難であった。 The time-division bidirectional switching units 210 and 216 use a high-speed NMOS (N-channel Metal Oxidize Semiconductor Field Effect Transistor) bus switch IC, but the NMOS source-gate voltage in the NMOS bus switch IC is about 1 V or more. If not secured, the NMOS bus switch is not conducted. Further, when the NMOS source-gate voltage in the NMOS bus switch IC is about 2 V, the conduction resistance Rd of the NMOS bus switch is high. Further, the NMOS bus switch conduction resistance Rd cannot be lowered unless the NMOS source-gate voltage in the NMOS bus switch IC is secured to about 2.5 V or more. Therefore, the signal passing through the time-division bidirectional switching unit is compressed within about 2.5V lower than the positive power supply voltage of the NMOS bus switch IC, and strongly within about 2V lower than the positive power supply voltage of the NMOS bus switch IC. Compressed and limited to about 1V lower than the positive power supply voltage of the NMOS bus switch IC. Specifically, the conduction resistance Rd of the NMOS bus switch IC is 2.1 V from the positive power supply voltage of the NMOS bus switch IC as shown in FIG. 8A of the schematic diagram of the conduction resistance characteristic of the NMOS bus switch IC according to one embodiment of the present invention. 10Ω, 2.5V 8Ω, 2.9V 7Ω, 3.3V 6Ω, 3.7V 5Ω, 4.3V 4Ω (see Non-Patent Document 8).
That is, when performing time-division bidirectional switching, the conduction resistance Rd at the ground potential SDI signal 0.8 Vp-p is changed from 10Ω to 7Ω by the NMOS bus switch, and the characteristic impedance Rz of the transmission line of the triax cable or coaxial cable = 5% or more with respect to 75Ω, the resistance value cannot be ignored, impedance mismatching occurs, and waveform distortion due to reflection occurs. Further, the change in resistance value of the SDI signal with an amplitude value of 0.8 Vp-p is a non-negligible change of about 4% with respect to 3Ω and 75Ω in the NMOS bus switch IC, and an asymmetrical waveform distortion occurs. Even if the equalizer equalizes the frequency characteristics such as amplifying the high-frequency component of the received signal on the receiving side and the 2970 Mbps 3G SDI signal is received, the waveform distortion and the upper and lower asymmetry are caused by the reflection of impedance mismatching. The phase change due to the waveform distortion remains and cannot be corrected. For this reason, it has been difficult to extend the length of the transmission cable.

改良された５Ｖ低容量バススイッチＩＣも製品化され、本発明の１実施例の低容量バススイッチＩＣの導通抵抗特性の模式図の図８Ｂのように、正電源電圧から１Ｖで６Ω、１．５Ｖで６．８Ω、２Ｖで５Ω、２．１Ｖで４．８Ω、２．５Ｖで４．３Ω、２．７Ｖから３．５Ｖで４．２Ω、３．９Ｖで４Ω、４．５Ｖで３．８Ωとなる（非特許文献９参照）。 An improved 5V low-capacity bus switch IC has also been commercialized, and as shown in FIG. 8B, which is a schematic diagram of the conduction resistance characteristics of the low-capacity bus switch IC of one embodiment of the present invention, 6Ω at 1V from the positive power supply voltage. 5V, 6.8Ω, 2V, 5Ω, 2.1V, 4.8Ω, 2.5V, 4.3Ω, 2.7V to 3.5V, 4.2Ω, 3.9V, 4Ω, 4.5V, 3. 8Ω (see Non-Patent Document 9).

特開平７−２０３３９９号公報Japanese Patent Laid-Open No. 7-203399 特開２０１０−０２１９９３号公報JP 2010-021993 A

ジェナム Security &Surveillance http://www.gennum.com/applications/security-surveillance/hdcctvJenham Security & Surveillance http://www.gennum.com/applications/security-surveillance/hdcctv ＡＲＩＢ−Ｂ０７ http://www.arib.or.jp/english/html/overview/doc/4-TR-B07v2_0.pdfARIB-B07 http://www.arib.or.jp/english/html/overview/doc/4-TR-B07v2_0.pdf テキサスインスツルメント製LMH0024 http://www.ti.com/lit/ds/symlink/lmh0024.pdfTexas Instruments LMH0024 http://www.ti.com/lit/ds/symlink/lmh0024.pdf テキサスインスツルメント製LMH0394 http://www.ti.com/lit/ds/symlink/lmh0394.pdfTexas Instruments LMH0394 http://www.ti.com/lit/ds/symlink/lmh0394.pdf ジェナム製GS2971A http://www.gennum.com/extranet/document/55977Gennum GS2971A http://www.gennum.com/extranet/document/55977 テキサスインスツルメント製LMH6703 http://www.ti.com/lit/ds/symlink/lmh6703.pdfTexas Instruments LMH6703 http://www.ti.com/lit/ds/symlink/lmh6703.pdf ＴＤＫ製mmz2012Equivalent Circuit http://www.tdk.co.jp/etvcl/equivalent/mmz2012.pdfTDK mmz2012Equivalent Circuit http://www.tdk.co.jp/etvcl/equivalent/mmz2012.pdf ルネサステクノロジ高速バススイッチ HD74CBTシリーズ http://hk.renesas.com/products/standard_ic/logic/hd74cbt/index.jspRenesas Technology High Speed Bus Switch HD74CBT Series http://hk.renesas.com/products/standard_ic/logic/hd74cbt/index.jsp 東芝５Ｖ低容量バススイッチ TC7SB66CFU, TC7SB67CFU http://www.semicon.toshiba.co.jp/docs/datasheet/en/LogicIC/TC7SB66CFU_TC7SB67CFU_en_datasheet_110401.pdfToshiba 5V Low Capacity Bus Switch TC7SB66CFU, TC7SB67CFU http://www.semicon.toshiba.co.jp/docs/datasheet/en/LogicIC/TC7SB66CFU_TC7SB67CFU_en_datasheet_110401.pdf

従来のトライアックスシステムのデジタル伝送では２７０Ｍｂｐｓ以上という高い周波数でのビットレートで伝送するため、ケーブルでの減衰量が大きくなってしまい、ケーブル長を延長することが困難であった。特に、時分割双方向切換を行う場合は、アナログ切換器の導通抵抗が、トライアックスケーブルまたは同軸ケーブルの伝送路の特性インピーダンスに対し、無視できない抵抗値となる。さらにＳＤＩ信号の振幅で抵抗値が変化をする。そのため、伝送ケーブル長を延長することが困難であった。 In the conventional digital transmission of the triax system, transmission is performed at a bit rate at a high frequency of 270 Mbps or more, so that the amount of attenuation in the cable increases and it is difficult to extend the cable length. In particular, when performing time-division bi-directional switching, the conduction resistance of the analog switch becomes a resistance value that cannot be ignored with respect to the characteristic impedance of the transmission line of the triax cable or coaxial cable. Further, the resistance value changes with the amplitude of the SDI signal. For this reason, it has been difficult to extend the length of the transmission cable.

本発明は、これらの欠点を除去し、時分割双方向切換のデジタル伝送でも長いケーブル長で運用できるトライアックスシステムを提供することを目的とする。 An object of the present invention is to eliminate these drawbacks and to provide a triax system that can be operated with a long cable length even in digital transmission with time-division bidirectional switching.

本発明は、上記の目的を達成するために、一つの伝送路を介して、デジタル化した映像信号、音声信号、制御信号を含むデジタル信号を時分割双方向切換送受するデジタル映像信号多重伝送装置において、前記伝送路の両側の終端に時分割多重を切換えるアナログ切換器のＩＣを有し、受信側に波形等化器または波形等化器を含む受信器を有し、前記デジタル化した映像信号、音声信号、制御信号を含むデジタル信号における前記アナログ切換器の導通抵抗の平均値が前記伝送路の特性インピーダンス抵抗Ｒｚの約１／１０以下でかつ、前記デジタル化した映像信号、音声信号、制御信号を含むデジタル信号における前記アナログ切換器の導通抵抗の変化が前記伝送路の特性インピーダンス抵抗Ｒｚの約１／３０以下、になるように、前記アナログ切換器の電源電圧の正電源Ｖｃｃを高く設定し、前記伝送路の前記伝送路の特性インピーダンス抵抗Ｒｚに対し、前記アナログ切換器の導通抵抗による終端抵抗の増加を補正する手段と、前記アナログ切換器の導通抵抗の変化による終端抵抗のずれによる信号波形の歪を補正する手段との少なくとも一方を有することを特徴とする映像信号多重伝送装置である。 In order to achieve the above object, the present invention provides a digital video signal multiplex transmission device for time-division bidirectional switching transmission / reception of digital signals including a digitized video signal, audio signal, and control signal via a single transmission line. And an analog switch IC for switching time division multiplexing at both ends of the transmission line, and a receiver including a waveform equalizer or a waveform equalizer on the receiving side, and the digitized video signal The average value of the conduction resistance of the analog switch in the digital signal including the audio signal and the control signal is about 1/10 or less of the characteristic impedance resistance Rz of the transmission line, and the digitized video signal, audio signal, and control The analog switch so that the change in the conduction resistance of the analog switch in the digital signal including the signal is about 1/30 or less of the characteristic impedance resistance Rz of the transmission line. Means for setting the positive power supply Vcc of the power supply voltage of the log switch high and correcting the increase in the termination resistance due to the conduction resistance of the analog switch with respect to the characteristic impedance resistance Rz of the transmission line of the transmission line; A video signal multiplex transmission apparatus comprising at least one of means for correcting distortion of a signal waveform due to a deviation of a termination resistance due to a change in conduction resistance of a switching device.

また、一つの伝送路を介して、デジタル化した映像信号、音声信号、制御信号を含むデジタル信号を時分割双方向切換送受するデジタル映像信号多重伝送装置において、前記伝送路の両側の終端に時分割多重を切換えるアナログ切換器のＮＭＯＳバススイッチＩＣを有し、受信側に波形等化器または波形等化器を含む受信器を有し、前記アナログ切換器のＮＭＯＳバススイッチＩＣの電源電圧の正電源Ｖｃｃを＋２．９Ｖ以上とし正電源Ｖｃｃと負電源Ｖｅｅの差Ｖａｂが４．５Ｖ以上５．５Ｖ以下とするか、または、前記伝送路の両側の終端に時分割多重を切換えるアナログ切換器の５Ｖ低容量バススイッチＩＣを有し、受信側に波形等化器または波形等化器を含む受信器を有し、前記アナログ切換器の５Ｖ低容量バススイッチＩＣの電源電圧の正電源Ｖｃｃを＋２．５Ｖ以上とし正電源Ｖｃｃと負電源Ｖｅｅの差Ｖａｂが４．５Ｖ以上５．５Ｖ以下とするかとし、前記伝送路の特性インピーダンス抵抗Ｒｚに対し、前記アナログ切換器の導通抵抗による終端抵抗の増加を補正する手段と、前記アナログ切換器の導通抵抗の変化による終端抵抗のずれによる信号波形の歪を補正する手段との少なくとも一方を有することを特徴とする映像信号多重伝送装置である。 Also, in a digital video signal multiplex transmission apparatus that transmits and receives digital signals including a digitized video signal, audio signal, and control signal via a single transmission line, time-division bidirectional switching is performed at both ends of the transmission line. An NMOS bus switch IC of an analog switch for switching division multiplexing is provided, a receiver including a waveform equalizer or a waveform equalizer on the receiving side, and the power supply voltage of the NMOS bus switch IC of the analog switch is positive. The power supply Vcc is +2.9 V or more and the difference Vab between the positive power supply Vcc and the negative power supply Vee is 4.5 V or more and 5.5 V or less, or an analog switch that switches time division multiplexing to both ends of the transmission line. A 5V low-capacity bus switch IC, a waveform equalizer on the receiving side or a receiver including a waveform equalizer, and a power supply for the 5V low-capacity bus switch IC of the analog switch Whether the positive power supply Vcc of the pressure is +2.5 V or more and the difference Vab between the positive power supply Vcc and the negative power supply Vee is 4.5 V or more and 5.5 V or less, and the analog switching device with respect to the characteristic impedance resistance Rz of the transmission line A video signal having at least one of a means for correcting an increase in termination resistance due to the conduction resistance of the analog signal and a means for correcting distortion of a signal waveform due to a deviation in termination resistance due to a change in the conduction resistance of the analog switch. Multiplex transmission device.

また、上記において、前記デジタル化した映像信号、音声信号、制御信号を含むデジタル信号における前記アナログ切換器のバススイッチＩＣの導通抵抗の変化が前記伝送路の特性インピーダンス抵抗Ｒｚの約１／１００以下になるように、前記アナログ切換器のバススイッチＩＣの電源電圧の正電源Ｖｃｃを設定した前記アナログ切換器のバススイッチＩＣと、前記伝送路の特性インピーダンス抵抗Ｒｚから前記アナログ切換器の導通抵抗の平均値Ｒｄ分低減した抵抗値Ｒｚ−Ｒｄの終端抵抗と、前記アナログ切換器の受信側の前記アナログ切換器の導通抵抗が低（く信号波形の圧縮されな）い信号波形極性を圧縮する接地されたショトキーバリアダイオードと抵抗の直列接続と、との少なくとも一方を有することを特徴とする映像信号多重伝送装置である。 In the above, the change in conduction resistance of the bus switch IC of the analog switch in the digital signal including the digitized video signal, audio signal, and control signal is about 1/100 or less of the characteristic impedance resistance Rz of the transmission line. The bus switch IC of the analog switch in which the positive power supply Vcc of the power supply voltage of the bus switch IC of the analog switch is set, and the conduction resistance of the analog switch from the characteristic impedance resistance Rz of the transmission line. The ground resistance compresses the signal waveform polarity when the terminating resistance of the resistance value Rz-Rd reduced by the average value Rd and the conduction resistance of the analog switch on the receiving side of the analog switch are low (the signal waveform is not compressed). A video signal having at least one of a Schottky barrier diode and a resistor connected in series. A transmission device.

上記映像信号多重伝送装置において、受信側の波形等化器または波形等化器を含む受信器の前に前記デジタル信号の波形を増幅する増幅器と、前記デジタル信号の波形を増幅する増幅器の（非反転増幅の負入力の接地抵抗または非反転増幅の正入力の接地抵抗または反転増幅の出力と反転極性の入力の入力抵抗または増幅器の出力抵抗または２段の増幅回路間の接続抵抗等の）回路特性抵抗に比較して、前記デジタル信号の波形のクロック基本波周波数におけるインピーダンスが低く、前記デジタル信号の波形のクロック高調波周波数におけるインピーダンスが高いインダクタと容量と抵抗との並列接続したものと抵抗との直列接続したものの近似の等価回路として表せるもの（以下インピーダンス体）を有し、前記波形等化器または波形等化器を含む受信器に入力する、前記デジタル信号の波形のクロック基本波周波数以下の低周波数成分を減衰し、前記デジタル信号の波形のクロック高調波成分を増強し、ショトキーバリアダイオードと抵抗とで、（前記アナログ切換器で圧縮されない）前記アナログ切換器で負方向の信号振幅を圧縮するか、または、前記アナログ切換器の５Ｖ低容量バススイッチＩＣの電源電圧を、正電源Ｖｃｃ約３．２Ｖで負電源Ｖｅｅを正電源Ｖｃｃと負電源Ｖｅｅの差Ｖａｂが４．５Ｖ以上５．５Ｖ以下と（して、伝送信号振幅０．８Ｖｐ−ｐでの切替器の導通抵抗の変化を少なく）するか、の少なくとも一方を行う事を特徴とする映像信号多重伝送装置である。
さらに、上記映像信号多重伝送装置において、送信側の前記アナログ切換器の前に前記デジタル信号の波形を増幅する増幅器と、前記インピーダンス体とを有し、送信側の前記アナログ切換器に入力する、前記デジタル信号の波形のクロック基本波周波数以下の低周波数成分を減衰し、前記デジタル信号の波形のクロック高調波成分を増強する事を特徴とする映像信号多重伝送装置である。
また、上記において、上記デジタル信号が（２５Ｍｂｐｓ、５０Ｍｂｐｓ、１００Ｍｂｐｓ、２７０Ｍｂｐｓ、１５００Ｍｂｐｓ、２９７０Ｍｂｐｓ等の）シリアルデジタルインタフェース（ＳＤＩ）信号であり、上記インピーダンス体がフェライトビーズまたは、フェライトビーズと抵抗または、インダクタと抵抗の少なくとも一つである事を特徴とする映像信号多重伝送装置である。 In the video signal multiplex transmission apparatus, an amplifier that amplifies the waveform of the digital signal and a non-amplifier that amplifies the waveform of the digital signal in front of a receiver-side waveform equalizer or a receiver including a waveform equalizer. Inverting amplification negative input ground resistance or non-inverting amplification positive input ground resistance or inverting amplification output and inverting polarity input resistance or amplifier output resistance or connection resistance between two stages of amplifier circuits) Compared to the characteristic resistance, the impedance at the clock fundamental frequency of the waveform of the digital signal is low, and the impedance at the clock harmonic frequency of the waveform of the digital signal is high. That can be expressed as an approximate equivalent circuit of those connected in series (hereinafter referred to as impedance body), the waveform equalizer or the waveform, etc. A low frequency component below the clock fundamental frequency of the digital signal waveform that is input to the receiver including the detector is attenuated, the clock harmonic component of the digital signal waveform is enhanced, and a Schottky barrier diode and a resistor The negative signal amplitude is compressed by the analog switch (not compressed by the analog switch) or the power supply voltage of the 5V low-capacity bus switch IC of the analog switch is set to a positive power supply Vcc of about 3.2 V. The negative power source Vee is set so that the difference Vab between the positive power source Vcc and the negative power source Vee is 4.5 V or more and 5.5 V or less (so that the change in the conduction resistance of the switch is small when the transmission signal amplitude is 0.8 Vp-p). Or a video signal multiplex transmission apparatus that performs at least one of the above.
Further, in the video signal multiplex transmission apparatus, the amplifier has an amplifier for amplifying the waveform of the digital signal before the analog switch on the transmission side, and the impedance body, and is input to the analog switch on the transmission side. The video signal multiplex transmission apparatus is characterized in that a low frequency component equal to or lower than a clock fundamental wave frequency of the waveform of the digital signal is attenuated to enhance a clock harmonic component of the waveform of the digital signal.
In the above, the digital signal is a serial digital interface (SDI) signal (such as 25 Mbps, 50 Mbps, 100 Mbps, 270 Mbps, 1500 Mbps, 2970 Mbps, etc.), and the impedance body is a ferrite bead, a ferrite bead and a resistor, or an inductor. The video signal multiplex transmission device is characterized in that it is at least one of resistors.

また、一つの伝送路を介して、デジタル化した映像信号、音声信号、制御信号を含むデジタル信号を時分割双方向切換送受するデジタル映像信号多重伝送装置において、前記伝送路の両側の終端に時分割多重を切換えるアナログ切換器のバススイッチＩＣを有し、受信側に波形等化器または波形等化器を含む受信器を有し、前記伝送路の前記伝送路の特性インピーダンス抵抗に対し、前記アナログ切換器のバススイッチＩＣの導通抵抗による終端抵抗の増加を補正する手段と、前記アナログ切換器のバススイッチＩＣの導通抵抗の変化による終端抵抗のずれによる信号波形の歪を補正する手段との少なくとも一方を有することを特徴とする映像信号多重伝送装置である。 Also, in a digital video signal multiplex transmission apparatus that transmits and receives digital signals including a digitized video signal, audio signal, and control signal via a single transmission line, time-division bidirectional switching is performed at both ends of the transmission line. A bus switch IC of an analog switch that switches division multiplexing, a receiver including a waveform equalizer or a waveform equalizer on the receiving side, and the characteristic impedance resistance of the transmission path of the transmission path, Means for correcting an increase in termination resistance due to the conduction resistance of the bus switch IC of the analog switch; and means for correcting distortion of the signal waveform due to a shift in termination resistance due to a change in the conduction resistance of the bus switch IC of the analog switch. A video signal multiplex transmission apparatus having at least one of them.

さらに、撮像素子と映像信号処理部とCPU(Central Processing Unit)を有する撮像部と、上記の映像信号多重伝送装置と、映像信号処理部と映像信号入出力部とCPUを有する制御部とを具備し、映像信号を時分割双方向多重伝送する事を特徴とする撮像装置である。 Furthermore, an image pickup unit having an image pickup device, a video signal processing unit, and a CPU (Central Processing Unit), the video signal multiplex transmission device, a video signal processing unit, a video signal input / output unit, and a control unit having a CPU are provided. The image pickup apparatus is characterized in that the video signal is time-division bidirectionally multiplexed.

以上説明したように本発明によれば、時分割双方向切換を行うアナログ切換器のＮＭＯＳバススイッチＩＣまたは５Ｖ低容量バススイッチＩＣの導通抵抗によるインピーダンスミスマッチングから発生する反射歪または、信号電圧による導通抵抗の変化による信号波形の非対称劣化を改善することができ、デジタル映像信号多重伝送装置のケーブル長を延ばすことができる。 As described above, according to the present invention, it is caused by reflection distortion generated by impedance mismatching due to conduction resistance of the NMOS bus switch IC or 5V low-capacitance bus switch IC of the analog switch that performs time-division bidirectional switching, or by the signal voltage. Asymmetry degradation of the signal waveform due to the change in conduction resistance can be improved, and the cable length of the digital video signal multiplex transmission apparatus can be extended.

本発明の一実施例の全体構成を示すブロック図The block diagram which shows the whole structure of one Example of this invention 従来の一実施例の全体構成を示すブロック図The block diagram which shows the whole structure of one conventional example 本発明の１実施例の反転増幅回路と切替器とのブロック図1 is a block diagram of an inverting amplifier circuit and a switch according to one embodiment of the present invention. 本発明の１実施例の非反転増幅回路と切替器とのブロック図1 is a block diagram of a non-inverting amplifier circuit and a switch according to one embodiment of the present invention. 本発明の１実施例の駆動回路と波形等化器または波形等化器を含む受信器と切替器とのブロック図1 is a block diagram of a drive circuit and a waveform equalizer or a receiver including a waveform equalizer and a switch according to an embodiment of the present invention. 本発明の１実施例の駆動回路と波形等化器または波形等化器を含む受信器と切替器とのブロック図1 is a block diagram of a drive circuit and a waveform equalizer or a receiver including a waveform equalizer and a switch according to an embodiment of the present invention. 本発明の１実施例の反転増幅回路と切替器とのブロック図1 is a block diagram of an inverting amplifier circuit and a switch according to one embodiment of the present invention. 本発明の１実施例の反転増幅回路と切替器とのブロック図1 is a block diagram of an inverting amplifier circuit and a switch according to one embodiment of the present invention. 本発明の１実施例の反転増幅回路の入出力波形図Input / output waveform diagram of inverting amplifier circuit of one embodiment of the present invention 本発明の１実施例の非反転増幅回路の入出力波形図Input / output waveform diagram of non-inverting amplifier circuit of one embodiment of the present invention 本発明の１実施例の駆動回路と波形等化器または波形等化器を含む受信器の入出力波形図I / O waveform diagram of receiver including drive circuit and waveform equalizer or waveform equalizer of one embodiment of the present invention 本発明の１実施例の駆動回路と波形等化器または波形等化器を含む受信器の入出力波形図I / O waveform diagram of receiver including drive circuit and waveform equalizer or waveform equalizer of one embodiment of the present invention 本発明の１実施例の反転増幅回路の入出力波形図Input / output waveform diagram of inverting amplifier circuit of one embodiment of the present invention 本発明の１実施例のフェライトビーズの周波数特性の模式図Schematic diagram of frequency characteristics of ferrite beads of one embodiment of the present invention 従来の駆動回路と波形等化器と切替器とのブロック図Block diagram of conventional drive circuit, waveform equalizer and switch 従来の駆動回路と波形等化器と切替器との入出力波形図Input / output waveform diagram of conventional drive circuit, waveform equalizer and switch 本発明の１実施例のＮＭＯＳバススイッチＩＣの導通抵抗特性の模式図The schematic diagram of the conduction resistance characteristic of NMOS bus switch IC of one Example of this invention 本発明の１実施例の低容量バススイッチＩＣの導通抵抗特性の模式図Schematic diagram of conduction resistance characteristics of low-capacity bus switch IC of one embodiment of the present invention

時分割双方向切換を行う場合は、背景技術の００１４段落のように、アナログ切換器の導通抵抗からインピーダンスミスマッチングが発生して反射による波形歪が発生する。さらにアナログ切換器の導通抵抗変化から、上下非対称の波形歪が発生する。そのため、受信側で受信信号の高周波数成分を増幅させる等の周波数特性補正や２９７０Ｍｂｐｓの３ＧのＳＤＩ信号受信用に改良された等化器（イコライザ）（非特許文献４参照）または波形等化器を含む受信器（レシーバ）（非特許文献５参照）での波形等化では、反射による波形歪や上下非対称の波形歪による位相変化は残ってしまい補正できない。そのため、インピーダンスミスマッチングの反射による波形歪やアナログ切換器の導通抵抗の変化により上下非対称の波形歪が発生すると、伝送ケーブル長を延長することが困難であった。 When time-division bidirectional switching is performed, impedance mismatching occurs from the conduction resistance of the analog switch as in paragraph 0014 of the background art, and waveform distortion due to reflection occurs. Furthermore, a waveform distortion that is asymmetrical in the vertical direction is generated from the change in the conduction resistance of the analog switch. For this reason, an equalizer (equalizer) (see Non-Patent Document 4) or a waveform equalizer improved for frequency characteristic correction such as amplifying a high frequency component of a received signal on the receiving side and for receiving a 2970 Mbps 3G SDI signal. In the waveform equalization in a receiver (receiver) including a non-patent document 5 (see Non-Patent Document 5), a waveform change due to reflection and a phase change due to an asymmetrical waveform distortion remain and cannot be corrected. For this reason, it is difficult to extend the length of the transmission cable when a waveform distortion due to impedance mismatching reflection or a waveform distortion asymmetrical due to a change in the conduction resistance of the analog switch occurs.

そこで、本発明では、ＳＤＩ信号０．８Ｖｐ−ｐにおけるアナログ切換器の導通抵抗によるインピーダンスミスマッチングを伝送路の特性インピーダンスＲｚ＝７５Ωの約１／５０以下に低減し、さらにアナログ切換器の導通抵抗変化をＲｚ＝７５Ωの約１／３０以下に低減するか補正する。
具体的には、一つの伝送路を介して、デジタル化した映像信号、音声信号、制御信号を含むデジタル信号を時分割双方向切換送受するデジタル映像信号多重伝送装置において、伝送路の両側の終端に時分割に双方向を切換えるアナログ切換器の非特許文献８のＮＭＯＳバススイッチＩＣを有し、受信側に波形等化器または波形等化器を含む受信器を有し、ＮＭＯＳバススイッチＩＣの電源電圧は、正電源Ｖｃｃを＋２．９Ｖ以上とし正電源Ｖｃｃと負電源Ｖｅｅの差Ｖａｂが４．５Ｖ以上５．５Ｖ以下とし、伝送するＳＤＩ信号の振幅０．８Ｖｐ−ｐ直流電位０Ｖの各電圧−０．４Ｖから＋０．４Ｖに対し、ＮＭＯＳバススイッチの導通抵抗が８Ωから６Ωと導通抵抗の変化を２Ωと伝送路の特性インピーダンス７５Ωに対し約２．７％と少なくする。または、ＮＭＯＳバススイッチＩＣが約３Ｖ以上の正電源を有し該正電源電圧より約２．５Ｖ以上低い（負の）電圧に前記ＮＭＯＳバススイッチＩＣを通過するデジタル信号をバイアスする。
そして、前記伝送路の特性インピーダンスＲｚ＝７５Ωに対し、ＮＭＯＳバススイッチＩＣの導通抵抗の平均値Ｒｄ約７Ω分低減したＲso＝Ｒｚ−Ｒｄ＝７５−７＝６８で６８Ωを終端抵抗値としてインピーダンスマッチングを取り、反射歪を低減する。 Therefore, in the present invention, the impedance mismatch due to the conduction resistance of the analog switch in the SDI signal 0.8 Vp-p is reduced to about 1/50 or less of the characteristic impedance Rz = 75Ω of the transmission line, and the conduction resistance of the analog switch is further reduced. Reduce or correct the change to about 1/30 or less of Rz = 75Ω.
Specifically, in a digital video signal multiplex transmission apparatus that transmits and receives a digital signal including a digitized video signal, audio signal, and control signal via a single transmission line, both ends of the transmission line are terminated. The NMOS bus switch IC of Non-Patent Document 8 of an analog switcher that switches bidirectionally in a time-sharing manner has a waveform equalizer or a receiver including a waveform equalizer on the receiving side, and the NMOS bus switch IC The power supply voltage is set such that the positive power supply Vcc is +2.9 V or more, the difference Vab between the positive power supply Vcc and the negative power supply Vee is 4.5 V or more and 5.5 V or less, and the amplitude of the transmitted SDI signal is 0.8 Vp-p DC potential 0 V With respect to the voltage -0.4V to + 0.4V, the conduction resistance of the NMOS bus switch is 8Ω to 6Ω, the change of the conduction resistance is 2Ω and about 2.7% of the characteristic impedance 75Ω of the transmission line is small. To. Alternatively, the NMOS bus switch IC has a positive power supply of about 3V or more, and biases the digital signal passing through the NMOS bus switch IC to a (negative) voltage lower than the positive power supply voltage by about 2.5V or more.
Then, with respect to the characteristic impedance Rz = 75Ω of the transmission line, impedance matching is performed with RΩ = Rz−Rd = 75−7 = 68 in which the average value Rd of the conduction resistance of the NMOS bus switch IC is reduced by about 7Ω and 68Ω as the termination resistance value. To reduce reflection distortion.

または、前記伝送路の両側の終端に時分割多重を切換えるアナログ切換器の非特許文献９の５Ｖ低容量バススイッチＩＣを有し、受信側に波形等化器または波形等化器を含む受信器を有し、５Ｖ低容量バススイッチＩＣの電源電圧は、正電源Ｖｃｃを＋２．５Ｖ以上とし正電源Ｖｃｃと負電源Ｖｅｅの差Ｖａｂが４．５Ｖ以上５．５Ｖ以下とするかとし、前記伝送路の特性インピーダンスＲｚ＝７５Ωに対し、５Ｖ低容量バススイッチＩＣの導通抵抗Ｒｄは４．８Ωから４．２Ωで平均値約４．５Ω分低減したＲso＝Ｒｚ−Ｒｄ＝７５−４．５＝７０．５≒７１≒６８＋２．７で６８Ωと２．７Ωの直列を終端抵抗値として平均誤差０．２Ω０．３％と誤差範囲以下の精度でインピーダンスマッチングを取り、反射歪を低減する。 Alternatively, a receiver including a 5 V low-capacity bus switch IC of Non-Patent Document 9 of an analog switcher that switches time-division multiplexing at both ends of the transmission line and including a waveform equalizer or a waveform equalizer on the receiving side The power supply voltage of the 5V low-capacity bus switch IC is such that the positive power supply Vcc is + 2.5V or more and the difference Vab between the positive power supply Vcc and the negative power supply Vee is 4.5V or more and 5.5V or less. The conduction resistance Rd of the 5V low-capacitance bus switch IC is reduced from 4.8Ω to 4.2Ω by an average value of about 4.5Ω with respect to the characteristic impedance Rz = 75Ω of the path Rso = Rz−Rd = 75−4.5 = When 70.5≈71≈68 + 2.7, a series resistance of 68Ω and 2.7Ω is used as the termination resistance value, and impedance matching is performed with an average error of 0.2Ω 0.3% and an accuracy within the error range to reduce reflection distortion.

出力終端抵抗とアナログ切換器の導通抵抗との合計値と、受信終端抵抗とアナログ切換器の導通抵抗との合計値と、トライアックスケーブルまたは同軸ケーブルの伝送路の特性インピーダンス抵抗７５Ωとがほぼ等しくなり、インピーダンスミスマッチングと反射による波形歪が低減する。さらにＳＤＩ信号の振幅値０．８Ｖｐ−ｐで抵抗値の変化が７５Ωに対しＮＭＯＳバススイッチＩＣで約２．７％と５Ｖ低容量バススイッチＩＣで約０．８％と低減し、上下非対称の波形歪が低減する。 The total value of the output termination resistance and the conduction resistance of the analog switch, the total value of the reception termination resistance and the conduction resistance of the analog switch, and the characteristic impedance resistance 75Ω of the transmission line of the triax cable or coaxial cable are substantially equal. Therefore, waveform distortion due to impedance mismatching and reflection is reduced. Furthermore, when the amplitude value of the SDI signal is 0.8 Vp-p, the change in resistance value is reduced to about 2.7% for the NMOS bus switch IC and about 0.8% for the 5 V low-capacity bus switch IC with respect to 75Ω, and is asymmetrical in the vertical direction. Waveform distortion is reduced.

ところで、本発明は、ＮＭＯＳバススイッチＩＣと５Ｖ低容量バススイッチＩＣに限定せず、導通抵抗が低く高速なアナログ切換器のＩＣが使用できる。ＳＤＩ信号の振幅値０．８Ｖｐ−ｐにおける前記アナログ切換器の導通抵抗の平均値が前記伝送路の特性インピーダンス抵抗Ｒｚの約１／１０以下でかつ、ＳＤＩ信号の振幅値０．８Ｖｐ−ｐにおける前記アナログ切換器の導通抵抗の変化が前記伝送路の特性インピーダンス抵抗Ｒｚの約１／３０以下、になるように、導通抵抗が低く高速なアナログ切換器のＩＣの導通抵抗の特性に基づいて、正電源Ｖｃｃと負電源Ｖｅｅの値と、出力終端抵抗と受信終端抵抗の値と、前記アナログ切換器の電源電圧の正電源Ｖｃｃを高く設定する。その結果、ＳＤＩ信号０．８Ｖｐ−ｐにおけるアナログ切換器の導通抵抗によるインピーダンスミスマッチングを低減し、さらにアナログ切換器の導通抵抗変化を低減する。 By the way, the present invention is not limited to the NMOS bus switch IC and the 5V low-capacity bus switch IC, and an analog switch IC having a low conduction resistance and a high speed can be used. The average value of the conduction resistance of the analog switch at the amplitude value 0.8 Vp-p of the SDI signal is about 1/10 or less of the characteristic impedance resistance Rz of the transmission line, and the amplitude value of the SDI signal is 0.8 Vp-p. Based on the characteristic of the conduction resistance of the analog switch IC having a low conduction resistance and high speed so that the change of the conduction resistance of the analog switch is about 1/30 or less of the characteristic impedance resistance Rz of the transmission line, The positive power supply Vcc and the negative power supply Vee, the output termination resistance and the reception termination resistance, and the positive power supply Vcc of the power supply voltage of the analog switch are set high. As a result, impedance mismatching due to the conduction resistance of the analog switch in the SDI signal 0.8 Vp-p is reduced, and further, the change in conduction resistance of the analog switch is reduced.

さらに、受信側の前記アナログ切換器の導通抵抗が低く信号波形の圧縮されない信号波形極性を圧縮する接地されたショトキーバリアダイオードと抵抗の直列接続とを有して、切替器で圧縮されない方を圧縮し、信号波形の上下のバランスをとる。
または、非特許文献９の５Ｖ低容量バススイッチＩＣの導通抵抗Ｒｄは、正電源電圧から２．７Ｖから３．５Ｖで４．２Ωと一定であることを利用し、５Ｖ低容量バススイッチを用いて、さらに正電源Ｖｃｃ＋３．２ＶでＶｅｅ−１．３Ｖから−２．３Ｖとすれば、接地電位のＳＤＩ信号の０．８Ｖｐ−ｐでの導通抵抗Ｒｄは４．２Ω一定で、抵抗値の変化がなくなり、上下非対称の波形歪がなくなる。 In addition, the analog switching device on the receiving side has a low conduction resistance and a signal waveform polarity that is not compressed and has a grounded Schottky barrier diode that compresses the signal waveform polarity and a series connection of resistors, and is not compressed by the switching device. Compress and balance the signal waveform up and down.
Alternatively, the conduction resistance Rd of the 5V low-capacity bus switch IC of Non-Patent Document 9 is fixed to 4.2Ω from the positive power supply voltage to 2.7V to 3.5V, and a 5V low-capacity bus switch is used. Further, when the positive power source Vcc + 3.2V is changed from Vee-1.3V to -2.3V, the conduction resistance Rd at 0.8Vp-p of the SDI signal at the ground potential is constant at 4.2Ω, and the resistance value changes. This eliminates the asymmetrical waveform distortion.

その結果、受信側において、ＳＤＩ信号の受信用のイコライザ（等化）ＩＣまたは波形等化器を含む受信器ＩＣで送信時の波形に戻す波形等化によるＳＤＩ信号の補正が容易となる。そのため、波形等化による劣化を最小限にする事が可能なるため、長いケーブルに応じた波形等化が可能となる。ケーブル２はトライアックスケーブルだけでなく、通常の同軸ケーブルでも従来より長いケーブルが伝送可能となる。さらに、ケーブル内の伝送波形とは独立に信号劣化を補正するので、中継ケーブルの挿入によるケーブル長の変更に容易に対応し、トライアックスケーブルだけでなく、通常の同軸ケーブルでも従来より長いケーブルが補正可能となる。また、２９７０Ｍｂｐｓの３ＧのＳＤＩ信号受信用に改良された等化器または波形等化器を含む受信器で波形等化が有効となり、より長いケーブルが補正可能となる。
さらに、１５００ＭｂｐｓのＨＤ−ＳＤＩ信号、２９７０Ｍｂｐｓの３ＧのＳＤＩ信号、約２４０００ＭｂｐｓのＵＨＤＴＶ用のＳＤＩ信号の伝送でも、トライアックスケーブルや通常の同軸ケーブルでも従来より長いケーブルが伝送可能となる。 As a result, on the receiving side, the SDI signal can be easily corrected by waveform equalization that is returned to the waveform at the time of transmission by the receiver IC including the equalizer (equalization) IC for receiving the SDI signal or the waveform equalizer. For this reason, deterioration due to waveform equalization can be minimized, so that waveform equalization corresponding to a long cable can be achieved. The cable 2 can transmit not only a triax cable but also a normal coaxial cable, which is longer than the conventional cable. Furthermore, since signal degradation is corrected independently of the transmission waveform in the cable, it is easy to adapt to cable length changes due to the insertion of relay cables, and not only triax cables but also ordinary coaxial cables can be longer than conventional cables. Correction can be made. In addition, waveform equalization is effective in a receiver including an equalizer or a waveform equalizer improved for receiving a 2970 Mbps 3G SDI signal, and a longer cable can be corrected.
In addition, transmission of 1500 Mbps HD-SDI signals, 2970 Mbps 3G SDI signals, and about 24000 Mbps UHDTV SDI signals, triax cables and ordinary coaxial cables can be transmitted.

以下、本発明の一実施例のトライアックスカメラシステムの全体を図１で説明してから、本発明の１実施例の反転増幅回路と非反転増幅回路のブロック図と入出力波形図と動作の模式図とを図３Ａ〜図３Ｃ、図４Ａ〜図４Ｃを用いて説明する。 Hereinafter, the entire triax camera system of one embodiment of the present invention will be described with reference to FIG. 1, and then the block diagram, input / output waveform diagram and operation of the inverting amplifier circuit and non-inverting amplifier circuit of one embodiment of the present invention will be described. The schematic diagrams will be described with reference to FIGS. 3A to 3C and FIGS. 4A to 4C.

図１は、本発明の一実施例のトライアックスカメラシステムの全体を示すブロック図であり、撮像部１とトライアックスケーブル２と制御部３で構成している。１０１は図示していない入射光を結像するためのレンズ部、１０２はレンズ部１０１で結像した光を光電変換する撮像素子、１０３は映像信号をデジタル映像信号に変換するA/Dコンバータ、１０４と１２７とはデジタル映像信号を所定のレベルに増幅する事や輪郭強調等の処理を施す映像処理部である。１０５と１３６とは映像の圧縮を行う映像圧縮部で、１０７と１３５とはデジタル映像信号とデジタル音声信号と制御信号（CPUデータ）とを多重化するENCODE部、１０８と１３３とはデジタル信号を増幅する増幅部で、１０９と１３４とはトライアックスケーブル２の周波数特性分を補正する増幅部で受信側の波形等化器または波形等化器を含む受信器の前にある。この増幅部の切換はケーブル２の長さに応じて撮像部１または制御部３のＣＰＵの１１３と１３０とからの制御により、増幅部がシャットダウン機能を有する増幅器や切り替え機能を有する増幅器や低インピーダンスの切換ＩＣで構成されていれば、増幅部１０８と１０９と１３３と１３４とで行う。双方向部１１２と１２１とが時分割多重のアナログ切換器であり、１０８と１０９と１３３と１３４との増幅部が、長いケーブル用と短いケーブル用と各２組ある場合は、双方向部１１２と１２１とで切換えても良い。１１３と１３０とは制御するためのCPU(Central Processing Unit)、１２０は撮像部１とトライアックスケーブル２とをつなぐ接栓で１４２はトライアックスケーブル２と制御部３をつなぐ接栓、１１２は撮像部１で生成された映像信号と制御部３より伝送されてきた外部映像信号の時分割切換を行う双方向部、１２１とは外部映像信号と撮像部１より伝送されてきた映像信号の切換を行う切換部、１１９と１２２とは伝送されてきた信号の波形等化を行う波形等化器または波形等化器を含む受信器、１１６と１２５とはもとのデジタル映像信号とデジタル音声信号とに復調するDECODE部、１１５と１２６とは映像の伸長を行う映像伸長部、１１４と１２８とはデジタル映像信号をアナログ映像信号に変換するＤ／Ａコンバータ（ＤＡＣ）、１３８は増幅器である。 FIG. 1 is a block diagram showing the entire triax camera system according to an embodiment of the present invention, which includes an imaging unit 1, a triax cable 2, and a control unit 3. 101 is a lens unit for imaging incident light (not shown), 102 is an image sensor that photoelectrically converts light imaged by the lens unit 101, 103 is an A / D converter that converts a video signal into a digital video signal, Reference numerals 104 and 127 denote video processing units that amplify the digital video signal to a predetermined level and perform processing such as contour enhancement. Reference numerals 105 and 136 denote video compression units that compress video, 107 and 135 denote ENCODE units that multiplex digital video signals, digital audio signals, and control signals (CPU data), and 108 and 133 denote digital signals. The amplifying units 109 and 134 are the amplifying units for correcting the frequency characteristic of the triax cable 2 and are located in front of the receiver-side waveform equalizer or the receiver including the waveform equalizer. The switching of the amplification unit is controlled by the CPU 113 and 130 of the imaging unit 1 or the control unit 3 according to the length of the cable 2, and the amplification unit has an amplifier having a shutdown function, an amplifier having a switching function, or a low impedance. If the switching IC is configured, the amplifying units 108, 109, 133, and 134 are used. When the bidirectional units 112 and 121 are time-division multiplexed analog switches, and there are two sets of amplifying units 108, 109, 133, and 134, one for long cables and one for short cables, the bidirectional unit 112 And 121 may be switched. 113 and 130 are CPUs (Central Processing Units) for control, 120 is a plug connecting the imaging unit 1 and the triax cable 2, 142 is a plug connecting the triax cable 2 and the control unit 3, and 112 is imaging. The bidirectional unit 121 performs time-division switching between the video signal generated by the unit 1 and the external video signal transmitted from the control unit 3, and 121 switches the external video signal and the video signal transmitted from the imaging unit 1. Switching unit 119 and 122 are a waveform equalizer for performing waveform equalization of a transmitted signal or a receiver including a waveform equalizer, 116 and 125 are original digital video signals and digital audio signals DECODE unit for demodulating, 115 and 126 for video decompression unit for video decompression, 114 and 128 for D / A converter (DAC) for converting digital video signal to analog video signal, 138 for amplification It is a vessel.

次に本発明の一実施例の動作について説明する。
電源投入時に撮像部１のＣＰＵの１１３または制御部３のＣＰＵの１３０でケーブル２の遅延量または減衰量を測定する事によりケーブル２の長さを検出する。検出したケーブル２の長さは撮像部１または制御部３のＣＰＵに伝送し、ケーブル２の長さは撮像部１と制御部３とで共用する。 Next, the operation of one embodiment of the present invention will be described.
When the power is turned on, the length of the cable 2 is detected by measuring the delay amount or attenuation amount of the cable 2 by the CPU 113 of the imaging unit 1 or the CPU 130 of the control unit 3. The detected length of the cable 2 is transmitted to the CPU of the imaging unit 1 or the control unit 3, and the length of the cable 2 is shared by the imaging unit 1 and the control unit 3.

背景技術の非特許文献１の様に、映像シリアルデジタルインタフェース（ＳＤＩ）信号はＧ（ｘ）＝（ｘ⁹ ＋ｘ⁴ ＋１）（ｘ＋１）という生成多項式による自己同期型スクランブルド（ＮｏｎＲｅｔｕｒｎＴｏＺｅｒｏ）ＮＲＺ−Ｉ符号を採用し、データの０／１を０→１，１→０の反転情報に置き換えることによって、極性フリーでスペクトルが均一に分布したＳＤＩ信号を実現している。こうした自己同期型スクランブルを掛けると、シリアル伝送路上に、１水平ラインに亘り、１ビットの１に続いて１９ビットの０が続くパターン（あるいはその反転パターン）の信号や、２０ビットの１が連続した後２０ビットの０が連続するパターン（あるいはその反転パターン）の信号が発生する場合がある。これらのパターンは、パソロジカルパターンと呼ばれている。したがって、パソロジカルパターンの最大長２０からＳＤＩ信号の基本クロック周波数の１／２０から３倍の高調波周波数を伝送すれば、誤りなくＳＤＩ信号を伝送できる。ＳＤＩ信号の生成にパソロジカルパターンの最大長をより短くする自己同期型スクランブルド符号を用いれば周波数帯域をさらに狭くできる。 As in Non-Patent Document 1 of the background art, the video serial digital interface (SDI) signal is self-synchronized scrambled by a generator polynomial of G (x) = (x ⁹ + x ⁴ +1) (x + 1) (Non Return To Zero) By adopting the NRZ-I code and replacing 0/1 of the data with inversion information of 0 → 1, 1 → 0, a polarity-free SDI signal with a uniformly distributed spectrum is realized. When such a self-synchronization type scramble is applied, a signal of a pattern (or its inverted pattern) in which a 19-bit zero follows a 1-bit 1 followed by a 1-bit 1 on a serial transmission line, or a 20-bit 1 continues. After that, a signal of a pattern in which 20 bits of 0s continue (or its inverted pattern) may be generated. These patterns are called pathological patterns. Therefore, if the harmonic frequency of 1/20 to 3 times the basic clock frequency of the SDI signal is transmitted from the maximum length 20 of the pathological pattern, the SDI signal can be transmitted without error. If a self-synchronized scrambled code that shortens the maximum length of the pathological pattern is used to generate the SDI signal, the frequency band can be further narrowed.

ここで、撮像部で生成された順方向のＳＤＩ信号はＮＴＳＣで２７０Ｍｂｐｓ、ＨＤＴＶで１５００Ｍｂｐｓのデータ量がある。３ＧのＳＤＩ信号は２９７０Ｍｂｐｓのデータ量がある。ＵＨＤＴＶ用のＳＤＩ信号は２４０００Ｍｂｐｓのデータ量が予想される。また、制御部より撮像部に送り返し伝送される送り返しの映像信号はＭＰＥＧ２で圧縮すると映像圧縮比がおおよそ１／５となり、順方向のＳＤＩ信号と圧縮した送り返しＳＤＩ信号の時分割切換または周波数選別を行う双方向部は時分割のアナログ切換器のＩＣが好ましい。Ｈ．２６４で圧縮すると撮像部で生成された順方向のＳＤＩ信号の１５００Ｍｂｐｓに対し送り返し方向の映像圧縮されたＳＤＩ信号の２５Ｍｂｐｓと映像圧縮比が１／６０と、パソロジカルパターンの最大長２０と高調波次数３との積６０倍の逆数の１／６０以下も可能となる。音声信号，制御信号（ＣＰＵデータ信号）をＳＤＩ信号に重畳してあるので、順方向のＳＤＩ信号と圧縮した送り返しＳＤＩ信号の時分割切換または周波数選別を行う双方向部は、順方向のＳＤＩ信号を高域通過フィルタ（ＨＰＦ）で通過させ、送り返し方向の映像圧縮されたＳＤＩ信号を低域通過フィルタ（ＬＰＦ）で通過させ、順方向のＳＤＩ信号と送り返し方向の映像圧縮されたＳＤＩ信号とを双方向伝送させる組み合わせでも良い。
また、制御部３から入力し撮像部１に送り返えされて撮像部１から出力する外部デジタル映像信号も上記と同様に伝送される。図１では、送り返し方向の映像圧縮は映像圧縮部１３６で圧縮されているが、圧縮された外部デジタル映像信号を入力しても良い。 Here, the forward SDI signal generated by the imaging unit has a data amount of 270 Mbps for NTSC and 1500 Mbps for HDTV. The 3G SDI signal has a data amount of 2970 Mbps. A data amount of 24000 Mbps is expected for the SDI signal for UHDTV. In addition, when the video signal sent back and transmitted from the control unit to the imaging unit is compressed by MPEG2, the video compression ratio becomes approximately 1/5, and time-division switching or frequency selection between the forward SDI signal and the compressed return SDI signal is performed. The bidirectional section to be performed is preferably a time-division analog switch IC. H. When compressed by H.264, the SDI signal compressed in the send-back direction is 25 Mbps, the video compression ratio is 1/60, the maximum length of the pathological pattern is 20 and the harmonics compared to 1500 Mbps of the forward SDI signal generated by the imaging unit. 1/60 or less of the reciprocal of 60 times the product of order 3 is also possible. Since the audio signal and the control signal (CPU data signal) are superimposed on the SDI signal, the bidirectional unit that performs time division switching or frequency selection between the forward SDI signal and the compressed return SDI signal is the forward SDI signal. Is passed through a high-pass filter (HPF), the video compressed SDI signal in the return direction is passed through the low-pass filter (LPF), and the forward SDI signal and the video compressed SDI signal in the return direction are A combination of bidirectional transmission may be used.
Further, an external digital video signal that is input from the control unit 3, sent back to the imaging unit 1, and output from the imaging unit 1 is also transmitted in the same manner as described above. In FIG. 1, the video compression in the return direction is compressed by the video compression unit 136, but a compressed external digital video signal may be input.

撮像部１の撮像素子１０２は、レンズ部１０１で結像された入射光を光電変換してデジタル映像信号処理部１０４に出力する。デジタル映像信号処理部１０４は、映像信号のレベル増幅や輪郭強調等の処理を施し出力する。映像圧縮部１０５で、ＨＤＴＶのＳＤＩ信号と３ＧのＳＤＩ信号の場合は低遅延の映像圧縮を行い、ＵＨＤＴＶ用のＳＤＩ信号の場合はＨ．２６４等の高圧縮比の映像圧縮を行い、ＳＤＩ信号を２７０Ｍｂｐｓに圧縮し、ＮＴＳＣのＳＤＩ信号の２７０ＭｂｐｓはそのままENCODE部１０７に出力される。ENCODE部１０７では、デジタル映像信号とデジタル音声信号とCPUデータとを多重化される。多重化された信号は、ケーブル２が長い場合には、増幅部１０８と１０９とにより増強される。短い場合には、一定の低増幅率とする。撮像部１より出力された補正デジタル信号波形は、ケーブル２を介して制御部３に伝送される。 The imaging element 102 of the imaging unit 1 photoelectrically converts incident light imaged by the lens unit 101 and outputs the converted light to the digital video signal processing unit 104. The digital video signal processing unit 104 performs processing such as level amplification and edge enhancement of the video signal and outputs the result. The video compression unit 105 performs low-delay video compression for HDTV SDI signals and 3G SDI signals, and H.264 for UHDTV SDI signals. Video compression with a high compression ratio such as H.264 is performed, the SDI signal is compressed to 270 Mbps, and the 270 Mbps of the NTSC SDI signal is output to the ENCODE unit 107 as it is. The ENCODE unit 107 multiplexes the digital video signal, digital audio signal, and CPU data. The multiplexed signal is enhanced by the amplifying units 108 and 109 when the cable 2 is long. If it is short, a constant low amplification factor is used. The corrected digital signal waveform output from the imaging unit 1 is transmitted to the control unit 3 via the cable 2.

上記は２７０ＭｂｐｓのＮＴＳＣの４：２：２映像信号の伝送について説明したが、ＨＤＴＶの映像信号のＨＤ−ＳＤＩの１５００Ｍｂｐｓ（４：２：２）や３０００Ｍｂｐｓ（４：４：４）やＳＨＤＴＶや２４０００Ｍｂｐｓのデータ量が予想されるＵＨＤＴＶのＳＤＩについても、Ａ／Ｄコンバータ、Ｄ／Ａコンバータ、増幅器、波形等化器または波形等化器を含む受信器、バススイッチＩＣ等が高速化すれば、適用可能となる。 The above describes the transmission of 270 Mbps NTSC 4: 2: 2 video signals, but HDTV video signal HD-SDI 1500 Mbps (4: 2: 2), 3000 Mbps (4: 4: 4), SHDTV and 24000 Mbps. UHDTV SDI, which is expected to have a large amount of data, can be applied if the speed of A / D converters, D / A converters, amplifiers, waveform equalizers, receivers including waveform equalizers, bus switch ICs, etc. is increased. It becomes possible.

さらに、撮像素子と映像信号処理部とCPU(Central Processing Unit)を有する撮像部（Camera Head）と、映像信号多重伝送部（Camera Adaptor）と、映像信号処理部と映像信号入出力部とCPUを有する制御部（Camera Control Unit）とを具備すれば、運動施設やホールの内部に光ケーブルを敷設し直すことなく、運動施設やホールに既に敷設されているトライアックスケーブルを用いて、映像信号を時分割双方向多重伝送し、運動施設やホールの外部の有線（光ファイバー網）または無線（Field Pick Up）の映像信号伝送手段で放送局に伝送するか録画するいわゆる放送中継が可能な撮像装置（テレビカメラ）が実現できる。 Furthermore, an image pickup unit (Camera Head) having an image pickup device, a video signal processing unit, and a CPU (Central Processing Unit), a video signal multiplex transmission unit (Camera Adapter), a video signal processing unit, a video signal input / output unit, and a CPU are provided. If you have a control unit (Camera Control Unit), you can use the triax cable already laid in the exercise facility or hall without re-laying the optical cable inside the exercise facility or hall. An imaging device capable of so-called broadcast relaying (TV) which transmits to a broadcast station or records video signals by means of wired (optical fiber network) or wireless (Field Pick Up) video outside a sports facility or hall. Camera).

背景技術で説明したように、電流帰還演算増幅器は小振幅で増幅度２倍なら１．２ＧＨｚ程度までの高周波数を増幅できる。しかし、電流帰還演算増幅器内部の増幅トランジスタのエミッタが負入力端子に接続されており、負帰還入力端子の接続インピーダンスは高周波数成分が抵抗成分でないと、高周波数で発振を起こしやすい。そのため、電流帰還演算増幅器の負帰還入力端子を容量で接地するのではなく、本発明の１実施例のフェライトビーズの周波数特性の模式図の図５の様な、おおよそ２５ＭＨｚまたは２７０ＭＨｚまたは１５００ＭＨｚまたは３０００ＭＨｚのクロック基本波周波数Ｆｃにおけるインピーダンス（抵抗）分が前記電流帰還演算増幅器の非反転増幅の負入力の接地抵抗または反転増幅の負入力の入力抵抗より低く、クロック高調波周波数におけるインピーダンス（抵抗）分が非反転増幅の負入力の接地抵抗または反転増幅の負入力の入力抵抗より高いフェライトビーズを電流帰還演算増幅器の出力と電流帰還演算増幅器の負入力間に設け、伝送信号の低周波数成分を減衰し高周波数成分を増強する。高周波数の出力インピーダンスが上昇してしまう場合は、電流バッファＩＣを追加する。 As described in the background art, the current feedback operational amplifier can amplify a high frequency up to about 1.2 GHz if the amplitude is small and the amplification degree is doubled. However, the emitter of the amplification transistor inside the current feedback operational amplifier is connected to the negative input terminal, and the connection impedance of the negative feedback input terminal is likely to oscillate at a high frequency unless the high frequency component is a resistance component. Therefore, the negative feedback input terminal of the current feedback operational amplifier is not grounded with a capacitor, but is approximately 25 MHz, 270 MHz, 1500 MHz, or 3000 MHz as shown in FIG. 5 of the schematic diagram of the frequency characteristics of the ferrite bead of one embodiment of the present invention. The impedance (resistance) component at the clock fundamental frequency Fc of the current feedback operational amplifier is lower than the ground resistance of the negative input of the non-inverting amplification or the input resistance of the negative input of the inverting amplification, and the impedance (resistance) component at the clock harmonic frequency. A ferrite bead is installed between the output of the current feedback operational amplifier and the negative input of the current feedback operational amplifier to attenuate the low-frequency component of the transmission signal. The high frequency component is enhanced. If the high frequency output impedance is increased, a current buffer IC is added.

さらに、波形等化器または波形等化器を含む受信器（以下波形等化器）の入力振幅に余裕がない場合は、伝送路（トライアックスケーブルまたは同軸ケーブル）が長く伝送路の損失が大きいときのみ、増幅度を高くし、伝送路が短く伝送路の損失が小さいときは増幅度を０ｄＢ（特性整合損失を除けば＋６ｄＢ）付近にする。 Furthermore, when there is no margin in the input amplitude of the waveform equalizer or the receiver including the waveform equalizer (hereinafter referred to as the waveform equalizer), the transmission line (triax cable or coaxial cable) is long and the loss of the transmission line is large. Only when the gain is increased, and when the transmission path is short and the loss of the transmission path is small, the gain is set to around 0 dB (+6 dB excluding characteristic matching loss).

制御部３に伝送されたデジタル信号波形は、ケーブル２が長い場合には、増幅部１０９とで基本波周波数以下の低周波数成分を減衰させ３次以上の高調波成分を増強してから波形等化器１２２で波形等化が行われ、その後DECODE部１２５によりもとのデジタル映像信号とデジタル音声信号とに復調し、映像伸縮部１２６で映像伸縮を行い、デジタル信号処理部１２７で信号処理後、Ｄ／Ａコンバータ１２８でアナログ映像信号に変換され増幅器１３８から出力する。又、DECODE部１２５からは、CPUデータ、音声データも再生される。増幅部の１０８と１０９と波形等化器の１１９と１２２との性能が向上し１５００Ｍｂｐｓ等の高いデータ量が伝送できる場合は、映像圧縮部１０５の圧縮比を下げてより低遅延とする。低遅延で高圧縮比の映像圧縮が可能となれば、映像圧縮部１０５の出力ＳＤＩ信号を２５Ｍｂｐｓ、５０Ｍｂｐｓ等の１００Ｍｂｐｓ以下に圧縮し、本発明の１実施例のフェライトビーズの周波数特性の模式図の図５の（ｃ）の様な低い周波数でインピーダンスが変化するフェライトビーズで、ＳＤＩ信号のクロック基本波周波数以下の低周波数成分を減衰させ、高調波成分を増強する。 When the cable 2 is long, the digital signal waveform transmitted to the control unit 3 attenuates the low frequency component below the fundamental frequency and amplifies the third and higher harmonic components with the amplification unit 109, and then the waveform, etc. Waveform equalization is performed by the equalizer 122, then the original digital video signal and digital audio signal are demodulated by the DECODE unit 125, the video expansion / contraction unit 126 performs video expansion / contraction, and the digital signal processing unit 127 performs signal processing. The analog video signal is converted by the D / A converter 128 and output from the amplifier 138. The DECODE unit 125 also reproduces CPU data and audio data. When the performances of the amplifiers 108 and 109 and the waveform equalizers 119 and 122 are improved and a high data amount such as 1500 Mbps can be transmitted, the compression ratio of the video compression unit 105 is lowered to lower the delay. If video compression with a low delay and a high compression ratio becomes possible, the output SDI signal of the video compression unit 105 is compressed to 100 Mbps or less such as 25 Mbps or 50 Mbps, and the schematic diagram of the frequency characteristics of the ferrite beads of one embodiment of the present invention The ferrite bead whose impedance changes at a low frequency as shown in FIG. 5C attenuates the low frequency component below the clock fundamental frequency of the SDI signal and enhances the harmonic component.

双方向部１１２と１２１とはＨＰＦとＬＰＦとで構成されており双方向部１１２と１２１とは時分割のアナログ切換器のＮＭＯＳバススイッチＩＣまたは５Ｖ低容量バススイッチである。通過信号振幅に余裕がない場合は、ケーブル２の長さが長い場合に送信側では増幅度を３次高調波までの周波数で一定としてオーバーシュートを防止して振幅を制限し、受信側で基本波周波数以下の低周波数成分を減衰させ３次以上の高調波成分を増強する。
以下、説明を簡易化するため、広帯域で一般的な電流帰還演算増幅器で説明する。広帯域な電圧帰還演算増幅器を用いても良い。 The bidirectional units 112 and 121 are constituted by HPF and LPF, and the bidirectional units 112 and 121 are NMOS bus switch ICs or 5V low-capacity bus switches of time-division analog switches. If there is no margin in the amplitude of the passing signal, when the length of the cable 2 is long, on the transmission side, the amplification level is constant at the frequency up to the third harmonic to prevent overshoot and limit the amplitude. The low frequency component below the wave frequency is attenuated and the third and higher harmonic components are enhanced.
Hereinafter, in order to simplify the description, a general current feedback operational amplifier in a wide band will be described. A broadband voltage feedback operational amplifier may be used.

図３Ａは本発明の１実施例の反転増幅回路のブロック図であり、図３Ｂは本発明の１実施例の非反転増幅回路のブロック図であり、図４Ａは本発明の１実施例の反転増幅回路の入出力波形図であり、図４Ｂは本発明の１実施例の非反転増幅回路の入出力波形図であり、図５は、本発明の１実施例のフェライトビーズの周波数特性の模式図である。本発明に用いるインピーダンス体は、図５のフェライトビーズの周波数特性例をしめす模式図のようなフェライトビーズまたは、図５と同様な周波数特性例をしめすインダクタと容量の並列接続と抵抗である。 3A is a block diagram of an inverting amplifier circuit according to one embodiment of the present invention, FIG. 3B is a block diagram of a non-inverting amplifier circuit according to one embodiment of the present invention, and FIG. 4A is an inverting circuit according to one embodiment of the present invention. FIG. 4B is an input / output waveform diagram of a non-inverting amplifier circuit according to an embodiment of the present invention, and FIG. 5 is a schematic diagram of frequency characteristics of a ferrite bead according to an embodiment of the present invention. FIG. The impedance body used in the present invention is a ferrite bead as shown in a schematic diagram showing an example of the frequency characteristic of the ferrite bead in FIG. 5 or a parallel connection and a resistor of an inductor and a capacitor showing an example of the frequency characteristic similar to that in FIG.

図３Ａと図３Ｂとは反転＋６ｄBや非反転＋１２ｄBで帯域３Ｆｃが確保できる電流帰還演算増幅器または電流帰還演算増幅器と電流バッファＩＣのＩＣ１を用いた場合である。背景技術で説明した様に電流帰還演算増幅器は０．２Ｖｐ−ｐの小振幅で０ｄＢなら１．８ＧＨｚ程度、＋６ｄＢなら１．２ＧＨｚ程度までの高周波数を増幅でき、２Ｖｐ−ｐの大振幅なら７５０ＭＨｚ程度までの高周波数を増幅できる。そのため、高周波数増幅に余裕ができるので、フェライトビーズの周波数特性のインピーダンス変化がより大きくなれば、より長いケーブルが補正できる。 FIG. 3A and FIG. 3B show the case where the current feedback operational amplifier or the current feedback operational amplifier IC1 of the current buffer IC that can secure the band 3Fc with inversion +6 dB or non-inversion +12 dB is used. As described in the background art, the current feedback operational amplifier can amplify a high frequency up to about 1.8 GHz at 0 dB with a small amplitude of 0.2 Vp-p and about 1.2 GHz at +6 dB, and 750 MHz at a large amplitude of 2 Vp-p. High frequency up to about can be amplified. Therefore, since there is room for high frequency amplification, a longer cable can be corrected if the impedance change of the frequency characteristic of the ferrite bead becomes larger.

図３Ａ〜図３Ｆにおいて、ＩＣ２、ＩＣ５〜ＩＣ１４はＮＭＯＳバススイッチＩＣであり、Ｄ１０，Ｄ１１はショトキーバリアダイオード（以下ＳＢＤ）、Ｚ１、Ｚ２，Ｚ５〜Ｚ２４は図５の周波数特性の模式図のようなフェライトビーズであり、Ｃ１〜Ｃ１４とＣｏは容量であり、Ｒｏは出力抵抗、Ｒsoは出力終端抵抗、Ｒ１〜Ｒ７，Ｒ１１，Ｒ１２は抵抗である。Ｖinは送信側入力信号、Ｖsoは送信側出力信号、Ｖrinは受信側入力信号、Ｖroは受信側増幅出力信号、Ｖoは受信側出力信号である。 3A to 3F, IC2, IC5 to IC14 are NMOS bus switch ICs, D10 and D11 are Schottky barrier diodes (hereinafter SBD), Z1, Z2, Z5 to Z24 are schematic diagrams of the frequency characteristics of FIG. C1 to C14 and Co are capacitances, Ro is an output resistance, Rso is an output termination resistance, and R1 to R7, R11, and R12 are resistances. Vin is a transmission side input signal, Vso is a transmission side output signal, Vrin is a reception side input signal, Vro is a reception side amplification output signal, and Vo is a reception side output signal.

図３Ａと図３Ｂとの増幅部１３４の出力抵抗Ｒｏは次の等化器１２２の入力の特性抵抗にそろえるが、増幅部１３４の増幅器の出力と次の等化器１２２の入力との配線長がデジタル信号の波形のクロック基本波周波数の波長の１／８（２７０ＭＨｚなら１５４ｍｍ）以下なら出力抵抗Ｒｏは短絡可能である。図３Ａと図３Ｂの様に、増幅部１０８として用いる場合は、出力終端抵抗Ｒsoは伝送路２の特性抵抗Ｒｚが一般に７５ΩからＮＭＯＳバススイッチＩＣの導通抵抗Ｒｄを引いた値となる。ＮＭＯＳバススイッチＩＣの導通抵抗Ｒｄは、正電源電圧Ｖｃｃから２．５Ｖで８Ω、２．９Ｖで７Ω、３．３Ｖで６Ωとなる。そのため、図３Ａと図３Ｂのアナログ切換器にＮＭＯＳバススイッチＩＣを用いた場合では、正電源Ｖｃｃ＋２．９Ｖでの直流電位ＳＤＩ信号の振幅での導通抵抗Ｒｄの８Ωから６Ωで平均７Ωとなる。出力終端抵抗Ｒsoは７５Ωから７Ωを引いた値で６８Ωとなる。図３Ａの受信終端抵抗Ｒ６は６８Ω程度、図３Ｂの受信終端抵抗Ｒ３と受信終端抵抗Ｒ４との合計は６８Ωが最適だが、３３＋３６＝６９で６９Ω程度でも誤差約１．３％で許容できる。
ＮＭＯＳバススイッチＩＣの導通抵抗Ｒｄは正電源電圧から２．９Ｖで７Ω、３．３Ｖで６Ω、３．７Ｖで５Ωとなるから、正電源Ｖｃｃを３．３Ｖ以上に高くすれば、出力終端抵抗Ｒsoは導通抵抗Ｒｄの平均６Ωを引いた６９Ωが最適だが６８Ωでも誤差約１．３％で許容できる。 The output resistance Ro of the amplifier 134 in FIGS. 3A and 3B matches the characteristic resistance of the input of the next equalizer 122, but the wiring length between the output of the amplifier of the amplifier 134 and the input of the next equalizer 122 is the same. Is less than 1/8 of the wavelength of the clock fundamental wave frequency of the digital signal waveform (154 mm for 270 MHz), the output resistor Ro can be short-circuited. 3A and 3B, when used as the amplifying unit 108, the output termination resistance Rso is a value obtained by subtracting the conduction resistance Rd of the NMOS bus switch IC from the characteristic resistance Rz of the transmission line 2 which is generally 75Ω. The conduction resistance Rd of the NMOS bus switch IC is 8Ω at 2.5V from the positive power supply voltage Vcc, 7Ω at 2.9V, and 6Ω at 3.3V. Therefore, when an NMOS bus switch IC is used in the analog switch of FIGS. 3A and 3B, the conduction resistance Rd at the amplitude of the DC potential SDI signal at the positive power supply Vcc + 2.9 V is 7Ω on average from 8Ω to 6Ω. The output termination resistance Rso is 68Ω by subtracting 7Ω from 75Ω. The optimum value of the receiving termination resistor R6 in FIG. 3A is about 68Ω and the total of the receiving termination resistor R3 and the receiving termination resistor R4 in FIG. 3B is 68Ω, but even 33 + 36 = 69 and 69Ω is acceptable with an error of about 1.3%.
The conduction resistance Rd of the NMOS bus switch IC is 7Ω at 2.9V from the positive power supply voltage, 6Ω at 3.3V, and 5Ω at 3.7V. Therefore, if the positive power supply Vcc is increased to 3.3V or more, the output termination resistance Rso is optimally 69Ω minus 6Ω on average of the conduction resistance Rd, but 68Ω is acceptable with an error of about 1.3%.

また、図３Ａと図３Ｂのアナログ切換器に非特許文献９の５Ｖ低容量バススイッチを用いた場合では、導通抵抗Ｒｄは正電源電圧Ｖｃｃから２．１Ｖで４．８Ω、２．５Ｖで４．３Ω、２．７Ｖから３．５Ｖで４．２Ωとなる。そのため、正電源Ｖｃｃ＋２．５Ｖでの直流電位ＳＤＩ信号の振幅での導通抵抗Ｒｄは４．８Ωから４．２Ωで平均４．５Ωとなる。ＲｚからＲｄを引き、７５−４．５＝７０．５＝３３＋３６＋１．５≒６８＋２．７となり、Ｒ６は６８Ωと２．７Ωの直列でＲｚ７５Ωからの誤差０．２Ωで０．３％と誤差範囲以下で、Ｒ３は３３ΩでＲ４は３６Ωと１．５ΩとでＲｚ７５Ωからの誤差はなくなる。
つまり、Ｒｓｏ＋Ｒｄ＝Ｒｚ、Ｒ６＋Ｒｄ＝Ｒｚ，Ｒ３＋Ｒ４＋Ｒｄ＝Ｒｚを誤差範囲以下でインピーダンスマッチングをとり、反射歪を低減する。 When the 5 V low-capacitance bus switch of Non-Patent Document 9 is used for the analog switch in FIGS. 3A and 3B, the conduction resistance Rd is 4.8Ω from the positive power supply voltage Vcc to 2.1 V, and 4 from 2.5 V. .3Ω, 4.2Ω from 2.7V to 3.5V. Therefore, the conduction resistance Rd at the amplitude of the direct current potential SDI signal at the positive power supply Vcc + 2.5V is 4.5Ω to an average of 4.5Ω from 4.8Ω. Rd is subtracted from Rz, and 75-4.5 = 70.5 = 33 + 36 + 1.5≈68 + 2.7. R6 is 68Ω and 2.7Ω in series, and the error range from Rz75Ω is 0.2Ω and 0.3% error range. In the following, R3 is 33Ω, R4 is 36Ω and 1.5Ω, and there is no error from Rz75Ω.
That is, impedance matching is performed with Rso + Rd = Rz, R6 + Rd = Rz, and R3 + R4 + Rd = Rz within an error range to reduce reflection distortion.

さらに、受信側のアナログ切換器の導通抵抗が低く信号波形の圧縮されない信号波形極性を圧縮する接地されたショトキーバリアダイオードＤ１０と抵抗Ｒ１１の直列接続で、信号波形の上下のバランスをとる。
非特許文献９の５Ｖ低容量バススイッチのＣの導通抵抗Ｒｄは、正電源電圧から２．７Ｖから３．５Ｖで４．２Ωと一定であることを利用し、５Ｖ低容量バススイッチを用いて、さらに正電源Ｖｃｃ＋３．２ＶでＶｅｅ−１．３Ｖから−２．３Ｖとすれば、接地電位のＳＤＩ信号の０．８Ｖｐ−ｐでの導通抵抗は４．２Ω一定で、抵抗値の変化がなくなり、上下非対称の波形歪がなくなる。そのため、上下非対称の波形歪の補正のＤ１０とＲ１１は不要となり、Ｄ１０またはＲ１１開放とする。 Further, the signal waveform is balanced in the vertical direction by the series connection of the grounded Schottky barrier diode D10 and the resistor R11, which compresses the signal waveform polarity which is not compressed and the signal waveform is not compressed.
The conduction resistance Rd of C of the 5V low-capacity bus switch of Non-Patent Document 9 is based on the fact that it is constant at 4.2Ω from 2.7V to 3.5V from the positive power supply voltage. Furthermore, if the positive power supply Vcc + 3.2V is changed from Vee-1.3V to -2.3V, the conduction resistance at 0.8Vp-p of the SDI signal of the ground potential is constant at 4.2Ω, and the resistance value is not changed. As a result, the asymmetrical waveform distortion is eliminated. For this reason, D10 and R11 for correcting waveform distortion that is asymmetrical in the vertical direction are not necessary, and D10 or R11 is opened.

図３Ａと図３Ｂと図４Ａと図４Ｂにおいて、バススイッチ器のＩＣ２の切替により、伝送ケーブルが近距離時は演算増幅器の負入力の接地抵抗または負入力の入力抵抗のＲ1と演算増幅器の出力と演算増幅器の負入力間の帰還抵抗のＲ２の値の比から増幅度（Gain）は周波数によらず一定で、出力は0.8Vp-pとなる。そして、伝送ケーブルが遠距離時は、例えばＳＤＩでは演算増幅器の出力と演算増幅器の負入力間の帰還のフェライトビーズＺ１の周波数特性から低周波数が減衰され、高周波数が増強される。具体的には、本発明の１実施例のフェライトビーズの周波数特性の模式図の図５の(a)BLM15BA220SNで基本波付近の300MHzでは73Ωで基本波成分の振幅はおおよそ0.4Vp-pと少なく、３倍高調波付近の1000MHzでは505Ωで、３倍高調波成分の振幅はおおよそ1.4Vp-pと大きくなる。またＨＤ−ＳＤＩではフェライトビーズＺ１が本発明の１実施例のフェライトビーズの周波数特性の模式図の図５の(ｂ)MMMZ0603F100Cが3並列で基本波付近の1500MHzでは66Ωで基本波成分の振幅はおおよそ0.4Vp-pと少なく、３倍高調波付近の4500MHzでは220Ωで、３倍高調波成分の振幅はおおよそ1.2Vp-pと大きくなる。通常、直径８．６ｍｍのトライアックスケーブルの３００ＭＨｚの減衰量は１００ｍで１２ｄＢである。したがって、６ｄＢ低域を減衰させ６ｄＢ高域を増幅すれば、ＳＤＩではおおよそ１００ｍ延長したケーブルでも波形等化が可能となる。図３Ａまたは図３Ｂの本発明の１実施例の増幅回路を、送信と受信の両方に設ければ、補正量とケーブル延長量は倍になり、ＳＤＩではおおよそ２００ｍ延長したケーブルでも波形等化が可能となる。 In FIG. 3A, FIG. 3B, FIG. 4A, and FIG. 4B, when the transmission cable is short-range by switching the bus switch IC2, R1 of the negative input ground resistance or negative input resistance of the operational amplifier and the output of the operational amplifier From the ratio of the value of the feedback resistor R2 between the negative input of the operational amplifier, the gain (Gain) is constant regardless of the frequency, and the output is 0.8 Vp-p. When the transmission cable is at a long distance, for example, in SDI, the low frequency is attenuated from the frequency characteristic of the feedback ferrite bead Z1 between the output of the operational amplifier and the negative input of the operational amplifier, and the high frequency is enhanced. Specifically, in the schematic diagram of the frequency characteristics of the ferrite bead of one embodiment of the present invention, the amplitude of the fundamental wave component is as small as approximately 0.4 Vp-p at 73Ω at 300 MHz near the fundamental wave in (a) BLM15BA220SN in FIG. At 1000 MHz near the 3rd harmonic, the amplitude of the 3rd harmonic component is as large as 1.4 Vp-p at 505Ω. In HD-SDI, the ferrite bead Z1 is a schematic diagram of the frequency characteristics of the ferrite bead of one embodiment of the present invention. FIG. 5 (b) MMMZ0603F100C is in parallel and the fundamental wave component amplitude is 66Ω at 1500 MHz near the fundamental wave. The amplitude of the third harmonic component is as large as 1.2Vp-p at 220Ω at 4500MHz near the third harmonic, as low as approximately 0.4Vp-p. Normally, the attenuation of 300 MHz of a 8.6 mm diameter triax cable is 12 dB at 100 m. Therefore, if the 6 dB low range is attenuated and the 6 dB high range is amplified, SDI enables waveform equalization even with a cable extended by approximately 100 m. If the amplifier circuit of one embodiment of the present invention of FIG. 3A or FIG. 3B is provided for both transmission and reception, the correction amount and the cable extension amount are doubled, and the waveform equalization is performed even for a cable extended by about 200 m in SDI. It becomes possible.

ケーブル２の長さが長い場合のみ、送信側で高域周波数成分を増強し低周波数成分を減衰を行う事で、受信側での波形等化による補正量が小さくなるため、波形等化による劣化を最小限にする事が可能なるため、長いケーブルに応じた波形等化が可能となる。さらに基本波の周波数に合わせてフェライトビーズの特性を選択することで、さらに長いケーブルに応じた波形等化が可能となる。
基本波周波数インピーダンスが負入力抵抗の半分以下で、３次高調波周波数インピーダンス分が負入力抵抗の２倍以上のフェライトビーズであれば、実用になる。 Only when the length of the cable 2 is long, the amount of correction due to waveform equalization on the reception side is reduced by enhancing the high frequency component and attenuating the low frequency component on the transmission side, so that degradation due to waveform equalization Therefore, it is possible to equalize a waveform according to a long cable. Furthermore, by selecting the characteristics of the ferrite bead according to the frequency of the fundamental wave, it is possible to equalize the waveform according to a longer cable.
If the fundamental frequency impedance is less than half of the negative input resistance and the third harmonic frequency impedance is twice or more than the negative input resistance, it is practical.

図３Ｃと図４Ｃにおいて、例えばＳＤＩではフェライトビーズZ1が模式図の図５の(a)BLM15BA220SNで、100MHzでは5Ωで無視でき、抵抗R5=220Ωと抵抗R2=680Ωとの並列で約167Ωで基本波成分の振幅はおおよそ0.4Vp-pで、３倍高調波付近の1000MHzでは505Ωで725Ωと抵抗R2=680Ωとの並列で約351Ωでと、３倍高調波成分の振幅はおおよそ0.8Vp-pとなる計算である。またＨＤ−ＳＤＩではフェライトビーズＺ１を本発明の１実施例のフェライトビーズの周波数特性の模式図の図５の(ｂ)MMMZ0603F100Cが３並列とすればよい。また、Ｈ．２６４等の映像圧縮が高画質で高圧縮比を維持してより低遅延となり、５０Ｍｂｐｓ等のより低いデータ量でカメラの映像信号が伝送可能となった場合は、フェライトビーズＺ１を本発明の１実施例のフェライトビーズの周波数特性の模式図の図５の(ｃ)MMMZ2012D301Bとすればよい。 3C and 4C, for example, in SDI, the ferrite bead Z1 is a schematic diagram (a) BLM15BA220SN in FIG. The amplitude of the wave component is approximately 0.4 Vp-p, and the amplitude of the triple harmonic component is approximately 0.8 Vp-p at approximately 351 Ω in parallel with 725 Ω at 505 Ω and resistance R2 = 680 Ω at 1000 MHz near the third harmonic. This is the calculation. In HD-SDI, the ferrite beads Z1 may be arranged in parallel with three (b) MMMZ0603F100C in FIG. 5 of the schematic diagram of the frequency characteristics of the ferrite beads of one embodiment of the present invention. H. When the video compression such as H.264 has a high image quality and maintains a high compression ratio, the delay becomes lower, and the video signal of the camera can be transmitted with a lower data amount such as 50 Mbps, the ferrite bead Z1 is used as the 1 of the present invention. FIG. 5 (c) MMMZ2012D301B in the schematic diagram of the frequency characteristics of the ferrite bead of the embodiment may be used.

例えばＳＤＩではフェライトビーズZ1が模式図の図５の(a)BLM15BA220SNで、基本波300MHz付近で73Ωで抵抗R5=75Ωとの直列で約148Ωでの振幅はおおよそ0.4Vp-pで、３倍高調波付近の1000MHzでは505Ωと抵抗R5=75Ωとの直列で約580Ωで、３倍高調波成分の振幅はおおよそ2.4Vp-pとなる計算である。またＨＤ−ＳＤＩではフェライトビーズＺ１が本発明の１実施例のフェライトビーズの周波数特性の模式図の図５の(ｂ)MMMZ0603F100Cが3並列とすれば、基本波1500MHz付近で66Ωで抵抗R5=75Ωとの直列で約141Ωでの振幅はおおよそ0.4Vp-pで、３倍高調波付近の4500MHzでは220Ωと抵抗R5=75Ωとの直列で約295Ωで、３倍高調波成分の振幅はおおよそ2.4Vp-pとなる計算である。通常、直径８．６ｍｍのトライアックスケーブルの１５００ＭＨｚの減衰量は１００ｍで約１９ｄＢである。したがって、６ｄＢ低域を減衰させ９ｄＢ高域を増幅すれば、ＨＤ−ＳＤＩではおおよそ８５ｍ延長したケーブルでも波形等化が可能となる。ＳＤＩではおおよそ１２５ｍ延長したケーブルでも波形等化が可能となる。 For example, in SDI, the ferrite bead Z1 is the schematic diagram of Fig. 5 (a) BLM15BA220SN. The amplitude at about 148Ω in series with the resistor R5 = 75Ω in the vicinity of the fundamental wave of 300MHz is approximately 0.4Vp-p, triple harmonic. At 1000MHz near the wave, it is about 580Ω in series with 505Ω and resistance R5 = 75Ω, and the amplitude of the triple harmonic component is about 2.4Vp-p. Also, in HD-SDI, if ferrite bead Z1 is a schematic diagram of the frequency characteristics of the ferrite bead of one embodiment of the present invention and (b) MMMZ0603F100C is three in parallel, the resistance is R5 = 75Ω at 66Ω near the fundamental wave 1500MHz. The amplitude at about 141Ω is approximately 0.4Vp-p in series, and at 4500MHz near the 3rd harmonic, it is about 295Ω in series with 220Ω and resistor R5 = 75Ω, and the amplitude of the 3rd harmonic component is approximately 2.4Vp. The calculation is -p. Normally, the attenuation of 1500 MHz of a 8.6 mm diameter triax cable is about 19 dB at 100 m. Therefore, if the 6 dB low range is attenuated and the 9 dB high range is amplified, the waveform equalization is possible even with a cable extended by about 85 m in HD-SDI. With SDI, waveform equalization is possible even with a cable extended by approximately 125 m.

そのため、１５００ＭｂｐｓのＨＤ−ＳＤＩにも対応できる。また、３００ＭｂｐｓのＳＤＩでは、高周波数増幅に余裕ができるので、フェライトビーズの周波数特性のインピーダンス変化がより大きくなれば、より長いケーブルが補正できる。
さらに増幅器やフェライトビーズの高周波数特性が改良されれば、２９７０Ｍｂｐｓの３ＧのＳＤＩ信号、約２４０００ＭｂｐｓのＵＨＤＴＶ用のＳＤＩ信号の伝送でも、トライアックスケーブルや通常の同軸ケーブルでも従来より長いケーブルが伝送可能となる。 For this reason, it is possible to deal with 1500-Mbps HD-SDI. In addition, since 300 Mbps SDI has a margin for high frequency amplification, a longer cable can be corrected if the impedance change of the frequency characteristic of the ferrite bead becomes larger.
Furthermore, if the high frequency characteristics of amplifiers and ferrite beads are improved, it is possible to transmit 2970 Mbps 3G SDI signals, SDI signals for UHDTV of about 24000 Mbps, and triax cables and ordinary coaxial cables. It becomes.

図３Ａと図３Ｂとで、増幅部のアナログ切換器で切換えるとしたが、図３Ａと図３Ｂとは、シャットダウン（ＳＤ）機能付きの演算増幅器で切換えて増幅しても良い。 In FIG. 3A and FIG. 3B, the switching is performed by the analog switching unit of the amplification unit. However, FIG. 3A and FIG. 3B may be switched and amplified by an operational amplifier with a shutdown (SD) function.

本発明の実施例１と同様の部分の説明は省略する。
本発明の実施例１の図３Ａと図３Ｂとの本発明の１実施例の増幅回路と切替器とのブロック図と、本発明の実施例２の図３Ｃと図３Ｄとの本発明の１実施例の駆動回路と波形等化器または波形等化器を含む受信器（以下波形等化器）と切替器とのブロック図との相違は、図３Ａと図３Ｂとの送出増幅回路が図３Ｃと図３Ｄとの駆動回路と容量のＣｏとに、図３Ａと図３Ｂとの受信増幅回路が図３Ｃと図３Ｄとの等化器に、変更されている。 Description of the same parts as those of the first embodiment of the present invention is omitted.
3A and 3B of the first embodiment of the present invention, a block diagram of the amplifier circuit and the switch of the first embodiment of the present invention, and FIGS. 3C and 3D of the second embodiment of the present invention. The difference between the block diagram of the drive circuit and the waveform equalizer or the receiver including the waveform equalizer (hereinafter referred to as the waveform equalizer) and the switching device of the embodiment is shown in FIG. 3A and FIG. 3B. 3C and FIG. 3D are changed to the drive circuit and the capacitor Co, and the reception amplification circuit of FIG. 3A and FIG. 3B is changed to the equalizer of FIG. 3C and FIG. 3D.

図３Ｃと図３Ｄのアナログ切換器にＮＭＯＳバススイッチＩＣを用いた場合では、電源電圧を正電源Ｖｃｃを＋２．９Ｖ以上３．３Ｖ程度まで高くとし正電源Ｖｃｃと負電源Ｖｅｅの差Ｖａｂが４．５Ｖ以上５．５Ｖ以下とし、負電源電圧Ｖｅｅを1．７Ｖ程度まで少なくし、伝送するＳＤＩ信号の振幅０．８Ｖｐ−ｐ直流電位０Ｖ（接地電位中心）の各電圧−０．４Ｖから＋０．４Ｖに対し、アナログ切換器のＮＭＯＳバススイッチの導通抵抗と導通抵抗の変化とを少なくする。ＮＭＯＳバススイッチＩＣの導通抵抗Ｒｄは、正電源電圧Ｖｃｃから２．５Ｖで８Ω、２．９Ｖで７Ω、３．３Ｖで６Ωとなる。そのため、出力抵抗Ｒsoと受信終端抵抗Ｒ６とは伝送路２の特性抵抗Ｒｚ一般に７５ΩからＮＭＯＳバススイッチＩＣでは、直流電位ＳＤＩ信号の振幅での導通抵抗Ｒｄの６Ωから８Ωで平均７Ωを引いた値で６８Ωとし、Ｒｚ７５Ω程度とする。
そのため、出力終端抵抗とＮＭＯＳバススイッチＩＣの導通抵抗との合計値と、受信終端抵抗とＮＭＯＳバススイッチＩＣの導通抵抗との合計値と、トライアックスケーブルまたは同軸ケーブルの伝送路の特性インピーダンス７５Ωとが誤差約１％とほぼ等しくなり、インピーダンスミスマッチングの反射による波形歪が低減する。さらに直流電位ＳＤＩ信号の振幅での振幅値０．８Ｖｐ−ｐで抵抗値の変化が７５Ωに対し約２％と低減し、上下非対称の波形歪が低減する。 In the case where the NMOS bus switch IC is used in the analog switch of FIGS. 3C and 3D, the power supply voltage is increased from + 2.9V to about 3.3V from the positive power supply Vcc, and the difference Vab between the positive power supply Vcc and the negative power supply Vee is 4. The negative power supply voltage Vee is reduced to about 1.7 V, and the amplitude of the transmitted SDI signal is 0.8 Vp-p DC voltage 0 V (center of ground potential) -0.4 V to +0 Reduce the conduction resistance and change in conduction resistance of the NMOS bus switch of the analog switch for .4V. The conduction resistance Rd of the NMOS bus switch IC is 8Ω at 2.5V from the positive power supply voltage Vcc, 7Ω at 2.9V, and 6Ω at 3.3V. Therefore, the output resistance Rso and the receiving termination resistance R6 are values obtained by subtracting 7Ω on average from 6Ω to 8Ω of the conduction resistance Rd at the amplitude of the DC potential SDI signal in the NMOS bus switch IC from the characteristic resistance Rz of the transmission line 2 in general 75Ω. 68Ω, and about Rz75Ω.
Therefore, the total value of the output termination resistance and the conduction resistance of the NMOS bus switch IC, the total value of the reception termination resistance and the conduction resistance of the NMOS bus switch IC, and the characteristic impedance 75Ω of the transmission line of the triax cable or coaxial cable Becomes approximately equal to about 1%, and waveform distortion due to reflection of impedance mismatching is reduced. Further, when the amplitude value of the direct current potential SDI signal is 0.8 Vp-p, the change in resistance value is reduced to about 2% with respect to 75Ω, and the asymmetrical waveform distortion is reduced.

また、図３Ｃと図３Ｄのアナログ切換器に非特許文献９の５Ｖ低容量バススイッチを用いた場合では、導通抵抗Ｒｄは正電源電圧Ｖｃｃから２．１Ｖで４．８Ω、２．５Ｖで４．３Ω、２．７Ｖから３．５Ｖで４．２Ωとなる。そのため、正電源Ｖｃｃ＋２．５Ｖでの直流電位ＳＤＩ信号の振幅での導通抵抗Ｒｄは４．８Ωから４．２Ωで平均４．５Ωとなる。ＲｚからＲｄを引き、７５−４．５＝７０．５≒７１≒６８＋２．７で６８Ωと２．７Ωの直列として、７５Ωに対する平均誤差０．２Ω０．３％と誤差範囲以下の精度でインピーダンスマッチングを取る。反射による波形歪が誤差範囲以下となる。さらに直流電位ＳＤＩ信号の振幅での振幅値０．８Ｖｐ−ｐで抵抗値の変化が７５Ωに対し約０．８％ｐ−ｐと誤差範囲以下に低減し、上下非対称の波形歪も誤差範囲以下になる。 When the 5 V low-capacity bus switch of Non-Patent Document 9 is used for the analog switch in FIGS. 3C and 3D, the conduction resistance Rd is 4.8Ω from the positive power supply voltage Vcc to 2.1 V, and 4 from 2.5 V. .3Ω, 4.2Ω from 2.7V to 3.5V. Therefore, the conduction resistance Rd at the amplitude of the direct current potential SDI signal at the positive power supply Vcc + 2.5V is 4.5Ω to an average of 4.5Ω from 4.8Ω. Rd is subtracted from Rz, and 75-4.5 = 70.5 ≒ 71 ≒ 68 + 2.7, and 68Ω and 2.7Ω are connected in series. I take the. Waveform distortion due to reflection is below the error range. Furthermore, when the amplitude of the direct current potential SDI signal is 0.8 Vp-p, the change in resistance value is reduced to approximately 0.8% pp with respect to 75Ω, which is less than the error range, and the asymmetrical waveform distortion is also within the error range. become.

さらに、受信側の前記アナログ切換器の導通抵抗が低く信号波形の圧縮されない信号波形極性を圧縮する接地されたＳＢＤのＤ１０と抵抗Ｒ１１の直列接続とを有して、切替器で圧縮されない方を圧縮し、信号波形の上下のバランスをとり、ＳＤＩ信号の受信用の等化器または波形等化器を含む受信器で送信時の波形に戻す波形等化をし易くする。その結果、延長したケーブルでも波形等化が可能となる。 In addition, the analog switch on the receiving side has a low conduction resistance and a signal waveform polarity that is not compressed and has a grounded SBD D10 that compresses the signal waveform polarity and a series connection of a resistor R11, and is not compressed by the switch. It compresses and balances the signal waveform up and down, and facilitates waveform equalization to return to the waveform at the time of transmission by an equalizer for receiving an SDI signal or a receiver including a waveform equalizer. As a result, waveform equalization is possible even with an extended cable.

また、５Ｖ低容量バススイッチＩＣの導通抵抗Ｒｄは、正電源電圧から２．７Ｖから３．５Ｖで４．２Ωと一定であることを利用し、５Ｖ低容量バススイッチを用いて、さらに正電源Ｖｃｃ＋３．２ＶでＶｅｅ−１．３Ｖから−２．３Ｖとすれば、接地電位のＳＤＩ信号の０．８Ｖｐ−ｐでの導通抵抗Ｒｄは４．２Ω一定で、抵抗値の変化がなくなり、上下非対称の波形歪がなくなる。そのため、上下非対称の波形歪の補正のＤ１０とＲ１１は不要となり、Ｄ１０またはＲ１１開放とする。
さらに、Ｒｓｏ＝Ｒ６＝Ｒｚ−Ｒｄ＝７５−４．２＝７０．８≒７１≒６８＋２．７で、ＲｓｏとＲ６とを６８Ωと２．７Ωの直列とすれば、Ｒｚ７５Ωからの誤差０．１Ωで０．１％とほとんどなくなる。つまり、反射による波形歪もほとんどなくなる。 Further, by utilizing the fact that the conduction resistance Rd of the 5V low-capacity bus switch IC is constant at 4.2Ω from 2.7V to 3.5V from the positive power supply voltage, further using the 5V low-capacity bus switch, When Vcc + 3.2V is changed from Vee-1.3V to -2.3V, the conduction resistance Rd at 0.8Vp-p of the SDI signal at the ground potential is constant at 4.2Ω, the resistance value does not change, and the asymmetry is vertical. No waveform distortion. For this reason, D10 and R11 for correcting waveform distortion that is asymmetrical in the vertical direction are not necessary, and D10 or R11 is opened.
Further, if Rso = R6 = Rz−Rd = 75−4.2 = 70.8≈71≈68 + 2.7, and Rso and R6 are in series of 68Ω and 2.7Ω, an error from Rz75Ω is 0.1Ω. With 0.1%, it almost disappears. That is, the waveform distortion due to reflection is almost eliminated.

つまり、従来の駆動回路と波形等化器と切替器とのブロック図の図６と、本発明の実施例２の図３Ｃと図３Ｄとの本発明の１実施例の駆動回路と波形等化器と切替器とのブロック図との相違は、アナログ切換器のＮＭＯＳバススイッチまたは５Ｖ低容量バススイッチのＩＣの電源電圧と、出力抵抗Ｒsoと受信終端抵抗Ｒ６とを工夫し、インピーダンスミスマッチングの反射による波形歪と抵抗値の変化による波形の非対称歪を低減したことである。従来の駆動回路と波形等化器と切替器との入出力波形図の図７のVrinの非対称歪が著しいのに対し、本発明の１実施例の駆動回路と波形等化器の入出力波形図の図４ＤのVrinの非対称歪は少ない。そのため、ＳＤＩ信号の受信用の等化器または波形等化器を含む受信器による波形等化が容易で、ケーブル長を伸ばすことが可能となる。 That is, FIG. 6 is a block diagram of a conventional drive circuit, waveform equalizer, and switch, and FIG. 3C and FIG. 3D of the second embodiment of the present invention are the drive circuit and waveform equalization of the first embodiment of the present invention. The difference between the block diagram of the switch and the switch is that the power supply voltage of the analog switch NMOS bus switch or 5V low-capacitance bus switch IC, the output resistance Rso and the reception termination resistor R6 are devised to reduce impedance mismatching. This is because the waveform distortion due to reflection and the asymmetric distortion of the waveform due to the change in resistance value are reduced. While the asymmetric distortion of Vrin in FIG. 7 in the input / output waveform diagram of the conventional drive circuit, waveform equalizer and switcher is significant, the input / output waveform of the drive circuit and waveform equalizer of one embodiment of the present invention. The asymmetric distortion of Vrin in FIG. Therefore, waveform equalization by a receiver including an equalizer for receiving an SDI signal or a waveform equalizer is easy, and the cable length can be increased.

さらに、本発明の実施例２の図３Ｃの本発明の１実施例の駆動回路と波形等化器と切替器とのブロック図では、超長距離ケーブル用に、受信側の前記アナログ切換器の導通抵抗が低く信号波形の圧縮されない信号波形極性を圧縮する接地されたＳＢＤと抵抗の直列接続とで、切替器で圧縮されない信号波形極性を圧縮し、信号波形の上下のバランスをとる。
または、５Ｖ低容量バススイッチを用いて正電源Ｖｃｃ＋３．２Ｖなら、図４ＤのVrinの反射による波形歪と抵抗値の変化による非対称歪は誤差範囲以下になる。 Furthermore, in the block diagram of the drive circuit, waveform equalizer, and switch of the first embodiment of the present invention in FIG. 3C of the second embodiment of the present invention, the analog switch on the receiving side is used for a very long distance cable. A series connection of a grounded SBD that compresses the uncompressed signal waveform polarity with a low conduction resistance and a resistor in series connects the signal waveform polarity that is not compressed by the switch to balance the signal waveform up and down.
Alternatively, if a positive power supply Vcc + 3.2 V is used using a 5 V low-capacity bus switch, the waveform distortion due to the reflection of Vrin in FIG. 4D and the asymmetric distortion due to the change in resistance value are below the error range.

その結果、従来の駆動回路と波形等化器と切替器との入出力波形図の図７のVrinの非対称歪が著しいのに対し、本発明の１実施例の駆動回路と波形等化器または波形等化器を含む受信器の入出力波形図の図４ＣのVrinの非対称歪はほとんどなく、波形等化器または波形等化器を含む受信器による波形等化が容易で、２７０ＭｂｐｓのＳＤＩ信号や１５００ＭｂｐｓのＨＤ−ＳＤＩ信号で、トライアックスケーブルや通常の同軸ケーブルでも超長距離ケーブルでの伝送が可能となる。
さらに駆動回路と波形等化器または波形等化器を含む受信器が改良されれば、２９７０Ｍｂｐｓの３ＧのＳＤＩ信号、約２４０００ＭｂｐｓのＵＨＤＴＶ用のＳＤＩ信号の伝送でも、トライアックスケーブルや通常の同軸ケーブルでも従来より長いケーブルが伝送可能となる。 As a result, the asymmetric distortion of Vrin in FIG. 7 in the input / output waveform diagram of the conventional drive circuit, waveform equalizer, and switcher is significant, whereas the drive circuit and waveform equalizer of one embodiment of the present invention or There is almost no asymmetric distortion of Vrin in FIG. 4C in the input / output waveform diagram of the receiver including the waveform equalizer, and the waveform equalization by the receiver including the waveform equalizer or the waveform equalizer is easy, and the 270 Mbps SDI signal With an HD-SDI signal of 1500 Mbps, it is possible to transmit a triax cable or a normal coaxial cable using a very long distance cable.
In addition, if the drive circuit and the waveform equalizer or the receiver including the waveform equalizer are improved, the transmission of the 2970 Mbps 3G SDI signal and the SDI signal for UHDTV of about 24000 Mbps may be performed using a triax cable or a normal coaxial cable. But longer cables can be transmitted.

本発明の実施例１と同様の部分の説明は省略する。
本発明の実施例１の図３Ａの本発明の１実施例の増幅回路と切替器とのブロック図と、本発明の実施例３の図３Ｅと図３Ｆの本発明の１実施例の増幅回路と切替器とのブロック図との相違は、図３Ａの送出増幅回路の抵抗Ｒ１４が図３Ｅと図３Ｆの送出増幅回路のフェライトビーズＺ２に、変更されている。さらに図３ＡではショトキーバリアダイオードＤ１０と抵抗Ｒ１１の直列接続の組であるのに対し、図３ＥではショトキーバリアダイオードＤ１１と抵抗Ｒ１２の直列接続の組が追加され、図３ＦではショトキーバリアダイオードＤ１１と抵抗Ｒ１２の直列接続の組となっている。ショトキーバリアダイオードＤ１０とショトキーバリアダイオードＤ１１とでは順方向効果電圧特性が異なっている。 Description of the same parts as those of the first embodiment of the present invention is omitted.
FIG. 3A of the first embodiment of the present invention is a block diagram of the amplifier circuit and the switch of the first embodiment of the present invention, and FIG. 3E of the third embodiment of the present invention is the amplifier circuit of the first embodiment of the present invention of FIG. The difference between the switch and the block diagram of the switch is that the resistor R14 of the delivery amplifier circuit of FIG. 3A is changed to the ferrite bead Z2 of the delivery amplifier circuit of FIGS. 3E and 3F. Further, in FIG. 3A, a series connection set of the Schottky barrier diode D10 and the resistor R11 is provided, whereas in FIG. 3E, a set of series connection of the Schottky barrier diode D11 and the resistance R12 is added, and in FIG. D11 and resistor R12 are connected in series. The Schottky barrier diode D10 and the Schottky barrier diode D11 have different forward effect voltage characteristics.

アナログ切換器の５Ｖ低容量バススイッチＩＣの電源電圧の正電源Ｖｃｃを＋２．９Ｖ以上とし正電源Ｖｃｃと負電源Ｖｅｅの差Ｖａｂが４．５Ｖ以上５．５Ｖ以下として、通過信号振幅に余裕を持たせて、送信側のオーバーシュートを許容させる。本発明の１実施例の低容量バススイッチＩＣの導通抵抗特性の模式図の図８Ｂのように、負電源Ｖｅｅの導通抵抗３．８Ωと正電源Ｖｃｃから２．３Ｖの導通抵抗４．８Ωの２．２Ｖｐ−ｐの通過信号振幅は許容される。その上で、ケーブル２の長さが長い場合に送信側で、フェライトビーズＺ２を用いオーバーシュートを許容して、送信側でも基本波周波数以下の低周波数成分を減衰させ３次以上の高調波成分を増強する。さらに、送信側の低容量バススイッチＩＣの導通抵抗が低く信号波形の圧縮されない信号波形極性を圧縮する接地されたショトキーバリアダイオードと抵抗の直列接続と、受信側の低容量バススイッチＩＣの導通抵抗が低く信号波形の圧縮されない信号波形極性を圧縮する接地されたショトキーバリアダイオードと抵抗の直列接続とを有して、送信側と受信側で圧縮されない方を圧縮し、信号波形の上下のバランスをとる。
低容量バススイッチＩＣの導通抵抗の変化が少なくなれば、受信側で圧縮されない方を圧縮するショトキーバリアダイオードＤ１０と抵抗Ｒ１１は必要はなくなり、ショトキーバリアダイオードＤ１１と抵抗Ｒ１２の直列接続の１組で良い。 The positive power supply Vcc of the power supply voltage of the 5V low-capacity bus switch IC of the analog switch is set to + 2.9V or more, and the difference Vab between the positive power supply Vcc and the negative power supply Vee is set to 4.5V or more and 5.5V or less, so that there is a margin in the passing signal amplitude. To allow overshoot on the transmission side. As shown in FIG. 8B of the schematic diagram of the conduction resistance characteristics of the low-capacity bus switch IC of one embodiment of the present invention, the conduction resistance 3.8Ω of the negative power source Vee and the conduction resistance 4.8Ω of 2.3 V from the positive power source Vcc. A passing signal amplitude of 2.2 Vp-p is allowed. In addition, when the length of the cable 2 is long, on the transmission side, ferrite beads Z2 are used to allow overshoot, and on the transmission side, the low frequency component below the fundamental frequency is attenuated and the third and higher harmonic components are attenuated. To strengthen. In addition, the conduction resistance of the low-capacity bus switch IC on the transmission side is low, and the grounded Schottky barrier diode that compresses the signal waveform polarity that is not compressed in the signal waveform is connected in series with the resistor, and the conduction of the low-capacity bus switch IC on the reception side Has a low resistance and uncompressed signal waveform has a grounded Schottky barrier diode that compresses the signal waveform polarity and a series connection of resistors, compresses the non-compressed side on the transmitting side and the receiving side, and to keep balance.
If the change in the conduction resistance of the low-capacity bus switch IC is reduced, the Schottky barrier diode D10 and the resistor R11 that compress the non-compressed side on the receiving side are not necessary, and the series connection 1 of the Schottky barrier diode D11 and the resistor R12 is not necessary. A pair is good.

本発明の実施例１から実施例３の産業上の利用として、トライアックスケーブルでの伝送の超長距離化だけでなく、２７０ＭｂｐｓのＳＤＩ信号や１５００ＭｂｐｓのＨＤ−ＳＤＩ信号で、や通常の同軸ケーブルでも超長距離ケーブルでの伝送が可能となるため、ＳＤＩ映像信号に電源を重畳する監視用途の同軸重畳でも超長距離化が容易となる。特に映像信号に定電圧電源を重畳すると超長距離化が容易となる。 As an industrial application of the first to third embodiments of the present invention, not only the ultra-long transmission of the triax cable but also the 270 Mbps SDI signal and the 1500 Mbps HD-SDI signal, or a normal coaxial cable However, since transmission using an ultra-long distance cable is possible, it is easy to achieve ultra-long distance even in the case of coaxial superimposition for monitoring purposes in which a power source is superimposed on an SDI video signal. In particular, if a constant voltage power supply is superimposed on a video signal, it is easy to achieve a very long distance.

１：撮像部、２：トライアックスケーブル、３：制御部、
１０１：レンズ部、１０２：撮像素子、
１０３，１２９，１４１：A/Dコンバータ（ADC）、
１０４，１２７，２０４、２１７：デジタル信号処理部、
１０５，１３６：映像圧縮部、
１０６：切換部、１１２，１２１：双方向部、
１０７，１３５：ENCODE部、１１６，１２５：DECODE部、
１１４，１２８，１３９，１４０：D/Aコンバータ（DAC）、
１０８，１０９，１３３，１３４，：増幅部、
１３８，１３９，２３８，２３９：駆動回路、１１３，１３０：CPU、
１１５，１２６：映像伸長部、１１９，１２２，２１９，２２２：波形等化器または波形等化器を含む受信器、
２１１、２１５：フィルタ、１２０，１４２：接栓、
２０８，２０９、２２２，２２４：MULTIPLEX部、
２１０，２１６：時分割双方向切換部
ＩＣ１，ＩＣ３：演算増幅器または演算増幅器と電流バッファ、
ＩＣ２，ＩＣ５：アナログ切換器、ＩＣ４：アナログ切換器、
Ｚ１〜Ｚ２：フェライトビーズ、Ｃ１〜Ｃ１４，Ｃｏ：容量、
Ｄ１０，Ｄ１１：ショトキーバリアダイオード（ＳＢＤ）、
Ｒｏ：出力抵抗、Ｒso：出力終端抵抗、Ｒ１〜Ｒ７，Ｒ１１，Ｒ１２：抵抗、
Ｒｚ：伝送路の特性インピーダンス抵抗、Ｒｄ：アナログ切換器の導通抵抗の平均値、
Ｖin：送信側入力信号、Ｖso：送信側出力信号、
Ｖrin：受信側入力信号、Ｖro：受信側増幅出力信号、Ｖo：受信側出力信号、
Ｖcc：正電源、Ｖee：負電源 1: imaging unit, 2: triax cable, 3: control unit,
101: Lens unit, 102: Image sensor,
103, 129, 141: A / D converter (ADC),
104, 127, 204, 217: digital signal processing unit,
105, 136: video compression unit,
106: switching unit, 112, 121: bidirectional unit,
107, 135: ENCODE part, 116, 125: DECODE part,
114, 128, 139, 140: D / A converter (DAC),
108, 109, 133, 134: amplifying unit,
138, 139, 238, 239: drive circuit, 113, 130: CPU,
115, 126: Video decompression unit, 119, 122, 219, 222: Waveform equalizer or receiver including waveform equalizer,
211, 215: filter, 120, 142: plug,
208, 209, 222, 224: MULTIPLEX section,
210, 216: time-division bidirectional switching units IC1, IC3: operational amplifier or operational amplifier and current buffer,
IC2, IC5: Analog switch, IC4: Analog switch,
Z1 to Z2: ferrite beads, C1 to C14, Co: capacity,
D10, D11: Schottky barrier diode (SBD),
Ro: output resistance, Rso: output termination resistance, R1 to R7, R11, R12: resistance,
Rz: characteristic impedance resistance of transmission line, Rd: average value of conduction resistance of analog switch,
Vin: transmission side input signal, Vso: transmission side output signal,
Vrin: reception side input signal, Vro: reception side amplified output signal, Vo: reception side output signal,
Vcc: positive power supply, Vee: negative power supply

Claims

In a digital video signal multiplex transmission apparatus for time-division bidirectional switching transmission / reception of digital signals including digitized video signals, audio signals, and control signals via one transmission line, time division multiplexing is performed at both ends of the transmission line. An analog switch IC for switching between the digital signal including a waveform equalizer or a receiver including a waveform equalizer on the receiving side, and the digital signal including the digitized video signal, audio signal, and control signal The average value of the conduction resistance of the switch is 1/10 or less of the characteristic impedance resistance Rz of the transmission line, and the conduction resistance of the analog switch in the digital signal including the digitized video signal, audio signal, and control signal. change 1/30 characteristic impedance resistor Rz of the transmission path, so that the positive power supply Vcc of the power supply voltage of the analog switching device A voltage for reducing a change in conduction resistance of the analog switch, and a means for correcting an increase in termination resistance due to the conduction resistance of the analog switch with respect to the characteristic impedance resistance Rz of the transmission line of the transmission line; A video signal multiplex transmission apparatus comprising: means for correcting distortion of a signal waveform due to a deviation of a termination resistance due to a change in conduction resistance of an analog switch;

In a digital video signal multiplex transmission apparatus for time-division bidirectional switching transmission / reception of digital signals including digitized video signals, audio signals, and control signals via one transmission line, time division multiplexing is performed at both ends of the transmission line. An analog bus NMOS switch IC having a waveform equalizer or a receiver including a waveform equalizer on the receiving side, and a positive power source Vcc of the power supply voltage of the analog bus NMOS bus switch IC. Is + 2.9V or more, and the difference Vab between the positive power supply Vcc and the negative power supply Vee is 4.5V or more and 5.5V or less, or 5V of an analog switch that switches time-division multiplexing at both ends of the transmission line. A capacitor bus switch IC having a waveform equalizer on the receiving side or a receiver including a waveform equalizer, and a power supply voltage for the 5 V low-capacity bus switch IC of the analog switch The positive power supply Vcc is set to +2.5 V or more, and the difference Vab between the positive power supply Vcc and the negative power supply Vee is set to 4.5 V or more and 5.5 V or less. Video signal multiplexing comprising: at least one of means for correcting an increase in termination resistance due to conduction resistance; and means for correcting distortion of a signal waveform due to termination resistance shift due to a change in conduction resistance of the analog switch Transmission equipment.

3. The video signal multiplex transmission apparatus of the transmission apparatus according to claim 2, wherein a change in conduction resistance of the bus switch IC of the analog switch in the digital signal including the digitized video signal, audio signal, and control signal is a characteristic of the transmission path. From the bus switch IC of the analog switch in which the positive power supply Vcc of the power supply voltage of the bus switch IC of the analog switch is set to 1/100 or less of the impedance resistance Rz , and the characteristic impedance resistance Rz of the transmission line The termination resistance of the resistance value Rz-Rd reduced by the average value Rd of the conduction resistance of the analog switch and the conduction resistance of the analog switch on the receiving side of the analog switch is grounded to compress the signal waveform polarity. video signal, characterized in that it comprises at least one of the Schottky barrier diode in series connection of resistors, and Multiplex transmission apparatus.

4. The video signal multiplex transmission device of the transmission device according to claim 1, wherein an amplifier for amplifying a waveform of the digital signal before a receiver including a waveform equalizer on the receiving side or a waveform equalizer, and the digital An inductor, a capacitor, and a resistor that have a low impedance at the clock fundamental frequency of the waveform of the digital signal and a high impedance at the clock harmonic frequency of the waveform of the digital signal compared to the circuit characteristic resistance of the amplifier that amplifies the signal waveform And digitally input to the waveform equalizer or a receiver including the waveform equalizer, which can be expressed as an approximate equivalent circuit (hereinafter referred to as an impedance body) of a serially connected device and a resistor connected in series Attenuates the low frequency component below the clock fundamental frequency of the signal waveform, and the clock harmonic component of the digital signal waveform Enhanced, in a Schottky barrier diode and a resistor, to compress the negative direction of the signal amplitude in the analog switching device, or, the power supply voltage of 5V Low Capacitance Bus Switch IC of the analog switching device, a positive power supply Vcc3.2V The video signal multiplex transmission apparatus is characterized in that the negative power source Vee performs at least one of the difference Vab between the positive power source Vcc and the negative power source Vee between 4.5V and 5.5V.

5. The video signal multiplex transmission device of the transmission device according to claim 4, further comprising: an amplifier that amplifies the waveform of the digital signal before the analog switch on the transmission side; and the impedance body, and the analog switch on the transmission side. A video signal multiplex transmission apparatus for attenuating a low frequency component equal to or lower than a clock fundamental wave frequency of the waveform of the digital signal input to the digital signal and enhancing a clock harmonic component of the waveform of the digital signal.

In a digital video signal multiplex transmission apparatus for time-division bidirectional switching transmission / reception of digital signals including digitized video signals, audio signals, and control signals through one transmission line, time division multiplexing is performed at both ends of the transmission line. An analog switch bus switch IC, and a receiver having a waveform equalizer or a waveform equalizer on the receiving side, the analog switch for the characteristic impedance resistance of the transmission line of the transmission line At least one of means for correcting an increase in termination resistance due to the conduction resistance of the bus switch IC of the switch and means for correcting distortion of the signal waveform due to a shift in the termination resistance due to a change in the conduction resistance of the bus switch IC of the analog switch A video signal multiplex transmission apparatus comprising:

An imaging unit having an imaging element, a video signal processing unit, and a CPU (Central Processing Unit), a video signal multiplex transmission device of the transmission device according to claim 1, a video signal processing unit, a video signal input / output unit, and a CPU And an image pickup apparatus characterized in that the video signal is time-division bidirectionally multiplexed.