JP5907099B2 - I / O processing device, address validity verification method, and address validity verification program - Google Patents

Description

  The present invention relates to an input / output processing apparatus, an address validity verification method, and an address validity verification program for verifying the validity of a transfer destination address accompanying data input / output.

  Today, information processing devices that transmit data from a peripheral processing device to a central processing device via an input / output processing device are part of the social infrastructure, and various functions are stopped due to a failure of the information processing device. May affect social life.

  Also, with the recent miniaturization of LSI (Large Scale Integration), the probability of data corruption due to alpha rays and the like is increasing. Therefore, even when data corruption occurs, it is required to remedy the data error by correcting or retrying the data and to continuously operate the information processing apparatus.

  Patent Document 1 describes a PCI (Peripheral Component Interconnect) Express TLP (Transaction Layer Packet) processing circuit that detects an error in data transmitted from a relay device. PCI Express is a registered trademark. In the following description, PCI Express may be referred to as PCIe.

  When the processing circuit described in Patent Document 1 receives a transaction layer packet (hereinafter also referred to as TLP), it generates a detection code for detecting an error occurring in the relay circuit of the device and adds it to the TLP. And store it in the buffer. Then, the processing circuit described in Patent Document 1 compares the TLP detection code again with the detection code stored in the buffer at the time of packet transmission to determine whether or not the transmitted signal is normal. When the processing circuit described in Patent Document 1 determines that the signal is abnormal, the processing circuit returns a NAK DLLLP (Not Acknowledge Data Link Layer Packet) signal to the transmission side device.

JP 2010-250665 A

  First, the operation of a general information processing apparatus using PCIe will be described. FIG. 14 is an explanatory diagram illustrating an example of the information processing apparatus. An information processing apparatus 1000 illustrated in FIG. 14 is a computer system called a server or a mainframe. The information processing apparatus 1000 includes a central processing unit 100, an input / output processing unit 200, and peripheral processing units 2000 and 3000.

  The central processing unit 100 includes a main memory (MM) 130, arithmetic processing units (EPU) 110 to 113, and a memory controller (MC) 120. The main memory 130 stores software instructions and data processed by the software. The arithmetic processing devices 110 to 113 read software instructions and data from the main memory 130 and execute each processing. The memory controller 120 connects the arithmetic processing devices 110 to 113, the main memory 130, and an IO controller 210 of the input / output processing device 200 described later, and controls mutual access.

  The arithmetic processing units 110 to 113 and the memory controller 120 are connected via a bus 140, the main memory 130 and the memory controller 120 are connected via a bus 150, and the IO controller 210 and the memory controller 120 are connected via a bus 160.

  The input / output processing device 200 is a device that transfers data between the main memory 130 and the peripheral processing devices 2000 and 3000 in accordance with instructions from the arithmetic processing devices 110 to 113. The input / output processing device 200 includes PCIe cards 280 to 283 for connecting to the peripheral processing devices 2000 and 3000, and a PCIe switch 240 for connecting the PCIe cards 280 to 283. The PCIe switch 240 and the PCIe cards 280 to 283 are connected by PCIe interfaces (I / F) 260 to 263, respectively.

  Further, the input / output processing device 200 includes an IO controller (IOC) 210 that controls data transfer between the peripheral processing devices 2000 and 3000 and the main memory 130 via the PCIe cards 280 to 283. The IO controller 210 and the memory controller 120 are connected by a bus 160. The IO controller 210 and the PCIe switch 240 are connected by a PCIe I / F 252 via ports 210-1 and 240-1.

  Further, the input / output processing device 200 includes a processor (PROC) 220 and a local memory (LM) 230. The processor 220 receives a data transfer instruction between the main memory 130 and the peripheral processing devices 2000 and 3000 from the arithmetic processing devices 110 to 113, and controls the IO controller 210 and the PCIe cards 280 to 283 to perform data transfer.

  The processor 220 operates according to firmware, for example. Hereinafter, the operation of the processor 220 according to the firmware may be described as the firmware performing various processes. The local memory 230 stores firmware and data used by the firmware.

  The processor 220 and the local memory 230 are connected by a bus 270. The processor 220 and the IO controller 210 are connected by a PCIe I / F 250 via ports 220-1 and 210-2. The processor 220 and the PCIe switch 240 are connected by a PCIe I / F 251 via ports 220-2 and 240-2. It is assumed that the PCIe port 220-1 and the PCIe port 220-2 of the processor 220 are respectively root complexes.

  The peripheral processing devices 2000 and 3000 are magnetic disk devices or the like, and are connected to the PCIe cards 280 to 283 by various I / Fs such as fiber channels. Data transfer is performed between the main memory 130 and the peripheral processing devices 2000 and 3000 through the following route. First, data is transmitted from the main memory 130 of the central processing unit 100 to the input / output processing device 200 via the bus 150, the memory controller 120, and the bus 160. Further, the data passes through the IO controller 210, PCIe I / F 252, PCIe switch 240, PCIe I / F 260-263, PCIe card 280-283, peripheral I / F 2001, 2002, 3001, 3002 of the input / output processing device 200. And transmitted to the peripheral processing devices 2000 and 3000. The same applies to the reverse direction.

  In the input / output processing device 200, the processor 220, the IO controller 210, the PCIe switch 240, and the PCIe cards 280 to 283 are all connected by a PCIe I / F. Since the PCIe port 220-1 and the PCIe port 220-2 of the processor 220 are each a root complex, they can be accessed as the same memory space including the local memory 230 from the processor 220 and the PCIe cards 280 to 283.

  The IO controller 210 and the memory controller 120 are connected by a bus 160. However, since the bus type and the memory space are usually different, when the main memory 130 is accessed from the PCIe card 280-283, the address conversion is performed by the conversion mechanism 211 (not shown in FIG. 14) of the IO controller 210. I / F conversion is performed.

  FIG. 15 is an explanatory diagram illustrating an example of an address conversion method. As shown in FIG. 15, an address space having a different base address from the address space 131 of the main memory 130 is set in an MMIO (Memory Mapped Input / Output) space 301 of the PCIe port 210-1 of the IO controller 210. . In this situation, when the MMIO space 301 is accessed, the IO controller 210 masks the input address with the value of the address translation mask register 213 by the translation mechanism 211. The IO controller 210 converts the address 302 at the time of input into the address 132 in the address space of the main memory 131 by adding the value of the address conversion base register 212 to the masked result.

  For example, in the example illustrated in FIG. 15, the address space 131 of the main memory 130 is set to 0x0 to 0xFFFFFFFFFF, and the MMIO space 301 of 0x800000000 to 0x80FFFFFFFFFF is allocated to the PCIe port 210-1 of the IO controller 210 as a copy. Further, 0x0 is set in the address translation base register 212, and 0x00FFFFFFFFFF is set in the address translation mask register 213.

  When the PCIe cards 280 to 283 write data to the address 0x8000FF00 of the main memory 130, the PCIe cards 280 to 283 access the address 0x8008000FF00 of the MMIO space 301. When the IOC 210 receives an access to the MMIO space 301, the conversion mechanism 211 calculates the calculated address 0x80000000FF00 by taking the logical product of the requested address 0x8008000FF00 and the value of the address conversion mask register 213. Further, the conversion mechanism 211 adds the value of the address conversion base register 212 to the calculated value to obtain 0x00008000FF00. The IO controller 210 accesses the address space 131 of the main memory 130 using the obtained address.

  In the information processing apparatus 1000, when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130, the arithmetic processing devices 110 to 113 create a channel program for transferring data from the peripheral processing devices 2000 and 3000 to the main memory 130. To do. The arithmetic processing units 110 to 113 store the created channel program in the main memory 130, and specify the channel program storage address to the input / output processing unit 200 to instruct the execution of the channel program. Then, the arithmetic processing devices 110 to 113 wait for a channel program end notification from the input / output processing device 200. The data processing is completed when the arithmetic processing units 110 to 113 receive the end notification.

  The execution instruction of the channel program from the arithmetic processing devices 110 to 113 to the input / output processing device 200 is performed by the arithmetic processing devices 110 to 113 accessing the IO controller 210 in memory. As a result, the IO controller 210 interrupts the PCIe port 220-1 of the processor 220, thereby instructing the firmware operating on the processor 220 to execute the channel program. This is a general method and will not be described in detail.

  FIG. 16 is an explanatory diagram showing an example of a channel program. FIG. 17 is an explanatory diagram showing an example of the channel program header. As illustrated in FIG. 16, the channel program 20 includes a channel program header (CPH) 20-0 and a plurality of channel command entries (CCE) 20-1 to n. Also, as illustrated in FIG. 17, the channel program header 20-0 has a channel number 20-0-1 for executing the channel program 20.

  The channel number 20-0-1 is a number for distinguishing the peripheral processing devices 2000 and 3000 connected to the input / output processing device 200 and the connection path. For example, channel numbers 0 to 15 are assigned to the peripheral processing devices 2000 and 3000 connected to the PCIe card 280, and channel numbers 16 to 31 are assigned to the peripheral processing devices 2000 and 3000 connected to the PCIe card 281. Further, channel numbers 32-47 are assigned to the peripheral processing devices 2000, 3000 connected to the PCIe card 282, and channel numbers 48-63 are assigned to the peripheral processing devices 2000, 3000 connected to the PCIe card 283.

  FIG. 18 is an explanatory diagram of an example of a channel command entry. As illustrated in FIG. 18, the channel command entry 20-n includes a command 20-n-1 and a flag 20-n-2 that modifies the command 20-n-1, and a count that stores a transfer count when data is transferred. 20-n-3 and a data transfer destination or data transfer source address 20-n-4 on the main memory 130.

  When the firmware that runs on the processor 220 is instructed to execute the channel program 20 from the arithmetic processing units 110 to 113, the firmware that has been read from the instructed address is executed. The firmware reads the channel program header 20-0 from the address designated first, and identifies the target peripheral processing devices 2000 and 3000 and the PCIe cards 280 to 283 from the channel number 20-0-1.

  Subsequently, the processor 220 reads the channel command entry 20-1 and performs processing corresponding to the command 20-1-1 and the flag 20-1-2. When the process corresponding to one channel command entry 20-n-1 is completed, the firmware reads the next channel command entry 20-n and executes the corresponding process. When all the channel command entries 20-n have been processed, the processor 220 notifies the arithmetic processing units 110 to 113 that the channel program 20 has ended.

  The end notification of the channel program 20 from the input / output processing device 200 to the arithmetic processing devices 110 to 113 is performed when the firmware operating on the processor 220 accesses the IO controller 210 in memory. Specifically, the IO controller 210 notifies the arithmetic processing devices 110 to 113 through the memory controller 120 of the interrupt, thereby giving the end notification. This is a general method and will not be described in detail.

  It is assumed that the channel command entry 20-n indicates an instruction for data transfer from the peripheral processing devices 2000 and 3000 to the main memory 130. In this case, the transfer count is stored in the count 20-n-3 of the channel command entry 20-n, and the address on the main memory 130 of the transfer destination is stored in the address 20-n-4.

  At this time, the processor 220 transfers the data by the count of 20-n-3 to the MMIO space 301 of the IO controller 210 corresponding to the address 20-n-4, and the PCIe corresponding to the channel number 20-0-1. Set to cards 280 to 283, respectively. The processor 220 waits for the completion of the data transfer until there is an interrupt from the PCIe card 280-283.

  For example, in FIG. 15, when the channel number is 0 and the address 20-n-4 is 0x8000FF00, the processor 220 sets the PCIe card 280 to transfer data to the address of 0x8008000FF00.

  The arithmetic processing devices 110 to 113 and the input / output processing device 200 can simultaneously execute a plurality of channel programs 20. The arithmetic processing units 110 to 113 issue instructions to execute other instructions and other channel programs 20 while waiting for the completion of the channel program 20 after instructing the input / output processing unit 200 to execute the channel program 20. Is possible. The input / output processing device 200 may execute the channel command entry 20-n of the other channel program 20 while waiting for the end of the data transfer after giving the data transfer instruction to the PCIe cards 280 to 283. Is possible. In addition, since these execution methods are not the main parts about this invention, detailed description is abbreviate | omitted.

  FIG. 19 is an explanatory diagram illustrating an example of packets transmitted and received. When data transfer is performed using the PCIe I / F, a packet 1 (physical layer packet) illustrated in FIG. 19 is transmitted and received between the PCIe I / Fs. The contents of the PCIe packet are determined for each layer to be processed. The transaction layer packet (TLP) 3 includes Header 3-1, Data 3-2 to be transmitted / received, and ECRC 3-3 for confirming the validity of Header 3-1 and Data 3-2. That is, it can be said that ECRC is given to the transmitted and received packets.

  Packet 2 represents a data link layer packet, and includes Sequence Number 2-1 and LCRC 2-2 in addition to the information included in TLP 3. Packet 1 includes Framing 1-1 and 1-2 in addition to the information included in packet 2.

  FIG. 20 is an explanatory diagram illustrating an example of the Header 3-1 when data is transferred from the PCIe card 280 to 283 to the main memory 130. The header 3-1 includes a format 3-1-1 indicating the format of the transaction layer packet 3 and request contents, a type 3-1-2, a requester ID 3-1-3 indicating a request source, and an address 3 corresponding to the request contents. -1-4.

  For example, in the example shown in FIG. 15, in the case of a memory write request with data, 011b is set to Format3-1-1, and 00000b is set to Type3-1-2. In addition, the bus number and device number of the PCIe card 280 to 283 as a data transmission source are set in the Requester ID 3-1-3, and 0x8008000FF00 is set in the Address 3-1-4.

  The ECRC 3-3 stores a 32-bit CRC (Cyclic Redundancy Code) for guaranteeing data integrity between ends (end-to-end) in the transaction layer. This CRC is written as Transaction Layer end to end 32 bit CRC. Further, this CRC may be referred to as an end-to-end cyclic redundancy check code (ECRC). CRCs are created for Header 3-1 and Data 3-2 at the transmission source of TRP 3, and added to ECRC 3-3 of TRP 3. The added CRC is used to verify the validity of Header 3-1 and Data 3-2 at the reception destination of TRP3. Hereinafter, using the CRC stored in the ECRC 3-3 may be simply referred to as using (using) the ECRC 3-3.

  For example, when data is transferred from the PCIe card 280 to 283 to the main memory 130, the PCIe card 280 to 283 creates a CRC of the transaction layer packet 3 and adds it to the ECRC 3-3. The PCIe port 210-1 of the IO controller 210 that is the transmission destination on the PCIe I / F verifies the validity of the packet received using the ECRC 3-3 of the transaction layer packet 3.

  For example, it is assumed that data corruption of the transaction layer packet 3 occurs in the PCIe switch 240 during data transfer from the PCIe card 280 to 283 to the main memory 130. Even in this case, data corruption can be detected by verifying the transaction layer packet 3 using the ECRC 3-3 on the PCIe port 210-1 of the IO controller 210.

  The PCIe has a function of notifying the root complex of an abnormality when an abnormality is detected by the ECRC 3-3. In the input / output processing device illustrated in FIG. 14, when an abnormality of the ECRC 3-3 is detected at the PCIe port 210-1 of the IO controller 210, an interrupt is notified to the PCIe port 220-2 of the processor 220.

  FIG. 21 is an explanatory diagram of an example of the configuration space of the PCIe port. The PCIe has an Advanced Error Reporting Extended Capability Structure 11 that indicates an abnormal content notified by interruption to the configuration space 10 of the PCIe port.

  FIG. 22 is an explanatory diagram showing the contents of the Advanced Error Reporting Extended Capability Structure. When an abnormality is detected in the ECRC 3-3, an ECRC abnormality is set in the Uncorrectable Error Status Register 11-1 shown in FIG. 22, and the Header 3-1 of the transaction layer packet 3 in which the ECRC abnormality is detected is set in the Header Log Register 11-4. Stored. Since these items are described in detail in the PCIe specification, detailed description is omitted.

  Here, a case where data corruption of the transaction layer packet 3 occurs in the PCIe switch 240 when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130 according to the instruction of the channel command entry 20-n. . When ECRC3-3 is added when the transaction layer packet 3 is transmitted by the PCIe card 280 to 283, the validity of the transaction layer packet 3 is verified by the ECRC3-3 at the PCIe port 210-1 of the IO controller 210. An ECRC abnormality is detected.

  When the PCIe port 210-1 detects an ECRC abnormality, the PCIe port 210-1 stores the header 3-1 of the transaction layer packet 3 in which the abnormality is detected in the Header Log Register 11-4. In addition, the PCIe port 210-1 sets an ECRC abnormality in the Uncorrectable Error Status Register 11-1 illustrated in FIG. 22 and notifies the processor 220 of the interrupt.

  The transaction layer packet 3 in which the ECRC abnormality is detected is discarded, and the garbled data is not transferred to the main memory 130. However, data transfer from the PCIe cards 280 to 283 to the main memory 130 is a posted transaction. Therefore, when viewed from the PCIe cards 280 to 283, the data transfer ends normally, so the firmware (processor 220) is notified that the transfer has ended. Therefore, when viewed from the firmware, it appears that the data transfer has been completed normally.

  On the other hand, when the firmware operating on the processor 220 receives an interrupt corresponding to the ECRC abnormality, the content of the Header Log Register 11-4 is checked to check the header 3-1 of the transaction layer packet 3 in which the ECRC abnormality is detected. Can be confirmed. However, the ECRC abnormality indicates that data corruption has occurred in Header 3-1 and Data 3-2, and therefore the correctness of the contents stored in Header Log Register 11-4 cannot be guaranteed. For this reason, the address command 3-1-4 of the Header 3-1 cannot identify the channel command entry 20-n performing the data transfer in which the ECRC abnormality is detected.

  When an ECRC abnormality is detected when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130 in order to guarantee the validity of the information processing device 1000, it is treated as a failure of the information processing device 1000 for this reason. There is a problem of being done.

  Also, in PCIe, ECRC is generally used to ensure end-to-end data integrity. In the processing circuit described in Patent Document 1, an abnormality of a signal is detected without using ECRC. However, since ECRC is a code generally used in PCIe, the complete data can be obtained while using this ECRC. It is desirable to be able to guarantee the sex.

  Therefore, the present invention provides an input / output processing apparatus and address that can suppress the influence of a failure within a local range even when an abnormal end-to-end cyclic redundancy check code (that is, an ECRC abnormality) is detected during packet transfer. It is an object to provide a validity verification method and an address validity verification program.

An input / output processing device according to the present invention is an input / output processing device using PCI Express, and a processing storage having a transfer area assigned as an area used for the data transfer process to a transfer program for executing the data transfer process Means, an address storage means having a verification area which is an address space specified by address verification information obtained by adding an error correction code of the address to an address indicating a transfer area, and an end-point cyclic redundancy check and address setting means for setting the transfer destination address of the received data parts have been given, when there is access to the verification region by the received data, address or et erroneous Ri correction code of a verification area set in the received data remove and identify the transfer area, use the transfer program is specified transfer area allocated To a data transfer control means for executing data transfer processing of the received data, and a failure detecting means for detecting an abnormality of the attached to the received data end-to-end cyclic redundancy check code, the data transfer control unit, the received data When an abnormality is detected in the end-to-end cyclic redundancy check code, the validity of the transfer area address is verified from the address verification information specified from the address indicating the verification area set in the received data. And

The address validity verification method according to the present invention is an address validity verification method using PCI Express, and indicates a transfer area allocated as an area used for the data transfer process for a transfer program that executes the data transfer process. A second address indicating a verification area which is an address space specified by address verification information generated by adding the error correction code of the first address to the first address is an end-to-end cyclic redundancy check code. set granted destination address of the received data, when there is access to the verification region by receiving data, the transfer area by deleting the second address or et erroneous Ri correction code that has been set in the received data identified, using the transfer program is specified transfer area allocated, performs a data transfer process of the received data, the receiving de Is detected from the second address set in the received data when an abnormality is detected in the end-to-end cyclic redundancy check code assigned to the received data. The validity of the first address is verified from the address verification information.

An address correctness verification program according to the present invention is an address correctness verification program applied to a computer using PCI Express, and the computer transfers the data transfer process to the transfer program for executing the data transfer process. The second address indicating the verification area which is the address space specified by the address verification information generated by adding the error correction code of the first address to the first address indicating the transfer area allocated as the area to be used Address setting processing for setting the address as the transfer destination address of the received data to which the end-to-end cyclic redundancy check code is assigned. When the verification area is accessed by the received data, the second address set in the received data remove the pressurized et erroneous Ri correction code identifies the transfer area, the specified transfer area is assigned The using transfer program, the data transfer control processing for executing data transfer processing of the received data, and, to execute the abnormality detection processing for detecting an abnormality of the attached to the received data end-to-end cyclic redundancy check code, data When an abnormality is detected in the end-to-end cyclic redundancy check code of the received data in the transfer control process, the validity of the first address is determined from the address verification information specified from the second address set in the received data. It is characterized by making it verify.

  According to the present invention, even when an ECRC abnormality is detected during packet transfer, the influence of a failure can be suppressed to a local range.

It is explanatory drawing which shows the example of transfer space. It is explanatory drawing which shows the example of the address format of transfer space. It is explanatory drawing which shows the example of MMIO space. It is explanatory drawing which shows the example of the address format of MMIO space. It is explanatory drawing which shows the structural example of IO controller. It is explanatory drawing which shows the example of a transfer control register. It is explanatory drawing which shows the example of a channel program management table. It is explanatory drawing which shows the example of a transfer space-channel number correspondence table. It is a 1st flowchart which shows the example of the process which performs a channel program. It is a 2nd flowchart which shows the example of the process which performs a channel program. It is a 1st flowchart which shows the operation example at the time of interruption generation | occurrence | production. It is a 2nd flowchart which shows the operation example at the time of interruption generation | occurrence | production. It is a block diagram which shows the outline | summary of the input-output processing apparatus by this invention. It is explanatory drawing which shows the example of information processing apparatus. It is explanatory drawing which shows the example of a method of address conversion. It is explanatory drawing which shows the example of a channel program. It is explanatory drawing which shows the example of a channel program header. It is explanatory drawing which shows the example of a channel command entry. It is explanatory drawing which shows the example of the packet transmitted / received. It is explanatory drawing which shows the example of Header. It is explanatory drawing which shows the example of the configuration space of a PCIe port. It is explanatory drawing which shows the content of Advanced Error Reporting Extended Capability Structure.

  First, an embodiment of an input / output processing apparatus according to the present invention will be described with reference to an information processing apparatus illustrated in FIG. As described above, the input / output processing device 200 according to the present embodiment is a device that includes the PCIe cards 280 to 283, the PCIe switch 240, the IO controller 210, and the processor 220, and executes processing in the channel program method. . In addition, about the part already demonstrated with reference to FIG. 14, description is abbreviate | omitted suitably.

  The PCIe cards 280 to 283 are interfaces for data transfer with the peripheral processing devices 2000 and 3000. The PCIe switch 240 connects the PCIe cards 280 to 283. Specifically, the ports 240-3 to 6 included in the PCIe switch 240 and the ports 280-1 to 283-1 included in the PCIe cards 280 to 283 are connected via the buses 260 to 263.

  The IO controller 210 controls data transfer between the peripheral processing devices 2000 and 3000 and the main memory 130 of the central processing unit 100 via the PCIe cards 280 to 283. The processor 220 controls the IO controller 210 and the PCIe cards 280 to 283. For example, the processor 220 executes each process according to the firmware.

  The IO controller 210 transfers data from the peripheral processing devices 2000 and 3000 to the main memory 130. The IO controller 210 receives a MMIO access from the PCIe cards 280 to 283 during data transfer, and a plurality of fixed-length transfer spaces 400 (not shown in FIG. 14) for transferring data to the main memory 130. Inside. Hereinafter, in order to identify p spaces assigned to the transfer space 400, each assigned transfer space is taken as the transfer space 400-p. The transfer space 400 is realized by, for example, a memory having an area for storing each transfer space.

  Further, the IO controller 210 has a conversion mechanism (not shown in FIG. 14) that performs address conversion between the input / output processing device 200 and the main memory 130 for each transfer space 400-p. The IO controller 210 has an MMIO space 300 (not shown in FIG. 14) in which 8-bit ECC is added to the address of the transfer space 400-p. In addition, when the IO controller 210 (more specifically, the conversion mechanism) accesses the MMIO space 300 from the PCIe card 280 to 283, the access is specified by deleting the added ECC (Error Correction Code). Has a function of processing as an access to the transfer space 400-p.

  When the input / output processing device 200 executes the channel program 20 for transferring data from the peripheral processing devices 2000 and 3000 to the main memory 130, one of the transfer spaces 400 -p is transferred to the channel program 20. Assign to.

  When performing the data transfer, the input / output processing device 200 adds an ECC for the address to the address of the transfer space 400-p to make the address of the MMIO space 300. The input / output processing device 200 sets the address of the MMIO space 300 as a transfer destination address in the PCIe card 280 to 283 and performs data transfer.

  These processes are described in, for example, firmware, and the processor 220 operates according to the firmware. The MMIO space 300 is realized by, for example, a memory having an area for storing information (hereinafter also referred to as address verification information) to which the address and ECC of the transfer space 400-p are added.

  Further, the input / output processing device 200 identifies the channel program 20 that performs data transfer using the transfer space 400-p.

  The IO controller 210 detects the presence or absence of an ECRC abnormality when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130. When the ECRC abnormality is detected, the processor 220 reads the transfer destination Address 3-1-4 from the Header Log Register 11-4 in the PCI config space of the IO controller 210. If the address 3-1-4 is within the range of the MMIO space 300, the processor 220 extracts the ECC from the address 3-1-4 and verifies the validity of the address 3-1-4. If the validity can be verified, the processor 220 obtains the transfer space 400-p from the address 3-1-4, and specifies the channel program using the transfer space 400-p. Then, the processor 220 re-executes the channel program. These processes are described in, for example, firmware, and the processor 220 operates according to the firmware.

  Hereinafter, specific contents of each component will be described. FIG. 1 is an explanatory diagram showing an example of the transfer space 400. In the following description, it is assumed that the input / output processing apparatus of the present invention uses the transfer space illustrated in FIG.

  As illustrated in FIG. 1, the transfer space 400 used by the IO controller 210 for data transfer of the PCIe port 210-1 is divided into a plurality of fixed-length transfer spaces 400-p. In the example shown in FIG. 1, the transfer space 400 is divided into 64 pieces. The firmware performs control to allocate one channel program 20 to each transfer space 400-p. In the example shown in FIG. 1, the size of the transfer space 400-p is 4 MB.

  FIG. 2 is an explanatory diagram showing an example of the address format of the transfer space 400. By dividing the transfer space 400 into a plurality of fixed-length transfer spaces 400-p, the address format 410 of the transfer space 400 is represented in the format illustrated in FIG. Base Address 410-1 is a base address of the transfer space 400. The transfer space number 410-3 indicates the number p corresponding to the transfer space 400-p. Offset 410-4 indicates an offset within the transfer space 400-p. In the example shown in FIG. 1, Base Address 410-1 is set to 0x800000000000000.

  A transfer space 400 illustrated in FIG. 1 is an address space inside the IO controller 210. FIG. 3 is an explanatory diagram showing an example of the MMIO space. FIG. 4 is an explanatory diagram showing an example of the address format of the MMIO space. The example shown in FIG. 3 shows the MMIO space 300 in the PCIe port 210-1 of the IO controller 210.

  The address format 310 of the MMIO space is a format in which ECC 310-2 is added to the address format 410 of the transfer space. The firmware calculates the ECC 310-2 from the address expressed in the transfer space address format 410, and stores the calculated ECC 310-2 in the third byte of the transfer space address format 410 so as to be the MMIO space address format 310. Set.

  Since the value of the ECC 310-2 changes according to the original transfer space address, for example, the MMIO space 300 has a range from 0x800000000000000 to 0x80FFFFFFFFFF with respect to the transfer space 400 illustrated in FIG.

  FIG. 5 is an explanatory diagram illustrating a configuration example of the IO controller 210 of the present embodiment. The IO controller 210 includes a conversion mechanism 500 that converts the address space of the bus 160 and the PCIe I / F 252 and the bus I / F when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130.

  FIG. 6 is an explanatory diagram showing an example of the transfer control register. The conversion mechanism 500 includes a transfer control register 510 illustrated in FIG. The transfer control register 510 is provided with a transfer control register corresponding to each transfer space 400-p in order to perform data transfer corresponding to the plurality of transfer spaces 400-p. Hereinafter, a transfer control register corresponding to each transfer space 400-p is referred to as a transfer control register 510-p.

  The transfer control register 510-p includes an address 510-p-1 for storing a base address on the main memory 130 as a transfer destination, a count 510-p-2 for storing a count to be transferred, and a flag 510-p- for controlling transfer. 3 is provided. FIG. 5 shows an example of the 0th transfer control register 510-0.

  The relationship among the MMIO space 300, the transfer space 400, the conversion mechanism 510, and the transfer control register 510 of the IO controller 210 when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130 will be described with reference to FIG.

  The PCIe I / F 252 transfers data to the address 303 in the MMIO space 300. When accessed to the MMIO space 300, the IO controller 210 removes the ECC 310-2 from the address 303 expressed in the address format 310 of the MMIO space and generates an address 304 converted into the address format 410 of the transfer space.

  Then, the IO controller 210 obtains the address of the corresponding transfer space 400-p from the address 304. The conversion mechanism 500 reads the value of the transfer control register 510-p corresponding to the transfer space 400-p. The conversion mechanism 500 sets a value obtained by adding the offset 410-4 of the address 304 and the address 510-p-1 as the address of the main memory space 131. Then, the conversion mechanism 500 accesses the main memory 130 using this address.

  In the example shown in FIG. 5, if the address 303 is 0x80xxx000zzzz, the address 304 with the ECC 310-2 removed is 0x8000000zzzz, and the transfer space number is 0. In this case, the transfer space number 400-0 is selected, and the conversion mechanism 510 selects the transfer control register 510-0, and adds the address 133-0-1 and the offset 410-4 of the address 304 to the main memory 130. Use as an address to access.

  The firmware operating on the processor 220 has a channel program management table for managing the execution of the channel program 20 for each channel number in the local memory 230. FIG. 7 is an explanatory diagram showing an example of the channel program management table. For example, the firmware manages the execution of the channel program 20 using the channel program management table 30 illustrated in FIG.

  The channel program management table 30 illustrated in FIG. 7 includes an address 30-m-1 of the channel program header being executed with the channel number m, an address 30-m-2 of the channel command entry being currently executed, A transfer space number 30-m-3 used for data transfer and a Flag 30-m-4 for storing the execution state of the channel program 20 are stored. Note that the channel program management table 30 illustrated in FIG. 7 assumes 64 channels.

  The firmware also has a transfer space-channel number correspondence table for managing the channel number m of the channel program 20 in the local memory 230. FIG. 8 is an explanatory diagram showing an example of a transfer space-channel number correspondence table. The transfer space-channel number correspondence table 40 illustrated in FIG. 8 manages the channel number m of the channel program 20 performing data transfer using the transfer space 400-p for each transfer space 400-p. For example, the firmware manages the channel number m of the channel program 20 using the transfer space-channel number correspondence table illustrated in FIG.

  The transfer space-channel number correspondence table 40 illustrated in FIG. 8 includes a flag 40-p-1 for storing the use state of the transfer space 400-p and a channel program that performs data transfer using the transfer space 400-p. 20 includes a channel number 40-p-2 for storing a channel number m corresponding to 20. Note that the transfer space-channel number correspondence table 40 illustrated in FIG. 8 also assumes 64 channels.

  9 and 10 are flowcharts showing an example of processing for executing a channel program. Here, some of the features of the present invention will be described, and a detailed description will be given later.

  The firmware (processor 220) executes the channel program 20 according to instructions from the arithmetic processing units 110 to 113. In the following description, the processing illustrated in FIGS. 9 and 10 may be referred to as channel program execution processing.

  The processor 220 reads the addresses 20-n-4 and counts 20-n-3 of the channel command entry 20-n, and addresses 510-p-1 and counts 510-p-2 of the transfer control register 510-p corresponding to the transfer space 400-p. Set to. Further, the processor 220 sets Flag 510-p-3 to transfer-enabled. This process is described in step S60-10 in FIG.

  Further, the processor 220 obtains the address a of the transfer space 400-p using the address represented by the address format 410 of the transfer space. Further, the processor 220 obtains an ECC using a SECDED (single-error-correcting and double-error-detecting code) code for the obtained address a. The processor 220 adds the obtained ECC to the third byte of the address a, and converts it to the address c which is the address format 310 of the MMIO space. This process is described in step S60-10 in FIG.

  Further, the processor 220 sets the address c as a transfer address to the PCIe cards 280 to 283 corresponding to the channel number 20-0-1, and starts data transfer. This process is described in step S60-11 in FIG.

  Further, in the channel program execution process, the processor 220 makes unused Flag 510-p-2 of the transfer control register 510-p and Flag 40-p-1 of the transfer space-channel number correspondence table 40-p after the data transfer ends. Set. This process is described in step S60-13 in FIG.

  Further, the processor 220 reads out Flag30-m-4 of the channel program management table 30-m and checks whether a failure has occurred. If a failure has occurred, the processor 220 adds 16 to the channel program header address 30-m-1 to determine the address of the first channel command entry 20-1. The processor 220 stores the address in the executing channel command entry address 30-m-2 and resets Flag 30-m-4 to retry the channel program. These processes are described in steps S60-14 to 16 in FIG.

  In the channel program execution process, the processor 220 checks Flag 510-p-2 of the transfer control register 510 when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130 according to the channel command entry 20-n. . The processor 220 obtains an unused transfer space p and sets Flag 510-p-2 in use. This process is described in step S60-6 in FIG.

  Further, the processor 220 stores the channel number 20-0-1 of the channel program 20 in the channel number 40-p-2 of the transfer space-channel number correspondence table 40-p corresponding to the transfer space, and Flag 40-p- Set 1 during use. This process is described in step 60-7 in FIG.

  Here, some of the features of the present invention have been described with reference to FIGS. 9 and 10. A description of the entire processing illustrated in FIGS. 9 and 10 will be described later.

  11 and 12 are flowcharts showing an operation example when an interrupt occurs. In the following description, the process illustrated in FIGS. 11 and 12 may be referred to as an interrupt process.

  In the interrupt process 70, the processor 220 determines whether or not the interrupt from the IO controller 210 is an ECRC abnormality detection of the PCIe port 210-1. When the ECRC abnormality is detected, the processor 220 reads out the Header Log Register 11-4, confirms the Format 3-1-1 and Type 3-1-2, and confirms whether the request in which the ECRC abnormality has occurred is the Memory Write. . This process is described in steps S70-8 and 9 in FIG.

  If the ECRC error request is Memory Write, the processor 220 confirms whether the Address 3-1-4 of the Header Log Register 11-4 is within the range of the MMIO space 300 of the IO controller 210. This process is described in steps S70-10 and 11 in FIG.

  When the address 3-1-4 is within the range of the MMIO space 300, the processor 220 determines that the address 3-1-4 is an address of the MMIO space address format 310, and the ECC 310-2 and the transfer space address format 410. To address c. Then, the processor 220 checks whether there is an error in the address c using the ECC 310-2. This process is described in steps S70-12 and 13 in FIG.

  If there is no error in the address c, the processor 220 determines that the address c is in the transfer space address format, obtains the transfer space 400-p, and transfers the transfer space-channel corresponding to the transfer space 400-p. The channel number 40-p-2 is read from the number correspondence table 40-p. This process is described in step S70-14 in FIG.

  Then, the processor 220 sets a failure state in Flag 30-m-4 of the channel program management table 30-m corresponding to the channel number 40-p-2. This process is described in step S70-15 in FIG.

  Here, some of the features of the present invention have been described with reference to FIGS. 11 and 12. The description of the entire process illustrated in FIGS. 11 and 12 will be described later.

  Next, an operation example of the input / output processing apparatus according to the present invention will be described with reference to FIGS. 9, 10, 11 and 12. FIG. First, with reference to FIG. 9 and FIG. 10, an operation when the arithmetic processing devices 110 to 113 give an instruction to transfer data from the peripheral processing devices 2000 and 3000 to the main memory 130 to the input / output processing device 200 will be described. To do.

  Prior to the processing illustrated in FIG. 9, the arithmetic processing devices 110 to 113 create a channel program 20 for transferring data from the peripheral processing devices 2000 and 3000 to the main memory 130 and store the channel program 20 in the main memory 130. . The arithmetic processing devices 110 to 113 specify the address where the channel program 20 is stored and instruct the input / output processing device 200 to execute the channel program 20.

  When the input / output processing device 200 is instructed to execute the channel program by the arithmetic processing devices 110 to 113, the firmware operating on the processor 220 executes the channel program execution processing illustrated in FIG. 9 and FIG.

  In the channel program execution process, first, the processor 220 reads the channel program header 20-0 of the channel program 20 from the address notified from the arithmetic processing units 110 to 113 (step S60-1). The processor 220 extracts the channel number 20-0-1 from the channel program header 20-0, and is notified from the arithmetic processing units 110 to 113 to the channel program header address 30-m-1 of the corresponding channel program management table 30-m. The stored address is stored (step S60-2).

  The processor 220 adds 16 to the channel program header address 30-m-1 to obtain the address of the channel command entry 20-1, and stores it in the executing channel command entry address 30-m-2 (step S60-3). .

  The processor 220 reads the channel command entry 20-n from the address indicated by the channel command entry 30-m-2 being executed, and checks the contents of the Command 20-n-1 (step S60-4).

  When the content of Command 20-n-1 is a data transfer instruction from the peripheral processing devices 2000 and 3000 to the main memory 130 (Yes in step S60-5), the processor 220 performs the following processing. The processor 220 confirms Flag 510-p-2 of the transfer control register 510-p of the IO controller 210 to perform data transfer, and obtains an unused transfer space 400-p. The processor 220 sets the flag 510-p-2 of the transfer space 400-p to be in use (step S60-6).

  The processor 220 sets the channel number 20-0-1 to the channel number 40-p-2 of the transfer space-channel number management table 40-p corresponding to the transfer space 400-p, and uses the Flag 40-p-1. (Step S60-7). Then, the processor 220 stores the transfer space number p in the transfer space number 30-m-2 of the channel program management table 30-m (step S60-8).

  Further, the processor 220 transfers the address 20-n-4 and the count 20-n-3 of the channel command entry 20-n to the transfer control register 510-p corresponding to the transfer space 400-p in order to transfer data to the main memory 130. p is stored in Address 510-p-1 and Count 510-p-2. Then, the processor 220 sets the flag 510-p-3 to transfer valid so that data can be transferred (step S60-9).

  The processor 220 obtains the head address a of the transfer space 400-p in the transfer space address format 410. Further, the processor 220 obtains an 8-bit ECC b for the address a using a SECDED code. The processor 220 obtains an address c by adding ECC b to the address a so as to be an address in the MMIO space address format 310 of the IO controller 210 (step S60-10).

  The processor 220 sets an address c as a data transfer destination address to the PCIe cards 280 to 283 corresponding to the channel number 20-m−1, and starts data transfer processing (step S60-11).

  With the above processing, data transfer from the peripheral processing devices 2000 and 3000 to the main memory 130 is started by the PCIe cards 280 to 283.

  When the data transfer is completed, the PCIe cards 280 to 283 notify the processor 220 that is executed according to the firmware that the data transfer has been completed. In the channel program execution process, the processor 220 (firmware) waits for the interrupt. That is, the processor 220 waits for the end of data transfer (step S60-12).

  When the data transfer is completed, in the channel program execution process, the processor 220 executes Flag 510-p-2 in the transfer control register 510-p of the IO controller 210 and Flag 40-m-1 in the transfer space-channel number management table 40-m. Is set to an unused state (step S60-13).

  The processor 220 reads Flag30-m-4 in the channel program management table 30-m and checks whether or not a failure has occurred (step S60-14). Here, it is assumed that no failure has occurred and no failure state is set in Flag 30-m-4 (No in step S60-15). In this case, the processor 220 confirms Flag 20-n-2 of the channel command entry 20-n, and confirms whether or not the channel program 20 has ended (step S60-18).

  If the channel program 20 has not ended (No in step S60-19), the processor 220 stores a value obtained by adding 16 to the channel command entry address 30-m-2 being executed in the channel program management table 30-m. (Step S60-20). Then, the processor 220 returns to the process of step S60-4 and processes the channel command entry 20-n.

  On the other hand, when the channel program 20 has ended (Yes in step S60-19), the processor 220 reports the end of the channel program 20 to the arithmetic processing units 110 to 113 (step S60-21).

  Next, referring to FIG. 11 and FIG. 12, when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130, data corruption occurs in the PCIe switch 240, and the PCIe port 210-1 of the IO controller 210. The operation when an ECRC abnormality is detected will be described.

  When the ECRC abnormality is detected at the PCIe port 210-1 of the IO controller 210 before the processing illustrated in FIG. 11, the IO controller 210 detects the ECRC abnormality by interrupting it to the processor 220 (firmware). Notify you. When the interrupt is notified, the processor 220 executes an interrupt process according to the firmware.

  First, the processor 220 reads the interrupt factor from the Config space of the PCIe port 220-2, and checks whether the interrupt factor is a failure notification from the PCIe port 210-1 of the IO controller 210 (step S70-1). This can be determined by checking the values of the Root Error Register and Error Source Identification Register.

  When the interrupt factor is a failure notification from the PCIe port 210-1 of the IO controller 210 (Yes in step S70-2), the processor 220 clears the failure factor of the PCIe port 220-2 (step S70-3). . The processor 220 reads the value of the Uncorrectable Error Status Register 11-1 from the Config space of the PCIe port 210-1 of the IO controller 210, and confirms whether the failure factor bx is an ECRC abnormality (step S70-4).

  If the failure factor bx is an ECRC abnormality (Yes in step S70-5), the processor 220 clears the ECRC abnormality factor of the Uncorrectable Error Status Register 11-1 of the PCIe port 210-1 of the IO controller 210 (step S70-6). ).

  The processor 220 reads Format3-1-1, Type3-1-2 and Address3-1-4 from the Header Log Register 11-4 (step S70-7), and confirms whether the request having an ECRC error is a Memory Write ( Step S70-8).

  If the ECRC request is a Memory Write (Yes in step S70-9), the processor 220 confirms that the address 3-1-4 is within the range of the MMIO space 300 of the IO controller 210 (step S70-10). .

  When the address 3-1-4 is within the range of the MMIO space 300 (Yes in step S70-11), the processor 220 changes the address 3-1-4 to the ECC 310-2 in order to make the MMIO space address format 310 of the IO controller 210. And the address c of the transfer space address format 410. Then, the processor 220 checks whether there is an error in the address c based on the ECC 310-2 (step S70-12).

  If there is no error in the address c (Yes in step S70-13), the processor 220 obtains the transfer space 400-p from the address c, and the channel number of the transfer space-channel number management table 40-p corresponding to the transfer space. The channel number m executing the channel program 20 in which the ECRC abnormality is detected is read from 40-p-2 (step S70-14).

  Then, the processor 220 sets a failure state in Flag 30-m-4 of the channel program management table 30-m corresponding to the channel number m (step S70-15). The processor 220 returns to step S70-4. Here, when the failure factor bx is not an ECRC abnormality (No in step S70-5), the processor 220 confirms another failure factor bx and performs a corresponding process (step S70-17). Thereafter, when there is no failure factor, the processor 220 ends the interrupt process.

  On the other hand, assume that the interrupt factor is not a failure notification from the PCIe port 210-1 of the IO controller 210 in step S70-2. In this case (No in step S70-2), the processor 220 performs corresponding processing according to the interrupt factor ax (step S70-16). Thereafter, when there is no failure factor, the processor 220 ends the interrupt process.

  In step S70-5, if the failure factor bx is not an ECRC abnormality (No in step S70-5), as described above, the processor 220 performs corresponding processing according to the failure factor bx (step S70-17). ). Thereafter, when there is no failure factor, the processor 220 ends the interrupt process.

  In step S70-9, the request in which the ECRC is abnormal is not Memory Write (No in step S70-9), or in step S70-11, Address 3-1-4 is not within the range of the MMIO space 300. (No in step S70-11) or it is assumed that there is an error in address c in step S17-13 (No in step S70-13). In this case, each of the processors 220 processes as a failure of the input / output processing device 200 (steps S70-18, 70-19, 70-20).

  In the channel program execution processing, after completion of data transfer by the PCIe cards 280 to 283, the processor 220 checks the Flag 30-m-4 in the channel program management table 30-m to check whether a failure has occurred. Is performed (see step S60-14).

  When a failure occurs, a failure state is set in Flag 30-m-4 of the channel program management table 30-m that manages the execution of the channel program 20 corresponding to the transaction layer packet 3 in which the ECRC abnormality occurred by the interrupt process. ing. Therefore, the processor 220 can recognize the occurrence of the failure (see step S60-15).

  The processor 220 stores the address obtained by adding 16 to the channel program header address 30-m-1 of the channel program management table 30-m in the executing channel command entry address 30-m-2 and clears Flag 30-m-4. To do. Thereafter, returning to step 60-4, the processor 220 re-executes the channel program 20, so that the influence of the failure can be suppressed to a local range even when an ECRC abnormality is detected during packet transfer. .

  As described above, according to the present embodiment, the input / output processing device includes the transfer space 400-p and the MMIO space 300. The transfer space 400-p has an area to which a channel program for executing data transfer processing is assigned. The MMIO space 300 has an area for storing information (address verification information) obtained by adding ECC to the address of the transfer space 400-p.

  Then, the processor 220 causes the PCIe cards 280 to 283 to set the address of the MMIO space 300 to Address 3-1-4 in the transaction layer packet 3 of the received data to which ECRC is assigned. Specifically, the processor 220 adds an ECC for the address to the address of the transfer space 400-p to make the address of the MMIO space 300. This address is set in the PCIe cards 280 to 283 to perform data transfer.

  The processor 220 identifies address verification information (that is, the address and ECC of the transfer space 400-p) from the address of the MMIO space 300 set in the received data. The processor executes the data transfer process of the received data by deleting the ECC from the address verification information and specifying the program in the transfer space 400-p.

  Here, when the processor 220 (specifically, the IO controller 210) detects an ECRC abnormality of the received data, the transfer space is determined from the address verification information specified from the address of the MMIO space 300 set in the received data. Validate the 400-p address.

  With the above configuration, even when an ECRC abnormality is detected during packet transfer, the influence of the failure can be suppressed to a local range.

  That is, in this embodiment, when data is transferred from the peripheral processing devices 2000 and 3000 to the main memory 130, the processor 220 adds ECC to the transfer address set by the PCIe card 280 to 283. Therefore, even if an ECRC abnormality occurs in the PCIe port 210-1 of the IO controller 210, the validity of the Address 3-1-4 can be confirmed by checking the ECC of the Address 3-1-4 stored in the Header Log Register 11-4. Can be verified.

  Further, for example, when a general method is used, even if Address 3-1-4 is normal, if a plurality of channel programs 20 are transferring data to the same address in main memory 130, Address 3- The channel program 20 corresponding to 1-4 cannot be specified. Therefore, the program cannot be relieved by a retry process.

  However, in this embodiment, the transfer space 400 of the IO controller 210 is divided into a plurality of transfer spaces 410-p, and the transfer space 410-p is assigned to each channel program. Therefore, it becomes possible to identify the channel program 20 in which the ECRC has become abnormal based on the normal Address 3-1-4. Therefore, even if an ECRC abnormality is detected, the channel program 20 can be re-executed, so that the data transfer process can be remedied without causing a failure of the information processing apparatus 1000 as a whole.

  Next, the outline of the present invention will be described. FIG. 13 is a block diagram showing an outline of the input / output processing apparatus according to the present invention. The input / output processing device according to the present invention has a processing storage means 81 (for example, transfer space 400) having a transfer area to which a program for executing data transfer processing (for example, channel program 20) is assigned, and an address (for example, transfer area) Address storage means 82 (for example, MIMO space 300) having a verification area for storing address verification information obtained by adding an error correction code (for example, ECC 310-2) of the address to address format 410), and an address indicating the verification area And address setting means 83 (for example, processor 220, PCIe card 280 to 283) for setting the received data transfer destination address (for example, Address 3-1-4) to which end-to-end cyclic redundancy check code (ECRC) is assigned, From the address indicating the verification area set in the received data. Data transfer control means 84 (for example, processor 220) that executes data transfer processing of received data by specifying address verification information, deleting an error correction code from the address verification information, and specifying a transfer area program; And an abnormality detecting means 85 (for example, an IO controller 210) for detecting an abnormality of the end-to-end cyclic redundancy check code (ECRC) given to the received data.

  When an abnormality is detected in the end-to-end cyclic redundancy check code of the received data, the data transfer control means 84 determines the address of the transfer area from the address verification information specified from the address indicating the verification area set in the received data. Verify the validity of.

  With such a configuration, even if an ECRC abnormality is detected during packet transfer, the influence of the failure can be suppressed to a local range.

  Specifically, the data transfer control means 84, when an abnormality is detected in the end-to-end cyclic redundancy check code of the received data, the address indicating the verification area set in the received data is a predetermined range indicating the verification area. The address verification information may be specified from the address indicating the verification area.

  The data transfer control unit 84 may verify the validity of the address in the transfer area using the error correction code included in the specified address verification information.

  Further, the process storage unit 81 may have a transfer area assigned for each transfer program. Then, the data transfer control means 84 may re-execute the data transfer process of the received data according to the transfer program specified from the address of the transfer area whose validity has been verified.

  According to such a configuration, it is possible to identify a transfer program (channel program) in which an ECRC abnormality occurred based on the address of the transfer area determined to be normal. Since the transfer program (channel program) can be re-executed even when an ECRC abnormality is detected, the data transfer process can be remedied without causing a failure of the entire information processing apparatus.

  Further, the input / output processing device may include code adding means (for example, PCIe cards 280 to 283) for adding an end-to-end cyclic redundancy check code to the received data.

DESCRIPTION OF SYMBOLS 100 Central processing unit 110-113 Arithmetic processing unit 120 Memory controller 130 Main memory 200 Input / output processing unit 210 IO controller 220 Processor 230 Local memory 240 PCIe switch 280-283 PCIe card 300 MMIO space 400 Transfer space 1000 Information processing device 2000, 3000 Peripheral processing equipment

Claims (9)

An input / output processing device using PCI Express,
A process storage means having a transfer area assigned as an area to be used for the data transfer process for the transfer program for executing the data transfer process ;
Address storage means having a verification area which is an address space specified by address verification information obtained by adding an error correction code of the address to an address indicating the transfer area;
An address setting means for setting an address indicating the verification area as a transfer destination address of received data to which an end-to-end cyclic redundancy check code is assigned;
When there is access to the verification region by said received data, address of a verification area set in the received data or et previous SL to remove the error correction code to identify the transfer region, the identified transfer region Data transfer control means for executing data transfer processing of received data using the assigned transfer program ;
An abnormality detecting means for detecting an abnormality of the end-to-end cyclic redundancy check code given to the received data;
The data transfer control means, when an abnormality is detected in the end-to-end cyclic redundancy check code of the received data, from the address verification information specified from the address indicating the verification area set in the received data, the transfer An input / output processing device characterized by verifying the validity of an area address. The data transfer control means, when an abnormality is detected in the end-to-end cyclic redundancy check code of the received data, when the address indicating the verification area set in the received data is within a predetermined range indicating the verification area The input / output processing device according to claim 1, wherein address verification information is specified from an address indicating the verification area. The input / output processing apparatus according to claim 2, wherein the data transfer control means verifies the validity of the address in the transfer area using an error correction code included in the specified address verification information. The processing storage means has a transfer area allocated for each transfer program,
The data transfer control means re-executes the data transfer processing of the received data according to a transfer program specified from the address of the transfer area whose validity is verified. I / O processing unit. The input / output processing device according to any one of claims 1 to 4, further comprising: a code adding unit that adds an end-to-end cyclic redundancy check code to the received data. An address validity verification method using PCI Express,
Address verification generated by adding an error correction code of the first address to a first address indicating a transfer area allocated as an area used for the data transfer process for a transfer program that executes the data transfer process A second address indicating a verification area which is an address space specified by the information is set as a transfer destination address of the received data to which the end-to-end cyclic redundancy check code is assigned;
When there is access to the verification region by said received data, said set in the received data a second address or found before Symbol remove the error correction code to identify the transfer region, the identified transfer region Using the assigned transfer program , execute the data transfer process of the received data,
Detecting an abnormality of the end-to-end cyclic redundancy check code attached to the received data;
When an abnormality is detected in the end-to-end cyclic redundancy check code of the received data, the validity of the first address is verified from the address verification information specified from the second address set in the received data An address validity verification method characterized by: When an error is detected in the end-to-end cyclic redundancy check code of received data, the verification area is indicated when the address indicating the verification area set in the received data is within a predetermined range indicating the verification area The address validity verification method according to claim 6, wherein address verification information is specified from an address. An address validity verification program applied to a computer using PCI Express,
In the computer,
Address verification generated by adding an error correction code of the first address to a first address indicating a transfer area allocated as an area used for the data transfer process for a transfer program that executes the data transfer process An address setting process for setting a second address indicating a verification area, which is an address space specified by information , to a transfer destination address of received data to which an end-to-end cyclic redundancy check code is assigned;
When there is access to the verification region by said received data, said set in the received data a second address or found before Symbol remove the error correction code to identify the transfer region, the identified transfer region A data transfer control process for executing a data transfer process of received data using the assigned transfer program ; and
An abnormality detection process for detecting an abnormality of the end-to-end cyclic redundancy check code attached to the received data is performed,
When an abnormality is detected in the end-to-end cyclic redundancy check code of the received data in the data transfer control process, from the address verification information specified from the second address set in the received data, the first Address validity verification program to verify the validity of the address. On the computer,
When an error is detected in the end-to-end cyclic redundancy check code of the received data in the data transfer control process, and the address indicating the verification area set in the received data is within a predetermined range indicating the verification area The address validity verification program according to claim 8, wherein address verification information is specified from an address indicating the verification area.

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