JP5905752B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor integrated circuit of SOI (S ilicon O n I nsulator ) structure, particularly by easy manufacturing process in a semiconductor substrate (bulk wafer) to form a low-cost of the SOI substrate, in this SOI substrate, high-speed, The present invention relates to the formation of a high-performance, high-reliability, and highly-integrated CMOS semiconductor integrated circuit.

FIG. 30 is a memory cell circuit diagram of a CMOS type SRAM (Static Random Access Memory), FIG. 31 is a schematic plan view of a conventional semiconductor device (CMOS type SRAM), and FIG. 32 is a schematic side sectional view of the conventional semiconductor device (CMOS type). It is a pp arrow sectional drawing of SRAM.
In FIG. 30, two P-channel MIS field-effect transistors and two N-channel MIS field-effect transistors form an information holding flip-flop, and two N-channel MIS field-effect transistors read or 1 shows a circuit diagram of a conventional CMOS SRAM memory cell comprising a write word transistor. FIG.
FIG. 31 is a plan view in which the CMOS SRAM memory cell of FIG. 30 is patterned with two conventional P-channel MIS field-effect transistors and four conventional N-channel MIS field-effect transistors. 32 shows a cross-sectional view of the CMOS type SRAM of FIG. 31 taken along the line p-p, where 61 is an n-type silicon substrate, 62 is a p-type impurity well region, 63 is a p ⁺ -type impurity well contact region, 64 is an n ⁺ type substrate contact region, 65 is a shallow trench isolation region, 66 is an n ⁺ type source region, 67 is an n type source region, 68 is an n type drain region, 69 is an n ⁺ type drain region, and 70 is p. ⁺ -type source region, the ^{p +} -type drain region 71, 72 is a gate oxide film, 73 gate electrode, the sidewall 74, 75 is a PSG film, 76 Edge film, 77 is a barrier metal, 78 is a conductive plug, 79 is an interlayer insulating film, 80 is a barrier metal, 81 is a first layer wiring, 82 is a barrier insulating film, 83 is an interlayer insulating film, 84 is a barrier metal, 85 Is a conductive plug, 86 is an insulating film, 87 is an interlayer insulating film, 88 is a barrier metal, 89 is a second layer wiring, 90 is a barrier insulating film, WL is a word line, BL is a bit line, VDD is a power supply voltage, VSS Indicates the ground voltage.
In FIG. 32, a gate electrode 73 is provided on a p-type impurity well region 62 selectively formed on an n-type silicon substrate 61 via a gate oxide film 72. 74, an n-type source region 67 and an n-type drain region 68 are self-aligned with the gate electrode 73 in the p-type impurity well region 62, and an n ⁺ -type drain region 69 is self-aligned with the sidewall 74. And a common n ⁺ -type source region 66, each having two conventional lateral N-channel MIS field-effect transistors forming part of a flip-flop, each having a read or write word transistor (also customary two lateral n-channel MIS field-effect transistor) is, n ⁺ -type source connected to the bit line Only the region 66 is shown (not shown, but the two P-channel MIS field-effect transistors forming part of the flip-flop are also selectively formed on the n-type silicon substrate 61. It is composed of a lateral MIS field effect transistor.) A CMOS SRAM memory cell composed of 6 elements is formed by appropriate connection by two layers of wiring.
Each region is miniaturized, and an n ⁺ -type source region or a p ⁺ -type source region common to two N-channel MIS field-effect transistors or two P-channel MIS field-effect transistors forming a flip-flop is provided. Although high integration is achieved by appropriately wiring using two-layer wiring, etc., the source / drain regions and the gate electrodes of the MIS field effect transistors must be provided with their respective occupied areas. It was difficult to achieve high integration because it was necessary.
In addition, since the source / drain region is directly provided in the semiconductor substrate or the impurity well region, a large junction capacitance is added, which makes it difficult to increase the speed.
Further, since the channel region can be formed only on the surface of the semiconductor substrate or the impurity well region, there is a disadvantage that the speeding up cannot be achieved although the channel length is reduced.
In addition, since the source / drain regions of all MIS field effect transistors are provided in the semiconductor substrate or the impurity well region formed in the semiconductor substrate, malfunction of the memory due to high voltage noise generated in the semiconductor substrate due to static electricity or the like, or latch specific to CMOS There was also a drawback that it was weak to the up characteristic.

JP2003-68883A

The problem to be solved by the present invention, as shown in the conventional example,
(1) Since the source / drain region and the gate electrode of the MIS field effect transistor to be used have to be provided with respective occupied areas, it is difficult to achieve high integration.
(2) Since the source / drain region is directly provided in the semiconductor substrate or the impurity well region, a large junction capacitance is added, and it is difficult to increase the speed.
(3) Since the channel region can be formed only on the surface of the semiconductor substrate or the impurity well region, speeding up was not achieved although the channel length was reduced.
(4) Since the source / drain regions of all the MIS field effect transistors are provided in the semiconductor substrate or the impurity well region formed in the semiconductor substrate, the malfunction of the memory due to high voltage noise generated in the semiconductor substrate due to static electricity or the like The latch-up characteristics could not be prevented.
Such problems are becoming more prominent, and it has become difficult to achieve higher speed, higher performance, higher reliability, and higher integration simply by forming a fine MIS field-effect transistor with the current technology. is there.

The above-described problem surrounds the first semiconductor layer provided in a parallel (lateral) direction to the main surface of the semiconductor substrate and the entire periphery of a part of the first semiconductor layer via the first gate insulating film. A first gate electrode (enclosed gate electrode) having the same gate length around the entire periphery, and an impurity provided in the first semiconductor layer, self-aligned with the first gate electrode (enclosed gate electrode) A lateral (horizontal) driving MIS field effect transistor comprising: a source / drain region comprising: a second semiconductor layer provided in a vertical (vertical) direction on the remaining portion of the first semiconductor layer; A second gate electrode (enclosed gate electrode) having an equal gate length surrounding all sides of the second semiconductor layer with a second gate insulating film interposed therebetween; and an upper portion of the second semiconductor layer and it from impurities provided relative to the lower And source and drain regions, and a vertical (perpendicular direction) driving the MIS field-effect transistor consisting of, is solved by a semiconductor device of the present invention which is provided via an insulating film on the semiconductor substrate.

As described above, according to the present invention, two kinds of lateral (horizontal) direction epitaxial Si layers formed on a semiconductor substrate through an insulating film by an easy process using a normal inexpensive semiconductor substrate. Is formed as a SOI substrate (fully depleted), and a lateral (horizontal) epitaxial Si layer and a longitudinal (vertical) epitaxial Si layer are used as SOI substrates (fully depleted). Since the vertical (vertical) MIS field effect transistor can be formed, the junction capacitance of the source / drain region can be reduced (substantially zero), the depletion layer capacitance can be reduced, the breakdown voltage of the source / drain region can be improved, and the subthreshold characteristics can be improved. The threshold voltage can be reduced.
In addition, since the film thickness of the SOI substrate of the lateral MIS field effect transistor can be determined by the film thickness of the grown silicon nitride film (Si ₃ N ₄ ), it is fully depleted so that it can be used for manufacturing with a large-diameter wafer. It is possible to easily form a semiconductor layer having an SOI structure.
In addition, since a channel region can be formed only in a semiconductor layer with good crystallinity that is not affected by an underlying insulating film, lateral (vertical) and vertical (vertical) MIS field effect transistors having stable characteristics can be formed. Is possible.
In addition, the gate electrode provided through the gate oxide film can surround and form an SOI substrate made of a lateral (horizontal) epitaxial Si layer or a longitudinal (vertical) epitaxial Si layer, so that the current path other than the channel is blocked. In addition to complete channel control without current leakage, channels can be formed on four sides (upper and lower sides and two side surfaces or four side surfaces in the channel width direction), increasing the occupied area of the surface (upper surface). Since the channel width can be increased without increasing the driving current, the driving current can be increased.
The MIS field effect transistor components (low and high concentration source / drain regions) are self-aligned with the lateral (horizontal) epitaxial Si layer for forming a fine channel region or the fine longitudinal (vertical) epitaxial Si layer. It is also possible to finely form a gate oxide film and a surrounding gate electrode.
Further, by using a lateral (lateral) MIS field-effect transistor and a vertical (vertical) MIS field-effect transistor together and properly using them, various highly integrated semiconductor integrated circuits can be formed.
In addition, since an SOI structure in which a lower layer wiring is formed under a lateral (lateral) MIS field effect transistor and a vertical (vertical) MIS field effect transistor can be formed, the degree of freedom of wiring is increased, and various highly integrated various types of transistors can be formed. A semiconductor integrated circuit can be formed.
In addition, since all of the MIS field effect transistors are formed in an SOI structure separated by an insulating film, it is possible to prevent memory malfunction due to high voltage noise generated by static electricity or the like or completely prevent latch-up characteristics peculiar to CMOS. Is possible.
In addition, since a semiconductor layer having a structure in which a Si layer having a small lattice constant is sandwiched between SiGe layers having a large lattice constant from the left and right or the top and bottom, the lattice constant of the Si layer can be increased from the left and right or the top and bottom SiGe layers. The speed can be increased by increasing the carrier mobility.
That is, high-speed, high-performance, high-reliability, and high-integration that enables the manufacture of semiconductor integrated circuits that can be used for high-speed, large-capacity communication devices, portable information terminals, in-vehicle devices, various electronic mechanical devices, space-related devices, etc. In addition, lateral (vertical) and vertical (vertical) MIS field effect transistors having an enclosing gate electrode can be obtained.
The present inventor has the art, encircling the gate electrode with the horizontal on the insulating film (lateral) type MIS field effect transistor and a vertical (vertical) type MIS field effect transistor coexistence structure (La teral M etal Insulator Semiconductor Field Effect Transistor and Ve rtical M etal Insulator Semiconductor Field Effect Transistor with S urrounding G ate O n In sulator) and named, abbreviated as LAMVEMSGOIN (ram Bem Sugoi down) structure.

Schematic plan view of the first embodiment of the semiconductor device of the present invention Schematic side cross-sectional view of the first embodiment of the semiconductor device of the present invention (pp cross-sectional view) Schematic side sectional view (qq arrow sectional view) of the first embodiment in the semiconductor device of the present invention. Schematic side cross-sectional view of the first embodiment of the semiconductor device of the present invention (cross-sectional view taken along line r-r) Schematic side sectional view (ss arrow sectional view) of the first embodiment of the semiconductor device of the present invention. Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Process sectional drawing (pp arrow directional cross-sectional view) of the manufacturing method of the 1st Example in the semiconductor device of this invention Schematic side cross-sectional view of the second embodiment of the semiconductor device of the present invention (pp cross-sectional view) Schematic plan view of the third embodiment of the semiconductor device of the present invention Schematic side cross-sectional view of a third embodiment of the semiconductor device of the present invention (pp cross-sectional view) Schematic side sectional view of the third embodiment of the semiconductor device of the present invention (qq arrow sectional view) Schematic side cross-sectional view of the third embodiment of the semiconductor device of the present invention (cross-sectional view taken along line r-r) Schematic side sectional view (ss arrow sectional view) of the third embodiment in the semiconductor device of the present invention. Schematic side cross-sectional view of the fourth embodiment in the semiconductor device of the present invention (cross-sectional view taken along the arrow pp) Schematic plan view of the fifth embodiment of the semiconductor device of the present invention Schematic side cross-sectional view of the fifth embodiment in the semiconductor device of the present invention (pp cross-sectional view) Schematic side sectional view of the fifth embodiment of the semiconductor device of the present invention (qq arrow sectional view) Schematic side cross-sectional view of the fifth embodiment of the semiconductor device of the present invention (cross-sectional view taken along arrow r-r) CMOS SRAM memory cell circuit diagram Schematic plan view of a conventional semiconductor device Schematic side sectional view of conventional semiconductor device (sectional view taken along pp arrow)

The present invention is
(1) An Si layer is selectively epitaxially grown in the vertical (vertical) direction on the Si substrate.
(2) A lateral (horizontal) direction epitaxial Si layer is grown on a part of the side surface of the longitudinal (vertical) direction epitaxial Si layer on the insulating film. (Semiconductor layer for forming a source / drain region of a lateral MIS field effect transistor and a semiconductor layer for forming an SOI substrate of a vertical MIS field effect transistor)
(3) An opening is formed to remove the Si layer and the surrounding insulating film corresponding to the channel portion.
(4) A Si layer for forming a channel region is grown between the exposed side surfaces of the Si layer. (Semiconductor layer for forming channel region of lateral MIS field effect transistor)
(5) A surrounding gate electrode is embedded flatly around the Si layer for channel formation via a gate insulating film. (Formation of gate oxide film and surrounding gate electrode of lateral MIS field effect transistor)
(6) A lateral (horizontal) epitaxial Si layer is selectively exposed, and a longitudinal (vertical) epitaxial Si layer is grown on the exposed lateral (horizontal) epitaxial Si layer. (Source / drain region and channel region forming semiconductor layer of vertical MIS field effect transistor)
(7) The source / drain region of the lateral (lateral) MIS field effect transistor is formed in self-alignment with the surrounding gate electrode, and the vertical (vertical) MIS is self-aligned with the epitaxial Si layer in the longitudinal (vertical) direction. A source / drain region of the field effect transistor is formed.
(8) The insulating film around the epitaxial Si layer is selectively opened in the vertical (vertical) direction in which the source / drain regions are formed, and the surrounding gate electrode is embedded flatly through the gate insulating film. (Formation of gate oxide film and surrounding gate electrode of vertical type MIS field effect transistor)
(9) A two-layer Cu wiring is formed, and a lateral (lateral) MIS field effect transistor and a vertical (vertical) MIS field effect transistor are appropriately connected.
Using technology such as
A lateral (horizontal) epitaxial semiconductor layer provided on a semiconductor substrate via an insulating film is an SOI substrate, and a gate electrode having a part of the SOI substrate surrounded vertically by a gate insulating film is provided. Information is obtained by two lateral N-channel MIS field effect transistors and two lateral P-channel MIS field effect transistors having a structure in which a source / drain region is provided on an SOI substrate. A gate in which a flip-flop for holding is formed and a vertical (vertical) direction epitaxial semiconductor layer formed in a part of a lateral (horizontal) direction epitaxial semiconductor layer is an SOI substrate, and a side surface of the SOI substrate is surrounded by a gate insulating film Two vertical layers (having an electrode and having a structure in which source / drain regions are provided opposite to the upper and lower portions of the SOI substrate) A word transistor for reading or writing is formed by an N-channel N-channel MIS field effect transistor, and is connected as appropriate by a lower layer wiring and a two-layer upper layer wiring to constitute a CMOS SRAM memory cell composed of six elements. is there.

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
Throughout the drawings, the same object is denoted by the same reference numeral. However, the diagonal lines in the side sectional view are shown only on the main insulating film, and the wiring is drawn with a slight back-and-forth displacement, and the horizontal and vertical sizes are accurate to show the main part of the invention. The dimensions are not shown.
FIG. 1 to FIG. 18 show a part of a semiconductor integrated circuit including a memory cell of a CMOS type SRAM according to a first embodiment of the semiconductor device of the present invention. FIG. 1 is a schematic plan view, and FIG. Cross-sectional view (pp arrow cross-sectional view, parallel to word line), FIG. 3 is a schematic side cross-sectional view (q-q arrow cross-sectional view, parallel to word line), and FIG. 4 is a schematic side cross-sectional view (r -R arrow sectional view, direction parallel to bit line), FIG. 5 is a schematic side sectional view (ss arrow sectional view, direction parallel to bit line), and FIGS. (a cross-sectional view taken along the line pp, parallel to the word line). (The memory cell circuit diagram of the CMOS type SRAM is the same as FIG. 30.)
FIGS. 1 to 5 show a part of a semiconductor integrated circuit including a CMOS SRAM memory cell using a silicon (Si) substrate and formed in a LAMVEMSGOIN structure. 1 is a p-type of about 10 ¹⁵ cm ^−3. 1 is a silicon nitride film (Si ₃ N ₄ ) of about 100 nm, 3 is a silicon oxide film (SiO ₂ ) of about 150 nm, and 4 is a silicon nitride film (Si ₃ ) of an element isolation region of about 50 nm. N _4), 5 is ¹⁰ 17 ^{cm -3} of about p-type lateral (horizontal) direction epitaxial Si layer (source drain region formation semiconductor layer), 6a is ¹⁰ 17 ^{cm -3} of about p-type lateral (horizontal) Direction epitaxial Si layer (channel region forming semiconductor layer), 6b is an n-type lateral (horizontal) direction epitaxial Si layer (channel region type) of about 10 ¹⁷ cm ⁻³ Forming semiconductor layer), 7 is a buried silicon nitride film (Si ₃ N ₄ ), and 8a is a p-type longitudinal (vertical) direction epitaxial Si layer (source / drain region and channel region forming semiconductor layer) of about 10 ¹⁷ cm ^−3. , 9 is an n ⁺ type source region of about 10 ²⁰ cm ⁻³ , 10 is an n type source region of about 5 × 10 ¹⁷ cm ⁻³ , 11 is an n type drain region of about 5 × 10 ¹⁷ cm ⁻³ , 12 Is an n ⁺ type drain region of about 10 ²⁰ cm ⁻³ , 13 is a gate oxide film (SiO ₂ ) of a lateral (lateral) MIS field effect transistor of about 5 nm, 14 is a lateral of about 35 nm in length and about 150 nm in thickness. (lateral) type encircling the gate electrode of the MIS field-effect transistor (WSi), 15 is 25nm approximately sidewall _(SiO 2), 16 is 5nm approximately vertical (Bate Cal) type MIS field effect transistor gate oxide film _(SiO 2), 17 the height 150nm approximately vertical (vertical) type MIS field effect transistor surrounds gate electrode (WSi), 18 is about 150nm phosphosilicate glass ( PSG) film, 19 is about 150 nm phosphosilicate glass (PSG) film, 20 is about 20 nm silicon nitride film (Si ₃ N ₄ ), 21 is about 10 nm barrier metal (TiN), and 22 is a conductive plug (W) , 23 is an interlayer insulating film (SiOC) of about 500 nm, 24 is a barrier metal (TaN) of about 10 nm, 25 is a first layer Cu wiring (including a Cu seed layer) of about 500 nm, and 26 is a barrier insulating film of about 20 nm. , 300 nm of about interlayer insulating film 27 (SiOC), 28 is 20nm approximately silicon nitride film _{(Si 3 N} 4), 9 is a barrier metal (TiN) of about 10 nm, 30 is a conductive plug (W), 31 is an interlayer insulating film (SiOC) of about 500 nm, 32 is a barrier metal (TaN) of about 10 nm, and 33 is a second layer of about 500 nm. Cu wiring (including Cu seed layer), 34 is a barrier insulating film of about 20 nm, 35 is a lower layer wiring (WSi) of about 70 nm, 36 is a p ⁺ type source region of about 10 ²⁰ cm ⁻³ , and 37 is 10 ²⁰ cm A p ⁺ -type drain region of about ⁻³ , WL is a word line, BL is a bit line, VDD is a power supply voltage, and VSS is a ground voltage.
In FIG. 1 (schematic plan view), two lateral (lateral) N-channel MIS field effect transistors and two lateral (lateral) P-channel MIS field effect transistors are appropriately connected by two layers of Cu wiring. A CMOS SRAM in which two vertical (vertical) N-channel MIS field effect transistors are appropriately connected to each other by a two-layer Cu wiring, and a word transistor for reading or writing is formed. A memory cell is shown.
2 in (p-p arrow sectional view, parallel to the word line), a silicon nitride film _{(Si 3 N} 4) 2 is provided on the silicon substrate 1 of p-type, silicon nitride _(Si 3 _{N 4} ) on 2 selectively silicon oxide film _(SiO 2) 3 is provided, on the silicon oxide film _(SiO 2) 3, the silicon nitride film _{(Si 3 N} 4) 4 and the silicon nitride film (Si ₃ A p-type lateral (horizontal) epitaxial Si layer 5 having n ⁺ -type source / drain regions (9, 10, 11, 12) separated by N ₄ ) 7 is provided and sandwiched between the epitaxial Si layers 5 is, on the location where the silicon oxide film (SiO 2) ₃ is not provided, p-type beside forming a channel region (horizontal) direction epitaxial Si layer 6a is provided, the epitaxial Si layer 5 and epitaxial SOI substrate in the transverse (lateral) type N-channel MIS field effect transistor of Si layer 6a is formed, the periphery of the epitaxial Si layer 6a is surrounded by the gate electrode (WSi) 14 via a gate oxide film _(SiO 2) 13 Two lateral (lateral) N-channel MIS field effect transistors having the structure described above are formed, and an n ⁺ -type source / drain region (9, 9) is formed on the epitaxial Si layer 5 provided with the n ⁺ -type drain region 12. 12) and a p-type longitudinal (vertical) epitaxial Si layer 8a in which a channel region is formed, and the periphery of the epitaxial Si layer 8a is surrounded by a gate electrode (WSi) 17 via a gate oxide film (SiO ₂ ) 16 Two vertical (vertical) N-channel MIS field effect transistors having the above structure are formed. It is made.
3 in (q-q arrow sectional view, parallel to the word line), a silicon nitride film _{(Si 3 N} 4) 2 is provided on the silicon substrate 1 of p-type, silicon nitride _(Si 3 _{N 4} ) on 2 selectively silicon oxide film _(SiO 2) 3 is provided, on the silicon oxide film _(SiO 2) 3, the silicon nitride film _{(Si 3 N} 4) 4 and the silicon nitride film (Si ₃ N ₄ ) n-type lateral (horizontal) epitaxial Si layer 5 formed with p ⁺ -type source / drain regions (36, 37) separated by N ₄ ) 7 is provided, sandwiched between epitaxial Si layers 5 and silicon oxide (SiO 2) film ₃ is on places not provided, next to the n-type forming a channel region (horizontal) direction epitaxial Si layer 6b is provided, the epitaxial Si layer 5 and the epitaxial Si layer 6 The SOI substrate in the transverse (lateral) type P-channel MIS field effect transistor is formed, the structure around the epitaxial Si layer 6b is being surrounded by the gate electrode (WSi) 14 via a gate oxide film _(SiO 2) 13 Two lateral (lateral) P-channel MIS field effect transistors are formed.
4 in (r-r arrow sectional view, parallel to the bit line), a silicon nitride film _{(Si 3 N} 4) 2 is provided on the silicon substrate 1 of p-type, silicon nitride _(Si 3 _{N 4} ) 2, an epitaxial Si layer (6 a, 6 b) separated by a silicon nitride film (Si ₃ N ₄ ) 4 is surrounded by a gate oxide film (SiO ₂ ) 13. A common surrounding gate electrode (WSi) 14 is provided for the P-channel MIS field effect transistor (right side) and the N-channel MIS field effect transistor (left side).
5 In (s-s cross section taken along, parallel to the bit line), a silicon nitride film _{(Si 3 N} 4) 2 is provided on the silicon substrate 1 of p-type, silicon nitride _(Si 3 _{N 4} ) on 2 is provided a silicon oxide film _(SiO 2) 3, on the silicon oxide film _(SiO 2) 3, the silicon nitride film _{(Si 3 N} 4) 4 are isolated by the vertical (vertical ) Type N channel MIS field effect transistor n ⁺ type drain region 12 and lateral (lateral) type P channel MIS field effect transistor p ⁺ type drain region 37 are connected by lower layer wiring (WSi) 35.
Therefore, two kinds of lateral (horizontal) epitaxial Si layers formed on the semiconductor substrate via an insulating film by an easy process using a normal inexpensive semiconductor substrate are defined as an SOI substrate (fully depleted type). A vertical (vertical) MIS field effect transistor having a lateral (horizontal) epitaxial Si layer and a vertical (vertical) epitaxial Si layer as an SOI substrate (fully depleted) is formed. Therefore, the threshold voltage can be reduced by reducing the junction capacitance of the source / drain region (substantially zero), reducing the depletion layer capacitance, improving the breakdown voltage of the source / drain region, and improving the subthreshold characteristics.
In addition, since the film thickness of the SOI substrate of the lateral MIS field effect transistor can be determined by the film thickness of the grown silicon nitride film (Si ₃ N ₄ ), it is fully depleted so that it can be used for manufacturing with a large-diameter wafer. It is possible to easily form a semiconductor layer having an SOI structure.
In addition, since a channel region can be formed only in a semiconductor layer having good crystallinity without being affected by the underlying insulating film, a lateral (vertical) type and vertical (vertical) type MIS field effect transistor having a stable LAMVEMSGOIN structure can be formed. Is possible.
In addition, the gate electrode provided through the gate oxide film can surround and form an SOI substrate made of a lateral (horizontal) epitaxial Si layer or a longitudinal (vertical) epitaxial Si layer, so that the current path other than the channel is blocked. In addition to complete channel control without current leakage, channels can be formed on four sides (upper and lower sides and two side surfaces or four side surfaces in the channel width direction), increasing the occupied area of the surface (upper surface). Since the channel width can be increased without increasing the driving current, the driving current can be increased.
The MIS field effect transistor components (low and high concentration source / drain regions) are self-aligned with the lateral (horizontal) epitaxial Si layer for forming a fine channel region or the fine longitudinal (vertical) epitaxial Si layer. It is also possible to finely form a gate oxide film and a surrounding gate electrode.
In addition, by coexisting and using a lateral (lateral) MIS field effect transistor and a vertical (vertical) MIS field effect transistor, an extremely highly integrated CMOS SRAM memory cell can be configured. The size can be reduced by about 80% compared to the SRAM memory cell size.
Further, since an SOI structure in which a lower layer wiring is formed under a lateral (lateral) MIS field effect transistor and a vertical (vertical) MIS field effect transistor can be formed, the degree of freedom of wiring is increased, and an extremely highly integrated CMOS type. It is possible to configure an SRAM memory cell.
In addition, since all of the MIS field effect transistors constituting the memory cell of the CMOS type SRAM can be formed in an SOI structure separated by an insulating film, it is possible to prevent malfunction of the memory due to high voltage noise generated by static electricity or the like or to be characteristic of CMOS. It is possible to completely prevent the latch-up characteristic.
That is, high-speed, high-performance, high-reliability, and high-integration that enables the manufacture of semiconductor integrated circuits that can be used for high-speed, large-capacity communication devices, portable information terminals, in-vehicle devices, various electronic mechanical devices, space-related devices, etc. In addition, lateral (vertical) and vertical (vertical) MIS field effect transistors having an enclosing gate electrode can be obtained.

  Next, the manufacturing method of the first embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. However, here, only the manufacturing method related to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method related to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. To do.

FIG.
A silicon nitride film (Si ₃ N ₄ ) 2 is grown on the p-type silicon substrate 1 by about 100 nm by chemical vapor deposition. Next, a silicon oxide film (SiO ₂ ) 3 of about 150 nm is grown by chemical vapor deposition. Next, although not shown in the cross-sectional view taken along the line pp, a normal lithography technique using an exposure drawing apparatus is used to change the silicon oxide film (SiO ₂ ) 3 to about 70 nm using a resist (not shown) as a mask layer. The hole is formed by isotropic dry etching. Next, the resist (not shown) is removed. Next, a tungsten silicide film (WSi) 35 (not shown) of about 70 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (hereinafter abbreviated as CMP) is performed, the tungsten silicide film (WSi) 35 on the silicon oxide film (SiO ₂ ) 3 is removed, and the tungsten silicide film (WSi) 35 is flatly formed in the opening portion. Embed (not shown). (This tungsten silicide film (WSi) 35 is used as a lower layer wiring for connecting the n ⁺ -type drain region and the p ⁺ -type drain region as shown in FIG. 5 (cross-sectional view taken along the arrow ss) of the completed drawing. Then, a silicon nitride film (Si ₃ N ₄ ) 4 is grown by about 50 nm by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 4, a silicon oxide film (SiO ₂ ) 3, and a silicon nitride film (Si ₃ N ₄ ) 2 is sequentially subjected to anisotropic dry etching to form an opening. Next, the resist (not shown) is removed.

FIG.
Next, a p-type longitudinal (vertical) epitaxial Si layer 38 is grown on the exposed p-type silicon substrate 1. Next, chemical mechanical polishing (CMP) is performed to planarize the p-type vertical (vertical) epitaxial Si layer 38 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 4. Next, a tungsten film 39 of about 50 nm is grown by selective chemical vapor deposition.

FIG.
Next, using an ordinary lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 4 is anisotropically dry etched using a resist (not shown) as a mask layer to form an opening. Next, the resist (not shown) is removed. Next, a p-type lateral (horizontal) epitaxial Si layer 5 is grown on the side surface of the exposed p-type longitudinal (vertical) epitaxial Si layer 38 to embed an opening portion of the silicon nitride film (Si ₃ N ₄ ) 4. . The remaining silicon nitride film (Si ₃ N ₄ ) 4 serves as an element isolation region.

FIG.
Next, the surface of the p-type lateral (horizontal) epitaxial Si layer 38 is oxidized at about 900 ° C. to grow a silicon oxide film (SiO ₂ ) (not shown) of about 20 nm. Next, using the thermally oxidized silicon oxide film (SiO ₂ , not shown) and the silicon nitride film (Si ₃ N ₄ ) 4 as mask layers, the tungsten film 39 and the p-type longitudinal (vertical) epitaxial Si layer 38 are sequentially different. The hole is formed by isotropic dry etching. (The opening width is about 100 nm) Next, a silicon nitride film (Si ₃ N ₄ ) 7 of about 60 nm is grown by chemical vapor deposition. Next, the silicon nitride film (Si ₃ N ₄ ) 4 and the silicon nitride film (Si ₃ N ₄ ) 7 on the flat surface of the p-type lateral (horizontal) epitaxial Si layer 5 and the thermally oxidized silicon oxide film (SiO ₂ , Chemical mechanical polishing (CMP) is performed to fill the opening portion with a silicon nitride film (Si ₃ N ₄ ) 7. (This region also becomes part of the element isolation region.)

FIG.
Next, a silicon oxide film (SiO ₂ ) 40 of about 150 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon oxide film (SiO ₂ ) 40, a p-type lateral (horizontal) epitaxial Si layer 5, a silicon nitride film ( Si ₃ N ₄ ) 4 (existing on both sides in the width direction of the Si layer 5) and the silicon oxide film (SiO ₂ ) 3 are selectively and sequentially subjected to anisotropic dry etching to form a silicon nitride film (Si ₃ N ₄ ) 2. An opening that exposes a portion is formed. At this time, the silicon nitride film (Si ₃ N ₄ ) 2 becomes an etching stopper film. Next, the resist (not shown) is removed.

FIG.
Next, a p-type lateral (horizontal) epitaxial Si layer 6a is grown between the side surfaces of the exposed p-type lateral (horizontal) epitaxial Si layer 5, and a p-type lateral (horizontal) epitaxial layer having a vacancy immediately below is grown. The Si layer 6a is formed. (At this time, a single crystal silicon layer having no influence of the underlying layer is formed immediately above the vacancies. The epitaxial Si layer 5 and the epitaxial Si layer 6a serve as an SOI substrate of a lateral (lateral) MIS field effect transistor). The entire periphery of the p-type lateral (horizontal) epitaxial Si layer 6a is oxidized to grow a gate oxide film (SiO ₂ ) 13 of about 5 nm. Next, using a normal lithography technique by an exposure lithography apparatus, a lateral (lateral) N-channel MIS field effect transistor is formed on a p-type lateral (horizontal) epitaxial Si layer 6a using a resist (not shown) as a mask layer. Boron ions are implanted to control the threshold voltage. Next, the resist (not shown) is removed. Next, using a normal lithography technique by an exposure drawing apparatus, a lateral (lateral) P-channel MIS field effect transistor is formed on a p-type lateral (horizontal) epitaxial Si layer 6a using a resist (not shown) as a mask layer. Phosphorus ion implantation for threshold voltage control is performed. (Finally, the p-type Si layer 6a is inverted to become the n-type Si layer 6b.) Next, the resist (not shown) is removed. Next, a tungsten silicide film (WSi) of about 100 nm is grown on the entire surface including the entire periphery of the gate oxide film (SiO ₂ ) 13 by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and the tungsten silicide film (WSi) grown on the silicon oxide film (SiO ₂ ) 40 is removed and planarized. Thus, a surrounding gate electrode (WSi) 14 of a lateral (lateral) MIS field effect transistor embedded flat in the opening is formed.

FIG.
Next, the silicon oxide film (SiO ₂ ) 40 is selectively dry etched anisotropically using a resist (not shown) as a mask layer by using a normal lithography technique by an exposure drawing apparatus, and p-type lateral (horizontal) An opening that exposes part of the directional epitaxial Si layer 5 is formed. Next, the resist (not shown) is removed. Next, a p-type vertical (vertical) epitaxial Si layer 8 a having a columnar structure is grown on the exposed p-type lateral (horizontal) epitaxial Si layer 5. Next, chemical mechanical polishing (CMP) is performed to planarize the p-type vertical (vertical) epitaxial Si layer 8 a protruding from the flat surface of the silicon oxide film (SiO ₂ ) 40. (Thus, the SOI substrate of the vertical MIS field effect transistor having the same height as the surrounding gate electrode (WSi) 14 of the lateral (lateral) MIS field effect transistor is formed).

FIG.
Next, the silicon oxide film (SiO ₂ ) 40 is removed by etching. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique by an exposure drawing apparatus, the resist (not shown) and the surrounding gate electrode (WSi) 14 are used as a mask layer to form an n-type source / drain region (10) of a lateral (lateral) MIS field effect transistor. 11) Phosphorus ion implantation is performed. Next, the resist (not shown) is removed. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. Next, a silicon oxide film (SiO ₂ ) of about 25 nm is grown by chemical vapor deposition. Next, whole surface anisotropic dry etching is performed to form a side wall (SiO ₂ ) 15 only on the side wall of the upper surface portion of the surrounding gate electrode (WSi) 14 and the side wall of the epitaxial Si layer 8a. Next, using a normal lithography technique using an exposure drawing apparatus, the sidewall (SiO ₂ ) 15 on the side wall of the epitaxial Si layer 8a is removed by etching using a resist (not shown) as a mask layer. Next, the resist (not shown) is removed. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, a lateral (lateral) MIS field effect transistor is formed using a resist (not shown), the surrounding gate electrode (WSi) 14 and the side wall (SiO ₂ ) 15 as mask layers using a normal lithography technique by an exposure drawing apparatus. Also, arsenic ions are implanted to form the n ⁺ -type source / drain regions (9, 12) of the vertical MIS field effect transistor. Next, the resist (not shown) is removed. Next, a lateral (lateral) MIS field effect transistor is formed using a resist (not shown), the surrounding gate electrode (WSi) 14 and the side wall (SiO ₂ ) 15 as mask layers using a normal lithography technique by an exposure drawing apparatus. Boron ions are implanted to form the p ⁺ type source / drain regions (36, 37). Next, the resist (not shown) is removed. Next, annealing is performed by an RTP (Rapid Thermal Processing) method to form an n-type source / drain region (10, 11), an n ⁺ -type source / drain region (9, 12), and a p ⁺ -type source / drain region (36, 37). . Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching.

FIG.
Next, a PSG film 18 of about 150 nm is grown by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed, and the surrounding gate electrode (WSi) 14 and the PSG film 18 on the epitaxial Si layer 8a are removed and planarized.

FIG.
Next, using an ordinary lithography technique by an exposure drawing apparatus, the PSG film 18 is selectively dry-etched anisotropically using a resist (not shown) as a mask layer to form an opening around the epitaxial Si layer 8a. To do. Next, the resist (not shown) is removed. Next, thermal oxidation is performed at about 750 ° C., and a gate oxide film (SiO ₂ ) 16 of about 5 nm is grown around the epitaxial Si layer 8a. Next, a tungsten silicide film (WSi) of about 100 nm is grown on the entire surface including the entire periphery of the gate oxide film (SiO ₂ ) 16 by chemical vapor deposition. Next, chemical mechanical polishing (CMP) is performed to remove the tungsten silicide film (WSi) grown on the flat surfaces of the epitaxial Si layer 8a, the surrounding gate electrode (WSi) 14 and the PSG film 18, and to flatten the opening. An embedded vertical gate (WSi) 17 of a vertical MIS field effect transistor is formed.

FIG.
Next, a PSG film 19 of about 150 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 20 of about 20 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 20, the PSG film 19 and the PSG film 18 are sequentially subjected to anisotropic dry etching using a resist (not shown) as a mask layer. , Forming a via. Next, the resist (not shown) is removed. Next, TiN 21 serving as a barrier metal is grown by sputtering. Next, tungsten (W) 22 is grown by chemical vapor deposition. Next, a conductive plug (W) 22 having a barrier metal (TiN) 21 is formed by chemical mechanical polishing (CMP).

FIG.
Next, an interlayer insulating film (SiOC) 23 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique by an exposure drawing apparatus, the interlayer insulating film (SiOC) 23 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 20 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 24 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is embedded in the opening portion flatly, and a first-layer Cu wiring 25 having a barrier metal (TaN) 24 is formed. Next, a silicon nitride film (Si ₃ N ₄ ) 26 serving as a Cu barrier insulating film is grown by chemical vapor deposition.

FIG.
Next, an interlayer insulating film (SiOC) 27 of about 500 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 28 of about 20 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 28, an interlayer insulating film (SiOC) 27, and a silicon nitride film (Si ₃ N) ₄ ) Anisotropic dry etching is sequentially performed on 26 to form vias. Next, the resist (not shown) is removed. Next, TiN 29 serving as a barrier metal is grown by sputtering. Next, tungsten (W) 30 is grown by chemical vapor deposition. Next, a conductive plug (W) 30 having a barrier metal (TiN) 29 is formed by chemical mechanical polishing (CMP).

2 (pp arrow cross-sectional view, parallel to word line), FIG. 3 (qq arrow cross-sectional view, parallel to word line), FIG. 4 (rr arrow cross-sectional view, bit line) (Parallel direction), FIG. 5 (ss arrow cross-sectional view, parallel to bit line)
Next, an interlayer insulating film (SiOC) 31 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique by an exposure drawing apparatus, the interlayer insulating film (SiOC) 31 is anisotropically dry etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 28 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 32 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is embedded in the opening portion flatly, and a second-layer Cu wiring 33 having a barrier metal (TaN) 32 is formed. Next, a silicon nitride film (Si ₃ N ₄ ) 34 serving as a Cu barrier insulating film is grown by chemical vapor deposition to complete a semiconductor integrated circuit including a CMOS type SRAM memory cell formed in the LAMVEMSGOIN structure of the present invention. .

FIG. 19 is a schematic sectional side view of the second embodiment of the semiconductor device of the present invention (plan view is the same as FIG. 1, pp arrow sectional view, parallel to the word line), and shows the silicon (Si) substrate. 1 shows a part of a semiconductor integrated circuit including CMOS SRAM memory cells formed in a LAMVEMSGOIN structure, wherein 1-4, 7, and 9-34 are the same as in FIG. (Horizontal) direction epitaxial SiGe layer (source / drain region forming semiconductor layer), 42 is a p-type lateral (horizontal) direction epitaxial strained Si layer (channel region forming semiconductor layer), and 43 is a p-type longitudinal (vertical) direction. Epitaxial SiGe layer (source / drain region forming semiconductor layer), 44a is a p-type longitudinal (vertical) direction epitaxial strained Si layer (channel region forming semiconductor layer), and 45 is a p-type longitudinal (vertical) direction. Shows the epitaxial SiGe layer (source drain region formation semiconductor layer).
In this figure, a lateral (horizontal) epitaxial Si layer (source / drain region forming semiconductor layer) 5 and a lateral (horizontal) epitaxial Si layer (channel region forming semiconductor layer) 6a are respectively lateral (horizontal) epitaxial SiGe. A layer (source / drain region forming semiconductor layer) 41 and a lateral (horizontal) direction epitaxial strained Si layer (channel region forming semiconductor layer) 42; and a longitudinal (vertical) direction epitaxial Si layer (source / drain region and The channel region forming semiconductor layer) 8a includes a longitudinal (vertical) direction epitaxial SiGe layer (source / drain region forming semiconductor layer) 43, a longitudinal (vertical) direction epitaxial strained Si layer (channel region forming semiconductor layer) 44a, and a longitudinal (vertical). ) Direction epitaxial SiGe layer (semiconductor for source / drain region formation) ) Next to almost the same structure as FIG. 2 except that 45 is formed from (lateral) type MIS field effect transistor and a vertical (vertical) type MIS field effect transistor is formed.
In this embodiment, the same effect as that of the first embodiment can be obtained, and the manufacturing method is somewhat complicated. However, a Si layer having a small lattice constant is sandwiched between SiGe layers having a large lattice constant from the left and right or above and below. Since a semiconductor layer having a structure can be formed, the lattice constant of the strained Si layer (channel region) can be expanded from the left and right or upper and lower SiGe layers, and a lateral (vertical) MIS field effect transistor and a vertical (vertical) MIS electric field. Since both the effect transistors can increase carrier mobility, higher speed can be achieved.

20 to 24 show a third embodiment of the semiconductor device according to the present invention, in which FIG. 20 is a schematic plan view, FIG. 21 is a schematic side sectional view (a cross-sectional view in the direction of arrow pp, parallel to the word line), FIG. 22 is a schematic side sectional view (q-q arrow sectional view, parallel to the word line), FIG. 23 is a schematic side sectional view (rr arrow sectional view, parallel to the bit line), and FIG. 24 is a schematic side. A cross-sectional view (s-s cross-sectional view, parallel to the bit line) is shown, and a part of a semiconductor integrated circuit including a CMOS SRAM memory cell formed in a LAMVEMSGOIN structure using a silicon (Si) substrate is shown. 1 to 35 are the same as those shown in FIGS. 1 to 5, and 8b is an n-type longitudinal (vertical) direction epitaxial Si layer.
In the figure, a flip-flop for holding information is formed by a vertical (vertical) MIS field effect transistor, and a word transistor for reading or writing is formed by a lateral (lateral) MIS field effect transistor. A lateral (vertical) MIS field effect transistor and a vertical (vertical) MIS field effect transistor having substantially the same structure as that shown in FIGS. 1 to 5 are formed except that the line and the ground line are formed by a lower layer wiring under the semiconductor layer. Has been.
In this embodiment, the same effect as that of the first embodiment can be obtained, and a large number of vertical (vertical) MIS field effect transistors with higher integration are used (four elements). Since the line is formed by the lower layer wiring under the semiconductor layer, the degree of freedom of the wiring is increased, so that higher integration is possible, and about 55% compared with the memory cell size of the conventional CMOS type SRAM. Miniaturization is possible.

FIG. 25 is a schematic sectional side view of the fourth embodiment of the semiconductor device of the present invention (plan view is the same as FIG. 20, pp arrow sectional view, parallel to the word line), and shows the silicon (Si) substrate. 1 shows a part of a semiconductor integrated circuit including CMOS SRAM memory cells formed in a LAMVEMSGOIN structure, and 1-4, 7, 9, 12, 16-28, and 31-37 are the same as FIG. , 41 and 43 to 45 are the same as those in FIG. 19, and 44b is an n-type longitudinal (vertical) direction epitaxial strained Si layer (channel region forming semiconductor layer).
In the figure, a lateral (horizontal) direction epitaxial Si layer (source / drain region forming semiconductor layer) 5 is formed of a lateral (horizontal) direction epitaxial SiGe layer (source / drain region forming semiconductor layer) 41, and The (vertical) direction epitaxial Si layer (source / drain region and channel region forming semiconductor layer) (8a, 8b) is the vertical (vertical) direction epitaxial SiGe layer (source / drain region forming semiconductor layer) 43, and the vertical (vertical) direction epitaxial is. Diagram of the third embodiment except that it is formed of a strained Si layer (channel region forming semiconductor layer) (44a, 44b) and a longitudinal (vertical) direction epitaxial SiGe layer (source / drain region forming semiconductor layer) 45. The lateral (lateral) MIS field effect transistor and vertical Type MIS field effect transistor is formed. (However, in the lateral (lateral) MIS field effect transistor, only the n ⁺ -type source / drain regions (9, 12) are shown).
In this embodiment, the same effects as those of the first and third embodiments can be obtained, and the manufacturing method is somewhat complicated. However, compared with the first embodiment, the speed is increased by increasing the mobility. However, it is possible to achieve higher integration by using a large number of vertical (vertical) MIS field-effect transistors.

26 to 29 show a fifth embodiment of the semiconductor device according to the present invention. FIG. 26 is a schematic plan view, FIG. 27 is a schematic side sectional view (sectional view taken along a line p-p), and FIG. 28 is a schematic side sectional view. 29 is a schematic side cross-sectional view (a cross-sectional view taken along an rr arrow), and FIG. 29 is a semiconductor including a CMOS inverter using a silicon (Si) substrate and having a LAMVEMSGOIN structure. A part of the integrated circuit is shown. 1-26 and 35 are the same as in FIGS. 1 to 5, and 8b is the same as in FIG. Although a circuit diagram of the CMOS type inverter is not shown, it is composed of a pair of P channel MIS field effect transistors and N channel MIS field effect transistors in the flip-flop portion of the memory cell circuit diagram of the CMOS type SRAM of FIG. is there.
In the figure, an SOI-structured inverter is formed which is composed of a vertical (vertical) P-channel MIS field effect transistor having an enclosing gate electrode and a lateral (lateral) N-channel MIS field effect transistor having an enclosing gate electrode. The encircling gate electrodes (14, 17) are directly connected, an input voltage (VIN) is applied, and the p ⁺ -type drain region 37 and the n ⁺ -type drain region 12 are lower layer wirings (WSi, indicated by a one-dot chain line) are connected by, is applied when the output voltage (VOUT) is, the ^{p +} -type source region is applied supply voltage (VDD), the ^{n +} -type source region ground voltage (VSS) is applied.
In this embodiment, since an SOI-structured inverter is formed, the junction capacitance of the source / drain region can be reduced (substantially zero), and the speed can be increased.
In addition, an inverter composed of a vertical (vertical) P-channel MIS field effect transistor that completely surrounds the gate electrode and a lateral (lateral) N-channel MIS field effect transistor that completely surrounds the gate electrode can be formed. It is possible to obtain a high-performance and high-speed inverter without the above.
In addition, since the lower layer wiring can be formed under the SOI substrate, it can be formed with a single Cu wiring layer, and the occupation area is fine by using a lateral (lateral) MIS field effect transistor and a vertical (vertical) MIS field effect transistor. High integration can be achieved by increasing the degree of freedom.

In the above embodiment, chemical vapor deposition is used when growing the semiconductor layer. However, the present invention is not limited to this, and molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) is also used. Alternatively, atomic layer crystal growth (ALE) or any other crystal growth method may be used.
The surrounding gate electrode, the gate oxide film, the barrier metal, the conductive plug, the wiring, the insulating film, and the like are not limited to the above embodiment, and any material may be used as long as it has the same characteristics.
Further, in the above-described embodiment, an SOI structure comprising a vertical (vertical) P-channel MIS field effect transistor having an enclosing gate electrode and a lateral (lateral) N-channel MIS field effect transistor having an enclosing gate electrode. Although an inverter is formed, an SOI structure comprising a lateral (lateral) P-channel MIS field effect transistor having an enclosed gate electrode and a vertical (vertical) N-channel MIS field effect transistor having an enclosed gate electrode An inverter may be formed.
In the above embodiment, the SRAM and the inverter are described. However, the present invention is not limited to this, and any semiconductor memory device, logic circuit, or microprocessor can be applied.

The present invention is particularly aimed at a high-speed, high-performance, high-reliability, and highly-integrated CMOS type semiconductor integrated circuit. However, the present invention is not limited to a CMOS, but also in a semiconductor integrated circuit composed of a single MIS field effect transistor. The lateral (lateral) MIS field effect transistor having the surrounding gate electrode and the vertical (vertical) MIS field effect transistor having the surrounding gate electrode can be selectively used depending on the circuit configuration.
The MIS field-effect transistor as well, may be available other field effect transistors, such as a liquid crystal for a TFT (T hin F ilm T ransistor ).

1 p-type silicon (Si) substrate 2 silicon nitride film (Si ₃ N ₄ )
3 Silicon oxide film (SiO ₂ )
4 Silicon nitride film in element isolation region (Si ₃ N ₄ )
5 p-type lateral (horizontal) direction epitaxial Si layer (source / drain region forming semiconductor layer)
6a p-type lateral (horizontal) direction epitaxial Si layer (semiconductor layer for forming channel region)
6b N-type lateral (horizontal) direction epitaxial Si layer (semiconductor layer for forming channel region)
7 Embedded silicon nitride film (Si ₃ N ₄ )
8a p-type vertical (vertical) direction epitaxial Si layer (source / drain region and channel region forming semiconductor layer)
8b n-type vertical (vertical) direction epitaxial Si layer (source / drain region and channel region forming semiconductor layer)
9 n ⁺ type source region 10 n type source region 11 n type drain region 12 n ⁺ type drain region 13 Gate oxide film (SiO ₂ ) of lateral (lateral) MIS field effect transistor
14 Lateral MIS Field Effect Transistor Surrounding Gate Electrode (WSi)
15 Side wall (SiO ₂ )
16 Vertical (vertical) type MIS field effect transistor gate oxide film (SiO ₂ )
17 Surrounding Gate Electrode (WSi) of Vertical (Vertical) MIS Field Effect Transistor
18 Phosphorsilicate glass (PSG) film 19 Phosphorsilicate glass (PSG) film 20 Silicon nitride film (Si ₃ N ₄ )
21 Barrier metal (TiN)
22 Conductive plug (W)
23 Interlayer insulation film (SiOC)
24 Barrier metal (TaN)
25 First layer Cu wiring (including Cu seed layer)
26 Barrier insulating film (Si ₃ N ₄ )
27 Interlayer insulation film (SiOC)
28 Silicon nitride film (Si ₃ N ₄ )
29 Barrier metal (TiN)
30 Conductive plug (W)
31 Interlayer insulation film (SiOC)
32 Barrier metal (TaN)
33 Second layer Cu wiring (including Cu seed layer)
34 Barrier insulating film (Si ₃ N ₄ )
35 Lower layer wiring (WSi)
36 p ⁺ type source region 37 p ⁺ type drain region 38 p type vertical (vertical) direction epitaxial Si layer 39 selective chemical vapor deposition conductive film (W)
40 Silicon oxide film (SiO ₂ )
41 p-type lateral (horizontal) direction epitaxial SiGe layer (semiconductor layer for forming a source / drain region)
42 p-type lateral (horizontal) direction epitaxial strained Si layer (semiconductor layer for forming channel region)
43 p-type vertical (vertical) direction epitaxial SiGe layer (source / drain region forming semiconductor layer)
44a p-type longitudinal (vertical) direction epitaxial strained Si layer (semiconductor layer for forming channel region)
44b n-type longitudinal (vertical) direction epitaxial strain Si layer (semiconductor layer for forming channel region)
45 p-type longitudinal (vertical) direction epitaxial SiGe layer (source / drain region forming semiconductor layer)

Claims (4)

A first semiconductor layer provided on the parallel (horizontal) direction to the main surface of the semiconductor substrate to surround the entire circumference of a portion of the first semiconductor layer via the first gate insulating film, equal omnidirectional A first gate electrode having a gate length (enclosed gate electrode) and a source / drain region made of an impurity provided in the first semiconductor layer and self-aligned with the first gate electrode (enclosed gate electrode) A lateral (horizontal) drive MIS field-effect transistor comprising: a second semiconductor layer provided in a vertical (vertical) direction on the remaining part of the first semiconductor layer; and the second semiconductor layer A second gate electrode (enclosed gate electrode) having the same gate length around the entire side surface of the semiconductor layer surrounded by the second gate insulating film, and an upper portion and a lower portion of the second semiconductor layer. Sosudore which is composed of impurity which is provided And emission regions, a vertical semiconductor device characterized by the (vertical) driving the MIS field-effect transistor, is provided via an insulating film on the semiconductor substrate made of. A lateral conductivity (horizontal direction) MIS field effect transistor of one conductivity type is provided in the first semiconductor layer, and an MIS field effect transistor of longitudinal conductivity (vertical direction) of opposite conductivity type is provided in the second semiconductor layer. The semiconductor device according to claim 1 , wherein the semiconductor device is provided. In the first semiconductor layer or the second semiconductor layer, according to claim 1, the lattice constants of a portion the source drain regions are provided, being greater than the lattice constant of a portion the channel region is provided Alternatively, the semiconductor device according to claim 2 .   In a semiconductor device having a first lateral (horizontal) epitaxial semiconductor layer, which is stacked on a semiconductor substrate with a first insulating film and a second insulating film interposed therebetween, and whose side surfaces are flatly embedded with a third insulating film. 4 insulating film, flat side surfaces of the fourth insulating film, the first lateral (horizontal) epitaxial semiconductor layer, and the first lateral (horizontal) epitaxial semiconductor layer The third insulating film and the second insulating film are selectively removed by etching to form an opening, and the first lateral (horizontal) epitaxial semiconductor layer is exposed between the exposed side surfaces. A step of forming two lateral (horizontal) direction epitaxial semiconductor layers, a step of forming a gate insulating film all around the second lateral (horizontal) direction epitaxial semiconductor layer, and surrounding the gate insulating film, Open A step of embedding a gate electrode in a flat portion, a step of selectively removing the fourth insulating film by etching, and exposing a part of a surface of the remaining first lateral (horizontal) epitaxial semiconductor layer, Performing a step of growing a vertical (vertical) direction epitaxial semiconductor layer on the exposed first lateral (horizontal) direction epitaxial semiconductor layer, and a step of planarizing the vertical (vertical) direction epitaxial semiconductor layer, A method of manufacturing a semiconductor device, wherein the height of the upper surface of the surrounding gate electrode and the height of the upper surface of the vertical (vertical) epitaxial semiconductor layer are matched.