JP5890998B2 - Semiconductor device and power supply method - Google Patents

Description

  The present invention relates to a semiconductor device and a power supply method, and more particularly, to a semiconductor device and a power supply method that can reduce power consumption.

  As a technique for reducing power consumption of a semiconductor device using a CMOS logic gate, there is a DVFS (Dynamic Voltage and Frequency Scaling) technique for controlling a power supply voltage according to a required speed. When the power supply voltage is controlled using the DVFS technique, delay monitors are provided at a plurality of locations of the semiconductor device, and the power supply voltage supplied to the semiconductor device can be controlled based on values measured by the delay monitor.

  Patent Document 1 discloses a technique related to the design of a semiconductor device equipped with a voltage control function. Patent Document 2 discloses a technology related to a semiconductor device that can form a replica circuit with high reliability and flexibility. Patent Document 3 discloses a technique that can minimize a decrease in an operation margin of a circuit formed over a semiconductor circuit even when the electrical characteristics of the element vary. Patent Documents 4 and 5 disclose techniques that can easily determine the amount of time-lapse deterioration margin of an LSI. Patent Document 6 discloses a technique related to a semiconductor integrated circuit capable of supplying a power supply voltage suitable for an internal circuit. Non-Patent Document 1 discloses a technique for controlling a power supply voltage supplied to a semiconductor circuit according to a measurement result in a delay monitor.

JP 2011-91277 A JP 2000-295084 A JP 2008-186931 A JP 2001-331545 A JP 2005-1000045 A JP 2009-10344 A

M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y. Hagihara, "Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes," IEEE Journal of Solid-State Circuits, vol. 41, pp. 805-814, April 2006.

  When the power supply voltage supplied to the internal circuit included in the semiconductor device is controlled, monitors can be provided at a plurality of locations in the internal circuit, and the power supply voltage can be controlled based on values measured by the monitor. However, since the characteristics of the internal circuit vary, the power supply voltage supplied to the internal circuit needs to be set in consideration of this variation. That is, it is necessary to provide a predetermined margin for the power supply voltage supplied to the internal circuit. This predetermined margin is an unnecessary margin for an internal circuit with little variation. Therefore, in this case, a power supply voltage higher than the actually required power supply voltage is supplied to the internal circuit with little variation, and there is a problem in that the power consumption of the semiconductor device including the internal circuit cannot be reduced. It was.

  A semiconductor device according to an aspect of the present invention is output from a power supply unit that supplies power to an internal circuit, a plurality of monitor units that monitor characteristics at a plurality of locations of the internal circuit, and the plurality of monitor units A control unit that controls the power supply unit according to a comparison result between a monitor value calculated based on the signal and a set comparison value, and the control unit has characteristic variation among the plurality of monitor units The comparison value is set according to.

  In the semiconductor device according to one embodiment of the present invention, the comparison value is set in accordance with the variation in characteristics in the plurality of monitor units provided in the internal circuit. Therefore, it is not necessary to provide a useless margin for the comparison value, and an optimum comparison value can be set, so that the power consumption of the semiconductor device can be reduced.

  A power supply method according to another aspect of the present invention is a method of supplying power to an internal circuit, wherein characteristics of the internal circuit at a plurality of locations are monitored, and a monitor value is calculated based on the monitoring results at the plurality of locations. Then, a comparison value is set according to the variation in the monitoring results at the plurality of locations, and the power supplied to the internal circuit is controlled according to the comparison result between the monitoring value and the set comparison value.

  In the power supply method according to another aspect of the present invention, the characteristics of the internal circuit at a plurality of locations are monitored, and the comparison value is set according to the variation in the characteristics at the plurality of locations. Therefore, it is not necessary to provide a useless margin for the comparison value, and an optimum comparison value can be set, so that the power consumption of the semiconductor device can be reduced.

  According to the present invention, a semiconductor device and a power supply method capable of reducing power consumption can be provided.

1 is a block diagram showing a semiconductor device according to a first embodiment; 2 is a block diagram illustrating an example of a monitor unit included in the semiconductor device according to the first embodiment; FIG. 3 is a block diagram illustrating an example of a control unit included in the semiconductor device according to the first embodiment; FIG. It is a block diagram which shows an example of the monitor value calculation part shown in FIG. It is a block diagram which shows an example of the variation value calculation part shown in FIG. It is a figure which shows an example of the comparison value stored in the register | resistor shown in FIG. It is a figure for demonstrating the effect of this invention. It is a figure for demonstrating the effect of this invention. FIG. 6 is a block diagram illustrating a variation value calculation unit included in a semiconductor device according to a second embodiment; FIG. 10 is a block diagram illustrating another example of a variation value calculation unit included in the semiconductor device according to the second embodiment; It is a block diagram which shows an example of the maximum value calculation part shown in FIG. 9, FIG. It is a block diagram which shows an example of the minimum value calculation part shown in FIG. 9, FIG. It is a block diagram which shows an example of the comparator shown in FIG. It is a block diagram which shows an example of the comparator shown in FIG. FIG. 6 is a block diagram illustrating an example of a monitor unit included in a semiconductor device according to a third embodiment; It is a timing chart for demonstrating operation | movement of the monitor part shown in FIG. FIG. 10 is a block diagram illustrating an example of a monitor unit included in a semiconductor device according to a fourth embodiment; FIG. 10 is a block diagram illustrating an example of a control unit included in a semiconductor device according to a fifth embodiment; It is a timing chart for demonstrating operation | movement of the control part shown in FIG. It is a timing chart for demonstrating operation | movement of the control part shown in FIG. 10 is a flowchart for explaining an operation of the semiconductor device according to the fifth embodiment; FIG. 10 is a block diagram illustrating an example of a control unit included in a semiconductor device according to a sixth embodiment; It is a timing chart for demonstrating operation | movement of the control part shown in FIG. FIG. 10 is a block diagram illustrating an example of a control unit included in a semiconductor device according to a seventh embodiment; FIG. 10 is a diagram for explaining an arrangement of monitor units included in a semiconductor device according to a seventh embodiment; FIG. 10 is a diagram for explaining an arrangement of monitor units included in a semiconductor device according to a seventh embodiment; FIG. 10 is a block diagram illustrating an example of a monitor unit included in a semiconductor device according to an eighth embodiment; FIG. 10 is a diagram for explaining the operation of the semiconductor device according to the eighth embodiment;

<Embodiment 1>
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a semiconductor device according to the first embodiment of the present invention. The semiconductor device shown in FIG. 1 includes an internal circuit 3 including monitor units 1_1 to 1_N and a control unit 2, and a power supply unit 4 (N is a positive integer. The same applies hereinafter). The internal circuit 3 shown in FIG. 1 is one power control unit, and the monitor units 1_1 to 1_N and the control unit 2 are provided for each power control unit. In FIG. 1, the internal circuit 3 and the power supply unit 4 are provided separately, but the internal circuit 3 and the power supply unit 4 may be integrated. In FIG. 1, the control unit 2 is provided in the internal circuit 3, but the control unit 2 may be provided separately from the internal circuit 3.

  The monitor units 1_1 to 1_N are provided at a plurality of locations in the internal circuit 3. The monitor units 1_1 to 1_N are provided for monitoring the characteristics of the internal circuit 3. For this reason, it is preferable that the monitor units 1_1 to 1_N are equally arranged in the internal circuit 3. Signals C_1 to C_N output from the monitor units 1_1 to 1_N are supplied to the control unit 2.

  FIG. 2 is a block diagram illustrating an example of the monitor unit 1_N included in the semiconductor device according to the present embodiment. The monitor unit 1_N includes a ring oscillator 11 and a counter 12. The ring oscillator 11 includes a NAND 1 and a delay element 13. As the delay element 13, for example, a buffer circuit or an even number of inverters (NOT gates) connected in series can be used. In addition, although an odd number of inverters connected in series may be used as the delay element 13, in this case, it is necessary to replace NAND1 with an AND circuit.

  An enable signal EN_N output from the control unit 2 is supplied to one input of the NAND 1. The output of the NAND 1 is supplied to the delay element 13. The output of the delay element 13 is supplied to the other input of the NAND 1 and the counter 12. The counter 12 is supplied with a reset signal output from the control unit 2. The count value C_N of the counter 12 is output to the control unit 2 as a signal indicating the characteristics of the place where the monitor unit 1_N is provided.

  The ring oscillator 11 does not oscillate when the enable signal EN_N is in an inactive state (that is, low level “0”). On the other hand, the ring oscillator 11 oscillates at a predetermined cycle when the enable signal EN_N is at a high level (that is, the active state “1”). Therefore, the ring oscillator 11 repeatedly outputs a low level signal and a high level signal to the counter 12 while the enable signal EN_N is at a high level. The counter 12 measures the number of times that the ring oscillator 11 has oscillated (that is, the number of pulses output from the ring oscillator 11) while the enable signal EN_N is at a high level. The controller 2 outputs a reset signal to the counter 12 to reset the counter value before measuring the number of times the ring oscillator 11 has oscillated.

  The count value C_N output from the counter 12 at this time indicates the characteristics of the internal circuit 3 where the monitor unit 1_N is disposed. That is, it can be said that the higher the count value C_N, the higher the oscillation frequency of the ring oscillator 11, and thus the faster the elements constituting the ring oscillator 11. Conversely, it can be said that the smaller the count value C_N, the lower the oscillation frequency of the ring oscillator 11, and thus the slower the elements constituting the ring oscillator 11.

  The control unit 2 generates a control signal CTRL for controlling the power supply unit 4 based on the signals C_1 to C_N output from the plurality of monitor units 1_1 to 1_N, and outputs the control signal CTRL to the power supply unit 4 . That is, the control unit 2 controls the power supply unit 4 according to the comparison result between the monitor value calculated based on the signals C_1 to C_N output from the plurality of monitor units 1_1 to 1_N and the set comparison value. . At this time, the control part 2 can set a comparison value according to the dispersion | variation in the characteristic in several monitor part 1_1-1_N.

  FIG. 3 is a block diagram illustrating an example of a control unit included in the semiconductor device according to the present embodiment. As shown in FIG. 3, the control unit 2 includes a variation value calculation unit 21, a monitor value calculation unit 22, a register 23, and a comparison unit 24.

  The monitor value calculation unit 22 calculates a monitor value C_AVE for comparison with the comparison value COMP in the comparison unit 24 based on signals (that is, count values) C_1 to C_N output from the plurality of monitor units 1_1 to 1_N. For example, as the monitor value C_AVE, an average value of the count values C_1 to C_N in the plurality of monitor units 1_1 to 1_N can be used. However, the monitor value C_AVE is not limited to the average value of the count values C_1 to C_N. For example, one value selected from the count values C_1 to C_N may be used. Values determined by the method can also be used.

  FIG. 4 is a block diagram illustrating an example of the monitor value calculation unit 22 illustrated in FIG. The monitor value calculation unit 22 illustrated in FIG. 4 is a circuit that calculates an average value of the count values C_1 to C_N as the monitor value C_AVE. FIG. 4 shows a case where the monitor value calculation unit 22 calculates the monitor value C_AVE using the four count values C_1 to C_4 as an example.

  The monitor value calculation unit 22 illustrated in FIG. 4 includes adders 30_1 to 30_3 and an averaging circuit 31. The adder 30_1 receives the count value C_1 and the count value C_2, and outputs a value obtained by adding these values to the adder 30_3. The adder 30_2 receives the count value C_3 and the count value C_4, and outputs a value obtained by adding these values to the adder 30_3. The adder 30_3 inputs the value output from the adder 30_1 and the value output from the adder 30_2, and outputs a value obtained by adding these values to the averaging circuit 31. That is, the value input to the averaging circuit 31 is a value obtained by adding all the count values C_1 to C_4. The averaging circuit 31 divides the value obtained by adding all the count values C_1 to C_4 by the number of count values (in this case, “4”), and outputs the value after the division as the monitor value C_AVE. For example, when the count value is expressed in binary, the averaging circuit 31 shifts right by 2 bits.

  In the above example, the case where the count value is four is shown as an example, but the circuit can be similarly configured even when the count value is four or more. That is, a plurality of adders for adding all the count values C_1 to C_N are provided. Then, the monitor value C_AVE can be calculated by dividing the value obtained by adding all the count values C_1 to C_N by the number (N) of the count values in the averaging circuit 31.

  The variation value calculation unit 21 illustrated in FIG. 3 can calculate, for example, the standard deviation (σ) of the count values C_1 to C_N in the plurality of monitor units 1_1 to 1_N as the variation value C_VAR. FIG. 5 is a block diagram illustrating an example of the variation value calculation unit 21. The variation value calculation unit 21 illustrated in FIG. 5 is a circuit that calculates the standard deviation (σ) of the count values C_1 to C_N as the variation value C_VAR. FIG. 5 shows an example in which the variation value calculation unit 21 calculates the variation value C_VAR using the four count values C_1 to C_4.

  The variation value calculation unit 21 illustrated in FIG. 5 includes subtractors 32_1 to 32_4, multipliers 33_1 to 33_4, adders 34_1 to 34_3, a divider 35, and a square root calculator 36. The subtractor 32_1 receives the count value C_1 and the average value C_AVE of the count values C_1 to C_4, and outputs a value (C_1-C_AVE) obtained by subtracting these values to the multiplier 33_1. Here, the average value C_AVE of the count values C_1 to C_4 can be obtained by using, for example, the monitor value calculation unit 22 shown in FIG. Thereafter, the same operation is performed for the subtractors 32_2 to 32_4.

The multiplier 33_1 receives the value (C_1-C_AVE) output from the subtractor 32_1 and outputs a value (C_1-C_AVE) ² obtained by squaring this value to the adder 34_1. The multiplier 33_2 receives the value (C_2-C_AVE) output from the subtractor 32_2, and outputs a value (C_2-C_AVE) ² obtained by squaring the value to the adder 34_1. Thereafter, the same operation is performed for the multipliers 33_3 to 33_4.

The adder 34_1 receives the value (C_1-C_AVE) ² output from the multiplier 33_1 and the value (C_2-C_AVE) ² output from the multiplier 33_2, and adds the value obtained by adding these values to the adder 34_3. Output to. The adder 34_2 receives the value (C_3-C_AVE) ² output from the multiplier 33_3 and the value (C_4-C_AVE) ² output from the multiplier 33_4, and adds the value obtained by adding these values to the adder 34_3. Output to. The adder 34_3 is a value obtained by adding the value output from the adder 34_1 and the value output from the adder 34_2 (that is, (C_1−C_AVE) ² + (C_2−C_AVE) ² + (C_3−C_AVE) ^2. + (C_4−C_AVE) ² ) is output to the divider 35.

The divider 35 divides the value output from the adder 34_3 by the number of count values “4”. For example, when the count value is expressed in binary, it is shifted right by 2 bits. The value obtained by the divider 35 is a dispersion value (σ ² ) of the count values C_1 to C_4. The square root calculator 36 calculates the standard deviation (σ) by calculating the square root of the variance (σ ² ) output from the divider 35. The obtained standard deviation (σ) is output to the comparison unit 24 as the variation value C_VAR.

  The register 23 illustrated in FIG. 3 stores a plurality of comparison values A (26_1), a comparison value B (26_2), and a comparison value C (26_3). The number of comparison values stored in the register 23 can be arbitrarily determined. The comparison value includes a set value (first set value) corresponding to the upper limit value of the monitor value C_AVE and a set value (second set value) corresponding to the lower limit value of the monitor value C_AVE. FIG. 6 shows an example of the comparison value stored in the register 23.

  As illustrated in FIG. 6, the register 23 stores, for example, as a comparison value A, a lower limit set value C_L_set_1 and an upper limit set value C_H_set_1. Here, the lower limit set value C_L_set_1 is a value set to prevent the monitor value C_AVE from becoming lower than this value. The upper limit set value C_H_set_1 is a value set to prevent the monitor value C_AVE from becoming higher than this value. That is, the control unit 2 generates the control signal CTRL such that the monitor value C_AVE is between the set value C_L_set_1 and the set value C_H_set_1.

  Similarly, the register 23 stores a lower limit set value C_L_set_2 and an upper limit set value C_H_set_2 as the comparison value B. The register 23 stores a lower limit set value C_L_set_3 and an upper limit set value C_H_set_3 as the comparison value C.

  Then, the register 23 sets the comparison value COMP according to the characteristic variation in the plurality of monitor units 1_1 to 1_N. That is, the register 23 sets the comparison value COMP according to the variation value C_VAR of the count values C_1 to C_N output from the variation value calculation unit 21. The set comparison value COMP is output to the comparison unit 24.

  Here, for example, the interval between the upper limit set value C_H_set_1 of the comparison value A and the lower limit set value C_L_set_1 is set wider than the interval between the upper limit set value C_H_set_2 of the comparison value B and the lower limit set value C_L_set_2. Shall. The interval between the upper limit set value C_H_set_2 of the comparison value B and the lower limit set value C_L_set_2 is set to be wider than the interval between the upper limit set value C_H_set_3 of the comparison value C and the lower limit set value C_L_set_3. .

  Further, the upper limit set value C_H_set_1 of the comparison value A is larger than the upper limit set value C_H_set_2 of the comparison value B, and the upper limit set value C_H_set_2 of the comparison value B is larger than the upper limit set value C_H_set_3 of the comparison value C. It is assumed that it is set. The lower limit setting value C_L_set_1 of the comparison value A is larger than the lower limit setting value C_L_set_2 of the comparison value B, and the lower limit setting value C_L_set_2 of the comparison value B is larger than the lower limit setting value C_L_set_3 of the comparison value C. It is assumed that it is set.

  In the semiconductor device according to the present embodiment, the register 23 compares as the variation of the count values C_1 to C_N output from the variation value calculation unit 21 decreases, that is, as the variation value (standard deviation) C_VAR decreases. The comparison value COMP is set so that the upper limit setting value of the value COMP is reduced and the interval between the upper limit setting value and the lower limit setting value of the comparison value COMP is narrowed.

  Referring to FIG. 6, when there is a relationship of a> b> c> d, and when the variation value (standard deviation) C_VAR is large (a> C_VAR ≧ b), the register 23 sets the comparison value A as the comparison value COMP. Output. When the variation value (standard deviation) C_VAR is relatively large (b> C_VAR ≧ c), the register 23 outputs the comparison value B as the comparison value COMP. When the variation value (standard deviation) C_VAR is relatively small (c> C_VAR ≧ d), the register 23 outputs the comparison value C as the comparison value COMP.

  The comparison unit 24 compares the comparison value COMP output from the register 23 with the monitor value C_AVE output from the monitor value calculation unit 22, and the monitor value C_AVE determines the upper limit set value and the lower limit set value of the comparison value COMP. A control signal CTRL is generated so as to be between and is output to the power supply unit 4. The control signal CTRL is a signal corresponding to the specification of the power supply unit 4, and is, for example, an encoded signal.

  The power supply unit 4 controls the power supply voltage Vdd supplied to the internal circuit 3 according to the control signal CTRL output from the comparison unit 24 of the control unit 2. Specifically, when the monitor value C_AVE becomes larger than the upper limit set value of the comparison value COMP, the operating frequency in the monitor unit is high, so that the control unit 2 supplies power so that the supplied power supply voltage Vdd is low. The supply unit 4 is controlled. On the contrary, when the monitor value C_AVE is smaller than the lower limit set value of the comparison value COMP, the operating frequency in the monitor unit is low, so that the control unit 2 supplies the power supply unit so that the supplied power supply voltage Vdd becomes high. 4 is controlled.

  7 and 8 are diagrams for explaining the effects of the invention according to the present embodiment. First, the effect of the invention according to the present embodiment will be described with reference to FIG. In a predetermined circuit formed in the internal circuit 3, a design value of a voltage for realizing a predetermined performance is V_nom. At this time, since the characteristics (chip performance) of the internal circuit 3 vary, as shown in the upper diagram of FIG. 7, the voltage for realizing the predetermined performance in the predetermined circuit formed in the internal circuit 3 The value is V_min_s (minimum value) to V_max_s (maximum value). That is, the voltage value for realizing the predetermined performance is distributed around V_nom. The standard deviation at this time is σ1.

  At this time, the power supply unit 4 needs to supply the power supply voltage Vdd of V_min_s to V_max_s in order to achieve a predetermined performance in a predetermined circuit formed in the internal circuit 3. When the variation in the characteristics of the internal circuit 3 is large (the upper diagram in FIG. 7), the monitor value and the performance of the internal circuit 3 are different from each other. Therefore, it is necessary to provide a margin for the power supply voltage, and the maximum voltage value V_max_s is increased There is a need to.

  On the other hand, as shown in the lower diagram of FIG. 7, when the variation in the characteristics (chip performance) of the internal circuit 3 is small, the standard deviation of the voltage values V_min_s to V_max_s ′ for realizing the predetermined performance is small (at this time) Is standard deviation). At this time, as shown in FIG. 7, the minimum voltage V_min_s for realizing the predetermined performance can be made the same in the case where the standard deviation is σ1 and in the case of σ2. Therefore, as shown in the lower diagram of FIG. 7, when the standard deviation is σ2, the variation in the characteristics of the internal circuit 3 is small, so the maximum voltage value V_max_s ′ is the maximum voltage value when the standard deviation is σ1. It can be made smaller than V_max_s by the amount indicated by reference numeral 52.

  In other words, when the variation in the characteristics of the internal circuit 3 is small (standard deviation σ2), the maximum value of the set voltage can be set to V_max_s ′. On the other hand, when the variation in the characteristics of the internal circuit 3 is large (standard deviation σ1), the maximum value of the set voltage needs to be the voltage V_max_s provided with a margin indicated by reference numeral 52 in the maximum value V_max_s ′ when the variation is small. is there.

  Conventionally, since the comparison value to be compared with the monitor value C_AVE is a fixed value, the maximum value V_maxs of the voltage for realizing the predetermined performance is set high, assuming that the variation in the characteristics of the internal circuit 3 is large. There was a need to do. Therefore, originally, even when the variation in the characteristics of the internal circuit 3 is small and the maximum voltage value for realizing the predetermined performance can be set low, the maximum voltage value is increased. Therefore, there is a problem that the power consumption of the semiconductor device increases.

  On the other hand, in the semiconductor device according to the present embodiment, the variation value calculation unit 21 calculates the variation values C_VAR of the count values C_1 to C_N in the plurality of monitor units 1_1 to 1_N, and compares them according to the variation values C_VAR. The comparison value COMP used in the unit 24 is determined. That is, when the variation in the characteristics of the internal circuit 3 is large, a comparison value with a large set value for the upper limit of the comparison value and a wide interval between the upper limit value and the lower limit value of the comparison value can be used as the comparison value COMP ( (See the upper diagram in FIG. 7). On the other hand, when the variation in the characteristics of the internal circuit 3 is small, a comparison value having a small comparison value upper limit setting value and a narrow interval between the comparison value upper limit value and lower limit value can be used as the comparison value COMP ( (See the lower diagram in FIG. 7).

  As described above, in the semiconductor device according to the present embodiment, the comparison value COMP used in the comparison unit 24 can be changed in accordance with the variation in the characteristics of the internal circuit 3. An optimal comparison value can be used. Therefore, it is not necessary to provide a useless margin for the comparison value, so that power consumption of the semiconductor device can be reduced.

  FIG. 8 is a diagram for explaining the effect of the invention according to the present embodiment. The voltage in FIG. 7 corresponds to the speed (count value) shown in FIG. As shown in FIG. 8, when the variation in the characteristics of the internal circuit 3 is large, the comparison value A (see FIG. 6) is used as the comparison value COMP. That is, as the comparison value COMP, a comparison value having an upper limit set value of C_H_set_1 and a lower limit set value of C_L_set_1 is used.

  When the monitor value C_AVE becomes larger than the upper limit set value C_H_set_1, the control unit 2 lowers the power supply voltage Vdd supplied from the power supply unit 4, and the monitor value C_AVE becomes smaller than the lower limit set value C_L_set_1. If this happens, the power supply voltage Vdd supplied from the power supply unit 4 is increased. By such control, the monitor value C_AVE can be kept between the lower limit set value C_L_set_1 and the upper limit set value C_H_set_1.

  In the case shown in the upper diagram of FIG. 8, since the characteristic variation of the internal circuit 3 is large, the upper limit set value C_H_set_1 is large as the comparison value COMP, and the interval between the upper limit set value C_H_set_1 and the lower limit set value C_L_set_1 53 uses a wide comparison value. On the other hand, since the variation in the characteristics of the internal circuit 3 is small in the case shown in the lower part of FIG. 8, the upper limit set value C_H_set_2 is smaller than the set value C_H_set_1 as the comparison value COMP and the upper limit set value C_H_set_2 and the lower limit of the comparison value A comparison value with a narrow interval 54 of the set value C_L_set_2 can be used.

  For example, when the variation in the characteristics of the internal circuit 3 is large (the upper diagram in FIG. 8), it is necessary to perform control so that the monitor value C_AVE is at the position of reference numeral 55. However, when the variation in the characteristics of the internal circuit 3 is small (the lower diagram in FIG. 8), the upper limit set value C_H_set_2 of the comparison value COMP can be set low, so that the monitor value C_AVE becomes a smaller value. The power supply voltage Vdd can be controlled (that is, the power supply voltage Vdd can be lowered).

  As described above, in the semiconductor device according to the present embodiment, the comparison value COMP used in the comparison unit 24 can be changed in accordance with the variation in the characteristics of the internal circuit 3, so that the variation in the characteristics of the internal circuit 3 can be changed. The optimum comparison value can be used according to the above. Therefore, it is not necessary to provide a useless margin for the comparison value, so that power consumption of the semiconductor device can be reduced.

  Therefore, the invention according to this embodiment can provide a semiconductor device and a power supply method capable of reducing power consumption.

<Embodiment 2>
Next, a second embodiment of the present invention will be described. In the semiconductor device according to the second embodiment, the configuration of the variation value calculation unit is different from that of the variation value calculation unit 21 described in the first embodiment. Since other than this is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 9 is a block diagram showing a variation value calculation unit 21 ′ included in the semiconductor device according to the present embodiment. The variation value calculation unit 21 ′ illustrated in FIG. 9 includes a maximum value calculation unit 37, a minimum value calculation unit 38, and a subtractor 39. FIG. 9 shows a case where the variation value calculation unit 21 ′ calculates the variation value C_VAR using four count values C_1 to C_4 as an example.

  The maximum value calculation unit 37 extracts the maximum value from the count values C_1 to C_4 and outputs the maximum value C_MAX to the subtractor 39. FIG. 11 is a block diagram illustrating an example of the maximum value calculation unit 37. The maximum value calculation unit 37 includes comparators 41_1 to 41_3. The comparator 41_1 receives the count values C_1 and C_2, and outputs the count value with the larger count value to the comparator 41_3. The comparator 41_2 receives the count values C_3 and C_4, and outputs the count value having the larger count value to the comparator 41_3. The comparator 41_3 outputs the larger count value of the count value output from the comparator 41_1 and the count value output from the comparator 41_2 as the maximum value C_MAX.

  FIG. 13 is a block diagram illustrating an example of the comparator 41_1 (the comparator 41_2 and the comparator 41_2 have the same configuration). The comparator 41_1 includes a subtractor 43 and a determination unit 44. The subtractor 43 receives the count value C_1 and the count value C_2, and outputs a value obtained by subtracting the count value C_2 from the count value C_1 to the determination unit 44. The determination unit 44 outputs the count value C_1 when the input value is a positive value, and outputs the count value C_2 when the input value is a negative value. When the count value is expressed in 2 bits, the determination unit 44 outputs the count value C_1 when the MSB (Most Significant Bit) of the input value is “0”, and the MSB of the input value is “ In the case of 1 ", the count value C_2 is output. At this time, when the negative integer is represented by 2's complement, the MSB is “1”.

  The minimum value calculation unit 38 illustrated in FIG. 9 extracts the minimum value from the count values C_1 to C_4 and outputs the minimum value C_MIN to the subtractor 39. FIG. 12 is a block diagram illustrating an example of the minimum value calculation unit 38. The minimum value calculation unit 38 includes comparators 42_1 to 42_3. The comparator 42_1 receives the count values C_1 and C_2, and outputs the count value having the smaller count value to the comparator 42_3. The comparator 42_2 receives the count values C_3 and C_4, and outputs the count value having the smaller count value to the comparator 42_3. The comparator 42_3 outputs the smaller count value of the count value output from the comparator 42_1 and the count value output from the comparator 42_2 as the minimum value C_MIN.

  FIG. 14 is a block diagram illustrating an example of the comparator 42_1 (the comparator 42_2 and the comparator 42_2 have the same configuration). The comparator 42_1 includes a subtracter 45 and a determination unit 46. The subtracter 45 receives the count value C_1 and the count value C_2, and outputs a value obtained by subtracting the count value C_2 from the count value C_1 to the determination unit 46. The determination unit 46 outputs the count value C_2 when the input value is a positive value, and outputs the count value C_1 when the input value is a negative value. When the count value is expressed by 2 bits, the determination unit 46 outputs the count value C_2 when the MSB (Most Significant Bit) of the input value is “0”, and the MSB of the input value is “ In the case of 1 ", the count value C_1 is output. At this time, when the negative integer is represented by 2's complement, the MSB is “1”.

  9 receives the maximum value C_MAX output from the maximum value calculator 37 and the minimum value C_MIN output from the minimum value calculator 38, and subtracts the minimum value C_MIN from the maximum value C_MAX. Is output as a variation value C_VAR. That is, in this embodiment, the variation value C_VAR increases as the difference between the maximum count value C_MAX and the minimum count value C_MIN increases. On the other hand, the smaller the difference between the maximum count value C_MAX and the minimum count value C_MIN, the smaller the variation value C_VAR.

  In the present embodiment, a variation value calculation unit 21 ″ shown in FIG. 10 may be used. The variation value calculation unit 21 ″ illustrated in FIG. 10 adds a divider 40 to the variation value calculation unit 21 ′ illustrated in FIG. That is, in this embodiment, a value obtained by subtracting the minimum value C_MIN of the count value from the maximum value C_MAX of the count value and further dividing by the average value of the count value ((C_MAX−C_MIN) / C_AVE) is used as the variation value. It may be used.

  In the variation value calculation unit 21 described in the first embodiment, the standard deviation is obtained as the variation value. At this time, since it is necessary to calculate squares and square roots, the configuration of the variation value calculation unit 21 is relatively complicated (see FIG. 5). Therefore, the amount of calculation when calculating the variation value C_VAR from the count values C_1 to C_N increases, and the calculation sometimes takes time.

  On the other hand, in this embodiment, as shown in FIGS. 9 to 14, the variation value calculation unit 21 ′ can be configured with a relatively simple configuration. Therefore, the amount of calculation when calculating the variation value C_VAR from the count values C_1 to C_N can be reduced, and the time required for calculating the variation value C_VAR can be shortened.

<Embodiment 3>
Next, a third embodiment of the present invention will be described. In the semiconductor device according to the third embodiment, the configuration of the monitor unit is different from the monitor unit 1_N (see FIG. 2) described in the first embodiment. Since other than this is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 15 is a block diagram showing a monitor unit 60 provided in the semiconductor device according to the present embodiment. A monitor unit 60 illustrated in FIG. 15 corresponds to each of the monitor units 1_1 to 1_N illustrated in FIG. That is, a plurality of monitor units 60 are provided at a plurality of locations in the internal circuit 3. The monitor unit 60 illustrated in FIG. 15 includes a monitor element 61 (first monitor element) and a monitor element 62 (second monitor element). Here, the monitor elements 61 and 62 include the same number of ring oscillators.

  The monitor element 61 includes a NAND 11, a plurality of inverters INV11_1 to INV11_N, and a counter 63. Here, the NAND 11 and the plurality of inverters INV11_1 to INV11_N constitute a ring oscillator, and an even number of inverters INV11_1 to INV11_N are connected in series.

  An enable signal EN_a output from the control unit 2 is supplied to one input of the NAND 11. The output of the inverter INV11_N is output to the other input of the NAND 11 and the counter 63. A reset signal output from the control unit 2 is supplied to the counter 63. The count value C_N_a of the counter 63 is output to the control unit 2 as a signal indicating the characteristics of the place where the monitor unit 60 is provided.

  The monitor element 62 includes a NAND 12, a plurality of inverters INV12_1 to INV12_N, and a counter 64. Here, the NAND 12 and the plurality of inverters INV12_1 to INV12_N constitute a ring oscillator, and an even number of inverters INV12_1 to INV12_N are connected in series.

  An enable signal EN_b output from the control unit 2 is supplied to one input of the NAND 12. The output of the inverter INV12_N is output to the other input of the NAND 12 and the counter 64. The counter 64 is supplied with a reset signal output from the control unit 2. The count value C_N_b of the counter 64 is output to the control unit 2 as a signal indicating the characteristics of the place where the monitor unit 60 is provided.

  FIG. 16 is a timing chart for explaining the operation of the monitor unit 60, and shows the waveforms of the enable signal EN_a supplied to the monitor element 61 and the enable signal EN_b supplied to the monitor element 62. As shown in FIG. 16, the enable signal EN_a supplied to the monitor element 61 is at a high level only during the monitoring period for monitoring the characteristics of the internal circuit 3. That is, the monitor element 61 operates in the same manner as the monitor unit 1_N described in the first embodiment.

  On the other hand, the enable signal EN_b supplied to the monitor element 62 is at a high level even outside the monitoring period. During the period when the enable signal EN_b is at the high level, the ring oscillator composed of the NAND 12 and the plurality of inverters INV12_1 to INV12_N oscillates. Since the ring oscillator included in the monitor element 62 oscillates longer than the ring oscillator included in the monitor element 61, the monitor element 62 deteriorates faster than the monitor element 61.

  At this time, the count value C_N_b reflecting the deterioration state of the circuit included in the internal circuit 3 can be output by approximating the period during which the enable signal EN_b is at the high level to the operation period of the circuit included in the internal circuit 3. .

  That is, when the deterioration of the circuit included in the internal circuit 3 has not progressed with time, the count value C_N_a of the monitor element 61 and the count value C_N_b of the monitor element 62 are substantially the same value in the same monitoring period. On the other hand, when the deterioration of the circuit included in the internal circuit 3 is progressing, the count value C_N_b of the monitor element 62 reflecting the deterioration state of the circuit included in the internal circuit 3 and the count of the monitor element 61 that operates only during the monitoring period. There is a difference between the value C_N_a. Therefore, when there is a difference between the count value C_N_a of the monitor element 61 and the count value C_N_b of the monitor element 62, the control unit 2 uses the count value C_N_b of the monitor element 62, thereby Control reflecting aging deterioration can be performed.

  For example, when the operation speed of the circuit element becomes slow due to deterioration of the circuit included in the internal circuit 3, the count value C_N_b of the monitor element 62 becomes smaller than the count value C_N_a of the monitor element 61. In this case, the control unit 2 can appropriately control the power supply voltage Vdd supplied to the internal circuit 3 by using the count value C_N_b of the monitor element 62. In other words, when the delay amount of the monitor element 62 with respect to the monitor element 61 becomes larger than a predetermined value, the control unit 2 sets a comparison value using the count value C_N_b that is the monitor result of the monitor element 62. be able to.

  As described above, in the semiconductor device according to the present embodiment, the monitor unit 60 is provided with the monitor element 61 that operates only during the monitor period and the monitor element 62 that operates outside the monitor period. When there is a difference between the count value C_N_a of the monitor element 61 and the count value C_N_b of the monitor element 62, the control reflecting the aging of the circuit included in the internal circuit 3 by using the count value C_N_b of the monitor element 62 Can do.

<Embodiment 4>
Next, a fourth embodiment of the present invention will be described. In the semiconductor device according to the fourth embodiment, the configuration of the monitor unit is different from the monitor unit 1_N (see FIG. 2) described in the first embodiment. Since other than this is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 17 is a block diagram showing a monitor unit 70 provided in the semiconductor device according to the present embodiment. A monitor unit 70 illustrated in FIG. 17 corresponds to each of the monitor units 1_1 to 1_N illustrated in FIG. That is, a plurality of monitor units 70 are provided at a plurality of locations in the internal circuit 3. The monitor unit 70 illustrated in FIG. 15 includes a monitor element 71 (third monitor element) and a monitor element 72 (fourth monitor element).

  The monitor element 71 includes a NAND 21, a plurality of inverters INV21_1 to INV21_N, and a counter 73. Here, the NAND 21 and the plurality of inverters INV21_1 to INV21_N constitute a ring oscillator, and an even number of inverters INV21_1 to INV21_N are connected in series.

  An enable signal EN_c output from the control unit 2 is supplied to one input of the NAND 21. The output of the inverter INV21_N is output to the other input of the NAND 21 and the counter 73. The counter 73 is supplied with a reset signal output from the control unit 2. The count value C_N_c of the counter 73 is output to the control unit 2 as a signal indicating the characteristics of the place where the monitor unit 70 is provided.

  The monitor element 72 includes a NAND 22, a plurality of inverters INV22_1 to INV22_M, and a counter 74. Here, the NAND 22 and the plurality of inverters INV22_1 to INV22_M constitute a ring oscillator, and an even number of inverters INV22_1 to INV22_M are connected in series. M is an integer larger than N.

  An enable signal EN_d output from the control unit 2 is supplied to one input of the NAND 22. The output of the inverter INV22_M is output to the other input of the NAND 22 and the counter 74. The counter 74 is supplied with a reset signal output from the control unit 2. The count value C_N_d of the counter 74 is output to the control unit 2 as a signal indicating the characteristics of the place where the monitor unit 70 is provided.

  In the present embodiment, the enable signal EN_c supplied to the monitor element 71 and the enable signal EN_d supplied to the monitor element 72 are the same signal. That is, the monitoring period during which the monitor element 71 and the monitor element 72 operate is the same period. However, since the number of inverters included in the monitor element 71 and the number of inverters included in the monitor element 72 are different, the count value C_N_c output from the monitor element 71 and the count value C_N_d output from the monitor element 72 are different.

  Here, the types of variations of the internal circuit 3 mainly include systematic variations and random variations. The systematic variation is a variation in a relatively wide range, and can be detected using, for example, monitor units provided at a plurality of locations in the internal circuit 3. On the other hand, random variation is variation in a relatively narrow range.

  In the present embodiment, by providing a plurality of monitor elements 71 and 72 in the monitor unit 70, it is possible to detect random variations. That is, as shown in FIG. 17, in this embodiment, two monitor elements having different numbers of inverters are provided. Specifically, the number of inverters INV22_1 to INV22_M of the monitor element 72 is made larger than the number of inverters INV21_1 to INV21_N of the monitor element 71. A random variation in the monitor unit can be detected by comparing a value obtained by multiplying the count value C_N_d of the monitor element 72 by the inverter stage number ratio (N / M) with the count value C_N_c of the monitor element 71. it can.

  In other words, the count value C_N_d of the monitor element 72 having a large number of inverter stages is a count value reflecting the variation of a larger number of gates than the number of gates on which the monitor element 71 is formed, and therefore the count value C_N_c of the monitor element 71. However, the influence of random variation is small (random variation is proportional to the reciprocal of the square root of the number of gate stages). Therefore, when the difference between the value obtained by multiplying the count value C_N_d of the monitor element 72 by the inverter stage number ratio (N / M) and the count value C_N_c of the monitor element 71 is small, it is determined that the random variation is small. Can do. Conversely, if the difference between the value obtained by multiplying the count value C_N_d of the monitor element 72 by the inverter stage number ratio (N / M) and the count value C_N_c of the monitor element 71 is large, it is determined that the random variation is large. be able to.

  The control unit 2 can determine the comparison value COMP used in the comparison unit in consideration of random variations in the monitor unit. That is, the comparison value COMP used in the comparison unit 24 is determined in consideration of the systematic variation obtained from the count values of the plurality of monitor units and the random variation obtained from the two monitor elements of each monitor unit. be able to. In other words, the control unit 2 can detect variation in characteristics in the monitor unit 70 based on the monitoring result of the monitoring element 71 and the monitoring result of the monitoring element 72, and set the comparison value COMP according to the variation.

  In the semiconductor device according to the present embodiment, the comparison value COMP used in the comparison unit 24 can be determined in consideration of random variation in addition to systematic variation, and therefore the power supply voltage Vdd supplied to the internal circuit. Can be controlled more appropriately.

<Embodiment 5>
Next, a fifth embodiment of the present invention will be described. In the semiconductor device according to the fifth embodiment, the configuration of the control unit is different from that of the control unit 3 (see FIG. 3) described in the first embodiment. Since other than this is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 18 is a block diagram illustrating an example of the control unit 80 included in the semiconductor device according to the present embodiment. As illustrated in FIG. 18, the control unit 80 includes a comparison value generation unit 81, a monitor value calculation unit 22, a register 83, a selector 84, and a comparison unit 24.

  The comparison value generation unit 81 receives the count values C_1 to C_N in the plurality of monitor units 1_1 to 1_N, and generates a comparison value according to these variation values (for example, standard deviation (σ)). Further, the comparison value generation unit 81 is supplied with a power-on signal PWR_ON indicating the timing when power is supplied to the internal circuit. The comparison value generator 81 generates a comparison value at the timing when the power-on signal PWR_ON is input, for example. The power-on signal PWR_ON is supplied from the outside through, for example, a terminal.

  The comparison value generated by the comparison value generation unit 81 is basically the same as the comparison value A, comparison value B, comparison value C,... According to the first embodiment. At this time, the comparison value generation unit 81 may generate a comparison value in consideration of the aging of the internal circuit (see Embodiment 3), and in addition to the systematic variation, the comparison value is also considered in consideration of random variation. A value may be generated (see Embodiment 4). The comparison value generated by the comparison value generation unit 81 is output to the selector 84.

  The register 83 stores a comparison value (fixed value). The comparison value stored in the register 83 is a comparison value that can be used for general purposes. For example, assuming that the variation in the characteristics of the internal circuit 3 is large, a comparison value in which the maximum value V_maxs of the voltage for realizing the predetermined performance is set higher (FIG. 7, upper diagram, FIG. 8). (See the above figure). That is, the comparison value stored in the register 83 is a comparison value that secures a large margin on the assumption that the variation in the characteristics of the internal circuit 3 is large. The comparison value (fixed value) stored in the register 83 is output to the selector 84.

  The selector 84 selects the comparison value (variable value) generated by the comparison value generation unit 81 or the comparison value (fixed value) stored in the register 83 according to the selection signal SEL, and selects the selected comparison value COMP. Is output to the comparator 24. The selection signal SEL may be supplied from the outside via, for example, a terminal, or may be supplied from a setting register (not shown).

  19A and 19B are timing charts for explaining the operation of the control unit 80 according to the present embodiment. The timing chart shown in FIG. 19A shows an operation when the power-on signal PWR_ON becomes high level after the selection signal SEL becomes high level. In the timing chart shown in FIG. 19B, an operation in the case where the power-on signal PWR_ON becomes high level before the selection signal SEL becomes high level is shown.

  First, the timing chart shown in FIG. 19A will be described. In the initial state, the selection signal SEL and the power-on signal PWR_ON are at a low level. Since the selection signal SEL is at the low level, the selector 84 selects the comparison value (fixed value) stored in the register 83. When the selection signal SEL transitions from the low level to the high level at the timing t1, the selector 84 selects the comparison value (variable value) generated by the comparison value generation unit 81. At this time, the selector 84 outputs the comparison value COMP1 (the comparison value before being updated by the comparison value generation unit 81) to the comparison unit 24. Thereafter, when the power-on signal PWR_ON transitions from the low level to the high level at timing t2, the comparison value generation unit 81 generates a comparison value based on the count values C_1 to C_N. The generated comparison value COMP2 is supplied to the comparison unit 24 via the selector 84.

  Next, the timing chart shown in FIG. 19B will be described. In the initial state, the selection signal SEL and the power-on signal PWR_ON are at a low level. Since the selection signal SEL is at the low level, the selector 84 selects the comparison value (fixed value) stored in the register 83. When the power-on signal PWR_ON transitions from the low level to the high level at timing t11, the comparison value generation unit 81 generates a comparison value based on the count values C_1 to C_N. The generated comparison value COMP2 is output to the selector 84. Thereafter, when the selection signal SEL transitions from the low level to the high level at the timing t12, the selector 84 selects the comparison value COMP2 generated by the comparison value generation unit 81 and outputs the comparison value COMP2 to the comparison unit 24.

  FIG. 20 is a flowchart for explaining the operation of the semiconductor device according to the present embodiment. First, the control unit 80 determines whether or not an interrupt has occurred (step S1). That is, it is determined that an interrupt has occurred when the power-on signal PWR_ON is at a high level. When there is an interruption (step S1: Yes), the control unit 80 adds up the monitor results (step S2). That is, the control unit 80 acquires and counts the count values C_1 to C_N in the monitor units 1_1 to 1_N. Thereafter, the comparison value generation unit 81 of the control unit 80 calculates a variation value using the count values C_1 to C_N (step S3), and generates a comparison value corresponding to the calculated variation value. In this way, the comparison value generation unit 81 updates the comparison value (step S4).

  The comparison unit 24 compares the comparison value COMP generated (updated) by the comparison value generation unit 81 with the monitor value C_AVE calculated by the monitor value calculation unit 22 (step S5). When the monitor value C_AVE is within the range of the comparison value COMP (step S6: Yes), the voltage control operation is terminated and the normal operation is resumed. On the other hand, when the monitor value C_AVE is outside the range of the comparison value COMP (step S6: No), the comparison unit 24 controls the power supply unit 4 so that the monitor value C_AVE is within the range of the comparison value COMP.

  As described above, in the semiconductor device according to the present embodiment, the comparison value generation unit 81 can flexibly generate a comparison value, so that the power supply voltage Vdd supplied to the internal circuit is more appropriately controlled. can do.

<Embodiment 6>
Next, a sixth embodiment of the present invention will be described. The semiconductor device according to the sixth embodiment differs from the control unit 80 described in the fifth embodiment in that a timer 88 is provided in the control unit 80 ′ as shown in FIG. Since other than this is the same as that of the fifth embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  When the circuit mounted on the internal circuit 3 is activated during use, the comparison value can be updated at the timing of use, that is, the timing of power supply. At this time, the update timing of the comparison value can be set by using the power-on signal PWR_ON indicating the timing at which power is supplied to the internal circuit 3.

  However, among the circuits mounted on the internal circuit 3, there is a circuit in which the power is continuously supplied without being turned off after the power is once supplied. In such a circuit, the timing for updating the comparison value cannot be set using the power-on signal PWR_ON.

  Therefore, in the semiconductor device according to the present embodiment, a timer 88 is provided in the control unit 80 ′, and an update timing signal RNW indicating the update timing of the comparison value is output to the comparison value generation unit 81. The timer 88 can be composed of a counter to which a clock signal is supplied, for example.

  FIG. 22 is a timing chart for explaining the operation of the semiconductor device according to the present embodiment. Since the selection signal SEL is at the low level in the initial state, the selector 84 selects the comparison value (fixed value) stored in the register 83. Thereafter, at timing t21, the selection signal SEL transitions from the low level to the high level. Accordingly, the selector 84 selects the comparison value (variable value) generated by the comparison value generation unit 81. At this time, the comparison value COMP1 is output from the selector 84 to the comparison unit 24.

  Thereafter, when the update timing signal RNW becomes high level at timing t22, the comparison value generation unit 81 updates the comparison value. At this time, the comparison value output from the selector 84 to the comparison unit 24 is updated from the comparison value COMP1 to the comparison value COMP2. Further, when the update timing signal RNW becomes high level at timing t23, the comparison value generation unit 81 updates the comparison value. At this time, the comparison value output from the selector 84 to the comparison unit 24 is updated from the comparison value COMP2 to the comparison value COMP3. In this way, the comparison value generation unit 81 updates the comparison value every time the update timing signal RNW becomes high level. Other operations are the same as those in the fifth embodiment.

<Embodiment 7>
Next, a seventh embodiment of the present invention will be described. In the semiconductor device according to the seventh embodiment, the configuration of the control unit is different from that of the control unit 3 (see FIG. 3) described in the first embodiment. Since other than this is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 23 is a diagram illustrating the control unit 90 included in the semiconductor device according to the present embodiment. In the present embodiment, a monitor selection unit 93 is newly provided in the control unit 90. The monitor selection unit 93 selects a monitor unit to be used from the monitor units 1_1 to 1_N according to the monitor selection signal M_SEL. That is, the monitor selection unit 93 can select a monitor unit to be used by outputting a high-level enable signal to the monitor unit to be used. Here, the monitor selection signal M_SEL may be supplied from the outside via, for example, a terminal, or may be supplied from a setting register (not shown).

  24A and 24B are diagrams for explaining the arrangement of the monitor units. The monitor units 95 and 96 shown in FIG. 24A are arranged more than the monitor units 97 and 98 shown in FIG. 24B. That is, the characteristics of the internal circuit can be monitored more accurately by using the monitor units 95 and 96 shown in FIG. 24A. On the other hand, when there are many monitor units, there is a problem that it takes time to calculate the count value obtained by the monitor units. In addition, since the number of the monitor units 97 and 98 shown in FIG. 24B is smaller than the number of the monitor units 95 and 96 shown in FIG. 24A, the calculation processing of the count value obtained by the monitor unit takes relatively long time. There is. On the other hand, since the number of monitor units is small, the accuracy of the monitor is inferior to that shown in FIG. 24A.

  In this embodiment, the combination shown in FIG. 24A with a large number of monitor units and the combination shown in FIG. 24B with a small number of monitor units can be selected using the monitor selection signal M_SEL. Therefore, the combination of the monitor units can be changed according to the needs of the user who uses the semiconductor device.

  In the present embodiment, the number of count values used in the variation value calculation unit 21 and the number of count values used in the monitor value calculation unit 22 can be changed as appropriate. That is, the variation value calculated by the variation value calculation unit 21 is used to determine the comparison value. Therefore, the comparison value can be determined more accurately by calculating the variation value using the count values of more monitor units. On the other hand, since the monitor value calculated by the monitor value calculation unit 22 is used to monitor the change in characteristics in the internal circuit, the number of count values used by the monitor value calculation unit 22 is the variation value calculation unit 21. It can be less than the number of count values used.

  Therefore, for example, when using the combination of monitor units shown in FIG. 24A, the monitor unit 95 and the monitor unit 96 (all monitor units) are used when the variation value calculation unit 21 calculates the variation value, and the monitor value calculation unit When the monitor value is calculated at 22, only the monitor unit 95 (monitor unit indicated by oblique lines) can be used. Similarly, when the combination of monitor units shown in FIG. 24B is used, the monitor unit 97 and the monitor unit 98 (all monitor units) are used when the variation value calculation unit 21 calculates the variation value, and the monitor value calculation unit When the monitor value is calculated at 22, only the monitor unit 97 (the monitor unit indicated by oblique lines) can be used.

  As described above, in the present embodiment, the monitor selection unit 93 is provided in the control unit 90, so that the monitor unit to be used can be appropriately selected according to the use situation or the like.

<Eighth embodiment>
Next, an eighth embodiment of the present invention will be described. In the semiconductor device according to the eighth embodiment, the configuration of the monitor unit is different from the monitor unit 1_N (see FIG. 2) described in the first embodiment. Since other than this is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 25 is a block diagram illustrating an example of a monitor unit included in the semiconductor device according to the present embodiment. As illustrated in FIG. 25, the monitor unit 101_N includes flip-flops FF1 to FF4, a critical path replica tcrit, and delay elements ta and tb. The flip-flop FF1 outputs the input data to the critical path replica tcrit according to the clock signal Tclk. The critical path replica tcrit is a delay element reflecting the path with the longest delay in the circuit included in the internal circuit 3. The delay elements ta and tb are delay elements having a predetermined delay value. The critical path replica tcrit and the delay elements ta and tb are connected to each other in series.

  The flip-flop FF2 stores the data output from the delay element tb according to the clock signal Tclk, and outputs a signal F_OUT_N_1 to the control unit 2. The flip-flop FF3 stores the data output from the delay element ta according to the clock signal Tclk, and outputs a signal F_OUT_N_2 to the control unit 2. The flip-flop FF2 stores the data output from the critical path replica tcrit according to the clock signal Tclk, and outputs a signal F_OUT_N_3 to the control unit 2. Here, the signals F_OUT_N_1 to F_OUT_N_3 output from the flip-flops are signals indicating monitoring results in the monitor unit 101_N.

  For example, it is assumed that the flip-flop FF1 outputs data “1” at the first timing when the clock Tclk rises. At this time, the data “1” reaches the flip-flop FF2 via the critical path replica tcrit and the delay elements ta and tb. Then, at the second timing when the clock Tclk rises next, the data “1” is stored in the flip-flop FF2. In this case, “1” is output to the control unit 2 as the signal F_OUT_N_1. However, if the delay at the critical path replica tcrit and the delay elements ta and tb is too large, the clock Tclk rises at the second timing before the data “1” arrives at the flip-flop FF2, and is stored in the flip-flop FF2. Data becomes “0”.

  Similarly, it is assumed that the flip-flop FF1 outputs data “1” at the first timing when the clock Tclk rises. At this time, the data “1” reaches the flip-flop FF3 via the critical path replica tcrit and the delay element ta. Then, at the second timing when the clock Tclk rises next, data “1” is stored in the flip-flop FF3. In this case, “1” is output to the control unit 2 as the signal F_OUT_N_2. However, when the delay at the critical path replica tcrit and the delay element ta is too large, the data stored in the flip-flop FF3 because the clock Tclk rises at the second timing before the data “1” arrives at the flip-flop FF3. Becomes "0".

  Similarly, it is assumed that the flip-flop FF1 outputs data “1” at the first timing when the clock Tclk rises. At this time, the data “1” reaches the flip-flop FF4 via the critical path replica tcrit. Then, at the second timing when the clock Tclk rises next, the data “1” is stored in the flip-flop FF4. In this case, “1” is output to the control unit 2 as the signal F_OUT_N_3. However, if the delay in the critical path replica tcrit is too large, the data stored in the flip-flop FF4 is “0” because the clock Tclk rises at the second timing before the data “1” arrives at the flip-flop FF4. It becomes.

  In the semiconductor device according to this embodiment, the delay in each monitor unit 101_N can be detected using the values of signals F_OUT_N_1 to F_OUT_N_3 (that is, “0” or “1”) output from each monitor unit 101_N. it can. Specifically, when the value of each signal output from the monitor unit 101_N is (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) = (1, 1, 1), the delay in the monitor unit 101_N is the smallest. That is, in this case, even when the path includes the critical path replica tcrit and the delay elements ta and tb (path having the longest delay), the data “1” has reached the flip-flop FF2. It can be said that the delay in the monitor unit 101_N is small.

  Thereafter, the values of the signals output from the monitor unit 101_N are (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) = (0, 1, 1), (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) = (0, 0, 1), (F_OUT_N_1, F_OUT_N_2) , F_OUT_N_3) = (0, 0, 0), it can be said that the delay in the monitor unit 101_N increases.

  In the present embodiment, when measuring the delay of the internal circuit 3 in each monitor unit 101_N, the frequency of the clock Tclk may be changed as appropriate. For example, when the value of each signal output from the monitor unit 101_N is (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) = (1, 1, 1), by increasing the frequency of the clock Tclk, (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) = A boundary between (1, 1, 1) and (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) = (0, 1, 1) can be detected. For example, when the value of each signal output from the monitor unit 101_N is (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) = (0, 0, 0), by reducing the frequency of the clock Tclk, (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) ) = (0, 0, 0) and (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) = (0, 0, 1) can be detected.

  Similar to the semiconductor device according to the first embodiment, the variation value calculation unit 21 included in the control unit 2 uses the values (F_OUT_N_1, F_OUT_N_2, F_OUT_N_3) of the signals output from the monitor unit 101_N to calculate the variation value C_VAR. Can be sought.

  FIG. 26 is a diagram for explaining the operation of the semiconductor device according to the present embodiment. As shown in FIG. 26, when the clock signal Tclk is larger than the upper limit set value tcrit + ta ′ + tb ′, the control unit 2 lowers the power supply voltage Vdd supplied from the power supply unit 4 and the clock signal Tclk is lower than the lower limit. Is smaller than the set value tcrit + ta ′, the power supply voltage Vdd supplied from the power supply unit 4 is increased. By such control, the clock signal Tclk can be kept between the lower limit set value tcrit + ta ′ and the upper limit set value tcrit + ta ′ + tb ′.

  Here, the set value tcrit + ta ′ and the set value tcrit + ta ′ + tb ′ are delay values that are control targets. The delay value ta ′ is a value obtained by correcting the delay value ta according to the variation value C_VAR. The delay value tb ′ is a value obtained by correcting the delay value tb according to the variation value C_VAR. That is, when the variation value C_VAR in each monitor unit is large, a value larger than the delay value tb is set as the delay value tb ′. Thus, since the upper limit set value tcrit + ta ′ + tb ′ can have a margin, the power supply voltage can be appropriately set even when the delay is larger.

  On the other hand, when the variation value C_VAR in each monitor unit is small, a value close to the delay value ta can be set as the delay value ta ′, and a value close to the delay value tb can be set as the delay value tb ′. That is, when the variation value C_VAR in each monitor unit is small, it is not necessary to provide a large margin for the comparison value, so that values close to the delay values ta and tb can be set as the delay value. Therefore, since the upper limit set value tcrit + ta ′ + tb ′ can be reduced, the power consumption of the semiconductor device can be reduced.

  In the semiconductor device according to the present embodiment, the case where two delay elements ta and tb are provided as delay elements has been described, but three or more delay elements may be provided. In this case, it is necessary to provide a flip-flop for storing data output from each delay element corresponding to each delay element.

  In the semiconductor device according to the present embodiment, the configuration in which the monitor unit 101_N includes the critical path replica tcrit has been described. However, in the semiconductor device according to the present embodiment, the monitoring unit including the ring oscillator described in the first embodiment is used as a monitoring unit that monitors the variation in characteristics of the internal circuit 3, and the performance of the circuit included in the internal circuit 3 ( As a monitoring unit that monitors (delay characteristics), a monitoring unit including the critical path replica tcrit described in the present embodiment may be used. As described above, by using the monitor unit including the critical path replica tcrit as the monitor unit that detects the performance of the circuit included in the internal circuit 3, it is possible to detect delay characteristics close to those of the actual circuit.

  The present invention has been described with reference to the above embodiment, but is not limited to the configuration of the above embodiment, and can be made by those skilled in the art within the scope of the invention of the claims of the present application. It goes without saying that various modifications, corrections, and combinations are included.

1_1 to 1_N Monitor unit 2 Control unit 3 Internal circuit 4 Power supply unit 11 Ring oscillator 12 Counter 13 Delay element 21 Variation value calculation unit 22 Monitor value calculation unit 23 Register 24 Comparison unit 26_1 to 26_3 Comparison value

Claims (16)

A power supply for supplying power to the internal circuit;
A plurality of monitoring units for monitoring characteristics at a plurality of locations of the internal circuit;
A control unit that controls the power supply unit according to a comparison result between a monitor value calculated based on signals output from the plurality of monitor units and a set comparison value;
The comparison value includes a first set value corresponding to the upper limit value of the monitor value and a second set value corresponding to the lower limit value of the monitor value;
The controller is configured such that the first set value is reduced and the interval between the first set value and the second set value is narrowed as the variation in characteristics of the plurality of monitor units is reduced. Setting the first and second set values to be
Semiconductor device. Each of the monitor units includes a ring oscillator and a counter that measures the number of times that the ring oscillator oscillates within a predetermined period.
The control unit sets the comparison value according to variations in count values in the plurality of monitor units, and is calculated based on the set comparison value and the count values output from the plurality of monitor units. Controlling the power supply unit according to the comparison result with the monitor value;
The semiconductor device according to claim 1 . The comparison value includes a first count value corresponding to the upper limit value of the monitor value and a second count value corresponding to the lower limit value of the monitor value,
The control unit reduces the first count value and decreases the interval between the first count value and the second count value as the variation of the count values in the plurality of monitor units decreases. Setting the first and second count values to be
The semiconductor device according to claim 2 . The semiconductor device according to claim 2 , wherein the monitor value is an average value of count values in the plurality of monitor units. 4. The semiconductor device according to claim 2 , wherein variation in the count values in the plurality of monitor units is determined based on a standard deviation of the count values in the plurality of monitor units. 4. The semiconductor device according to claim 2 , wherein variations in the count values in the plurality of monitor units are determined based on a difference between a maximum value and a minimum value of the count values in the plurality of monitor units. The variation of the count values in the plurality of monitor units is determined based on a value obtained by dividing the difference between the maximum value and the minimum value of the count values in the plurality of monitor units by the average value of the count values in the plurality of monitor units. The semiconductor device according to claim 2 . Each of the monitor units includes first and second monitor elements including the same number of ring oscillators,
The first monitor element operates only in a monitor period for monitoring the characteristics of the internal circuit, and the second monitor element operates in a period other than the monitor period,
The controller detects aged deterioration of the internal circuit based on a monitoring result of the first monitoring element and a monitoring result of the second monitoring element;
The semiconductor device according to any one of claims 1 to 7. When the delay amount of the second monitor element with respect to the first monitor element is larger than a predetermined value, the control unit uses the monitor result of the second monitor element to calculate the comparison value. The semiconductor device according to claim 8, which is set. Each of the monitor units includes a third monitor element including a ring oscillator having a predetermined number of stages, and a fourth monitor element including a ring oscillator having more stages than the ring oscillator included in the third monitor element,
The control unit detects a variation in characteristics in the monitor unit based on a monitoring result of the third monitoring element and a monitoring result of the fourth monitoring element, and sets the comparison value according to the variation.
The semiconductor device according to any one of claims 1 to 7. Wherein the control unit, the power supply of the internal circuit updates the comparison value every time the ON state, the semiconductor device according to any one of claims 1 to 10. Wherein, after the power of the internal circuit is turned on, and updates the comparison value every time a predetermined time passes, the semiconductor device according to any one of claims 1 to 10. Wherein the control unit further comprises a monitor selector for selecting a monitor unit to be used from among the plurality of monitor portions, the semiconductor device according to any one of claims 1 to 12. Wherein the control unit, the monitoring unit is selected to be less than the number of the monitor unit to be used when the number of monitor sets the comparison value used in calculating the monitor value, claim 13 A semiconductor device according to 1. Each of the monitor units
A first flip-flop that operates in response to a predetermined clock signal;
A critical path replica for delaying data output from the first flip-flop and a plurality of delay elements;
A plurality of second flip-flops that operate in response to the predetermined clock signal, each storing data output from the critical path replica and data output from each of the plurality of delay elements,
The control unit monitors the characteristics of the internal circuit according to each data output from the plurality of second flip-flops.
The semiconductor device according to claim 1 . A method of supplying power to an internal circuit,
Monitor the characteristics of the internal circuit at multiple locations;
Calculate monitor values based on the monitor results at the plurality of locations,
Set a comparison value according to the variation in the monitoring results in the plurality of locations,
Controls the power supply to be supplied to the internal circuit in response to a result of comparison between the set comparison value and the monitor value,
The comparison value includes a first set value corresponding to the upper limit value of the monitor value and a second set value corresponding to the lower limit value of the monitor value;
When setting the comparison value, the first setting value and the second setting value are reduced so that the first setting value decreases as the variation in characteristics of the plurality of monitor units decreases. Setting the first and second set values so that the interval is narrow;
Power supply method.

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