JP5861496B2 - Multiprocessor device and power control method for multiprocessor device - Google Patents

Description

  The present invention relates to a multiprocessor device and a power control method for the multiprocessor device.

  Conventionally, a multiprocessor device having a plurality of processors that perform bidirectional communication is known. In a multiprocessor device, an increase in power consumption is a problem, and there is a great demand for reducing power consumption. The power consumption of the processor core, CPU, and the like included in each processor can be reduced, for example, when the installed OS (operating system) changes the power state. On the other hand, power control of parts other than the processor core and CPU is relatively difficult.

  An HDD controller that performs power management control is known. In the HDD controller, when the CPU performs write access to a command register for writing a write command to the HDD, the command register write monitoring unit transmits access information to the power management control unit. In addition, the transfer end monitoring unit transmits transfer end information to the HDD to the power management control unit in a predetermined state. When receiving the transfer end signal, the power management control unit issues a command to shift to the power management mode for the interface, and when receiving access information from the command register write monitoring unit, issues a command to return from the power management mode to the normal mode.

JP 2008-293476 A

  However, the conventional HDD controller is not intended for a multiprocessor device having a plurality of processors that perform bidirectional communication. Therefore, the conventional HDD controller cannot appropriately control the power of the communication interface in a multiprocessor device having a plurality of processors that perform bidirectional communication.

  In one aspect, an object of the present invention is to operate a communication interface in a multiprocessor apparatus including a plurality of processors that perform bidirectional communication, and to appropriately operate a communication interface.

One embodiment of the present invention provides:
A multiprocessor device in which a plurality of processors communicate bidirectionally,
The processors included in the plurality of processors are:
A receiving unit that is maintained in a power-supplied state and receives data from outside the processor;
A transmitter for transmitting data to the outside of the processor;
Power is supplied to the transmitter when the transmitter transmits data to the outside of the processor, and power supply to the transmitter is interrupted when the transmitter does not transmit data to the outside of the processor. A power control unit to control;
Equipped with a,
Each of the processors includes an execution unit that executes an instruction, and a memory control unit that controls a memory accessed by the execution unit,
Whether the power control unit supplies power to the transmission unit based on a signal generated when the execution unit accesses the memory space and a signal generated when the memory control unit is predetermined. It is a multiprocessor device that determines whether or not .

  According to one embodiment, in a multiprocessor device including a plurality of processors that perform bidirectional communication, the communication interface can be operated with power saving and appropriately.

1 is an overall configuration example of a multiprocessor device 1 according to an embodiment of the present invention. 2 is a hardware configuration example of a multi-core processor chip 10. It is a figure which shows the hardware constitutions regarding the communication connection between multi-core processor chips. 3 is an example of a flowchart showing a flow of control by a power supply circuit 30. It is explanatory drawing for demonstrating the process in which the Tx part activation signal generation part 32 produces | generates a Tx part activation signal. It is an example of table data 36A held by the L3 cache controller unit 36.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

  Hereinafter, a multiprocessor device and a power control method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is an overall configuration example of a multiprocessor device 1 according to an embodiment of the present invention. The multiprocessor device 1 includes multicore processor chips 10 # 0, 10 # 1, 10 # 2, and 10 # 3. Each multi-core processor chip can communicate bidirectionally via the serial communication line 50. Each multi-core processor chip is connected to a DIMM (Dual Inline Memory Module) 40 # 0, 40 # 1, 40 # 2, and 40 # 3, respectively. Each DIMM is a memory module in which a plurality of DRAM (Dynamic Random Access Memory) chips are mounted on a printed circuit board, and functions as a main memory of each multi-core processor chip. Hereinafter, when it is not distinguished which multi-core processor chip, it will be described simply as the multi-core processor chip 10.

  FIG. 2 is a hardware configuration example of the multi-core processor chip 10. The multi-core processor chip 10 includes cores 11 (0), 11 (1), 11 (2), 11 (3), an inter-core connection network 20, DDR controllers 22, 23, DDR memory interfaces 24, 25, And an L3 cache 26 which is the lowest cache memory.

  The cores 11 (0), 11 (1), 11 (2), and 11 (3) are respectively connected to the L1 caches 13 (0), 13 (1), 13 (2), and 13 (3), and the L2 cache 14 ( 0), 14 (1), 14 (2), and 14 (3). Each core includes various arithmetic units for executing instructions, an LSU (Load Store Unit), and the like. Hereinafter, the cores 11 (0), 11 (1), 11 (2), and 11 (3) are collectively referred to as the processor core unit 11.

  The inter-core connection network 20 connects the cores. The DDR controllers 22 and 23 and the DDR memory interfaces 24 and 25 function as an interface between the DIMM corresponding to the multi-core processor chip 10.

  The multi-core processor chip 10 includes inter-processor communication interfaces 28 (0), 28 (1), 28 (2), and 28 (3). The inter-processor communication interfaces 28 (0), 28 (1), and 28 (2) are connected to, for example, serial communication lines 50 that connect to other multi-core processor chips 10. The inter-processor communication interface 28 (3) is connected to an I / O hub (not shown) for connecting to, for example, an HDD (Hard Disk Drive), a PCI Express, or the like. Hereinafter, when it is not distinguished which inter-processor communication interface, it will be described simply as the inter-processor communication interface 28.

  FIG. 3 is a diagram illustrating a hardware configuration related to communication connection between multi-core processor chips. This figure shows a configuration related to communication connection between the multi-core processor chip 10 # 0 and the multi-core processor chip 10 # 1.

  The inter-processor communication interface 28 of each multi-core processor chip has a Tx portion 28A and an Rx portion 28B. The Tx unit 28A of the multicore processor chip 10 # 0 is connected to the Rx unit 28B of the multicore processor chip 10 # 1 via the serial communication line 50. The Tx unit 28A of the multicore processor chip 10 # 0 is connected to the Rx unit 28B of the multicore processor chip 10 # 1 via the serial communication line 50. The Rx portion side of the serial communication line 50 is connected to a ground terminal or the like via a termination resistor R.

  The Tx unit 28A of each multi-core processor chip includes, for example, a transmission buffer 28Aa, an IO buffer 28Ab, and the like. Further, the Rx unit 28B of each multi-core processor chip includes, for example, a reception buffer 28Aa, an IO buffer 28Ab, and the like.

  Power is supplied from the power source 29 to the inter-processor communication interface 28. Power is steadily supplied to the Rx unit 28B of the inter-processor communication interface 28 while the power supply 29 is activated, that is, while the multiprocessor device 1 is activated. For this reason, the Rx unit 28B can receive the data transmitted by other nodes without leaking.

  On the other hand, power supply on / off control is performed by the power supply circuit 30 on the Tx portion 28A of the inter-processor communication interface 28. FIG. 4 is an example of a flowchart showing the flow of control by the power supply circuit 30. The power supply circuit 30 first determines whether or not the Tx unit activation signal is input (S100). When the Tx unit activation signal is input, the power supply circuit 30 supplies power to the Tx unit 28A (S102). When the Tx unit activation signal is not input, the power supply circuit 30 determines whether there is transmission data in the transmission buffer 28Aa (S104). When there is transmission data in the transmission buffer 28Aa, the power supply circuit 30 supplies power to the Tx unit 28A (S102). If the Tx unit activation signal is not input and there is no transmission data in the transmission buffer 28Aa, the power supply circuit 30 cuts off the power supply to the Tx unit 28A (S106).

  The Tx unit activation signal generation unit 32 generates a Tx unit activation signal based on a control signal generated by each component in the multi-core processor chip and outputs it to the power supply circuit 30. Hereinafter, a method for generating the Tx portion activation signal will be described.

  FIG. 5 is an explanatory diagram for explaining a process in which the Tx unit activation signal generation unit 32 generates a Tx unit activation signal. The Tx unit activation signal generator 32 receives signals A and B from the processor core unit 11, signals E from the Rx read signal generator 34, and signals C and D from the L3 cache controller 36 that controls the L3 cache 26. , Respectively. Further, the signal F is input from the processor core unit 11 to the L3 cache controller unit 36.

  The signal A is an other-node memory space access signal generated when the processor core unit 11 accesses a memory space other than the DIMM connected to its own node, that is, the multi-core processor chip. Hereinafter, other multi-core processor chips are referred to as “other nodes”. The memory space other than the DIMM connected to the own node is a memory space indicating, for example, a DIMM connected to another node, an HDD connected to the I / O hub, a PCI Express, or the like.

  The signal B is a non-cacheable space access signal generated when the processor core unit 11 accesses the non-cacheable space. The non-cacheable space is a memory space indicating, for example, an HDD or a PCI Express connected to an I / O hub.

  The signal C is output when a cache miss occurs as a result of the L3 cache controller 36 searching the L3 cache 26 in response to the input of the signal F, which is a load / store access signal, from the processor core unit 11. L3 cache miss signal.

  The signal D is an other node cache coherency maintenance request signal generated when the L3 cache controller unit 36 updates the L3 cache 26. The L3 cache controller unit 36 refers to, for example, the table data 36A, and generates another node cache consistency holding request signal. FIG. 6 is an example of table data 36A held by the L3 cache controller unit 36. The table data 36A includes, for example, a flag 1 indicating whether or not the data has been transferred to another node, and a flag 2 indicating whether or not the data stored in the L3 cache 26 is new to the DIMM 40 of the local node. The data associated with the address. When the L3 cache controller unit 36 updates a part of the data stored in the L3 cache 26, the L3 cache controller unit 36 refers to the flag 1 associated with the cache line including the corresponding data and finds that the data has been transferred. Then, another node cache consistency maintaining request signal is transmitted to another node. More specifically, the other node cache consistency maintaining request signal is a signal requesting that the cache line including the corresponding data stored in the L3 cache 26 of the other node is invalidated. The flag 2 is referred to when writing data stored in the L3 cache 26 to the DIMM 40 at a desired timing. That is, if the flag 2 is turned on, it can be seen that the data stored in the L3 cache 26 is newer than the data stored in the DIMM 40, so that the L3 cache controller unit 36, for example, When is replaced or invalidated, the corresponding data is written to the DIMM 40.

  The signal E is generated by the Rx read signal generation unit 34 when there is a read access from another node in the data access from the other node to the own node.

  The Tx part activation signal generator 32 generates and outputs a Tx part activation signal G based on these signals. Expression (1) is a logical expression indicating a condition for the Tx unit activation signal generation unit 32 to generate the signal G.

Signal G = Signal A AND (Signal B OR Signal C) OR Signal D OR Signal E (1)
The signal A is a signal generated when the processor core unit 11 accesses the memory space of the other node, but the access destination data stored in the memory space of the other node is stored in the L3 cache 26. Actually, data access to other nodes does not occur. On the other hand, since the signal B is a non-cacheable space access signal and the signal C is an L3 cache miss signal, it indicates that none of the data corresponding to the L3 cache 26 exists.

  Accordingly, the logical sum “signal A AND (signal B OR signal C)” indicates that the processor core unit 11 “actually” accesses the memory space of another node. , A Tx portion activation signal G is generated.

  Further, since the signal D is an other-node cache coherency maintenance request signal transmitted to the other node by the L3 cache controller unit 36, data transmission to the other node is actually performed. Therefore, when the signal D is input, the Tx portion activation signal G is generated.

  Further, since the signal E is a signal generated when there is a read access from another node, data transmission for returning the data stored in the access destination to the other node is actually performed. Therefore, when the signal E is input, the Tx portion activation signal G is generated.

  Based on the input control signal, the Tx unit activation signal generation unit 32 accurately determines whether or not the Tx unit 28A is actually transmitting data to another node, and the Tx unit activation signal G can be generated. Further, since the Tx unit activation signal generation unit 32 generates the Tx unit activation signal G based on the logical sum with respect to the control signal, it is put into practical use without using complicated software. More specifically, the Tx unit activation signal generation unit 32 is put into practical use without revising software such as an OS mounted on the multi-core processor chip 10.

(Another example of the logical sum for generating the Tx portion activation signal G)
By the way, an SMP (Symmetric Multi-Processor) configuration is known as a configuration of a multiprocessor device. In the multiprocessor device adopting the SMP configuration, the own node memory space and the other node memory space are not distinguished in software, and therefore the processor core unit may not be able to generate the signal A. In this case, the Tx unit activation signal generation unit 32 generates the Tx unit activation signal G using the following equation (2) instead of the above equation (1).

Signal G = Signal B OR Signal C OR Signal D OR Signal E (2)
By doing so, the signal G is also generated when the processor core unit 11 tries to access the DIMM 40 of its own node and a cache miss occurs. In this case, unnecessary power supply to the Tx unit 28A is performed. Will be made. However, in other cases, since it is possible to accurately determine whether or not the Tx unit 28A is actually transmitting data to another node, the multiprocessor device adopting the above equation (2) It has sufficient practicality.

  On the other hand, when the multiprocessor device adopts a configuration called a ccNUMA (Cache coherent Non-Uniformed Memory Access) architecture, the own node memory space and the other node memory space are clearly distinguished. In this case, the processor core unit can easily generate the signal A. Therefore, the multiprocessor device adopting ccNUMA can adopt the above equation (1), and can reduce power consumption as compared with the multiprocessor device adopting the SMP configuration.

  According to the multiprocessor device and its power control method of the present embodiment described above, the Tx unit activation signal generation unit 32 uses the Tx unit 28A to actually send data to other nodes based on the input control signal. It is possible to accurately determine whether or not it is a scene where transmission is performed.

  Since the power supply circuit 30 performs on / off control of power supply to the Tx unit 28A based on the Tx unit activation signal, the power consumption of the Tx unit 28A can be reduced.

  Further, power is constantly supplied to the Rx unit 28B of the inter-processor communication interface 28 while the power supply 29 is activated, that is, while the multiprocessor device is activated. For this reason, the Rx unit 28B can receive the data transmitted by other nodes without leaking.

  As a result, the multiprocessor device of the present embodiment can operate the communication interface 28 with power saving and appropriately.

  Further, since the Tx unit activation signal generation unit 32 generates the Tx unit activation signal G based on the logical sum with respect to the control signal, it is put into practical use without using complicated software.

  The “power control unit” in the claims corresponds to, for example, the Tx unit activation signal generation unit 32 and the power supply circuit 30, and the “memory control unit” corresponds to the L3 cache controller unit 36, for example, The “unit” corresponds to the processor core unit 11, for example.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

  For example, although a configuration in which a plurality of multi-core processor chips are connected by the serial communication line 50 is illustrated, the multi-processor device may be entirely mounted on one chip.

Regarding the above description, the following items are further disclosed.
(Appendix 1)
A multiprocessor device in which a plurality of processors communicate bidirectionally,
The processors included in the plurality of processors are:
A receiving unit that is maintained in a power-supplied state and receives data from outside the processor;
A transmitter for transmitting data to the outside of the processor;
Power is supplied to the transmitter when the transmitter transmits data to the outside of the processor, and power supply to the transmitter is interrupted when the transmitter does not transmit data to the outside of the processor. A power control unit to control;
A multiprocessor device comprising:
(Appendix 2)
Each of the processors includes an execution unit that executes an instruction, and a memory control unit that controls a memory accessed by the execution unit,
Whether the power control unit supplies power to the transmission unit based on a signal generated when the execution unit accesses the memory space and a signal generated when the memory control unit is predetermined. To decide,
The multiprocessor device according to appendix 1.
(Appendix 3)
The memory accessed by the execution unit includes a cache memory,
The signal generated when the memory control unit is predetermined includes a signal generated when the memory control unit requests to invalidate data stored in the cache memory of another processor.
The multiprocessor device according to appendix 2.
(Appendix 4)
The memory accessed by the execution unit includes a cache memory,
The signal generated when the memory control unit is predetermined includes a signal generated when a cache miss occurs.
The multiprocessor device according to appendix 2.
(Appendix 5)
A power control method for a multiprocessor device in which a plurality of processors communicate bidirectionally,
A power control unit of a processor included in the plurality of processors,
Maintain the receiving unit that receives data from outside the processor in a powered state,
When a transmission unit that transmits data to the outside of the processor transmits data to the outside of the processor, power is supplied to the transmission unit,
Cutting off the power supply to the transmitter when the transmitter does not transmit data outside the processor;
A power control method for a multiprocessor device.
(Appendix 6)
A multiprocessor device according to any one of appendices 1 to 4,
Each of the processors included in the plurality of processors is a distributed shared memory type system in which an address space is allocated so as to mainly access a main memory connected to itself.
(Appendix 7)
A multiprocessor device according to any one of appendices 1 to 4,
Each of the processors included in the plurality of processors is configured by one chip, and performs bidirectional communication using an inter-chip interface.

DESCRIPTION OF SYMBOLS 1 Multiprocessor device 10 Multicore processor chip 11 Core 20 Inter-core connection network 26 L3 cache 28 Inter-processor communication interface 28A Tx part 28B Rx part 29 Power supply 30 Power supply circuit 32 Tx part Activation signal generation part 34 Rx read signal generation part 36 L3 Cache controller 40 DIMM
50 Serial communication line

Claims (4)

A multiprocessor device in which a plurality of processors communicate bidirectionally,
The processors included in the plurality of processors are:
A receiving unit that is maintained in a power-supplied state and receives data from outside the processor;
A transmitter for transmitting data to the outside of the processor;
Power is supplied to the transmitter when the transmitter transmits data to the outside of the processor, and power supply to the transmitter is interrupted when the transmitter does not transmit data to the outside of the processor. A power control unit to control;
Equipped with a,
Each of the processors includes an execution unit that executes an instruction, and a memory control unit that controls a memory accessed by the execution unit,
Whether the power control unit supplies power to the transmission unit based on a signal generated when the execution unit accesses the memory space and a signal generated when the memory control unit is predetermined. To decide,
Multiprocessor device. The memory accessed by the execution unit includes a cache memory,
The signal generated when the memory control unit is predetermined includes a signal generated when the memory control unit requests to invalidate data stored in the cache memory of another processor.
The multiprocessor device according to claim 1 . The memory accessed by the execution unit includes a cache memory,
The signal generated when the memory control unit is predetermined includes a signal generated when a cache miss occurs.
The multiprocessor device according to claim 1 . A power control method for a multiprocessor device in which a plurality of processors communicate bidirectionally,
A power control unit of a processor included in the plurality of processors,
Maintain the receiving unit that receives data from outside the processor in a powered state,
Transmitter for transmitting data to the processor external performs the power supply to the transmission unit to send the data to the processor outside,
When the transmission unit does not transmit data outside the processor, the power supply to the transmission unit is cut off ,
Each of the processors includes an execution unit that executes an instruction, and a memory control unit that controls a memory accessed by the execution unit,
Whether the power control unit supplies power to the transmission unit based on a signal generated when the execution unit accesses the memory space and a signal generated when the memory control unit is predetermined. To decide,
A power control method for a multiprocessor device.

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